aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2024-04-23Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragonWIP/23Apr2024Tom Rini74-19103/+4390
Support is added for 5 new Qualcomm SoCs: * QCM2290 and SM6115 are low and mid range SoCs used on the RB1 and RB2 respectively. SM6115 is also used in some mid-range smartphones/tablets. Initial support includes buttons and USB (host and gadget). * SM8250 is a flagship SoC from 2020 used on the RB5, as well as many flagship smartphones. The board can boot to a U-Boot prompt, but is missing regulators necessary for USB support. * SM8550, and SM8650 are flagship mobile SoCs from 2023 and 2024 respectively. Found on many high end smartphones. In addition: * Support is added for the Schneider HMIBSC board. * mach-snapdragon switches to OF_UPSTREAM * IPQ40xx gets several regressions fixed and some overall cleanup. * The MSM serial driver gains the ability to generate the bit-clock automatically, no longer relying on a custom DT property. * The Qualcomm SMMU driver gets a generic compatible (so per-SoC compatibles don't need to be added). * Support for the GENI I2C controller is added. * The qcom SPMI driver has SPMI v5 support fixed, and v7 support added. * The qcom sdhci driver gets some fixes for SDCC v5 support. * SDM845 gains sdcard support * Support is added for the Synopsys eUSB2 PHY driver (used on SM8550 and SM8650) * SYS_INIT_SP_BSS_OFFSET is set to 1.5M to give us more space for FDTs. * RB2 gets a work-around to fix the USB dr_mode property before booting Linux.
2024-04-23configs: qcom_defconfig: enable GENI I2C DriverNeil Armstrong1-0/+1
Enable the GENI I2C driver in the default Qualcomm defconfig. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23i2c: Add support for Qualcomm Generic Interface (GENI) I2C controllerNeil Armstrong4-0/+851
Add Support for the Qualcomm Generic Interface (GENI) I2C interface found on newer Qualcomm SoCs. The Generic Interface (GENI) is a firmware based Qualcomm Universal Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple bus protocols depending on the firmware type loaded at early boot time based on system configuration. It also supports the "I2C Master Hub" which is a single function Wrapper that only FIFO mode I2C. It replaces the fixed-function QUP Wrapper found on older SoCs. The geni-se.h containing the generic GENI Serial Engine registers defines is imported from Linux. Only FIFO mode is implemented, neither SE DMA nor GPI DMA are implemented. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom_defconfig: generate SMBIOS tablesCaleb Connolly1-1/+1
EFI initialisation fails without this, and with proper SMBIOS v3 support in (and automatic generation of useful tables) there's no reason for us not to do this on qcom platforms. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom_defconfig: define safe default SYS_LOAD_ADDRCaleb Connolly1-1/+1
Defining this as 0 results in bootm causing a null pointer exception... Define it at a safe default which is valid RAM on most qcom boards. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom_defconfig: enable OF_BOARD_SETUPCaleb Connolly1-0/+1
Use our new ft_board_setup(). Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mach-snapdragon: implement ft_board_setup() for USB role selectionCaleb Connolly1-0/+20
Some Qualcomm boards have only one USB controller which is muxed between the type-c port and an internal USB hub for type-A and ethernet. We modify the DT for these to force them to host mode in U-Boot. However in Linux DRD role switching is supported (required, even). Use ft_board_setup() to adjust the dr_mode property for these boards. While we're here, define pr_fmt for this file so we can more easily identify log messages. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23arm: dts: qrb4210-rb2-u-boot: add u-boot fixupsCaleb Connolly1-0/+6
Add a fixup to force dr_mode to host for U-Boot. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23phy: qcom: snps-femto-v2: drop clocksCaleb Connolly1-14/+0
There is a clock associated with this phy, but it's always from the rpmhcc and isn't actually needed for the hardware to work. Drop all the clock handling from the driver. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23iommu: qcom-smmu: add qcom generic compatibleCaleb Connolly1-0/+1
With the exception of SDM845, most other Qualcomm SoCs have the Qualcomm specific (but not SoC) specific SMMU compatible string. Add it here so we can match those without having to add individual SoCs to the list here. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23gpio: qcom_pmic: add pm8150lCaleb Connolly1-0/+1
This is used for the volume keys on some SM8150/SM8250 devices. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23gpio: qcom_pmic: add pm6125Caleb Connolly1-0/+1
As with some other modern PMICs, writing to the GPIOs seems to make the device reset. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: support controller version 7Neil Armstrong1-4/+29
Add the defines and support for SPMI arbiters version 7, which can handle up to 1024 peripherals, and can also drive a secondary bus which is not implemented yet. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: handle peripheral ownershipNeil Armstrong1-4/+29
The cnfg registers provides the owner id for each peripheral, so we can use this id to check if we're allowed to write register to each peripherals. Since the v5 can handle more peripherals, add the max_channels to scan more starting from version 5, make the channel_map store 32bit values and introduce the SPMI_CHANNEL_READ_ONLY flag to mark a peripheral as read-only. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: properly format commandNeil Armstrong1-20/+55
Since version 2, the cmd format has changed, takes helpers from Linux driver and use a switch/case to handle all versions in msm_spmi_write/read() command. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23spmi: msm: fix version 5 supportNeil Armstrong1-10/+9
Properly use ch_offset in msm_spmi_write() reg access. Fixes: f5a2d6b4b03 ("spmi: msm: add arbiter version 5 support") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23board: add support for Schneider HMIBSC boardSumit Garg7-0/+204
Support for Schneider Electric HMIBSC. Features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI Features enabled in U-Boot: - RAUC updates - Environment protection - USB based ethernet adaptors Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23arm: dts: qcom: Add Schneider HMIBSC board dtsSumit Garg1-0/+491
Schneider HMIBSC board dts has already been reviewed upstream on the linux-arm-msm mailing list. So once it comes through the Linux kernel release cycle into the U-Boot dts/upstream subtree, a switch to OF_UPSTREAM can be made. For the time being maintain the U-Boot copy. Link: https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@linaro.org/ Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: apq8016: Add GPIO pinctrl functionSumit Garg1-0/+1
Add GPIO pinctrl function to enable driving GPIO pins as output low or high. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: Add support for driving GPIO pins outputSumit Garg1-5/+20
Add support for driving the GPIO pins as output low or high. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial_msm: Enable RS232 flow controlSumit Garg1-4/+6
SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23apq8016: Add support for UART1 clocks and pinmuxSumit Garg3-14/+35
SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by defaultSumit Garg1-1/+1
Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is loaded as a first stage bootloader. It leads to secondary CPUs bringup failure and later causing the Linux kernel to freeze. So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's actually required. Fixes: 059d526af312 ("mach-snapdragon: generalise board support") Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: support all pin functionsRobert Marko1-13/+293
Currently, IPQ4019 pinctrl driver supports only a very limited number of pin functions and is not fully DT compatible with Linux pinctrl nodes. IPQ40xx SoC-s sometimes use different pin function numbers for the same function depending on the pin number, so for example I2C0 on GPIO58 uses function number 3 while on GPIO59 it uses function number 2. So, in order to make the driver compatible with upstream DTS to avoid the need to patch the pinctrl nodes in U-Boot and support all of the missing pin functions lets rework the driver based on upstream Linux IPQ4019 pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses different function numbers pased on the exact pin number. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOCRobert Marko1-0/+1
If compiled with logging and debug UART support, the following is printed: serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This is due to the fact that IPQ4019 pinctrl driver is not available prior to relocation and thus MSM serial will fail probing as pinctrl provider is not available. So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTSRobert Marko1-1/+1
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so as a preparation update pinctrl driver to look for the upstream pin format. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mach-ipq40xx: import GPIO header from mach-snapgradonRobert Marko1-6/+31
Pinctrl driver was refactored and moved, but the required header that it depends on was not included. Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: allow selecting with ARCH_IPQ40XXRobert Marko1-1/+1
IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used. Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23arm: mach-ipq40xx: dont select SMEM by defaultRobert Marko1-2/+0
IPQ40xx SoC-s dont have proper SMEM support like more modern Qualcomm SoC-s so there is no point in selecting the required drivers. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom_defconfig: set SYS_INIT_SP_BSS_OFFSETCaleb Connolly1-0/+1
Give us lots of room for the appended FDT. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23arm: dts: drop qcom dts filesCaleb Connolly19-19189/+0
These files are all identical (or older) than those in dts/upstream. Drop them as we now use upstream DTS files with OF_UPSTREAM. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mach-snapdragon: use OF_UPSTREAMCaleb Connolly5-7/+4
Switch to using upstream DT from dts/upstream. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: msm: calculate bit clock dividerCaleb Connolly2-27/+70
The driver currently requires the bit clock divider be hardcoded in devicetree (or use the hardcoded default from apq8016). The bit clock divider is used to derive the baud rate from the core clock: baudrate = clk_rate / csr_div clk_rate is the actual programmed core clock rate which is returned by clk_set_rate(), and this UART driver only supports a baudrate of 115200. We can therefore determine the appropriate value for UARTDM_CSR by iterating over the possible values and finding the one where the equation above holds true for a baudrate of 115200. Implement this logic and drop the non-standard DT bindings for this driver. Tested on dragonboard410c. Tested-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: ipq4019: return valid rate when setting UART clockCaleb Connolly1-1/+1
clk_set_rate() should return the clock rate that was set. The IPQ4019 clock driver doesn't set any rates yet but it should still return the expected value so that drivers can work properly. For a baud rate of 115200 with an expected bit clock divisor of 16, the clock rate should be 1843200 so return that frequency. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: apq8016: return valid rate when setting UART clockCaleb Connolly1-2/+2
The clk_init_uart() helper always returns 0, but we're meant to return a real clock rate. Given that we hardcode 115200 baud, just return the clock rate that we set. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: msm_serial: remove .clk_rate from debug UARTRobert Marko1-1/+0
MSM serial in DEBUG UART mode is trying to set .clk_rate, but the msm_serial_data structure does not have such property at all, so lets remove it as otherwise it will fail compiling. Fixes: 90023bdfe979 ("serial: msm: add debug UART") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23serial: allow selecting MSM debug UART with ARCH_IPQ40XXRobert Marko1-1/+1
Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX devices also use the same UART HW so they can also use the debug UART. So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: fix vendor_spec_cap0 registersCaleb Connolly1-2/+2
The addresses were mistakenly swapped. Put them right. Reported-by: Sumit Garg <sumit.garg@linaro.org> Fixes: a737d8962cae ("mmc: msm_sdhci: correct vendor_spec_cap0 register for v5") Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23MAINTAINERS: add Qualcomm mailing listCaleb Connolly1-0/+2
Add the newly created u-boot-qcom mailing list to keep track of Qualcomm patches. Additionally, link to the U-Boot Snapdragon custodian tree. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mach-snapdragon: Allow other board vendors apart from QcomSumit Garg1-5/+9
Qcom SoCs derived boards can come from various OEMs/ODMs and not just Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly corressponding to the actual board vendor. Suggested-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23qcom_defconfig: enable SM8550 & SM8650 clock driverNeil Armstrong1-0/+2
Enable the SM8550 & SM8650 clock driver in the Qualcomm defconfig. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk: qcom: Add SM8650 clock driverNeil Armstrong3-0/+341
Add the GCC and TCSRCC clock driver for the SM8650 SoC. The GCC driver uses the clk-qcom infrastructure to support GDSCs, Resets and gates. While the TCSRCC is a simpler clock driver which only supports gates. The GCC enable and set_rate callbacks contains some tweaks to setup clocks for Debug UART, SDCard controller and USB. The TCSRCC gates returns the XO frequency, which is used by the Synopsys eUSB2 driver to determine the PHY configuration. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk: qcom: Add SM8550 clock driverNeil Armstrong3-0/+343
Add the GCC and TCSRCC clock driver for the SM8550 SoC. The GCC driver uses the clk-qcom infrastructure to support GDSCs, Resets and gates. While the TCSRCC is a simpler clock driver which only supports gates. The GCC enable and set_rate callbacks contains some tweaks to setup clocks for Debug UART, SDCard controller and USB. The TCSRCC gates returns the XO frequency, which is used by the Synopsys eUSB2 driver to determine the PHY configuration. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23dts: sdm845-db845c-u-boot: adjust MMC clocksCaleb Connolly1-0/+7
Remove the reference to the xo clock which is on the unsupported rpmhcc clock controller. It isn't needed for MMC functionality. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23pinctrl: qcom: sdm845: add special pin namesCaleb Connolly1-1/+12
Adjust sdm845_get_pin_name() to return the correct names for the special pins. This fixes a non-fatal -ENOSYS error when probing MMC. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23clk/qcom: sdm845: enable SDCC2 core clockCaleb Connolly2-0/+18
Allow setting the clock rate for the SD card core clock. This is required for SD card support on SDM845 devices. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: use a more sensible default clock rateCaleb Connolly1-1/+1
We currently default to the lowest rate but this actually doesn't work on most platforms. Default to the HS400 speed instead which is most common on Qualcomm platforms. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: print core versionCaleb Connolly1-0/+2
This is useful for debugging. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: use modern DT handlingCaleb Connolly1-9/+19
using fdtdec_* functions is incompatible with OF_LIVE and generally offers a less friendly interface. Update to use dev_read_* functions instead. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-23mmc: msm_sdhci: correct vendor_spec_cap0 register for v5Caleb Connolly1-4/+7
The V4 and V5 controllers have quite varied register layouts. Inherit the register offsets and naming from the Linux driver. More version specific offsets can be inherited from Linux as needed. Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
generated by cgit v1.1 at 2024-08-05 18:30:22 +0000