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2022-10-20Merge tag 'u-boot-rockchip-20221020' of ↵WIP/20Oct2022Tom Rini30-1092/+3631
https://source.denx.de/u-boot/custodians/u-boot-rockchip - dts update and sync for rk356x, rk3288, rk3399 from Linux; - Add rk3399 EAIDK-610 board support; - Update for puma-rk3399 board; - some fix and typo fix in different drivers;
2022-10-20Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini8-21/+50
2022-10-20Merge tag 'clk-2023.01' of https://source.denx.de/u-boot/custodians/u-boot-clkTom Rini3-7/+23
Clock patches for 2023.01 This contains various fixes (some long overdue) for the next release.
2022-10-20Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini230-1037/+657
Beside some rather unexciting sync of the DTs from the kernel tree, and some Kconfig cleanup, there are some improvements for the ARMv5 Allwinner family, to support boards with the F1C200s (64MB DRAM) better. We will get actual board support as soon as the DTs have passed the Linux review process. There is also support for the X96 Mate TV Box, featuring the H616 SoC and a full 4GB of DRAM. Also we found the secret to enable SPI booting on the H616 (pin PC5 must be pulled to GND), so the SPI boot support patch is now good to go. Passed the gitlab CI, plus briefly tested on Pine64-LTS, LicheePi Nano, X96 Mate and OrangePi Zero.
2022-10-20riscv: ae350: Check firmware_fdt_addr headerRick Chen1-1/+1
Check firmware_fdt_addr header to see if it is a valid fdt blob. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-10-20riscv: andes_plic.c: use modified IPI schemeYu Chien Peter Lin1-3/+4
The IPI scheme in OpenSBI has been updated to support 8-core AE350 platform, the plicsw configuration needs to be modified accordingly. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-20riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+Bin Meng1-1/+1
Since OpenSBI commit bf3ef53bb7f5 ("firmware: Enable FW_PIC by default"), OpenSBI runs directly at the load address without any code movement. This causes the SPL version of QEMU 'virt' U-Boot does not boot Linux kernel anymore. In that case, OpenSBI is loaded and runs at 0x81000000, and it creates a 512KiB PMP window from that address. When booting the Linux kernel, moving kernel to its linking address 0x80200000 overlaps the PMP window, and a PMP access failure is raised. Update SPL_OPENSBI_LOAD_ADDR to load OpenSBI to a safe address. Reported-by: Yangjie Zhang <pyjmstr@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Yangjie Zhang <pyjmstr@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-20k210: fix k210_pll_calc_config()Heinrich Schuchardt2-2/+2
The k210 driver is selected by sandbox_defconfig. Building the sandbox on 32bit systems fails with: test/dm/k210_pll.c: In function ‘dm_test_k210_pll_calc_config’: include/linux/bitops.h:11:38: warning: left shift count >= width of type [-Wshift-count-overflow] 11 | #define BIT(nr) (1UL << (nr)) | ^~ test/dm/k210_pll.c:36:54: note: in expansion of macro ‘BIT’ 36 | error = abs((error - BIT(32))) >> 16; | ^~~ Use the BIT_ULL() macro to create a u64 value. Replace abs() by abs64() to get correct results on 32bit system Apply the same for the unit test. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-10-20riscv: support building double-float modulesHeinrich Schuchardt2-3/+27
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-10-20cmd/sbi: user friendly short textsHeinrich Schuchardt1-9/+9
In the sbi command use the same short texts for the legacy extensions as the SBI specification 1.0.0. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-20cmd/sbi: error message for failure to get spec versionHeinrich Schuchardt1-2/+5
If calling 'Get SBI specification version' fails, write an error message and return CMD_RET_FAILURE. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-20cmd/sbi: format RustSBI version numberHeinrich Schuchardt1-0/+1
The SBI command can print out the version number of the SBI implementation. Choose the correct output format for RustSBI. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-19clk: update clk_clean_rate_cache to use private clk structPatrick Delaunay1-1/+17
In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220620153717.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid Link: https://lore.kernel.org/r/20220712142352.RESEND.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid/
2022-10-19rockchip: clk: pll: Fix constant typoMichal Suchanek1-3/+3
Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs") Signed-off-by: Michal Suchanek <msuchanek@suse.de> Link: https://lore.kernel.org/r/20220928104129.13240-1-msuchanek@suse.de
2022-10-19clk: change return type of clk_get_parent_rate from long long to ulongMichal Suchanek2-3/+3
All functions getting and setting clock rate use ulong for rate, only clk_get_parent_rate is an exception. Change the return value to match other clock rate funcrions. Most users directly assign the rate to unsigned long anyway, and the few users that use u64 (not s64) multiply the rate so they may need the extra bits for the result in their use case. Fixes: 4aa78300a0 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220928103757.11870-1-msuchanek@suse.de
2022-10-19suniv: add UART1 supportAndre Przywara2-0/+5
Some boards with the Allwinner F1C100s family SoCs use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19suniv: move SKIP_LOWLEVEL_INIT_ONLY into KconfigAndre Przywara2-2/+2
So far we stated the lack of a lowlevel() init function for the Allwinner F1C100s board by defining the respective SKIP_* symbol in the board's defconfig. However we don't expect any *board* to employ such low level code, so expect this to be never used for the ARMv5 Allwinner SoCs. Select the appropriate symbols in the Kconfig, so that we can remove them from the defconfig, and avoid putting them in future defconfigs for other boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19sunxi: fix 32MB load address layoutAndre Przywara1-9/+9
The default load addresses for the various payloads (kernel, DT, ramdisk) on systems with just 32MB of DRAM have some issues: For a start the preceding comment doesn't match the actual values: apparently they were copied from the 64MB S3 layout, then halved, but since 0x5 is NOT the half of 0x10, they don't match up. Also those projected maximum sizes are quite restrictive: it's not easy to build a compressed kernel image with just 4MB. The only defconfig in mainline Linux that supports the F1C100s (the only 32MB user so far) creates a 6MB compressed / 15MB uncompressed kernel. Rearrange the default load addresses to accommodate such a kernel: we allow an 7MB/16MB kernel, and up to 5MB of ramdisk, stuffing the smaller binaries like the DTB towards the end, just before the relocated U-Boot. Shrink the size for DTB and scripts on the way, there is no need for allowing up to 512K for them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MBAndre Przywara4-19/+34
Traditionally we assumed that every Allwinner board would come with at least 256 MB of DRAM, and set our DRAM layout accordingly. This affected both the default load addresses, but also U-Boot's own address expectations (like being loaded at 160 MB). Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So far we special-cased those *chips*, as there was only one chip per DRAM size. However new chips force us to take a more general approach. Introduce a Kconfig symbol, which provides the minimum DRAM size of the board. If nothing else is specified, we use 256 MB, and default to smaller values for those co-packaged SoCs. Then select the different DRAM maps according to this new symbol, so that different SoCs with the same DRAM size can share those definitions. Inspired by an idea from Icenowy. This is just refactoring: compiled for all boards before and after this patch: the binaries were identical. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19configs: sunxi: licheepi_nano: enable D-CacheIcenowy Zheng1-1/+0
As the compile error when D-Cache is enabled is gone, we can have D-Cache enabled now. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-10-19sunxi: fix SUNIV build when enabling D-CacheIcenowy Zheng1-1/+1
The enable_caches function in architecture-specific board code is only necessary for V7A CPUs, code for both V8A and ARM926 have already declared this function. Only provide our implementation of enable_caches() for V7A CPUs. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-10-19sunxi: defconfig: Add X96 Mate TV boxAndre Przywara2-0/+20
The X96 Mate TV box is a TV box with the Allwinner H616 SoC. It is available with up to 4GB of DRAM and 64GB eMMC. The DRAM chips require a different configuration when compared to the OrangePi Zero2, we must not use read/write training and write leveling. Add a defconfig for the box, so that we can easily build U-Boot for it. We synced the .dts file already from the kernel tree. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19arm: dts: rockchip: rk356x: sync with Linux 6.0FUKAUMI Naoki7-748/+1891
prepare for rk3566 based board Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: jerry: Enable RESET driverSimon Glass1-0/+1
At present the display does not work since it needs the reset driver to operate. Fix this by enabling it. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: cd529f7ad62 ("rockchip: video: edp: Add missing reset support") Fixes: 9749d2ea29e ("rockchip: video: vop: Add reset support") Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: migrate to u-boot-rockchip-spi.binQuentin Schulz3-9/+12
Now that a single binary containing TPL/SPL correctly formatted for SPI flashes and U-Boot proper, can be generated by binman, let's do it. Also update the documentation to tell the user to use this newly generated file instead of manually generating and flashing the binaries. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: migrate to u-boot-rockchip.binQuentin Schulz2-8/+11
The offset of the SPL payload on Puma is different than for other Rockchip devices in that it is stored at offset 256K instead of much further away in the MMC. Flashing one binary instead of two at different offsets is much more user friendly so let's migrate to it by modifying the offset in the Puma specific Device Tree. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: migrate to TPLQuentin Schulz3-7/+7
Depending on the toolchain used to compile the SPL for Puma RK3399-Q7 module, the board does not boot because the resulting binary is too big to fit in SRAM. Let's add a TPL so that there's no need to fiddle with or hack the defconfig to have a working bootloader. This follows what's been done for the majority of other RK3399-based boards. See the original commit for the first migrations: bdc00080111f "rockchip: rk3399: update defconfig for TPL" Unfortunately, the offset in SPI-NOR for U-Boot proper needs to be modified, since the move from SPL to TPL+SPL for idbloader.img (and the "only the first 2KB per 4KB blocks are written" "hack" for rkspi format) increased the size above 256KB. Let's move it to 512KB to, hopefully, be safe. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: remove useless CONFIG_SYS_SPI_U_BOOT_OFFSQuentin Schulz1-1/+0
The SPL payload offset when booting from SPI defaults to CONFIG_SYS_SPI_U_BOOT_OFFS but can be overridden by u-boot,spl-payload-offset. The Device Tree for Puma Haikou has this property so there's no need to have this one option in the defconfig, especially since they are not in sync and therefore confusing. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: load environment from same medium as one used to load ↵Quentin Schulz2-0/+38
U-Boot proper Chances are when one boots U-Boot proper from a given storage medium, they want the same medium to be used to load and store the environment. This basically allows to have completely separate U-Boot (TPL/SPL/U-Boot proper/environment) per storage medium which is convenient when working with recovery from SD-Card as one would just need to insert a properly configured SD-Card into the device to have access to their whole debug setup. No fallback mechanism is provided as to not dirty other storage medium environment by mistake. However, since arch_env_get_location() is called by env_init() which is part of the pre-relocation process, a valid, non-ENVL_UNKNOWN, value shall be returned otherwise the relocation fails with the following message: initcall sequence 00000000002866c0 failed at call 0000000000256b34 (err=-19) This valid, non-ENVL_UNKNOWN, value is ENVL_NOWHERE which requires to always select CONFIG_ENV_IS_NOWHERE otherwise this work-around does not work. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: allow loading environment from SPI-NOR flashQuentin Schulz1-0/+2
There's a SPI-NOR flash available from which SPL and U-Boot proper can be booted, it makes sense to also allow this medium to store U-Boot environment so let's enable it. The Device Tree advertises a max frequency of 50MHz so let's set the config option appropriately. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: load environment from same MMC as used for loading ↵Quentin Schulz1-0/+22
U-Boot proper Automatically detect which MMC device (SD-Card or eMMC) was used to load U-Boot proper and load the environment from that MMC device instead of a hardcoded one. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: remove unused default ENV_OFFSET for SPI flashesQuentin Schulz1-3/+0
CONFIG_ENV_OFFSET is set in the defconfig to a different value already so this isn't used. Let's remove it as to not confuse users. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: allow non-SD-Card-loaded SPL to load U-Boot proper ↵Quentin Schulz2-1/+25
from SD-Card Trying to load U-Boot proper from SPL when SPL was not loaded from SD-Card is currently not working because the SDMMC pins aren't muxed correctly. It is assumed the BootROM is doing this for us when booting from SD-Card hence why it's not needed when booting TPL/SPL from SD-Card. The pinctrl properties are removed from the SPL DT property removal list and the pinctrl configuration nodes made available in the SPL DT, in addition to the pull-up configurations to allow loading U-Boot proper from SD-Card as a fallback mechanism for SPI-NOR and eMMC. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: use gpio-hog instead of fixed-regulator for enabling ↵Quentin Schulz2-21/+16
eMMC/SPI-NOR On Haikou devkit, it is possible to disable eMMC and SPI-NOR to force booting from SD card or USB via rkdeveloptool by toggling a switch. This switch needs to be overridden in software to be able to access eMMC and SPI-NOR once the device has booted from SD Card. Puma SoM can override this pin via gpio3_d5. Until now, fixed regulator device was abused to model this, but since there's now support for GPIO hogs, let's use it. Since we want to be able to boot the SPL from SD Card but give it the ability to load U-Boot proper from a fallback medium such as eMMC and SPI-NOR, SPL support for GPIO hogs needs to be enabled too. Support for other kinds of regulators are not needed anymore, so let's disable them. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: fix boot_targets swap depending on U-Boot proper load ↵Quentin Schulz1-12/+13
medium distroboot should try first on the same MMC medium as the one the SPL loaded U-Boot proper from. This was the case when the introducing commit was merged because the default order was eMMC first and then SD card. The check was therefore made only on whether we booted from SD card, because otherwise the order was the expected one. However, in commit b212ad24a604 ("rockchip: Fix MMC boot order"), the order was swapped. Meaning our simple check is now useless. Let's fix that by accounting for all scenarii: default boot_targets has mmc0 first but booting from SD Card, mmc1 first but booting from eMMC. Fixes: b212ad24a604 ("rockchip: Fix MMC boot order") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: rk3399: Add EAIDK-610 supportAndy Yan5-0/+1025
Specification - Rockchip RK3399 - LPDDR3 4GB - TF sd scard slot - eMMC - AP6255 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 work in otg mode - 12V DC Power supply The dts file is sync from linux-next[0]. [0]:https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts Signed-off-by: Andy Yan <andyshrk@163.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: puma-rk3399: remove dead codeQuentin Schulz1-16/+0
CONFIG_SERIAL_TAG is not selectable for ARM64 machines. While get_board_serial is weakly defined if ENV_VARS_UBOOT_RUNTIME_CONFIG is defined, it is only called when CONFIG_SUPPORT_PASSING_ATAGS is defined, which also is not selectable for ARM64 machines. Therefore this is dead code so let's remove it. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19ram: rockchip: fix typo in KConfig option labelQuentin Schulz1-1/+1
RAM_PX30_DDR4 is for DDR4 support and not DDR3 so let's fix the typo. Fixes: 2db36c64bd5a ("ram: rockchip: px30: add a config-based ddr selection") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: px30: support debug uart on UART0Quentin Schulz2-2/+54
UART0 can obviously also be used for debug uart in U-Boot, so let's add its support. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: rk3399: fix incorrect ifdef check on SPL_GPIOQuentin Schulz1-22/+28
The check to perform is on CONFIG_SPL_GPIO and not SPL_GPIO. Because this was never compiled in, it missed an include of cru.h that was not detected before. Let's include it too. Also switch to IS_ENABLED in-code check as it is the preferred inclusion/exclusion mechanism. Fixes: 07586ee4322a ("rockchip: rk3399: Support common spl_board_init") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: rk3399: fix incorrect ifdef check on SPL_DM_REGULATORQuentin Schulz1-8/+9
The check to perform is on CONFIG_SPL_DM_REGULATOR and not SPL_DM_REGULATOR. Also switch to in-code check instead of ifdefs. Fixes: 07586ee4322a ("rockchip: rk3399: Support common spl_board_init") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> # Rock960 Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented rangeXavier Drudis Ferran1-1/+1
The original code set up the DDR clock to 48 MHz, not 50MHz as requested, and did it in a way that didn't satisfy the Application Notes in RK3399 TRM [1]. 2.9.2.B says: PLL frequency range requirement [...] FOUTVCO: 800MHz to 3.2GHz 2.9.2.A : PLL output frequency configuration [...] FOUTVCO = FREF / REFDIV * FBDIV FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 FREF = 24 MHz The original code gives FOUTVCO: 24MHz/1 * 12 = 288MHz < 800MHz And the resulting FOUTPOSTDIV is 288MHz / 3 / 2 = 48MHz but the requested frequency was 50MHz Note: 2.7.2 Detail Register Description PMUCRU_PPLL_CON0 says fbdiv Feedback Divide Value Valid divider settings are: [16, 3200] in integer mode So .fbdiv = 12 wouldn't be right. But 2.9.2.C says: PLL setting consideration [...] The following settings are valid for FBDIV: DSMPD=1 (Integer Mode): 12,13,14,16-4095 (practical value is limited to 3200, 2400, or 1600 (FVCOMAX / FREFMIN)) [...] So .fbdiv = 12 would be right. In any case FOUTVCO is still wrong. I thank YouMin Chen for confirmation and explanation. Despite documentation, I don't seem to be able to reproduce a practical problem with the wrong FOUTVCO. When I initially found it I thought some problems with detecting the RAM capacity in my Rock Pi 4B could be related to it and my patch seemed to help. But since I'm no longer able to reproduce the issue, it works with or without this patch. And meanwhile a patch[2] by Lee Jones and YouMin Chen addresses this issue. Btw, shouldn't that be commited? So this patches solves no visible problem. Yet, to prevent future problems, I think it'd be best to stick to spec. An alternative to this patch could be {.refdiv = 1, .fbdiv = 75, .postdiv1 = 6, .postdiv2 = 6}; This would theoretically consume more power and yield less jitter, according to 2.9.2.C : PLL setting consideration [...] For lowest power operation, the minimum VCO and FREF frequencies should be used. For minimum jitter operation, the highest VCO and FREF frequencies should be used. [...] But I haven't tried it because I don't think it matters much. 50MHz for DDR is only shortly used by TPL at RAM init. Normal operation is at 800MHz. Maybe it's better to use less power until later when more complex software can control batteries or charging or whatever ? Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Link: [1] https://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf Link: [2] https://patchwork.ozlabs.org/project/uboot/list/?series=305766 Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Tested-by: Michal Suchánek <msuchanek@suse.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19arm: dts: rockchip: rk3288: partial sync from LinuxJohan Jonker3-66/+296
Partial sync of rk3288.dtsi from Linux version 5.18 Changed: only properties and functions that are not yet included swap some clocks positions fix some irq numbers style and sort nodes Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19arm: dts: rockchip: update cpu and gpu nodesJohan Jonker1-37/+111
In order to better compare the Linux rk3288.dtsi version with the u-boot version update the cpu and gpu nodes. Changed: use operating-points-v2 update thermal for all cpus add labels to all cpus change gpu compatible change gpu interrupt names Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19arm: dts: rockchip: rk3288: move thermal sub nodes to dtsiJohan Jonker2-88/+73
In order to better compare the Linux rk3288.dtsi version with the u-boot version move thermal sub nodes to the dtsi file and remove rk3288-thermal.dtsi Changed: replace underscore in nodename remove comments about sensor and ID use gpu phandle add #cooling-cells to gpu node lower critical temparature remove linux,hwmon property Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19phycore-rk3288: Avoid enabling partition support in SPLSimon Glass1-0/+1
This is not needed or used, and adds code size. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-19rockchip: phycore_rk3288: remove phycore_init() functionJohan Jonker2-47/+0
The phycore_rk3288 board has a SPL size problem, so remove phycore_init() function to stay within the limits. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-18Merge branch '2022-10-18-TI-platform-updates'Tom Rini20-384/+410
- Assorted fixes and improvements to some TI platforms
2022-10-18watchdog: omap_wdt: Switch required include for watchdog definesTom Rini1-1/+1
All of the required values for using the omap_wdt.c driver are found in <asm/ti-common/omap_wdt.h> and this is what is indirectly pulled in via <asm/arch/hardware.h> when it exists. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-10-18Nokia RX-51: Fix compilation with non-zero CONFIG_SYS_TEXT_BASEPali Rohár1-2/+2
For some unknown reason GNU assembler version 2.31.1 (arm-linux-gnueabi-as from Debian Buster) cannot compile following code from located in file board/nokia/rx51/lowlevel_init.S: kernoffs: .word KERNEL_OFFSET - (. - CONFIG_SYS_TEXT_BASE) when CONFIG_SYS_TEXT_BASE is set to 0x80008000. It throws strange compile error which is even without line number: AS board/nokia/rx51/lowlevel_init.o {standard input}: Assembler messages: {standard input}: Error: attempt to get value of unresolved symbol `L0' make[2]: *** [scripts/Makefile.build:293: board/nokia/rx51/lowlevel_init.o] Error 1 I have no idea about this error and my experiments showed that ARM GNU assembler is happy with negation of that number. So changing code to: kernoffs: .word . - CONFIG_SYS_TEXT_BASE - KERNEL_OFFSET and then replacing mathematical addition by substraction of "kernoffs" value (so calculation of address does not change) compiles assembler file without any error now. There should be not any functional change. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-17 10:33:39 +0000