aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2022-09-29test: Support testing malloc() failuresSimon Glass4-0/+33
It is helpful to test that out-of-memory checks work correctly in code that calls malloc(). Add a simple way to force failure after a given number of malloc() calls. Fix a header guard to avoid a build error on sandbox_vpl. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-09-29test: Fix missing livetree test runsSimon Glass3-3/+6
At present the live tree tests are not run on sandbox. This bug is in two parts, with a duplicate flag value and incorrect logic in the test runner. This was not noticed because the bug was fixed in a later commit and does not cause test failures. Fix this. Fixes: 7b1dfc9fd7e ("dm: core: Prepare for updating the device tree with ofnode") Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29event: Pass the images to EVT_FT_FIXUPSimon Glass2-0/+3
Pass the boot images along as well, in case the fixups need to look at them. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29dm: core: Pass a root node to of_find_node_by_phandle()Simon Glass4-5/+10
This function currently assumes that the control FDT is used. Update it to allow a root node to be passed, so it can work with any tree. Also add a comment to ofnode_get_by_phandle() so that its purpose is clear. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29event: Allow multiple spy declarations for each eventSimon Glass2-3/+5
At present only one spy is allowed per event. Update the naming to allow more than one, since some need this flexibility, e.g. the EVT_FT_FIXUP event. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29event: Fix a typo in the EVENT helpSimon Glass1-1/+1
Fix the help message. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29sandbox: power: Update PMIC driver to use logSimon Glass1-4/+6
Use the log functions instead of pr_...() so we can avoid using __func__. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-09-29log: update the comment for log_msg_ret()Simon Glass1-1/+4
Add some advice on string size here. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29treewide: Drop image_header_t typedefSimon Glass55-175/+179
This is not needed and we should avoid typedefs. Use the struct instead and rename it to indicate that it really is a legacy struct. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29treewide: Drop image_info_t typedefSimon Glass2-4/+4
This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29treewide: Drop bootm_headers_t typedefSimon Glass27-110/+111
This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29image: Fix BOOTM_STATE valuesSimon Glass1-12/+12
Tidy up the code style for these. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-27Merge tag 'u-boot-stm32-20220927' of ↵Tom Rini52-487/+652
https://source.denx.de/u-boot/custodians/u-boot-stm into next - Increase SYS_MALLOC_F_LEN for STM32 MCU's board - SPL fixes for STM32F7 MCUs - Device tree alignement with kernelv6.0-rc4 for MCU's board - Device tree alignement with kernelv6.0-rc3 for MPU's board - Update DDR node for STM32MP15 - Cleanup config file for STM32MP1 - Update for cmd_stm32key command - Fix compatible string to add partitions for STM32MP1 - Update for stm32programmer tool
2022-09-27configs: increase SYS_MALLOC_F_LEN for STM32 MCU's boardPatrice Chotard12-12/+0
Some STM32 MCU's board need their SYS_MALLOC_F_LEN value enlarged to avoid the "alloc space exhausted" error message during their boot process. Use the default SYS_MALLOC_F_LEN value which is set to 0x2000 in Kconfig. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-26Merge tag 'xilinx-for-v2023.01-rc1-v2' of ↵WIP/26Sep2022-nextTom Rini38-54/+976
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
2022-09-26Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini27-1287/+217
into next
2022-09-26configs: stm32f746-disco: Remove CONFIG_SYS_UBOOT_START flagPatrice Chotard1-1/+0
By pressing "c" key during SPL execution, we force U-boot execution instead of a kernel XIP image. This fixes a hard fault when booting stm32f746-disco in SPL with "c" key pressed during SPL execution. U-Boot SPL 2022.10-rc5-00009-g40d02baa91 (Sep 20 2022 - 17:21:21 +0200) Trying to boot from XIP Hard fault pc : 080083fc lr : 08000d1b xPSR : 21000000 r12 : 2004f108 r3 : 080083fd r2 : 00000028 r1 : 2004f0c8 r0 : 2004f0e4 Resetting CPU ... This is due to SYS_UBOOT_START flag set to 0x080083FD which is not correct. If unset, SYS_UBOOT_START is set by default to CONFIG_SYS_TEXT_BASE which match with our requirement. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26configs: stm32f769-disco: Fix internal flash sizePatrice Chotard3-5/+5
arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769 MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for STM32F746. The flash layout is quite similar between the 2 SoCs : STM32F746 STM32F769 4 * 32KB sectors 4 * 32KB sectors 1 * 128KB sector 1 * 128KB sector 3 * 256KB sectors 7 * 256KB sectors Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26configs: stm32746g-eval: Fix CONFIG_SYS_SPL_ARGS_ADDRPatrice Chotard1-1/+1
STM32F746 embeds 1 MB of internal flash [0x08000000-0x080fffff], fix CONFIG_SYS_SPL_ARGS_ADDR accordingly It solves hard fault when jumping from SPL to U-Boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26configs: stm32f746-disco: Fix CONFIG_SYS_SPL_ARGS_ADDRPatrice Chotard1-1/+1
STM32F746 embeds 1 MB of internal flash [0x08000000-0x080fffff], fix CONFIG_SYS_SPL_ARGS_ADDR accordingly It solves hard fault when jumping from SPL to U-Boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26configs: stm32746g-eval: Fix SPL bootPatrice Chotard1-3/+4
Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26configs: stm32f769-disco: Fix SPL bootPatrice Chotard1-3/+4
Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26configs: stm32f746-disco: Fix SPL bootPatrice Chotard1-3/+4
Commit 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' replaces CONFIG_SYS_FDT_BASE by CONFIG_SYS_SPL_ARGS_ADDR. As CONFIG_SYS_SPL_ARGS_ADDR enables additional code when enable, it increases SPL size over the initial 0x8000 limit. Increase the SPL size to 0x9000 to fix SPL boot. Set SPL_SIZE_LIMIT to 0x9000 to avoid similar issue in the future. Fixes 'b4b9a00ed593 ("Convert CONFIG_SYS_SPL_ARGS_ADDR to Kconfig")' Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26ARM: dts: stm32: DT sync with kernel v6.0-rc4 for MCU's boardsPatrice Chotard19-275/+209
Device tree alignment with kernel v6.0-rc4. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-26arm64: versal-net: Add support for mini configurationMichal Simek4-0/+161
Versal NET mini configuration is designed for running memory test. Current output is on DCC but changing serial0 alias to pl011 will move console to serial port. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aec3f41a4cc48c45b8f07dd6e423d5838dbcc9d7.1663589964.git.michal.simek@amd.com
2022-09-26arm64: versal-net: Add defconfig for Versal NETMichal Simek2-25/+134
Use one defconfig for supporting multiple different platforms. DTB reselection is enabled to choose DT based on SOC detection. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/82cc7c1ca8850270cc2ebc992d835a37aa3d236f.1663589964.git.michal.simek@amd.com
2022-09-26reset: zynqmp: Enable reset driver for Versal NETJay Buddhabhatti1-0/+1
Enable zynqmp reset driver for Versal NET. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c8c26618f87d8451c6ffa9487809a24718bff6a7.1663589964.git.michal.simek@amd.com
2022-09-26mailbox: zynqmp: Enable ipi mailbox driver for Versal NETJay Buddhabhatti1-1/+1
Enable mailbox configs for Versal NET. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b3a9a6a58b74d17e2ec5f60617fa42062fbab951.1663589964.git.michal.simek@amd.com
2022-09-26firmware: zynqmp: Add Versal NET compatible stringJay Buddhabhatti1-0/+1
Add compatible string for Versal NET. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ec73f786e1c89094752ff3693f6f0fb4536c85c5.1663589964.git.michal.simek@amd.com
2022-09-26clk: versal: Enable clock driver for Versal NETJay Buddhabhatti2-1/+2
Add support for Versal NET compatible string in clock driver. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20a35d0c1ffcc222fbe93dd406cdd0aff92f5223.1663589964.git.michal.simek@amd.com
2022-09-26spi: zynqmp_gqspi: Add support for Versal NETMichal Simek1-1/+2
Add support for Versal NET platform. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f374e9a81f2d85de1240029f3ba5f6423cfa0680.1663589964.git.michal.simek@amd.com
2022-09-26spi: cadence_qspi: Add support for Versal NET platformMichal Simek3-2/+7
Trivial changes to support cadence ospi driver for Versal NET platform. Also avoid ospi flash reset for now. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0789141f432189aab69bc496fe33e0218d1d7510.1663589964.git.michal.simek@amd.com
2022-09-26arm64: versal-net: Add support for Versal NET platformMichal Simek19-7/+614
Versal NET platform is based on Versal chip which is reusing a lot of IPs. For more information about new IPs please take a look at DT which describe currently supported devices. The patch is adding architecture and board support with soc detection algorithm. Generic setting should be very similar to Versal but it will likely diverge in longer run. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
2022-09-26riscv: ae350: Disable AVAILABLE_HARTSRick Chen2-0/+2
Disable AVAILABLE_HARTS mechanism to make sure that all harts can boot to Kernel shell successfully. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen6-5/+23
In SMP all harts will register themself in available_hart during start up. Then main hart will send IPI to other harts according to this variables. But this mechanism may not guarantee that all other harts can jump to next stage. When main hart is sending IPI to other hart according to available_harts, but other harts maybe still not finish the registration. Then the SMP booting will miss some harts finally. So let it become an option and it will be enabled by default. Please refer to the discussion: https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-26spl: introduce SPL_XIP to configNikita Shubin8-8/+15
U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-09-25Merge tag 'dm-next-25sep22' of ↵WIP/25Sep2022-nextTom Rini48-404/+765
https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next sandbox SCSI conversion to driver model final patch for blk improvements
2022-09-25sandbox: Add a test for SCSISimon Glass5-0/+58
Add a simple uclass test for SCSI. It reads the partition table from a disk image and checks that it looks correct. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: Convert to use driver model for SCSISimon Glass9-29/+135
At present sandbox is producing a warning about SCSI migration. Drop the legacy code and replace it with a new implementation. Also drop the SATA command, which does not work with driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move request-handling code to scsi_emulSimon Glass4-77/+109
Move this code into the emulator file so it can be used by multiple drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: Enable SCSI for all buildsSimon Glass5-2/+22
This will be needed to run unit tests, once the SCSI code is used for USB as well. Enable it for all sandbox builds. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move structs to header fileSimon Glass2-26/+55
Move these to the SCSI header file so we can access them from multiple emulators. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Remove setup calls from handle_read()Simon Glass1-7/+22
Move the device-specific code out into the top-level function. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move reply setup out of helperSimon Glass1-13/+9
Move this code out of the helper function so we can (later) add it as part of the shared emulation code. Set a default value of 0 for buff_used since that is what we use when there is an error. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move file size into shared structSimon Glass2-4/+5
Move this information into struct scsi_emul_info so we can use it in common code. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: scsi: Move block size into shared structSimon Glass2-5/+8
Move this information into struct scsi_emul_info so we can use it in common code. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25scsi: Move vendor/product info into the shared structSimon Glass2-6/+9
Move this information into struct scsi_emul_info so we can use it in common code. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: Move buffer to scsi_emul_infoSimon Glass2-11/+35
Move the buffer into this struct so it can be shared between different implementations. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25scsi: Move core emulation state into a new structSimon Glass2-30/+62
In preparation for sharing the emulation code between two drivers, move some of the fields into a new struct. Use a separate header file so it can be used by various drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25scsi: Move cmd_phase enum to the headerSimon Glass2-15/+22
This can be used by common files, so move it to the SCSI header and rename it. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-03 22:23:00 +0000