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2021-10-26env: superfluous check before free()WIP/2021-10-26-add-nand-biterr-and-bugfixesHeinrich Schuchardt1-4/+2
Free() checks if its argument in NULL. There is no need for the caller to do the same. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-10-26dfu: Sort Kconfig entries alphabeticallyMarek Vasut1-7/+7
The DFU_MTD Kconfig entry is in the wrong position, move it into the correct alphabetically sorted position. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-10-26lib: uuid: fix the test on RNG device presencePatrick Delaunay1-1/+1
Correct the test on RNG device presence,when ret is equal to 0, before to call dm_rng_read function. Without this patch the RNG device is not used when present (when ret == 0) or a data abort occurs in dm_rng_read when CONFIG_DM_RNG is activated but the RNG device is not present in device tree (ret != 0 and devp = NULL). Fixes: 92fdad28cfdf ("lib: uuid: use RNG device if present") CC: Matthias Brugger <mbrugger@suse.com> CC: Torsten Duwe <duwe@suse.de> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-26common: Kconfig.boot: add config SPL_FIT_RSASSA_PSSPhilippe Reynes1-0/+7
The padding pss is only supported on u-boot and tools since commit 2bbed3ff8c7f ("image: Use Kconfig to enable FIT_RSASSA_PSS on host") This commit adds the config SPL_FIT_RSASSA_PSS to support the padding pss in the SPL. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-26lib: rsa: rsa-verify: also check that padding is not NULLPhilippe Reynes1-1/+1
This commit adds a check on the padding in the function rsa_verify_key to avoid using a NULL pointer. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-26firmware: scmi: fix struct layout for scmi_clk_rate_set_inClément Léger1-2/+2
First two fields are reversed compared to what is expected by the SCMI specification. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Fixes: 60388844836 ("clk: add clock driver for SCMI agents")
2021-10-26cmd: nand biterr - Add support for nand biterr commandBalamanikandan Gunasundar1-3/+124
The command shall be used to induce bit errors in the nand page manually. The code flips a bit in the specified offset without changing the ECC. This helps to see how the software handles the error. The patch is ported from https://patchwork.ozlabs.org/project/uboot/patch/\ 1325691123-19565-1-git-send-email-holger.brunck@keymile.com The implementation is inspired from 'mtd-utils/nand-utils/nandflipbits.c' Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
2021-10-26Merge branch '2021-10-25-assorted-updates'Tom Rini7-14/+111
- Allow redundant environment on the eMMC HW boot partitions - Use LMB in "loads" - env, dfu + spi, OPTEE bugfixes
2021-10-25dfu: dfu_sf: Read the SPI flash in 16 MiB chunksMarek Vasut1-2/+12
Not all SPI flashes and controllers can do continuous transfer longer than 16 MiB, so perform the DFU read in 16 MiB chunks. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2021-10-25arm: spl: prepare for jumping to OPTEERicardo Salveti3-3/+30
Make sure to (if applicable) flush the D-cache, invalidate I-cache, and disable MMU and caches before jumping to OPTEE. This fixes the SDP->SPL->OPTEE boot flow on iMX6Q and most likely on some other ARM SoCs. Signed-off-by: Ricardo Salveti <ricardo@foundries.io> Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2021-10-25env: mmc: Add support for redundant env in both eMMC boot partitionsMarek Vasut2-5/+47
Currently the MMC environment driver supports storing redundant environment only in one eMMC partition at different offsets. This is sub-optimal, since if this one boot partition is erased, both copies of environment are lost. Since the eMMC has two boot partitions, add support for storing one copy of environment in each of the two boot partitions. To enable this functionality, select CONFIG_SYS_REDUNDAND_ENVIRONMENT to indicate redundant environment should be used. Set CONFIG_SYS_MMC_ENV_PART to 1 to indicate environment should be stored in eMMC boot partition. Set CONFIG_ENV_OFFSET equal to CONFIG_ENV_OFFSET_REDUND, and both to the offset from start of eMMC boot partition where the environment should be located. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2021-10-25loads: Block writes into LMB reserved areas of U-BootMarek Vasut1-0/+12
The loads srec loading may overwrite piece of U-Boot accidentally. Prevent that by using LMB to detect whether upcoming write would overwrite piece of reserved U-Boot code, and if that is the case, abort the srec loading. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-25env: mmc: Add missing eMMC bootpart restoration to env eraseMarek Vasut1-4/+10
If the environment is stored in eMMC hardware boot partition, the environment driver first stores the currently selected eMMC boot partition, then does the requested operation, and then restores the original boot partition settings. In case the environment operation fails, the boot partition settings are also restored. The 'env erase' implementation in the MMC environment driver lacks the path which restores the boot partition. This could lead to various failure modes, like the system boots the wrong copy of bootloader etc. Fix this by filling in the missing restoration path. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2021-10-25Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiWIP/25Oct2021Tom Rini27-35/+305
- Add and enable watchdog driver - Prepare for SYSRESET driven AXP poweroff - Prepare for SoCs without MMC2 - Some fixes for extending SPL (SPL-DM for RISC-V) - Some preparations for proper VBUS management - Fix secure monitor move
2021-10-25mmc: sunxi: conditionally include MMC2 initialization codeIcenowy Zheng1-0/+2
Allwinner R329 has no MMC2. Only include the code of MMC2 if the base address of it is defined. Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25sunxi: only include alias for eMMC when mmc2 usedIcenowy Zheng1-0/+2
Some Allwinner SoCs (e.g. R329) doesn't have a MMC2 controller at all, and on boards that we do not utilize MMC2, the alias for it is just useless. Only include the alias when we specify CONFIG_MMC_SUNXI_EXTRA_SLOT to 2. Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25sunxi: dts: H616: Enable the watchdogSamuel Holland1-1/+0
For some reason, the watchdog was disabled in the H616 device tree. Most likely this is a copy-paste from the H6 device tree: the H6 watchdog is disabled because it is broken in some chips. However, there is no evidence of issues with the H616 watchdog. Enable the watchdog node so it can be used by the driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25Merge tag 'u-boot-imx-20211022' of ↵Tom Rini52-278/+880
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20211022 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9561 - i.MX8: - Toradex Verdin (switch to binman, cleanup, etc.) - Phytec phycore_imx8mm (fixes, boot from SPI-NOR) - fixes for imx8mp_evk - doc (i.MX): MX8MM with Fast boot - i.MX6: - Toradex : colibri-imx6ull with eMMC, fixes - i.MX7ULP : - preparation for OPTEE + Serial Number - generic: - imx8m_image: Support ddr3 firmware
2021-10-25sunxi: Enable watchdog timer support by defaultSamuel Holland1-0/+1
A watchdog helps recover from hangs or failure to boot an OS. It can also be used by the sysreset framework to intentionally reset the system. Now that a driver is available, let's enable this functionality on sunxi boards. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25watchdog: Add a driver for the sunxi watchdogSamuel Holland3-0/+197
This driver supports the sun4i/sun6i/sun20i watchdog timers. They have a maximum timeout of 16 seconds. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25clk: sunxi: Extend DM_RESET selection to SPLSamuel Holland1-0/+1
The sunxi clock driver exposes a reset controller, so it selects the reset controller framework. Ensure that dependency is also satisfied when building the driver for the SPL. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25sunxi: SPL SPI: Allow larger SPLAndre Przywara1-3/+7
The more recent Allwinner SoCs BootROMs can actually load SPL images larger than 32KB. We use this on the H616 to fit the extra code needed for the PMIC into the image, and have provisions in board.c to respect that larger SPL size when booting from MMC. However the sunxi SPL SPI loader has a hardcoded load offset of 32KB, which will fail on the H616. To fix this, use the same algorithm we use for MMC: if the SPL size is smaller than 32KB, we use 32KB, otherwise we expect the U-Boot payload directly after the SPL code. This prepares for SPI booting with larger SPLs like on the H616. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-25power: pmic: axp: Implement poweroff via sysresetSamuel Holland2-1/+50
The AXP PMICs have the ability to power off the system. The existing code for this is duplicated for each PMIC variant, and uses the legacy non-DM "pmic_bus" interface. When SYSRESET is enabled, this can all be replaced with a sysreset device using the DM_PMIC interface. Since the trigger bit is the same on all PMIC variants, use the register definitions from the oldest supported PMIC. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25power: axp: Avoid do_poweroff conflict with sysresetSamuel Holland6-1/+11
The sysreset uclass has an option to provide the do_poweroff() function. When that option is enabled, the AXP power drivers should not provide their own definition. For the AXP305, which is paired with 64-bit systems where TF-A provides PSCI, there is another possible conflict with the PSCI firmware driver. This driver can be enabled even if CONFIG_PSCI_RESET is disabled, so make sure to use the right symbol in the condition. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25include: axp_pmic: Include headers for all variantsSamuel Holland6-12/+10
A single DM-based driver should be able to support some feature for several PMIC variants where the interface is the same. For example, all PMIC variants use the same register bit to trigger poweroff. However, currently only definitions for a single PMIC are available at a time. This requires drivers to use #ifdefs and different indentifiers for each variant they support. Let's simplify this by making register definitions for all variants available from the header. Then no preprocessor conditions are needed; the driver can use the register definition from any variant that supports the relevant feature. An exception is the GPIO-related definitions, which do not use unique identifiers. So for now, keep them like before. They will be cleaned up along with the GPIO driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25include: axp_pmic: Add missing header guard definitionSamuel Holland1-0/+1
This header attempted to avoid multiple inclusion using a header guard. But the preprocessor symbol was never defined, so the guard had no effect. Fix this by defining the symbol. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25tools: mksunxiboot: Use sunxi_image header directlySamuel Holland1-1/+1
When adding eGON support to mkimage, the struct boot_file_head definition was moved to its own header. This is the only thing mksunxiboot needed out of asm/arch/spl.h. Clean up the relative include by switching to new header. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25sunxi: A23/A33/H3: Actually move the secure monitorSamuel Holland1-0/+2
commit 1ebfc0c631e3 ("sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2") attempted to move the secure monitor to SRAM A2. But not all sun8i SoCs have SRAM A2, so a check was put in for SUNXI_SRAM_A2_SIZE to avoid breaking the other SoCs. However, because the header providing SUNXI_SRAM_A2_SIZE was not included, this unintentionally skipped the new definitions on all SoCs. Fix this by including the right header. Fixes: 1ebfc0c631e3 ("sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Support VBUS detection via power supplySamuel Holland2-0/+8
The device tree binding provides for getting VBUS state from a device referenced by phandle, as an optional alternative to using a GPIO. In U-Boot, where there is no power supply class, this VBUS detection will be implemented using a regulator device and its get_enable method. Let's hook this up to the PHY driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Refactor VBUS detection to match LinuxSamuel Holland1-13/+12
The Linux driver checks the VBUS detection GPIO first; then VBUS power supply; then finally assumes VBUS is present. When adding VBUS power supply support, we want to match that order, so we get the same behavior in case both a GPIO and a power supply are provided in the device tree. So refactor the function a bit to remove the early return, and use the same "assume VBUS is present" final fallback. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25phy: sun4i-usb: Remove a couple of debug messagesSamuel Holland1-4/+0
Both of these messages log the GPIO number of the ID detection GPIO, which is not terribly useful, especially in the VBUS detection function. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25sunxi: Select SPL_SEPARATE_BSSSamuel Holland1-0/+1
sunxi-common.h defines CONFIG_SPL_BSS_START_ADDR to put SPL's BSS in DRAM. Due to this, we must select SPL_SEPARATE_BSS, or else SPL will attempt to load its DTB from the wrong address (after BSS in DRAM). This change fixes booting with SPL_OF_CONTROL=y. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-23Merge https://source.denx.de/u-boot/custodians/u-boot-spiWIP/23Oct2021Tom Rini19-108/+159
- Fix mtd erase with mtdpart (Marek Behún) - NXP fspi driver fixes (Kuldeep Singh)
2021-10-23spi: nxp_fspi: Implement errata workaround for LS1028AKuldeep Singh1-5/+48
Errata ERR050568 description says that "Flash access by FlexSPI AHB command may not work with platform frequency equal to 300 MHz" on LS1028A. By default, smaller length reads(equal to RX FIFO size) are done by IP bus and larger length reads using AHB bus. For adding errata workaround, use IP bus to read entire flash contents and disable AHB path when platform frequency is 300Mhz. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23spi: nxp-fspi: Add support for IP read onlyKuldeep Singh1-4/+20
Add support for disabling AHB bus and read entire flash contents via IP bus only. Please note, this enables IP bus read using a quirk which can be enabled directly in device-type data or in existence of an errata where AHB bus may need to be disabled. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: spi-nor-ids: Add SECT_4K to mt25qu512aKris Chaplin1-1/+1
The mt25qu512a supports 4K or 64K sectors, so adding SECT_4K to enable 4K sector usage. Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com> [jagan: droped Tested-by of patch author and datasheet link] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: spi-nor-ids: Add is25lp512 and is25wp512 devicesKris Chaplin1-0/+4
Add is25lp512 and is25wp512 devices to spi-nor id table Tested on Intel n5x hardware with QSPI carrier card Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com> [jagan: droped Tested-by of patch author] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-23mtd: Remove mtd_erase_callback() entirelyMarek Behún15-91/+5
The original purpose of mtd_erase_callback() in Linux at the time it was imported to U-Boot, was to inform the caller that erasing is done (since it was an asynchronous operation). All supplied callback methods in U-Boot do nothing, but the mtd_erase_callback() function was (until previous patch) grossly abused in U-Boot's mtdpart implementation for completely different purpose. Since we got rid of the abusement, remove the mtd_erase_callback() function and the .callback member from struct erase_info entirely, in order to avoid such problems in the future. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-23mtd: mtdpart: Make mtdpart's _erase method saneMarek Behún1-8/+18
The _erase() method of the mtdpart driver, part_erase(), currently implements offset shifting (for given mtdpart partition) in a weird way: 1. part_erase() adds partition offset to block address 2. parent driver's _erase() method is called 3. parent driver's _erase() method calls mtd_erase_callback() 4. mtd_erase_callback() subtracts partition offset from block address so that the callback function is given correct address The problem here is that if the parent's driver does not call mtd_erase_callback() in some scenario (this was recently a case for spi_nor_erase(), which did not call mtd_erase_callback() at all), the offset is not shifted back. Moreover the code would be more readable if part_erase() not only added partition offset before calling parent's _erase(), but also subtracted it back afterwards. Currently the mtd_erase_callback() is expected to do this subtracting since it does have to do it anyway. Add the more steps to this procedure: 5. mtd_erase_callback() adds partition offset to block address so that it returns the the erase_info structure members as it received them 6. part_erase() subtracts partition offset from block address This makes the code more logical and also prevents errors in case parent's driver does not call mtd_erase_callback() for some reason. (BTW, the purpose of mtd_erase_callback() in Linux is to inform the caller that it is done, since in Linux erasing is done asynchronously. We are abusing the purpose of mtd_erase_callback() in U-Boot for completely different purpose. The callback function itself has empty implementation in all cases in U-Boot.) Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Check for ctrlc() in spi_nor_erase()Marek Behún1-0/+5
May it possible to interrupt the spi_nor_erase() function. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Call mtd_erase_callback() from spi_nor_erase()Marek Behún1-2/+18
The spi_nor_erase() function does not call mtd_erase_callback() as it should. The mtdpart code currently implements the subtraction of partition offset in mtd_erase_callback(). This results in partition offset being added prior calling spi_nor_erase(), but not subtracted back on return. The result is that the `mtd erase` command does not erase the whole partition, only some of it's blocks: => mtd erase "Rescue system" Erasing 0x00000000 ... 0x006fffff (1792 eraseblock(s)) jedec_spi_nor spi-nor@0: at 0x100000, len 4096 jedec_spi_nor spi-nor@0: at 0x201000, len 4096 jedec_spi_nor spi-nor@0: at 0x302000, len 4096 jedec_spi_nor spi-nor@0: at 0x403000, len 4096 jedec_spi_nor spi-nor@0: at 0x504000, len 4096 jedec_spi_nor spi-nor@0: at 0x605000, len 4096 jedec_spi_nor spi-nor@0: at 0x706000, len 4096 This is obviously wrong. Add proper calling of mtd_erase_callback() into the spi_nor_erase() function. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Don't check for zero length in spi_nor_write() / ↵Marek Behún1-6/+0
spi_nor_erase() This check is already done in all callers: mtdcore's mtd_write() / mtd_erase(), legacy spi_nor_write() / spi_flash_erase(). No reason to do this here as well. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-23mtd: spi-flash: Check for zero length in legacy spi_flash_*()Marek Behún1-0/+9
Check for zero length in the legacy spi_flash_read() / spi_flash_write() / spi_flash_erase() functions. On zero length, return 0 immediately, don't call the underlying method. Rationale: - these legacy functions call the _read(), _write() and _erase() methods of struct mtd - the DM callers of these methods already check for zero length - making all callers of these methods check for zero length makes it possible to remove the check from implementations of these _read(), _write() and _erase() methods Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-23mtd: spi-nor-core: Check return value of write_disable() in spi_nor_erase()Marek Behún1-1/+3
The cleanup code of spi_nor_erase() function calls write_disable(), but does not return it's return value even in case of failure. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Don't overwrite return value if it is non-zeroMarek Behún1-2/+4
The cleanup code of the spi_nor_erase() function overwrites the ret variable with return value of clean_bar(), even if the ret variable is already set. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Check return value of write_enable() in spi_nor_erase()Marek Behún1-1/+3
The spi_nor_erase() function does not check return value of the write_enable() call. Fix this. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor-core: Try cleaning up in case writing BAR failedMarek Behún1-1/+1
Use the cleanup codepath of spi_nor_erase() also in the event of failure of writing the BAR register. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
2021-10-23mtd: spi-nor: Add support for Spansion S25FL256LTakahiro Kuwano2-0/+20
The S25FL256L is a part of the S25FL-L family and has the same feature set as S25FL128L except the density. The datasheet can be found in the following link. https://www.cypress.com/file/316171/download The S25FL256L is 32MB NOR Flash that does not support Bank Address Register. This fixup is activated if CONFIG_SPI_FLASH_BAR is enabled and returns ENOTSUPP in setup() hook to avoid further ops. Tested on Xilinx Zynq-7000 FPGA board. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
2021-10-23mtd: spi-nor-ids: Add GD25LQ256D ChipYanhong Wang1-0/+5
Add Gigadevice GD25LQ256D SPI NOR chip. https://www.gigadevice.com/datasheet/gd25lq256d/ Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [jagan: updated commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-22Merge tag 'efi-2022-01-rc1' of ↵Tom Rini29-324/+295
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2022-01-rc1 Documentation: Use Sphinx 3.43. Move system reset documentation to HTML UEFI: Fix linking EFI apps with LLVM Fix alignment of loaded image Correct simple network protocol test Code cleanup
generated by cgit v1.1 at 2024-08-05 16:32:47 +0000