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2023-08-16Merge tag 'u-boot-stm32-20230816' of ↵WIP/16Aug2023Tom Rini25-80/+375
https://source.denx.de/u-boot/custodians/u-boot-stm DHSOM: Power cycle Buck3 in reset DHCOM: Switch DWMAC RMII clock to MCO2 stm32f746: fix display pinmux stm32mp: psci: Inhibit PDDS because CSTBYDIS is set stm32mp1: DT alignment with v6.4 stm32mp1: add splashscreen with STMicroelectronics logo stm32mp1: clk: remove error for disabled clock in stm32mp1_clk_get_parent serial: stm32: Extend TC timeout
2023-08-16serial: stm32: extend TC timeoutValentin Caron1-6/+12
Waiting 150us TC bit couldn't be enough. If TFA lets 16 bits in USART fifo, we has to wait 16 times 87 us (time of 10 bits (1 byte in most use cases) at a baud rate of 115200). Fixes: b4dbc5d65a67 ("serial: stm32: Wait TC bit before performing initialization") Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOMMarek Vasut2-4/+32
The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK pad for the PHY and the same 50 MHz clock are fed back to ETHRX via internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad using external pad-to-pad connection. Option (1) has two downsides. ETHCK_K is supplied directly from either PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and since the same PLL output is also used to supply SDMMC blocks, the performance of SD and eMMC access is affected. The second downside is that using this option, the EMI of the SoM is higher. Option (2) solves both of those problems, so implement it here. In this case, the PLL4_P is no longer limited and can be operated faster, at 100 MHz, which improves SDMMC performance (read performance is improved from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M count=1). The EMI interference also decreases. Ported from Linux kernel commit 73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16board: stm32mp1: add splash screen with stmicroelectronics logoPatrick Delaunay6-1/+13
Display the STMicroelectronics logo with features VIDEO_LOGO and SPLASH_SCREEN on STMicroelectronics boards. With CONFIG_SYS_VENDOR = "st", the logo st.bmp is selected, loaded at the address indicated by splashimage and centered with "splashpos=m,m". Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16ARM: dts: stm32mp: alignment with v6.4Patrick Delaunay10-56/+299
Device tree alignment with Linux kernel v6.4. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16ARM: stm32: Inhibit PDDS because CSTBYDIS is setMarek Vasut1-1/+1
The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never enter CStandby state and would always end up in CStop state. Clear the PDDS bit, which indicates the CA cores can enter CStandby state as it makes little sense to keep it set with CSTBYDIS also set. This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR PDDS bits are set, then the chip enters CStandby state even though the PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that from happening. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-08-16ARM: dts: stm32: fix display pinmux for stm32f746-discoDario Binacchi1-1/+1
As reported by the datasheet (DocID027590 Rev 4) for PG12: - AF9 -> LCD_B4 - AF14 -> LCD_B1 So replace AF14 with AF9 for PG12 in the dts. Fixes: fe63d3cfb77ef ("ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16clk: stm32mp1: remove error for disabled clock in stm32mp1_clk_get_parentPatrick Delaunay1-1/+2
To disabled a clock in clock tree initialization for a mux of STM32MP15, the selected clock source index is set with the latest possible index for the number of bit used. Today this valid configuration cause a error in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock is not needed for the used ETH PHY without crystal: no parents defined for clk id 123 This patch change the level of this message to avoid this trace for valid clock tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-08-16ARM: stm32: Power cycle Buck3 in reset on DHSOMMarek Vasut3-10/+15
In case the DHSOM is in suspend state and either reset button is pushed or IWDG2 triggers a watchdog reset, then DRAM initialization could fail as follows: " RAM: DDR3L 32bits 2x4Gb 533MHz DDR invalid size : 0x4, expected 0x40000000 DRAM init failed: -22 ### ERROR ### Please RESET the board ### " Avoid this failure by not keeping any Buck regulators enabled during reset, let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3 VDD enabled during reset is ST specific, move this addition to ST specific SPL board initialization so that it wouldn't affect the DHSOM . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-08-15Merge tag 'efi-2023-10-rc3' of ↵WIP/15Aug2023Tom Rini42-144/+185
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2023-10-rc3 Documentation: * Correct description of board_get_usable_ram_top * Add partition API to HTML documentation * Describe lmb_is_reserved * doc/sphinx/requirements.txt: Bump certifi up UEFI: * Fix efi_add_known_memory * Make distro_efi_boot() static Other: * Correct return type board_get_usable_ram_top
2023-08-15common: return type board_get_usable_ram_topHeinrich Schuchardt35-35/+35
board_get_usable_ram_top() returns a physical address that is stored in gd->ram_top. The return type of the function should be phys_addr_t like the current type of gd->ram_top. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15efi_loader: fix efi_add_known_memory()Heinrich Schuchardt1-1/+1
In efi_add_known_memory() we currently call board_get_usable_ram_top() with an incorrect value 0 of parameter total_size. This leads to an incorrect value for ram_top depending on the code in board_get_usable_ram_top(). Use the value of gd->ram_top instead which is set before relocation by calling board_get_usable_ram_top(). Fixes: 7b78d6438a2b ("efi_loader: Reserve unaccessible memory") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15bootmeth: efi: Make distro_efi_boot() staticBin Meng1-1/+1
As it is only called in bootmeth_efi.c Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15doc: add partition API to HTML documentationHeinrich Schuchardt3-98/+119
* Convert comments in part.h to Sphinx style. * Create documentation page for the partition API. * Add the partition API page to the API index page. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-15doc: description of board_get_usable_ram_top()Heinrich Schuchardt1-5/+10
Improve the description of function board_get_usable_ram_top(). Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-15lmb: description lmb_is_reserved, lmb_is_reserved_flagsHeinrich Schuchardt1-3/+18
* provide a description for function lmb_is_reserved() * improve the description of funciton lmb_is_reserved_flags() Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15doc/sphinx/requirements.txt: Bump certifi upTom Rini1-1/+1
Upgrade certifi to the latest version, to remove e-Tugra from the root store. Link: https://groups.google.com/a/mozilla.org/g/dev-security-policy/c/C-HrP1SEq1A?pli=1 Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15Merge tag 'ubi-updates-for-v2023.10-rc3' of ↵Tom Rini1-1/+1
https://source.denx.de/u-boot/custodians/u-boot-ubi ubi changes for v2023.10-rc3 Fix: - Fix 'ubi list' command arguments parsing from Dmitry
2023-08-15Merge tag 'i2c-updates-for-v2023.10-rc3' of ↵Tom Rini1-0/+42
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c updates for v2023.10-rc3 Bugfixes: - mvtwsi driver fix stuck "bus error" state from Sam
2023-08-15cmd: ubi: Fix 'ubi list' command arguments parsingDmitry Dunaev1-1/+1
This fixes allowed argc variable value for arguments parsing Fixes: 6de1daf64b1 ("cmd: ubi: Add 'ubi list' command") Signed-off-by: Dmitry Dunaev <dunaev@tecon.ru>
2023-08-15i2c: mvtwsi: reset controller if stuck in "bus error" stateSam Edwards1-0/+42
The MVTWSI controller can act either as a master or slave device. When acting as a master, the FSM is driven by the CPU. As a slave, the FSM is driven by the bus directly. In what is (apparently) a safety mechanism, if the bus transitions our FSM in any improper way, the FSM goes to a "bus error" state (0x00). I could find no documented or experimental way to get the FSM out of this state, except for a controller reset. Since U-Boot only uses the MVTWSI controller as a bus master, this feature only gets in the way: we do not care what happened on the bus previously as long as the bus is ready for a new transaction. So, when trying to start a new transaction, check for this state and reset the controller if necessary. Note that this should not be confused with the "deblocking" technique (used by the `i2c reset` command), which involves pulsing SCL repeatedly if SDA is found to be held low, in an attempt to force the bus back to an idle state. This patch only resets the controller in case something else had previously upset it, and (in principle) results in no externally-observable change in behavior. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-08-14Merge tag 'u-boot-rockchip-20230814' of ↵WIP/14Aug2023Tom Rini25-119/+1085
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add board: rk3568 EmbedFire Lubancat 2 - Fixes for rk3568 clock and pinctrl; - Fixes for rk3308 clock and uart; - rk3328 rock64 updates; - Video fix on veyron board;
2023-08-14Merge tag 'video-20230814' of ↵Tom Rini4-2/+7
https://source.denx.de/u-boot/custodians/u-boot-video - fix NULL dereference in vidconsole_measure() - fix simplefb format for raspberrypi-4b - fix typo in Kconfig
2023-08-14pinctrl: rockchip: Fix drive and input schmitt on RK3568Jonas Karlman1-25/+31
On RK3568 most pins have a configurable drive strength of level 0-5 and some pins level 0-11. When rk3568_set_drive is called with a strength value above 7 the drv value written to reg may overflow into the write enable bits, resulting in a bad configuration. This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after drive is configured according to the device tree. Could not get PHY for ethernet@fe010000: addr 0 Level 6-11 can be configured using a second reg for some pins, however the drv value is reused resulting in lower 6 bits being written to reg. Input schmitt is configured in 2-bit fields on RK3568 compared to earlier generation and 2'b10 should be used to enable input schmitt. Change to use regmap_update_bits with a rmask to fix the overflow issue and closer match the linux driver. Bit shift the drv value used for the second reg to configure drive strength level 6-11. Also write correct values for input schmitt setting. Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-13rpi: set the correct parameter for simple framebuffer nodeMeng Li1-0/+2
When raspberrpi-4b platform boots up, there are 2 sets of same bootup log displayed on HDMI monitor screen, it looks like the screen is split into 2 parts. The root cause is that video format of u-boot is different from kernel. The fixing "a8r8g8b8" video format is used in u-boot, but "r5g6b5" video format from framebuffer node is used in kernel image. In order to avoid weird display status on screen, it needs to set the correct parameter for simple framebuffer node even if it has existed. Signed-off-by: Meng Li <Meng.Li@windriver.com>
2023-08-13bcm2835: Add simiple-framebuffer for use with fkmsJason Wessel1-0/+3
When the fkms dtb overlay is used only the simple-framebuffer is presented as a usable video display. So, add "simple-framebuffer" compatible to enable video driver bcm2835. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Meng Li <Meng.Li@windriver.com>
2023-08-13video: kconfig: Fix a typo in SPL_VIDEO_REMOVEBin Meng1-1/+1
Add one space between 'before' and 'loading'. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-13video: vidconsole: Fix null dereference of ops->measureBin Meng1-1/+1
At present vidconsole_measure() tests ops->select_font before calling ops->measure, which would result in a null dereference when the console driver provides no ops for measure. Fixes: b828ed7d7929 ("console: Allow measuring the bounding box of text") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-12rockchip: MAINTAINERS: fix board name for Radxa ROCK 4C+FUKAUMI Naoki1-1/+1
align with other ROCK series. Fixes: 2b506407c8 ("rockchip: Add MAINTAINERS entry for Radxa Rock 4C+") Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12dts: rockchip: rk3308: Avoid warning for serial probe on prerelocMassimo Pegorer1-0/+27
Make device tree complete and consistent for pre relocation phase. Some nodes are missing, causing warnings to be issued on serial port probing during pre relocation phase (uclass_get_device_by_phandle_id fails when called by pinctrl_select_state_full: none of these failures is fatal nor causing issues). Add to *-u-boot.dtsi all required nodes with the 'bootph-some-ram' attribute. Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3308: Support reading UART rate and clock registersMassimo Pegorer3-2/+74
Add support to read RK3308 registers used to configure UART clocks, and thus to get UART rate and baudrate. This fixes clock_get_rate returning error on serial device probing. Moreover, there is no need anymore to use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files for all cases where UART is not inited by U-Boot proper or by SPL o by TPL code but by a preliminary external boot phase (for Rock PI S, UART is inited by external TPL). Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3308: Fix ordering between masking and shiftingMassimo Pegorer1-5/+5
As per definitions of masks and shift offsets in cru_rk3308.h, values read from registers must be first masked and then shifted. By the way, this fix is binary invariant, because in all of fixed cases the shift offset is zero. Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: spl: Drop out of scope debug message related to uart initMassimo Pegorer1-11/+0
Debug uart is no more inited in board_init_f function: remove this debug message from board_init_f. If an earliest-as-possible message after debug uart initialization is needed, enable DEBUG_UART_ANNOUNCE Kconfig option, instead. Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: spl: Drop useless call to debug_uart_initMassimo Pegorer1-2/+0
Since commit 0dba45864b2a ("arm: Init the debug UART") function debug_uart_init is called in crt files _main before calling board_init_f. Therefore, there is no need to call it again inside board_init_f implementation in arm/mach-rockchip/spl.c. Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: rk356x-u-boot: Set max-frequency prop in sdhci nodeJonas Karlman1-2/+1
Most board device trees for RK356x set max-frequency = <200000000> in the sdhci node, some boards like Quartz64 do not. This result in an error message due to sdhci driver trying to set a clock rate of 0 instead of the max-frequency value. rockchip_sdhci_probe clk set rate fail! Fix this by setting a common max-frequency in rk356x-u-boot.dtsi. A patch to set default max-frequency of sdhci node in linux is planned. Also remove the forced status = "okay" for the sdhci and sdmmc0 nodes, boards already set correct state for these nodes. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3568: Add dummy support for GMAC speed clocksJonas Karlman1-0/+4
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the assigned-clocks property of the gmac1 node. This result in a ENOENT error when driver core tries to set a parent for this clock. The clock speed in rgmii/rmii mode is changed using clk_set_rate of the tx_rx clock and not using clk_set_parent of the speed clock. Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk driver to allow a driver for gmac node to probe. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3568: Include UART clocks in SPLJonas Karlman1-3/+3
The clock driver for RK3568 does not include support for UART clocks in SPL. This result in the following message with high enough loglevel. ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 Fix this by including support for UART clocks in SPL. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_divJonas Karlman2-2/+5
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide, not 5 bits wide as currently defined in CPLL_25M_DIV_MASK. Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clkDamon Ding1-1/+1
Fix use of wrong clk selection for CLK_PWM1 on RK3568. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: cru: Enable cpu info support for rk3568Anton2-0/+4
Add cru structure definition in head file to support cpu_info driver. Series-version: 2 Series-changes: 2 Format the patch header, add commit message and signature. Signed-off-by: Anton <vao@asu-vei.ru> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12video: avoid build failure on veyron boardAlvaro Fernando García1-2/+5
533ad9dc avoided an overflow but causes compilation failure on 32bit boards (eg. veyron speedy) this commit uses div_u64 which has a fallback codepath for 32bit platforms Signed-off-by: Alvaro Fernando García <alvarofernandogarcia@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: rk3568: Add EmbedFire Lubancat 2 supportAndy Yan6-0/+854
LubanCat2 is a rk3568 based SBC from EmbedFire. Specification: - Rockchip rk3568 - LPDDR4/4X 1/2/4/8 GB - TF scard slot - eMMC 8/32/64/128 GB - Gigabit ethernet x 2 - HDMI out - USB 2.0 Host x 1 - USB 2.0 Type-C OTG x 1 - USB 3.0 Host x 1 - Mini PCIE interface for WIFI/BT module - M.2 key for 2280 NVME - 40 pin header The dts file is sync from linux mainline. Signed-off-by: Andy Yan <andyshrk@163.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: rv1126: Enable fdtoverlay supportJagan Teki2-0/+2
Add fdtoverlay_addr_r and enable OF_LIBFDT_OVERLAY for the use of DT overlay in RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: dts: rk3328: rock64: Align spi flash entryPeter Robinson2-2/+2
Align the SPI flash entry with upstream. There's no need to diverge here. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: dts: rk3328: Add rng details to u-boot.dtsiPeter Robinson2-0/+8
Add the rk3328 rng details to the u-boot.dtsi and enable the RNG on the Rock64 to be able to provide a random seed via UEFI. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> (Fix typo message) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12config: rock64: enable efuse for stable mac addrPeter Robinson1-0/+1
Enable the rockchip efuse driver on the Rock64 to provide a stable ethernet address on the device. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12pci: rockchip: Release resources on failing probeJonas Karlman1-51/+57
The PCIe driver for RK3399 is affected by a similar issue that was fixed for RK35xx in the commit e04b67a7f4c1 ("pci: pcie_dw_rockchip: release resources on failing probe"). Resources are not released on failing probe, e.g. regulators may be left enabled and the ep-gpio may be left in a requested state. Change to use regulator_set_enable_if_allowed and disable regulators after failure to keep regulator enable count balanced, ep-gpio is also released on regulator failure. Also add support for the vpcie12v-supply, remove unused include and check return value from dev_read_addr_name. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12rockchip: rk3399: remove duplicate call to regulators_enable_boot_onQuentin Schulz1-10/+0
An earlier commit makes the common SPL code call regulators_enable_boot_on and regulators_enable_boot_off before iterating over possible boot media for U-Boot proper. There is therefore no need to do this in the rk3399-specific code, so let's remove it. Cc: Quentin Schulz <foss+uboot@0leil.net> Tested-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-08-10Merge https://source.denx.de/u-boot/custodians/u-boot-watchdogTom Rini2-20/+22
- cmd: cyclic: Remove duplicate command name in help text (Alexander) - ftwdt010: need to reset watchdog in ftwdt010_wdt_start() (Sergei)
2023-08-10Merge https://source.denx.de/u-boot/custodians/u-boot-riscvWIP/10Aug2023Tom Rini11-28/+50
+ Add USB host support on VisionFive2 board + Enable SPI flash support on VisionFive2 board + Enable Random Number Generator in RISC-V QEMU board + Display new SBI extension + Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM (Loosely-Integrated Memory)
generated by cgit v1.1 at 2024-08-05 18:44:58 +0000