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2021-04-29phy: marvell: cp110: initialize only enabled UTMI unitsOmri Itach1-25/+26
UTMI should be initialized only for enabled device tree nodes. This fix overrides current internal configuration array entry with the next DT entry data if error is detected during the current DT entry parsing or the current port is disabled. This way the internal configuration structure will only contain valid ports information obtained from the DT. Change-Id: I9c43c6a5d234e15ae9005d1c9bc983fc1f3544b8 Signed-off-by: Omri Itach <omrii@marvell.com> Signed-off-by: Ken Ma <make@marvell.com>
2021-04-29phy: marvell: add missing speed during info printsIgal Liberman1-2/+3
In get_speed_string() we have an array (speed_strings[]) which includes all possible speed strings. This array size and content must be aligned to the speed defines in comphy_data.h. This patch adds missing 5.125G speed, aligns speed_strings[] and fixes incorrect printing when speed > 5.0G. Change-Id: I9900d23595094be321be0c62fcaa88036324568e Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29phy: marvell: rename comphy related definitions to COMPHY_XXIgal Liberman18-274/+288
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29phy: marvell: add comphy type PHY_TYPE_USB3jinghua2-13/+14
- For some Marvell SoCs, like armada-3700, there are both USB host and device controller, but on PHY level the configuration is the same. - The new type supports both USB device and USB host - This patch is cherry-picked from u-boot-2015 as-is. Change-Id: I01262027edd8ec23391cff6fb409b3009aedfbb9 Signed-off-by: jinghua <jinghua@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29arm: octeontx2: cn9130-crb.dtsi: Disable eth2 for nowStefan Roese1-3/+1
Because of the incorrectly supported SGMII_2500 mode, this patch disables eth2 for now until this issue will be fixed in mainline. Also fix an incorrect comment. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Marek Behun <marek.behun@nic.cz>
2021-04-29arm: octeontx2: Add Octeon TX2 CN9130 CRB supportKonstantin Porotchkin5-0/+152
This patch adds the base support for the Marvell Octeon TX2 CN9130 CRB. Not all interfaces are supported fully yet. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRBKonstantin Porotchkin5-1/+453
This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN9130 CRB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29arm: armada: configs: Move environment location for mvebuKonstantin Porotchkin2-2/+2
Move the default environment location to the end of 4MB flash region. This change allows to accomodate larger flash boot images making space for forthcoming code changes. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29arm: armada: dts: Add support for ap807-based platformsKonstantin Porotchkin8-379/+330
Add support for SoCs based on AP807 die. Remove unused include file for Armada-8020 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29arm: armada: dts: Use a single dtsi for cp110 die descriptionKonstantin Porotchkin13-944/+504
Use a single dtsi file for CP110 die instead of master/slave. Moving to single file will allow miltiple DTSI inclusions with re-defined CP index and name. This change will also allow support for SoCs containing more than two CP110 dies on board. Move pin control definitions from CP110 DTS to board DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29cmd/mvebu: fix the bubt commandKonstantin Porotchkin2-2/+2
- fix the dependency for MMC boot (add XENON to MVEBU_MMC) - fix the bubt destination assignment (missing # in "else" case) Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-29power: regulator: Add support for regulator-force-boot-offKonstantin Porotchkin2-0/+61
Add support for regulator-force-boot-off DT property. This property can be used by the board/device drivers for turning off regulators on early init stages as pre-requisite for the other components initialization. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-04-28Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini1-5/+12
2021-04-28Merge tag 'u-boot-amlogic-20210428' of ↵Tom Rini1-4/+11
https://source.denx.de/u-boot/custodians/u-boot-amlogic - net: designware: fix PHY reset with DM_MDIO, fixing boot of (at least) Odroid-C4
2021-04-28net: designware: fix PHY reset with DM_MDIONeil Armstrong1-4/+11
The dw_eth_pdata is not accessible from the mdio device, it gets the mdio bus plat leading to random sleeps (-10174464 on Odroid-HC4). This moves the dw_mdio_reset function to a common one taking the ethernet device as parameter and use it from the dw_mdio_reset and dm_mdio variant functions. Fixes: 5160b4567c ("net: designware: add DM_MDIO support") Reported-by: Mark Kettenis <mark.kettenis@xs4all.nl> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-28usb: ehci-mx6: Limit PHY address parsing to !CONFIG_PHYMarek Vasut1-5/+12
For systems which use generic PHY support and implement USB PHY driver, the parsing of PHY properties is unnecessary, disable it. Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-28mtd: cfi: Fix PPB lock status readoutMarek Vasut1-5/+5
According to S26KL512S datasheet [1] and S29GL01GS datasheet [2], the procedure to read out PPB lock bits is to send the PPB Entry, PPB Read, Reset/ASO Exit. Currently, the code does send incorrect PPB Entry, PPB Read and Reset/ASO Exit is completely missing. The PPB Entry sent is implemented by sending flash_unlock_seq() and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID. However, both [1] and [2] specify the last byte of PPB Entry as 0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID, that is 0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY. Since this does make sense, this patch fixes it and thus also aligns the code in flash_get_size() with flash_real_protect(). The PPB Read returns 00h in case of Protected state and 01h in case of Unprotected state, according to [1] Note 83 and [2] Note 17, so invert the result. Moreover, align the arguments with similar code in flash_real_protect(). Finally, Reset/ASO Exit command should be executed to exit the PPB mode, so add the missing reset. [1] https://www.cypress.com/file/213346/download Document Number: 001-99198 Rev. *M Table 40. Command Definitions, Nonvolatile Sector Protection Command Set Definitions [2] https://www.cypress.com/file/177976/download Document Number: 001-98285 Rev. *R Table 7.1 Command Definitions, Nonvolatile Sector Protection Command Set Definitions Fixes: 03deff433e ("cfi_flash: Read PPB sector protection from device for AMD/Spansion chips") Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-28configs: Resync with savedefconfigTom Rini71-314/+135
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-04-28reset: fix reset_get_by_index_nodev index handlingNeil Armstrong1-1/+1
This fixes an issue getting resets index 1 and 3+, the spurius "> 0" made it return the index 0 or 1, whatever index was passed. The dm_test_reset_base() did not catch it, but the dm_test_reset_base() extension catches it and this fixes the regression. This also fixes a reggression on Amlogic G12A/G12B SoCs, where HDMI output was disable even when Linux was booting. Fixes: ea9dc35aab ("reset: Get the RESET by index without device") Reported-by: B1oHazard <ty3uk@mail.ua> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-28test: reset: Extend base reset test to catch errorNeil Armstrong2-7/+36
With this extended test, we get the following failure : => ut dm reset_base Test: dm_test_reset_base: reset.c test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2) Test: dm_test_reset_base: reset.c (flat tree) test/dm/reset.c:52, dm_test_reset_base(): reset_method3.id == reset_method3_1.id: Expected 0x14 (20), got 0x2 (2) Failures: 2 A fix is needed in reset_get_by_index_nodev() when introduced in [1]. [1] ea9dc35aab ("reset: Get the RESET by index without device") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-28IOMUX: Fix buffer overflow in iomux_replace_device()Yuichiro Goto1-2/+6
Use of strcat() against an uninitialized buffer would lead to buffer overflow. This patch fixes it. Fixes: 694cd5618c ("IOMUX: Introduce iomux_replace_device()") Signed-off-by: Yuichiro Goto <goto@k-tech.co.jp> Cc: Peter Robinson <pbrobinson@gmail.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2021-04-28pinctrl: single: fix a never true comparisonDario Binacchi1-2/+2
As reported by Coverity Scan for Das U-Boot, the 'less-than-zero' comparison of an unsigned value is never true. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2021-04-28pinctrl: single: check function mask to be non-zeroDario Binacchi1-0/+9
Otherwise it can generate a division by zero, which has an undefined behavior. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-04-28Makefile: fix generation of defaultenv.h from empty initial fileRasmus Villemoes1-3/+2
When CONFIG_USE_DEFAULT_ENV_FILE=y and the file CONFIG_DEFAULT_ENV_FILE is empty (or at least doesn't contain any non-comment, non-empty lines), we end up feeding nothing into xxd, which in turn then outputs nothing. Then blindly appending ", 0x00" means that we end up trying to compile (roughly) const char defaultenv[] = { , 0x00 } which is of course broken. To fix that, change the frobbing of the text file so that we always end up printing an extra empty line (which gets turned into that extra nul byte we need) - that corresponds better to the binary format consisting of a series of key=val nul terminated strings, terminated by an empty string. Reported-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-04-28fs: btrfs: fix the false alert of decompression failureQu Wenruo1-2/+14
There are some cases where decompressed sectors can have padding zeros. In kernel code, we have lines to address such situation: /* * btrfs_getblock is doing a zero on the tail of the page too, * but this will cover anything missing from the decompressed * data. */ if (bytes < destlen) memset(kaddr+bytes, 0, destlen-bytes); kunmap_local(kaddr); But not in U-boot code, thus we have some reports of U-boot failed to read compressed files in btrfs. Fix it by doing the same thing of the kernel, for both inline and regular compressed extents. Reported-by: Matwey Kornilov <matwey.kornilov@gmail.com> Link: https://bugzilla.suse.com/show_bug.cgi?id=1183717 Fixes: a26a6bedafcf ("fs: btrfs: Introduce btrfs_read_extent_inline() and btrfs_read_extent_reg()") Signed-off-by: Qu Wenruo <wqu@suse.com>
2021-04-28arm: zimage: Use correct symbol to hide messages in SPLSamuel Holland1-7/+5
When zImage support was added to SPL, the messages were hidden to reduce code size. However, the wrong config symbol was used. Since this file is only built when CONFIG_SPL_FRAMEWORK=y, the messages were always hidden. Use the correct symbol so the messages are printed in U-Boot proper. Also use IS_ENABLED to drop the #ifdef. Fixes: 431889d6ad9a ("spl: zImage support in Falcon mode") Signed-off-by: Samuel Holland <samuel@sholland.org>
2021-04-28powerpc: introduce CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLDRasmus Villemoes3-2/+23
When flush_cache() is called during boot on our ~7M kernel image, the hundreds of thousands of WATCHDOG_RESET calls end up adding significantly to boottime. Flushing a single cache line doesn't take many microseconds, so doing these calls for every cache line is complete overkill. The generic watchdog_reset() provided by wdt-uclass.c actually contains some rate-limiting logic that should in theory mitigate this, but alas, that rate-limiting must be disabled on powerpc because of its get_timer() implementation - get_timer() works just fine until interrupts are disabled, but it just so happens that the "big" flush_cache() call happens in the part of bootm where interrupts are indeed disabled. [1] [2] [3] I have checked with objdump that the generated code doesn't change when this option is left at its default value of 0: gcc is smart enough to see that the ">=" comparison is tautologically true, hence all assignments to "flushed" are eliminated as dead stores. On our board, setting the option to something like 65536 ends up reducing total boottime by about 0.8 seconds. [1] https://patchwork.ozlabs.org/project/uboot/patch/20200605111657.28773-1-rasmus.villemoes@prevas.dk/ [2] https://lists.denx.de/pipermail/u-boot/2021-April/446906.html [3] https://lists.denx.de/pipermail/u-boot/2021-April/447280.html Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28powerpc: lib: remove leftover CONFIG_5xxRasmus Villemoes1-2/+0
CONFIG_5xx hasn't existed since commit 502589777416 (powerpc, 5xx: remove support for 5xx). Remove this last mention of it. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28allow opting out of WATCHDOG_RESET() from timer interruptRasmus Villemoes4-3/+12
Having WATCHDOG_RESET() called automatically from the timer interrupt runs counter to the idea of a watchdog device - if the board runs into an infinite loops with interrupts still enabled, the watchdog will never fire. When using CONFIG_(SPL_)WDT, the watchdog_reset function is a lot more complicated than just poking a few SOC-specific registers - it involves accessing all kinds of global data, and if the interrupt happens at the wrong time (say, in the middle of an WATCHDOG_RESET() call from ordinary code), that can end up corrupting said global data. Allow the board to opt out of calling WATCHDOG_RESET() from the timer interrupt handler by setting CONFIG_SYS_WATCHDOG_FREQ to 0 - as that setting is currently nonsensical (it would be compile-time divide-by-zero), it cannot affect any existing boards. Add documentation for both the existing and extended meaning of CONFIG_SYS_WATCHDOG_FREQ. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28timer: mpc83xx_timer: fix build with CONFIG_{HW_, }WATCHDOGRasmus Villemoes1-1/+5
The code, which is likely copied from arch/powerpc/lib/interrupts.c, lacks a fallback definition of CONFIG_SYS_WATCHDOG_FREQ and refers to a non-existing timestamp variable - obviously priv->timestamp is meant. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-04-28watchdog: use time_after_eq() in watchdog_reset()Rasmus Villemoes1-1/+1
Some boards don't work with the rate-limiting done in the generic watchdog_reset() provided by wdt-uclass. For example, on powerpc, get_timer() ceases working during bootm since interrupts are disabled before the kernel image gets decompressed, and when the decompression takes longer than the watchdog device allows (or enough of the budget that the kernel doesn't get far enough to assume responsibility for petting the watchdog), the result is a non-booting board. As a somewhat hacky workaround (because DT is supposed to describe hardware), allow specifying hw_margin_ms=0 in device tree to effectively disable the ratelimiting and actually ping the watchdog every time watchdog_reset() is called. For that to work, the "has enough time passed" check just needs to be tweaked a little to allow the now==next_reset case as well. Suggested-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de>
2021-04-28Prepare v2021.07-rc1Tom Rini1-2/+2
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-04-28ARM: rmobile: Enable NVMe support on RCar3Marek Vasut1-0/+1
Enable support for PCIe NVMe devices. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-04-28ARM: rmobile: Enable CONFIG_SYS_FLASH_PROTECTIONMarek Vasut6-6/+9
Enable CONFIG_SYS_FLASH_PROTECTION on Salvator-X(S), ULCB, Ebisu, which means the Spansion HF PPB protection bits can be operated using the 'protect' U-Boot command. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-04-28clk: renesas: Synchronize Gen2 MSTP teardown tablesMarek Vasut3-6/+6
Synchronize Gen2 MSTP teardown tables with datasheet Rev.2.00 Feb 01, 2016. This corrects the following bits: - added H2 MSTP3[10] SCIF2 - added H2/M2/E2 MSTP7[29] TCON - removed E2 MSTP5[22] Thermal Sensor - removed E2 MSTP10[31,24:22] SRC0, SRC7:9 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2021-04-28clk: renesas: Only ever access documented bits in clock driver teardownMarek Vasut7-81/+81
The clock driver used a heavy-handed approach where it turned off all available clocks, while also possibly setting bits which are not documented in the R-Car datasheet. Update the tables so that only the bits which are documented are set or cleared when tearing down the clock driver. Note that the only clock left running before booting Linux are now MFIC, INTC-AP, INTC-EX and SCIF2 / SCIF0 on V3x. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2021-04-28sunxi: DT: A64: Update devicetree files from Linux 5.12Andre Przywara17-76/+215
Import updated devicetree files from the Linux v5.12 release. Besides some node and audio port renames this changes the PHY modes to either rgmii-id or rgmii-txid. From the board files the Pinephone sees a lot of updates. This also adds the long missing USB PHY property for controller 0, which allows the U-Boot PHY driver to eventually use port 0 in host mode (pending another U-Boot patch). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
2021-04-28sunxi: DT: R40: Update device tree files from Linux 5.12Ivan Uvarov6-49/+375
Update R40 .dts{,i} and dt-binding headers to current version from kernel. Files taken from Linux 5.12-rc1 release (commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8) Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-04-28net: sun8i-emac: Fix pinmux setup for Allwinner H5Andre Przywara1-2/+6
Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-04-28mips: octeon: ebb7304: Add support for some I2C devicesAaron Williams2-1/+15
This patch adds support for the following I2C devices connected to I2C bus 0 on the Octeon EBB7304: - Dallas DS1337 RTC - TLV EEPROM Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28mips: octeon: dts/dtsi: Change UART DT node to use clocks propertyAaron Williams2-4/+2
We already have a clock driver for MIPS Octeon. This patch changes the Octeon DT nodes to supply the clock property via the clock driver instead of using an hard-coded value, which is not correct in all cases. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28mips: octeon: Add Octeon III NIC23 board supportStefan Roese10-0/+670
This patch adds the basic support for the PCIe target board equipped with the Octeon III CN2350 SoC. Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-28mips: octeon: mrvl, cn73xx.dtsi: Add AHCI/SATA DT nodeStefan Roese1-0/+19
Add the AHCI compatible SATA DT node to the Octeon CN73xx dtsi file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28scsi: Add ata_swap_buf_le16() to support big-endian platformsStefan Roese1-0/+6
Otherwise the output will look like this on MIPS Octeon NIC23: Device 0: (0:0) Vendor: ATA Prod.: aSDnsi klUrt aII Rev: 4X11 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512) instead of this version: Device 0: (0:0) Vendor: TA Prod.: SanDisk Ultra II Rev: X411 Type: Hard Disk Capacity: 457862.8 MB = 447.1 GB (937703088 x 512) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28ata: ahci: Fix usage on big-endian platformsStefan Roese1-12/+11
This patch adds a few missing virt_to_phys() to use the correct physical address for DMA operations in the common AHCI code. This is done to support the big-endian MIPS Octeon platform. Additionally the code a cleaned up a bit (remove some empty lines) and made a bit better readable. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS OcteonStefan Roese2-2/+3
This patch enables the usage of the MVEBU AHCI/SATA driver. The only changes necessary to support MIPS Octeon via DT based probing are, to add the compatible DT property and the use of dev_remap_addr() so that the correct mapped address is used in the Octeon case (phys != virt). Please note that this driver supports the usage of the "scsi" command and not the "sata" command, since it does not provide an own "scan" function, which is needed for the "sata" cmd support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28mips: octeon: cpu.c: Enable AHCI/SATA supportStefan Roese1-1/+20
For easy AHCI/ SATA integration, this patch adds board_ahci_enable() for the MVEBU AHCI driver, which will be used by this platform. This platform specific "enable" function will setup the proper endian swapping in the AHCI controller so that it can be used by the common AHCI code. Additionally the endian swizzle entry for AHCI in octeon_should_swizzle_table[] is removed, as this enabled the original lowlevel code function, e.g. octeon_configure_qlm(), for the QLM setup to work correctly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmdStefan Roese1-0/+327
This patch adds the necessary platform infrastructure code, so that the MIPS Octeon drivers "serial_octeon_pcie_console" & "serial_bootcmd" can be used. This is e.g. the bootmem initialization in a compatible way to the Marvell 2013 U-Boot, so that the exisiting PC remote tools like "oct-remote-console" & "oct-remote-load" can be used. This is be done in the newly introduced arch_misc_init(), which calls the necessary init functions when enabled. These patches are in preparation for the MIPS Octeon NIC23 board support, which is a desktop PCIe target board enabling these features. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28serial: serial_octeon_bootcmd.c: Add PCI remote console supportStefan Roese3-0/+194
This patch adds the PCI bootcmd feature for MIPS Octeon, which will be used by the upcoming Octeon III NIC23 board support. It enables the use of the "oct-remote-load" and "oct-remote-bootcmd" on host PC's to communicate with the PCIe target and load images into the onboard memory and issue commands. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-04-28serial: serial_octeon_pcie_console.c: Add PCI remote console supportStefan Roese3-0/+379
This patch adds the PCI remote console feature for MIPS Octeon, which will be used by the upcoming Octeon III NIC23 board support. It enables the use of the "oct-remote-console" tool on host PC's to communicate with the PCIe target. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
generated by cgit v1.1 at 2024-07-14 07:22:00 +0000