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2023-04-16Merge branch 'master_sh/gen4/rswitch' of ↵WIP/16Apr2023Tom Rini9-0/+1549
https://source.denx.de/u-boot/custodians/u-boot-sh
2023-04-16Merge branch 'master_sh/gen4/mmcfix' of ↵Tom Rini1-1/+1
https://source.denx.de/u-boot/custodians/u-boot-sh
2023-04-16Merge branch 'master' of git://git.denx.de/u-boot-coldfireTom Rini39-53/+141
2023-04-16ARM: renesas: Enable rswitch, serdes and PHY driver on R8A779F0 S4 SpiderMarek Vasut1-0/+5
Enable Renesas RSwitch driver, matching SERDES PHY driver and Marvell 10G ethernet PHY driver in R8A779F0 S4 Spider board configuration to make ethernet available via the RSwitch ports. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-16configs: m68k: Use default shell promptMarek Vasut9-9/+0
The current shell prompt '->' interferes with CI matching on 'bdinfo' output. When CI test.py attempts to locate memory information in the 'bdinfo' output, it matches on '->' prefix which is identical to the shell prefix. Switch the prompt to default '=>' one to avoid this interference. Suggested-by: Tom Rini <trini@konsulko.com> # found the CI oddity Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-16net: rswitch: Add Renesas Ethernet SwitchPhong Hoang3-0/+1148
This patch adds Ethernet Switch support that found on R-Car S4 (r8a779f0) SoC. This is extracted from multiple patches from downstream BSP, with additional rework of the network device registration. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Marek: Rework the driver to support all ports via subdrivers. Split the driver up, add generic PHY framework support. Generic code clean ups.] Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-16phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8Marek Vasut5-0/+396
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0). The datasheet describes initialization procedure without any information about registers' name/bits. So, this is all black magic to initialize the hardware. Especially, all channels should be initialized at once. This driver is imported and adjusted from Linux 6.3-rc1 commit: 50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-16mmc: tmio: Use IS_ENABLED() to check for CONFIG_ optionMarek Vasut1-1/+1
Use IS_ENABLED() instead of CONFIG_IS_ENABLED() to check for CONFIG_ option which is identical across all of U-Boot and xPL builds. Fixes: 2769ddc99fd ("mmc: tmio: Replace ifdeffery with IS_ENABLED/CONFIG_IS_ENABLED macros") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-15travis-ci: Add m68k M5208EVBE machineMarek Vasut2-0/+33
Add m68k M5208EVBE machine configured to test U-Boot m68k support. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-04-15CI: Add m68k targetMarek Vasut2-0/+13
Add M5208EVBE board to CI. This does not use default config due to limitations of QEMU emulation, instead the timer is switched from DMA timer to PIT timer and RAMBAR accesses are inhibited. Local QEMU launch command is as follows: $ qemu-system-m68k -nographic -machine mcf5208evb -cpu m5208 -bios u-boot.bin Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-15arch: m68k: Add QEMU specific RAMBAR workaroundMarek Vasut2-3/+12
The QEMU emulation of m68k does not support RAMBAR accesses, add Kconfig option which inhibits those accesses, so that U-Boot can be started in m68k QEMU for CI testing purpopses until QEMU emulation improves. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-15arch: m68k: Introduce trivial PIT based timerMarek Vasut3-3/+59
The QEMU emulation of m68k does not support DMA timer, the only timer that is supported is the PIT timer. Implement trivial PIT timer support for m68k. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-15arch: m68k: Use existing CONFIG_MCFTMR instead of CFG_MCFTMRMarek Vasut24-40/+26
There is an existing CONFIG_MCFTMR Kconfig symbol, use it and drop all other instances of CFG_MCFTMR. This duality is likely a result of bogus conversion to Kconfig. Fixes: 7ff7b46e6ce ("m68k: rename CONFIG_MCFTMR to CFG_MCFTMR") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-04-14Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/14Apr2023Tom Rini37-91/+199
- mvebu: Boot support for 4K Native disks (Pali) - a38x: Perform DDR training sequence again for 2nd boot (Tony)
2023-04-14Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini19-274/+564
The biggest change is some refactoring of the H616 DRAM driver, which allows better fine-tuning for each board, and is the base for pending LPDDR3 and LPDDR4 support, needed by new boards. The sun8i-emac Ethernet driver sees some refactoring that enables it for the Allwinner D1 EMAC IP. The sunxi HDMI driver is now using more DT properties. Also the early SPL code now supports some odd H616 SoC variant. There are some more patches pending, that require the final review touches and some testing, I will send a separate PR for them later. The gitlab CI completed successfully, and I boot tested a few boards with different SoCs, via FEL and SD card, into Linux.
2023-04-13ddr: marvell: a38x: Perform DDR training sequence again for 2nd bootTony Dinh1-7/+0
- DDR Training sequence happens very fast. The speedup in boot time is negligible by skipping the training sequence during 2nd boot or after. So remove the check and skip. - This change improves the robustness of DDR training. If u-boot crashed during DDR training, the training could be left in a limbo state, where the BootROM has recorded that it is already in a 2nd boot. The training must be repeated in this scenario to get out of this limbo state, but due to the check it cannot be performed. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-04-13arm: mvebu: spl: Allow to build SATA kwbimage for 4K Native disksPali Rohár3-0/+18
Add a new config option CONFIG_MVEBU_SPL_SATA_BLKSZ for specifying block size of SATA disk. This information is used during building of SATA kwbimage and must be correctly set, otherwise BootROM does not load SPL. For 4K Native disks CONFIG_MVEBU_SPL_SATA_BLKSZ must be set to 4096. Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Martin Rowe <martin.p.rowe@gmail.com>
2023-04-13tools: kwboot: Add support for parsing SATA images with non-512 block sizePali Rohár1-1/+34
Currently kwboot expected that sector size for SATA image is always 512 bytes. If SATA image cannot be parsed with sector size of 512 bytes, try larger sector sizes which are power of two and up to the 32 kB. Maximal theoretical value is 32 kB because ATA IDENTIFY command returns sector size as 16-bit number. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13tools: kwbimage: Add support for SATA images with non-512 byte block sizePali Rohár1-27/+71
SATA kwbimage contains offsets in block size unit, not in bytes. Until now kwbimage expected that SATA disk always have block size of 512 bytes. But there are 4K Native SATA disks with block size of 4096 bytes. New SATA_BLKSZ command allows to specify different block size than 512 bytes and therefore allows to generate kwbimage for disks with different block sizes. This change add support for generating SATA images with different block size. Also it add support for verifying and dumping such images. Because block size itself is not stored in SATA kwbimage, image verification is done by checking every possible block size (it is any power of two value between 512 and 32 kB). Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13tools: kwbimage: Simplify align codePali Rohár1-24/+24
Replace repeated code patterns by generic code. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13tools: imagetool: Extend print_header() by params argumentPali Rohár30-29/+41
This allows image type print_header() callback to access struct image_tool_params *params. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-13cmd: mvebu/bubt: a38x: Do not hardcode SATA block size to 512Pali Rohár1-2/+5
Find SATA block device by blk_get_devnum_by_uclass_id() function and read from it the real block size of the SATA disk. In case of error, fallback back to 512 bytes. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-13arm: mvebu: spl: Do not hardcode SATA block size to 512Pali Rohár1-3/+8
Find SATA block device by blk_get_devnum_by_uclass_id() function and read from it the real block size of the SATA disk. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-04-12sunxi: A64: drop boot0 header reservationAndre Przywara9-9/+0
In the early days of the Allwinner A64 U-Boot support, we relied on a vendor provided "boot0" binary to perform the DRAM initialisation. This replaced the SPL, and required to equip the U-Boot (proper) binary with a vendor specific header to be recognised as a valid boot0 payload. Fortunately these days are long gone (we gained SPL and DRAM support in early 2017!), and we never needed to use that hack on any later 64-bit Allwinner SoC. Since this is highly obsolete by now, remove that option from the defconfigs of all A64 boards. We leave the code still in here for now, since some people expressed their interest in this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: arm64: boot0.h: runtime check for RVBAR addressAndre Przywara2-4/+24
Some SoCs of the H616 family use a die variant, that puts some CPU power and reset control registers at a different address. There are examples of two instances of the same board, using different die revisions of the otherwise same H313 SoC. We need to write to a register in that block *very* early in the SPL boot, to switch the core to AArch64. Since the devices are otherwise indistinguishable, let the SPL code read that die variant and use the respective RVBAR address based on that. That is a bit tricky, since we need to do that in hand-coded AArch32 machine language, shared by all 64-bit SoCs. To avoid build dependencies in this mess, we always provide two addresses to choose from, and just give identical values for all other SoCs. This allows the same code to run on all 64-bit SoCs, and controls this switch behaviour purely from Kconfig. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: boot0.h: allow RVBAR MMIO address customisationAndre Przywara2-5/+14
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need to program the 64-bit start code address into an MMIO mapped register that shadows the architectural RVBAR register. This address is SoC specific, with just two versions out there so far. Now a third address emerged, on a *variant* of an existing SoC (H616). Change the boot0.h start code to make this address a Kconfig selectable option, to allow easier maintenance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: Add TPR2 parameter for H616 DRAM driverJernej Skrabec4-24/+75
It turns out that some H616 and related SoCs (like H313) need TPR2 parameter for proper working. Add it. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize some of H616 DDR3 timingsJernej Skrabec1-4/+5
Currently twr2rd, trd2wr and twtp are constants, but according to vendor driver they are calculated from other values. Do that here too, in preparation for later introduction of new parameter. While at it, introduce constant for t_wr_lat, which was incorrectly calculated from tcl before. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize "unknown feature" in H616 DRAM driverJernej Skrabec4-11/+44
Part of the code, previously known as "unknown feature", also doesn't have constant values. They are derived from TPR0 parameter in vendor DRAM code. Let's move that code to separate function and introduce TPR0 parameter here too, to ease adding new boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize bit delay code in H616 DRAM driverJernej Skrabec4-49/+163
These values are highly board specific and thus make sense to add parameter for them. To ease adding support for new boards, let's make them same as in vendor DRAM settings. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Make bit delay function in H616 DRAM code voidJernej Skrabec1-3/+1
Mentioned function result is always true and result isn't checked anyway. Let's make it void. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Always configure ODT on H616 DRAMJernej Skrabec2-3/+2
Vendor H616 DRAM code always configure part which we call ODT configuration. Let's reflect that here too. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Convert H616 DRAM options to single settingJernej Skrabec5-133/+117
Vendor DRAM settings use TPR10 parameter to enable various features. There are many mores features that just those that are currently mentioned. Since new will be added later and most are not known, let's reuse value from vendor DRAM driver as-is. This will also help adding support for new boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: parameterize H616 DRAM ODT valuesJernej Skrabec5-22/+61
While ODT values for same memory type are similar, they are not necessary the same. Let's parameterize them and make parameter same as in vendor DRAM settings. That way it will be easy to introduce new board support. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: cosmetic: Fix H616 DRAM driver code styleJernej Skrabec1-37/+37
Fix code style for pointer declaration. This is just cosmetic change to avoid checkpatch errors in later commits. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Fix write to H616 DRAM CR registerJernej Skrabec1-1/+1
Vendor DRAM code actually writes to whole CR register and not just sets bit 31 in mctl_ctrl_init(). Just to be safe, do that here too. Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12ARM: dts: sun6i: mixtile-loftq: Add USB1 VBUS regulatorSamuel Holland1-0/+17
This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no regulator exists in its device tree. Add the regulator, so USB will continue to work when the PHY driver switches to using the regulator uclass instead of a GPIO. Update the device tree here because it does not exist in Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12net: sun8i-emac: Remove the SoC variant IDSamuel Holland1-14/+0
Now that all differences in functionality are covered by individual flags, remove the enumeration of SoC variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12net: sun8i-emac: Use common syscon setup for R40Samuel Holland1-17/+15
While R40 puts the EMAC syscon register at a different address from other variants, the relevant portion of the register's layout is the same. Factor out the register offset so the same code can be shared by all variants. This matches what the Linux driver does. This change provides two benefits beyond the simplification: - R40 boards now respect the RX delays from the devicetree - This resolves a warning on architectures where readl/writel expect the address to have a pointer type, not phys_addr_t. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12net: sun8i-emac: Add a flag for the internal PHY switchSamuel Holland1-1/+3
Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12net: sun8i-emac: Add a flag for RMII supportSamuel Holland1-8/+7
Describe this feature instead of using the SoC ID. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12net: sun8i-emac: Add a structure for variant dataSamuel Holland1-20/+45
Currently, EMAC variants are distinguished by their identity, but this gets unwieldy as more overlapping variants are added. Add a structure so we can describe the individual feature differences between the variants. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12video: sunxi: dw-hdmi: Use DM for HVCC regulatorSamuel Holland1-0/+9
The HDMI PHY depends on the HVCC supply being enabled. So far we have relied on it being enabled by an earlier firmware stage (SPL or TF-A). Attempt to enable the regulator here, so we can remove that dependency. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12video: sunxi: dw-hdmi: Use DM for clock gates and resetsSamuel Holland1-6/+21
This abstracts away the CCU register layout, which is necessary for supporting new SoCs like H6 with a reorganized CCU. One of the resets is referenced from the PHY node instead of the controller node, so it will have to wait until the PHY code is factored out to a separate driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-11Merge tag 'for-v2023-07-rc1' of ↵WIP/11Apr2023Tom Rini44-66/+325
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c updates for v2023-07-rc1 - designware_i2c: remove apparently redundant read of 'i2c, speeds' DT property from Rasmus Villemoes - fix: correct I2C deblock logic from Haibo Chen - imx_lpi2c: Fix misuse the IS_ENABLED for DM clock from Ye Li - m68k: convert to DM from Angelo Dureghello
2023-04-11m68k: upgrading all boards to dm i2cAngelo Dureghello13-35/+23
Upgrading all board configs where i2c is involved to DM i2c. Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11m68k: dts: add i2c nodesAngelo Dureghello23-0/+272
Add all the i2c nodes for each family, and add specific i2c overwrites in the related board-specific dts. Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11i2c: fsl_i2c: fix m68k transfertsAngelo Dureghello2-7/+19
This driver is actually used for powerpc and m68k/ColdFire. On ColdFire SoC's, interrupt flag get not set if IIEN flag (mbcr bit6, interrupt enabled) is not set appropriately before each transfert. As a result, the transfert hangs forever waiting for IIEN. This patch set IIEN before each transfert, while considering this fix as not harming powerpc arch. Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11m68k: mcf5441x: fix CONFIG_SYS_FSL_I2C definitionAngelo Dureghello1-3/+2
Fix CONFIG_SYS_FSL_I2C to correct name CONFIG_SYS_I2C_FSL. Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
2023-04-11board: stmark2: add i2c0 pinmux pad configurationAngelo Dureghello1-0/+2
Add CFG option to enable proper pinmux pad setting for i2c0. Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
generated by cgit v1.1 at 2024-07-17 06:45:53 +0000