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2023-05-15Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flashWIP/15May2023Tom Rini2-1/+10
- cfi: respect reg address length (Nuno)
2023-05-15mtd: cfi: respect reg address lengthNuno Sá2-1/+10
flash_get_size() will get the flash size from the device itself and go through all erase regions to read protection status. However, the device mappable region (eg: devicetree reg property) might be lower than the device full size which means that the above cycle will result in a data bus exception. This change fixes it by reading the 'addr_size' during probe() and also use that as one possible upper limit. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
2023-05-14Merge branch 'master_rzn1/rzn1' of ↵WIP/14May2023Tom Rini44-4/+5477
https://source.denx.de/u-boot/custodians/u-boot-sh - R-Car RZN1 support
2023-05-14Merge branch '2023-05-13-bootstd-updates-and-improvements'Tom Rini30-148/+180
- Assorted bootstd fixes and cleanups. This should fix problems with Debian, and make script-based distributions work when BOOTMETH_DISTRO is enabled now (as BOOTMETH_DISTRO was renamed and then reintroduced).
2023-05-13bootstd: Create a new BOOTMETH_DISTROSimon Glass1-1/+9
We cannot be sure what bootmeth a distro will need to use. Add a new BOOTMETH_DISTRO option which collects these together. Select this from BOOTSTD_DEFAULTS so that it is clear what is needed. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Make BOOTMETH_EFILOADER depend on EFI_LOADER, select if EFI_LOADER] Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-13bootstd: Rename distro and syslinux to extlinuxSimon Glass18-126/+136
We use the terms 'distro' to mean extlinux but they are not really the same. 'Distro' could refer to any method of booting a distribution, whereas extlinux is a particular method. Also we sometimes use syslinux, but it is better to use the same term in all cases. Rename distro to syslinux and also update bootstd uses of syslinux to use extlinux instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-05-13bootstd: Tidy up reporting of errorsSimon Glass4-8/+8
In a few cases the error handling is not quite right. Make sure we return the actual error in distro_efi_read_bootflow_file() rather than -EINVAL. Return -IO when a file cannot be read. Also show the error name if available. This does not change operation, but does make it easier to diagnose problems. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-05-13bootstd: Correct default boot commandSimon Glass3-4/+4
The patch to relax flag requirements was not accepted[1], so we still have to have separate bootcommands depending on CMD_BOOTFLOW_FULL. The previous attempt at this did not work, since it used the wrong name for the options. Fix this and change the message to mention BOOTSTD_FULL since this affects not just the flags, but all functionality, so is more likely what the user wants. Drop the useless condition on CMD_BOOTFLOW_FULL while we are here. [1] https://patchwork.ozlabs.org/project/uboot/patch/20230329071655.1959513-2-sjg@chromium.org/ Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: a91492b6e9c ("bootstd: Provide a default command")
2023-05-13bootstd: Require HUSH_PARSER for script bootingSimon Glass1-0/+1
Armbian uses a script which needs the HUSH parser. It is likely that other distros will do the same. Enable it by default, just in case. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Jonas Karlman <jonas@kwiboo.se>
2023-05-13bootstd: usb: Avoid initing USB twiceSimon Glass2-0/+8
This causes crashes on some boards, e.g. rockpro64. In any case, we should not do it. Check the usb_started flag to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Tom Rini <trini@konsulko.com>
2023-05-13usb: Tidy up the usb_start flagSimon Glass6-8/+6
This should be declared in a header file so that type-checking works correctly. Add a single declaration to usb.h and remove the others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-05-13bootstd: Work around missing partition 1Simon Glass1-1/+8
If there is no partition numbered 1, we decide that there are no partitions at all. That may not be correct, since at least one Debian installed has just a single partition numbered 2. Continue searching up to partition 3, just in case. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-05-13doc: renesas: add Renesas board docsRalph Siemsen4-0/+132
As a starting point, list all currently supported Renesas boards. For the RZ/N1 board, add details about booting and flashing. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13tools: spkgimage: add Renesas SPKG formatRalph Siemsen7-0/+497
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG image from QSPI, NAND or USB DFU. Support this format in mkimage tool. SPKGs can optionally be signed, however creation of signed SPKG is not currently supported. Example of how to use it: tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \ -T spkgimage -a 0x20040000 -e 0x20040000 \ -d u-boot.bin u-boot.bin.spkg The config file (spkgimage.cfg in this example) contains additional parameters such as NAND ECC settings. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13board: schneider: add RZN1 board supportRalph Siemsen14-0/+1917
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: rmobile: Add support for Renesas RZ/N1 SoCRalph Siemsen3-2/+47
The RZ/N1 is a family of SoC devices from Renesas, featuring: * ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3 * Integrated SRAM up to 6MB * Integrated gigabit ethernet switch * Optional DDR2/3 controller * I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD Add basic support for this family, modeled on the existing RZA1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: dts: add devicetree for Renesas RZ/N1 SoCRalph Siemsen2-0/+626
This is taken directly from Linux kernel 6.3 (commit 457391b0380335d5e9a5babdec90ac53928b23b4) Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ram: cadence: add driver for Cadence EDACRalph Siemsen6-0/+605
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13pinctrl: renesas: add R906G032 driverRalph Siemsen5-0/+529
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC. This is quite rudimentary right now, and only supports applying a default pin configuration as specified by the device tree. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13clk: renesas: add R906G032 driverRalph Siemsen3-0/+1110
Clock driver for the Renesas RZ/N1 SoC family. This is based on Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"), with the following additional patch series applied: https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siemsen@linaro.org/ Notable difference: this version avoids allocating a 'struct clk' for each clock source, as this is problematic before relocation. Instead, it uses the same approach as existing Renesas R-Car Gen2/3 clock drivers, using a temporary structure filled on-the-fly. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13clk: renesas: prepare for non R-Car clock driversRalph Siemsen2-2/+9
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3. This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing recursion into the drivers/clk/reneasas directory, without bringing in the R-Car support code. The support code contains platform specific access (TMU_BASE) which is not needed on other Renesas devices such as RZ/N1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13ARM: armv7: add non-SPL enable for Cortex SMPENRalph Siemsen1-0/+5
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S") added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For platforms not using SPL boot, add the corresponding non-SPL config, so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-11Merge https://source.denx.de/u-boot/custodians/u-boot-x86WIP/11May2023Tom Rini58-147/+380
- Various fixes for Google chromebooks - Various minor enhancements for coreboot
2023-05-11x86: samus: Adjust TPL start and pre-reloc memory sizeSimon Glass1-2/+2
Move the TPL up a little to make room for the refcode binary blob. Also increase the pre-relocation memory to make space for recent additions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: samus: Don't include audio and SATA in TPLSimon Glass1-2/+2
These are not used in TPL so disable the drivers to save space. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Simplify cpu_jump_to_64bit_uboot()Simon Glass1-27/+5
This copies the cpu_call64() function to memory address and then jumps to it. This seems to work correctly even when called from SPL, which is running from SPI flash. Drop the copy as it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11spl: Commit MTRRs only in board_init_f_r()Simon Glass1-1/+0
We don't need to commit the SPI-flash MTRR change immediately, since it is now done in the board_init_f_r(). Also this causes chromebook_link64 to hang, presumably since we are still running from CAR (Cache-as-RAM) in SPL. Coral handles this OK, perhaps since it is running from a different memory area, but it has no effect on Coral anyway. Drop the extra mtrr_commit() in the SPL implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: spl: Avoid using init_cache_f_r() from SPLSimon Glass1-1/+2
This function is used by U-Boot proper. It does not set up MTRRs when SPL is enabled, but we do want this done when it is called from SPL. In fact it is confusing to use the same function from SPL, since there are quite a few conditions there. All init_cache_f_r() really does is commit the MTRRs and set up the cache. Do this in the SPL's version of this function instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Tidy up address for loading U-Boot from SPLSimon Glass1-10/+3
Use the binman symbols for this, to avoid hard-coding the value. We could use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to obtain the offset and size through the same mechanism. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: sysreset: Set up LPC only after relocationSimon Glass1-2/+7
Probing LPC can cause PCI enumeration to take place, which significantly increases pre-relocation memory usage. Also, LPC is somtimes enabled directly by SPL. Adjust the logic to probe the LPC only after relocation. This allows chromebook_link64 to start up without a much larger CONFIG_SYS_MALLOC_F_LEN value. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: spl: Show debugging for BSSSimon Glass1-0/+2
Show the area of memory cleared for BSS, when debugging is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: mrc: Correct SPL debug messageSimon Glass1-1/+1
SPL printf() does not normally support %#x so just use %x instead. Hex is expected in U-Boot anyway. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Tidy up availability of string functionsSimon Glass2-2/+8
For now, just enable the fast-but-large string functions in 32-boot U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit builds since we only have 32-bit assembly. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2023-05-11x86: Support debug UART in 64-bit modeSimon Glass1-0/+7
The debug UART is already set up in SPL, so there is no need to do anything here. We must provide the (empty) function though. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: samus: Drop EFI_LOADERSimon Glass1-0/+1
This adds a lot of code so that it cannot be built with the binary blobs. It is not used on this board. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: ivybridge: Ensure LPC is available for GPIO baseSimon Glass1-8/+9
The bd82x6x_get_gpio_base() does not work if the LPC is not set up. Probe it early to avoid this problem. In chromebook_link64 this problem shows up as an inability to read the GPIO straps for the memory type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11sf: Rename spi-nor-tiny functionsSimon Glass1-8/+8
The 'tiny' SPI nor functions have the same name as their big brothers, which can be confusing. Use different names so it is clear which version is in the image. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11sf: Guard against zero erasesizeSimon Glass1-1/+2
With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero error. Check for this and return a proper error instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11binman: Support writing symbols for ucode etypesSimon Glass3-4/+4
Allow symbol writing in these cases so that U-Boot can find the position and size of U-Boot at runtime. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11dm: Emit the arch_cpu_init_dm() even only before relocationSimon Glass18-21/+21
The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11coreboot: Enable ms commandSimon Glass1-0/+1
This is useful when looking for tables in memory. Enable it for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: nvme: coreboot: Enable NVMeSimon Glass1-0/+1
Enable support for NVMe storage devices. Update the driver to enable the bus master bit, since coreboot does not do that automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11nvme: Enable PCI bus masteringSimon Glass1-0/+5
U-Boot sets up devices ready for use, but coreboot does not. Enable this so that NVMe works OK from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Show unimplemented sysinfo tagsSimon Glass3-0/+16
Sometimes coreboot adds new tags that U-Boot does not know about. These are silently ignored, but it is useful to at least know what we are missing. Add a way to collect this information. For Brya it shows: Unimpl. 38 41 37 34 42 40 These are: LB_TAG_PLATFORM_BLOB_VERSION LB_TAG_ACPI_CNVS LB_TAG_FMAP LB_TAG_VBOOT_WORKBUF LB_TAG_TYPE_C_INFO LB_TAG_BOARD_CONFIG Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Log function names and line numbersSimon Glass1-0/+4
Turn these options on to make it easier to debug things. Also enable dhrystone so we can get some measure of performance. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Scan PCI after relocationSimon Glass1-0/+1
Enable this so that PCI devices can be used correctly without needing to do a manual scan. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Document how to enable the debug UARTSimon Glass1-0/+29
This is not obvious so add a little note about how it works. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: coreboot: Use a memory-mapped UARTSimon Glass2-2/+0
This is much more common on modern hardware, so default to using it. This does not affect the normal UART, but does allow the debug UART to work, since it uses serial_out_shift(), etc. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11pci: coreboot: Don't read regions when bootingSimon Glass1-0/+4
When U-Boot is the second-stage bootloader, PCI is already set up. We cannot read the regions from the device tree. There is no point anyway, since PCI devices have already been allocated according to the regions and it is not safe for U-Boot to make any changes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Fixes: f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()") Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11x86: Allow locating the UART from ACPI tablesSimon Glass2-8/+116
When coreboot does not pass a UART in its sysinfo struct, there is no easy way to find it out. Since coreboot does not actually init the serial device when serial is disabled, it is not possible to make it add this information to the sysinfo table. Add a way to obtain this information from the DBG2 ACPI table, which is normally set up by coreboot. For now this only supports a memory-mapped 16550-style UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-08-05 16:32:01 +0000