Age | Commit message (Collapse) | Author | Files | Lines |
|
https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.04-rc3
zynqmp:
- Cover missing _SE chip variants to fix fpga programming
versal:
- Enable LTO for mini configurations
versal-net:
- Enable LTO for mini configurations
- Fix GIC address to aligned with real silicon
xilinx:
- DTs cleanup and fixups
- Enable HTTP boot
- Add missing spl header to zynqmp.c
|
|
Previous addresses where used in past in emulation environment but never
gets to silicon that's why use correct addresses.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5d3d0e1afb1f673ffeb4a1c5d7f040475c806a30.1707220293.git.michal.simek@amd.com
|
|
Signed-off-by: Tom Rini <trini@konsulko.com>
|
|
- Add the button command patch, update MAINTAINERS entry for a platform,
fix a problem with the hash command, fix a problem on K3 platforms and
revert a change on verdin-am62.
|
|
This reverts commit d2099587d661c6ca2309256c0e04c06e26c8d34c.
According to TI changing the VDD_CORE while the SoC is running is not
allowed, the voltage must be set before the AM62 device reset is
released, revert this change therefore.
The correct solution would be to program the PMIC during manufactoring
according to the speed grade of the SoC.
Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1318338/am623-booting-from-mmc-failed-after-lowering-vdd_core-to-0-75v/5036508#5036508
Fixes: d2099587d661 ("board: verdin-am62: set cpu core voltage depending on speed grade")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
|
|
With the relatively new button API in U-Boot, it's now much easier to
model the common usecase of mapping arbitrary actions to different
buttons during boot - for example entering fastboot mode, setting some
additional kernel cmdline arguments, or booting with a custom recovery
ramdisk, to name a few.
Historically, this functionality has been implemented in board code,
making it fixed for a given U-Boot binary and requiring the code be
duplicated and modified for every board.
Implement a generic abstraction to run an arbitrary command during boot
when a specific button is pressed. The button -> command mapping is
configured via environment variables with the following format:
button_cmd_N_name=<button label>
button_cmd_N=<command to run>
Where N is the mapping number starting from 0. For example:
button_cmd_0_name=vol_down
button_cmd_0=fastboot usb 0
This will cause the device to enter fastboot mode if volume down is held
during boot.
After we enter the cli loop the button commands are no longer valid,
this allows the buttons to additionally be used for navigating a boot
menu.
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Tegra30
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
|
|
Add correct check for parameter count.
This fixes this issue when `hash` cmd is invoked without params:
=> hash
data abort
pc : [<bf739204>] lr : [<ba6effa8>]
reloc pc : [<60019204>] lr : [<5afcffa8>]
sp : ba6dd9c8 ip : bf7391f0 fp : bf74ec14
r10: 00000001 r9 : ba6dfea0 r8 : bf7ea030
r7 : 00000000 r6 : ba6effa8 r5 : 00000000 r4 : ffffffff
r3 : bf7c257c r2 : 00000001 r1 : 00000000 r0 : bf7e6e34
Flags: nZCv IRQs off FIQs on Mode SVC_32
Code: e5934004 e1a0e003 e59f3050 e2444001 (e5f4c001)
Resetting CPU ...
resetting ...
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
|
|
AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt.
This causes a lockup at A53 SPL when accessing NAND controller
or ELM registers.
A good option would be to softrest GPMC block at probe
but this cannot be done for AM64 as SOFTRESET bit is marked
as reserved in SYSCONFIG register.
Fix the issue by disabling all IRQs at probe.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
|
|
Add myself as co-maintainer for Poplar board, as I'm currently
working on it (re-testing releases, addressing issues etc).
CC: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
CC: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com>
|
|
https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request doc-2024-04-rc2
Documentation:
* Fix and extend utf8_to_utf32_stream() documentation
* Fix rendering of OpenSBI logo in VisionFive 2 description
* Document imxrt1170-evk board
* codingstyle.rst: Clarify include section
UEFI:
* simplify error message in efi_disk_create_raw()
|
|
Some platforms (such as the Lichee Pi 4A) have their dwmac device
addressable only in high memory space. Storing the node's base address
on 32 bits is not possible in such case.
Use platform's physical address type to store the base address.
Signed-off-by: Nils Le Roux <gilbsgilbert@gmail.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
Rework the section about includes slightly. We should not be using
common.h anywhere, so remove that from examples and ask people to send
patches removing it when found. Doing this also means we need to reword
other parts of this section. Be clearer about using alphabetical
ordering.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
|
|
Clarify usage of buffer argument.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
|
|
The error message
Adding disk for usb_mass_storage.lun0 failed (err=-9223372036854775788/0x8000000000000014)
provides a decimal and a hexadecimal notation of the EFI status code
EFI_ALREADY_STARTED which is defined as (EFI_ERROR_MASK | 20).
The decimal output does not convey the value 20 clearly.
With the patch we write
Adding block device usb_mass_storage.lun0 failed, r = 20
similar to other EFI error messages.
Fixes: 952018117ab4 ("dm: sandbox: Switch over to using the new host uclass")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
|
|
The rendering of the OpenSBI logo should look like the screen output.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
|
|
Add documentation for imxrt1170-evk.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Add index page entry, adjust formatting.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19583
- Fix the i.MX8MP SPI compatible string.
- Let the SPL clock code do the configuration on Data Modul i.MX8M Plus
eDM SBC.
- Enable secure boot on the imx93_var_som board.
|
|
Add missing prototype to fix the below sparse warning
warning: no previous prototype for 'spl_spi_get_uboot_offs'
[-Wmissing-prototypes]
Fixes: 2c8a09219cdb ("arm64: zynqmp: Add multiboot support for SPL/SPI offset calculation")
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240207083328.1673752-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
|
|
When SOM dt is combined with kd240 overlay DPSUB is enabled but kd240 has
no DP wired that's why change disable it via status property.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f6de217b3350c9d59032ef54800882e48f240398.1706791116.git.michal.simek@amd.com
|
|
usb0 is already updated but forget to also update usb1.
Fixes: 4ff083f09bc2 ("arm64: zynqmp: Do not expose usbhub nodes")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/862ca748670f18f25d88aa5b43c37e3dd6aa35eb.1706791116.git.michal.simek@amd.com
|
|
Node name has to be renamed to be aligned with dt-schema and also
xlnx,zynqmp-nvmem-fw switched to fixed-layout.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/32899b20c1e282aab16c32074b1c9a3f45f6dac8.1706791116.git.michal.simek@amd.com
|
|
There is no dt schema associated with it. Also Linux driver have been
removed in Xilinx Linux tree and never gets to upstream that's why remove
description for it.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6685ee980d9b475f95eef6b2a74795adc4ac4619.1706791116.git.michal.simek@amd.com
|
|
fpga-full is not aligned with the latest dt-schema. Generic name
fpga-region should be used.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/78e6e3f287f79917eb92c6c74accbaf955526aad.1706791116.git.michal.simek@amd.com
|
|
kr260 revA/revA01 is using discrete oscilator for DP (27MHz) and si5332 for
other clocks but clocks are different compare to kv260 that's why fix it to
aligned with the latest schematics.
On the other handle kr260 revB/revA03 also contains 74.25 MHz discrete
clock chip for SLVC-EC output which is not defined.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e87ae94979c6efc909740bb1a569505042e4f876.1706626255.git.michal.simek@amd.com
|
|
Describe 25Mhz fixed oscilator which is providing clock for PL based
ethernet IPs. Physicially it is one chip but it is described as 2 fixed
clock to be aligned with other SOM versions which were using integrated
clock generators where clocks could be adjusted via i2c (si5332 chips).
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c430aeacaa76d9f61ed3f874f721a33049f45eb9.1706514396.git.michal.simek@amd.com
|
|
Board description describes the hard part of chip (PS) but programmable
logic (PL) part is not described in this file. But clocks on the board are
not only connected to PS but also wired to PL. And because two revisions
are available where revA is using one si5332 and revB multiple clock chips
using the same clock labels helping with keeping only one device tree
overlay which targets PL. That's why synchronize clock labels and use
labels from revB which are more generic.
Unfortunately if there is driver for si5332 chip split could happen again
but it is still worth to do it now and solve this issue when occurs.
Reported-by: Sagar Karmarkar <sagar.karmarkar@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/abac6069e6029ed4076ec7b9d6b33604b6072aa3.1706253871.git.michal.simek@amd.com
|
|
Without 'silabs,skip-recall' property, the driver on System Controller
re-calibrates the output clock frequency at probe() time based on the NVRAM
setting. This re-calibration causes a glitch on the output clock. At
power-on, Versal is also booting and expecting a glitch-free clock for
its correct operation. System Controller should skip the re-calibration
step to prevent any clock instability for Versal.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bbb2322c94503f0e6b369c60312b7546500fad95.1706170068.git.michal.simek@amd.com
|
|
Enable EFI_HTTP_BOOT to be able to booting OS via http.
In case of that dhcp server is not providing dns server IP set it up via
setenv dnsip <ip addr>.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b78a7d8b0100c724f657c0997b273e073cf31a14.1706093917.git.michal.simek@amd.com
|
|
Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.
Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240126081139.3210211-1-venkatesh.abbarapu@amd.com
|
|
Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.
Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240126080900.3209323-1-venkatesh.abbarapu@amd.com
|
|
ID code is added for zu67dr_SE, zu11eg_SE, zu19eg_SE and zu47dr_SE
variants. SE is the select edition of restricted devices with the
capabilities.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240123045715.893652-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
|
|
https://source.denx.de/u-boot/custodians/u-boot-sh
|
|
Enable AHAB support in the imx93_var_som configuration.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
|
|
Probing the MU is needed to prevent this error in the SPL:
ele dev is not initialized
Authenticate container hdr failed, return -19, resp 0x0
IND = INVALID
ele dev is not initialized
Error: release container failed, resp 0x0!
IND = INVALID
SPL: failed to boot from all boot devices
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
|
|
Put imx9_probe_mu declaration in a new mu.h header file.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
|
|
Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead
of the fsl,imx51-ecspi compatible string. Add the new compatible string
to fix ECSPI operation on i.MX8MP.
For details, see Linux:
48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk")
8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul")
Fixes: 451799a6ceac ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
|
|
The SPL clock code does configure the ECSPI clock frequency, which has
to match the mxc-spi driver configuration for successful SPI NOR boot.
Drop the assigned-clock from DT ecspi1 node on this board to let the
SPL clock code do the configuration and keep it aligned with the driver
expectation.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
|
|
Add board code for the Renesas R8A779H0 V4M Gray Hawk board.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
Initial support for the Renesas Gray Hawk CPU and BreakOut boards.
The arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi is extended version of:
https://lore.kernel.org/linux-renesas-soc/b657402113267acd57aece0b4c681b707e704455.1706194617.git.geert+renesas@glider.be/
The version currenty submitted upstream lacks functionality which is
present in this series. Once the upstream support implements that
missing functionality, these DTs will be updated to match.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
Add Renesas R8A779H0 V4M DT extras for U-Boot.
Until the RPC node becomes part of main DT, keep it here as
an extension so that board code can enable and use the RPC
to access SPI NOR.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC.
The current version is imported and modified from:
https://lore.kernel.org/linux-renesas-soc/4107bc3d7c31932da29e671ddf4b1564ba38a84c.1706194617.git.geert+renesas@glider.be/
The modifications contain nodes from previous version
which are useful in U-Boot and not part of the Linux
kernel DT yet. The following nodes were added:
- pfc
- gpio0..gpio7
- i2c0..i2c3
- avb0..avb2
- mmc0
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
Support RPC SPI on R8A779H0 V4M SoC.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
|
|
Add Kconfig entry and PRR ID to support R8A779H0 V4M SoC.
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
Add pinctrl tables for R8A779H0 V4M SoC.
The current version of these PFC tables is imported and squashed from:
https://lore.kernel.org/linux-renesas-soc/cover.1706264667.git.geert+renesas@glider.be/
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.
The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
|
|
Add clock tables for R8A779H0 V4M SoC.
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/
The current version still contains PLL7 extras from the
previous version to provide ethernet support in U-Boot.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
Add power domain indices for R-Car V4M (R8A779H0).
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c5cbef71178cada761e9da7bcbb6f21334f93ef8.1706194617.git.geert+renesas@glider.be/
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V4M (R8A779H0) SoC.
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be/
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
|
|
https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20240209
- sparse error checking fix when using raw chunks
- 2 new additions (AVB, AB) of myself to the MAINTAINERS file
|
|
The return value of write_sparse_chunk_raw is unsigned, so the existing
check has no effect. Use IS_ERR_VALUE to detect error instead, which is
what write_sparse_chunk_raw does itself.
Fixes: 62649165cb0 ("lib: sparse: Make CHUNK_TYPE_RAW buffer aligned")
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/u-boot/1b323ec3-59b0-490b-a2f0-fd961dafcf49@moroto.mountain/
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20240201181851.221701-1-sean.anderson@seco.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
|