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2024-03-13Merge tag 'efi-2024-04-rc5' of ↵WIP/13Mar2024Tom Rini8-19/+22
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request efi-2024-04-rc5 Documentation: * fix Python string escapes * develop: commands: Fix function prototype * fix incorrect path Documentation * fix mistyped "env flags" command * board: phytec: phycore-am62x: Update artifact names UEFI: * Invoke ft_board_setup() before efi_carve_out_dt_rsv()
2024-03-13Merge tag 'mips-fixes-for-v2024.04' of ↵Tom Rini3-3/+20
https://source.denx.de/u-boot/custodians/u-boot-mips - mips: implement __udivdi3 to fix building of SquashFS - mips: fix bug in cache init on MIPS32r2 or later
2024-03-13mips: fix change_k0_cca()Daniel Schwierzeck1-2/+2
The intention of change_k0_cca() is to read the C0.Config register into register $t0, update $t0 with the new cache coherency mode passed in $a0 and write back $t0 to C0.Config. With MIPS32 R2 or later instruction sets, this can be achieved with a single instruction with INS. The source and destination register of the INS instruction is passed as first parameter. In case of change_k0_cca() it is register $t0. But for writing back the updated value to C0.Config, the incorrect $a0 register is used. This is only correct in the MIPS32 R1 code path. Fix the `mtc0` instruction to write back the value of the $t0 register. Fix the MIPS32 R1 code path to also store the updated value in $t0. Reported by user ddqxy138 on Github. https://github.com/u-boot/u-boot/commit/b838586086af3278bcaead3720c7a18813cf4619 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2024-03-13mips: implement __udivdi3Linus Walleij2-1/+18
Squashfs wasn't compiling because the lldiv() directives turn into __udivdi3 and we are using private libgcc. After this squashfs compiles for MIPS. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Bartel Eerdekens <barteleerdekens@gmail.com>
2024-03-13doc: fix incorrect path DocumentationHeinrich Schuchardt1-4/+4
When copying the build system for Linux we missed to replace some instances of 'Documentation' by 'doc'. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-13doc/sphinx: fix Python string escapesBenjamin Gray4-7/+7
Python 3.6 introduced a DeprecationWarning for invalid escape sequences. This is upgraded to a SyntaxWarning in Python 3.12, and will eventually be a syntax error. Fix these now to get ahead of it before it's an error. Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Message-ID: <20230912060801.95533-3-bgray@linux.ibm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Adapted for U-Boot Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-13doc: board: phytec: phycore-am62x: Update artifact namesWadim Egorov1-3/+3
Use proper binary artifact names for HSFS devices. Do not use the *_unsigned binaries. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Dhruva Gole <d-gole@ti.com>
2024-03-13doc: develop: commands: Fix function prototypeAlexander Dahl1-1/+1
When using the previous prototype you got a compiler warning like this: warning: initialization of 'int (*)(struct cmd_tbl *, int, int, char * const*)' from incompatible pointer type 'int (*)(struct cmd_tbl *, int, int, const char **)' [-Wincompatible-pointer-types] Fixes: 3d9640f55cb2 ("doc: expand README.commands") Signed-off-by: Alexander Dahl <ada@thorsis.com>
2024-03-13efi_loader: Don't carve out memory reservations too earlyMark Kettenis1-4/+7
Moving the efi_carve_out_dt_rsv() call in commit 1be415b21b2d ("efi_loader: create memory reservations in ACPI case") broke boards that create additional memory reservations in ft_board_setup() since it is now called before those additional memory reservations are made. This is the case for the rk3588 boards and breaks booting OpenBSD on those boards. Move the call back to its original location and add a call in the code path used for ACPI. Fixes: 1be415b21b2d ("efi_loader: create memory reservations in ACPI case") Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-13doc: fix mistyped "env flags" commandThomas Weißschuh1-1/+1
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-03-12Merge https://source.denx.de/u-boot/custodians/u-boot-riscvWIP/12Mar2024Tom Rini9-25/+29
* riscv: lib: improve extension detection * riscv: sbi: fix display format and global variable storage * sifive: fu740: reduce DDR speed * board: starfive vf2: switch to standard boot and fix DTS
2024-03-12board: starfive: maintainer: Add visionfive2 PCIe driverMinda Chen1-0/+1
Add PCIe driver file to visionfive2 board MAINTAINERS list. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12board: starfive: Update maintainer of VisionFive v2 boardMinda Chen1-1/+1
Update the maintainer of Starfive VisionFive v2 board. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12cmd: sbi: formatting PolarFire Hart Software Services versionHeinrich Schuchardt1-0/+1
The 'PolarFire Hart Software Services' SBI implementation returns the version of the incorporated OpenSBI. Format the number accordingly. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-12cmd: sbi: Correctly display unknown implementation IDsHeinrich Schuchardt1-1/+1
For an unknown implementation ID an output like SBI 1.0Unknown implementation ID 16777216 Extensions: sbi_set_timer ... was shown. The number 16777216 is not the implementation ID. * Show the correct number * Use a hexadecimal output format * Add a missing line feed Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
2024-03-12riscv: dts: jh7110: Enable PLL node in SPLBo Gan1-0/+4
Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on OSC clock (24Mhz). As a result, all peripherals have to run at a much lower frequency, and loading from sdcard/emmc is slow. Thus, enabling PLL node in dts to fix this. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12riscv: cpu: improve multi-letter extension detection in supports_extension()Conor Dooley1-6/+16
The first multi-letter extension after the single-letter extensions does not have to be preceded by an underscore, which could cause the parser to mistakenly find a single-letter extension after the start of the multi-letter portion of the string. Three letters precede multi-letter extensions (s, x & z), none of which are valid single-letter extensions. The dt-binding also allows multi-letter extensions starting with h, but no such extension have been frozen or ratified, and the unprivileged spec no longer uses "h" as a prefix for multi-letter hypervisor extensions, having moved to "sh" instead. For that reason, modify the parser to stop at s, x & z to prevent this overrun, ignoring h. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-12riscv: dts: jh7110: fix indentationLeon M. Busch-George1-1/+1
Signed-off-by: Leon M. Busch-George <leon@georgemail.eu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12serial: move sbi_dbcn_available to .data sectionHeinrich Schuchardt1-1/+1
U-Boot SPL loads the device-tree directly behind main U-Boot overlapping the .bss section. reserve_fdt() is called in board_init_f() to relocate the device-tree to a safe location. Debug UARTs are enabled before board_init_f(). With sbi_dbcn_available in the .bss section the device-tree is corrupted when _debug_uart_init() is called in the SBI serial driver. Move the variable to the .data section. Link: https://bugs.launchpad.net/ubuntu/+source/u-boot/+bug/2054091 Fixes: dfe08374943c ("risc-v: implement DBCN based debug console") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-12riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/sThomas Perrot1-1/+1
It appears that there is some timing marginality either in the board layout or the SoC that results in occasional data corruption on some boards. We observed this issue on some of the new HiFive Unmatched RevB boards during volume production as well as some of the original HiFive Unmatched boards from 2021 in our possession. This means that there are other boards out there that might have the issue too. We have done some limited testing with DDR4 at 1600MT/s and faulty boards (failing at 1866MT/s) passed. We plan further testing after we procure a temperature chamber. Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-12starfive: visionfive2: switch to standard bootNam Cao2-14/+2
Distro boot scripts are deprecated. Use standard boot instead. Signed-off-by: Nam Cao <namcao@linutronix.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-03-11Prepare v2024.04-rc4v2024.04-rc4Tom Rini2-2/+2
Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-11Merge tag 'u-boot-imx-master-20240311' of ↵WIP/11Mar2024Tom Rini9-15/+345
https://gitlab.denx.de/u-boot/custodians/u-boot-imx - Use TF-A on imx8mp_beacon to fix boot regression. - Use latest 6.8 dts for imx8mp_beacon. - Fix the RAM initialization for phycore_imx8mp PCL-070 rev 1. - Describe the 0087 i.mx8m mini product variant in tdx-cfg-block.
2024-03-11configs: Resync with savedefconfigTom Rini6-14/+14
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-11arm: dts: imx8mp-beacon-kit: Resync DTS with Linux 6.8Adam Ford3-6/+321
The device tree has evolved over time, so re-sync. This also partial reverts one change on the PCIe, because U-Boot doesn't have a proper driver. However, since the clock is configured to generate a 100MHz reference clock by default, a proper driver isn't really necessary. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2024-03-11toradex: tdx-cfg-block: add 0087 i.mx8m mini product variantJoao Paulo Goncalves2-0/+2
Add new product id 0087 Verdin iMX8M Mini Quad 2GB IT. Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
2024-03-11configs: imx8mp_beacon: Fall back to using TF-AAdam Ford1-7/+0
When the board was originally added, it enabled some features which allowed it to bypass Trusted Firmware, but as the feature set of Linux grew and more features became available, the U-Boot config options which bypassed TF-A caused issues, so it needs to return to the standard operating mode of using TF-A or the system no longer boots. Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2024-03-11board: phycore_imx8mp: Use 2GHz RAM timings for PCL-070 from pcb_rev 1Benjamin Hahn1-2/+4
We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from pcb rev 3 or newer. Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-03-11board: phytec: common: phytec_som_detection: Add phytec_get_som_typeBenjamin Hahn2-0/+18
Add a function that gets the som_type from the EEPROM. Add an enum for the som_type. Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-03-09Merge https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini1-1/+1
- Singular quirk DT property rename.
2024-03-09net: phy: Use PHY MDIO address from DT if availableWIP/09Mar2024Marek Vasut1-0/+3
In case the PHY is fully described in DT, use PHY MDIO address from DT directly instead of always using auto-detection. This also fixes the behavior of 'mdio list' in such DT setup, which now prints the PHY connected to the MAC correctly. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/05Mar2024Tom Rini9-1/+202
- net: mv88e6xxx: fix missing SMI address initialization (Marek) - mvebu: turris_omnia: Enable networking via ethernet switch (Marek) - mvebu: helios-4: add config fragment for spi booting et al (Josua) - rng: Add Turris Mox rTWM RNG driver (Max)
2024-03-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini10-20/+100
One fix makes the reboot more robust on some older board, another one stabilises the initial clock setup on the A10/A20. Two patches make sure our DRAM init does not actually change the content of the DRAM array, which allows to use DRAM for Linux' pstore functionality. We get SPI support for U-Boot proper for one more SoC, that patch was lingering around for a while, and should not affect other SoCs, so I am merging this now. As an added bonus, we get the defconfig file for a new board, the DT was already synced from the kernel tree. The CI looked happy with changes, and I tested them on five different boards with different SoCs.
2024-03-05rng: Add Turris Mox rTWM RNG driverMax Resch3-0/+132
A RNG driver for Armada 3720 boards running the Turris Mox rWTM firmware from CZ.NIC in the secure processor. Signed-off-by: Max Resch <resch.max@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2024-03-05board: helios-4: add config fragment for spi bootingJosua Mayer1-0/+4
Add a config fragment with required differences for booting from spi flash instead of sd-card (default). Settings for environment location are based on vendor u-boot: https://github.com/kobol-io/u-boot/blob/helios4/include/configs/helios4.h#L59 The fragment can be applied on top of helios4_defconfig by make: make helios4_defconfig spiboot.config Signed-off-by: Josua Mayer <josua@solid-run.com>
2024-03-05arm: mvebu: helios4_defconfig: enable setexpr commandJosua Mayer1-1/+0
Update the helios4 defconfig to enable the 'setexpr' command, which is a default and useful for various complex boot-scripts. Signed-off-by: Josua Mayer <josua@solid-run.com>
2024-03-05arm: dts: armada-38x-solidrun-microsom: configure i2c0 busJosua Mayer1-0/+5
SolidRun Armada-388 SoM has an i2c bus supporting on-som eeprom, and peripherals on a carrier. armada-38x.dtsi disables this bus by default, it should be enabled by som or carrier dts. Linux has moved i2c0 from helios-4 board dts to som dtsi, including status, pinctrl and clock speed. Copy these settings from mainline. This fixes accessing i2c bus from u-boot commandline. Signed-off-by: Josua Mayer <josua@solid-run.com>
2024-03-05arm: mvebu: turris_omnia: Enable networking via ethernet switchMarek Mojík2-0/+53
The Turris Omnia contains the Marvell 88E6176 ethernet switch. Add config options and device tree to enable the support. Signed-off-by: Marek Mojík <marek.mojik@nic.cz> Signed-off-by: Marek Behún <kabel@kernel.org>
2024-03-05net: mv88e6xxx: fix missing SMI address initializationMarek Mojík1-0/+8
The mv88e6xxx driver does not currently initialize the smi_addr field, but instead keeps the default zero value. This leads to driver being unusable on devices where the switch is not on address zero of the mdio bus. Fix this problem by reading the SMI address from device tree. Signed-off-by: Marek Mojík <marek.mojik@nic.cz> Reviewed-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2024-03-05sunxi: restore modified memoryAndrey Skvortsov1-2/+14
Current sunxi DRAM initialisation code does several test accesses to the DRAM array to detect aliasing effects and so determine the correct row/column configuration. This changes the DRAM content, which breaks use cases like soft reset and Linux's ramoops mechanism. Fix this problem by saving and restoring the content of the DRAM cells that is used for the test writes. Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-03-05sunxi: reorganize mctl_mem_matches_* functionsAndrey Skvortsov3-19/+15
mctl_mem_matches and mctl_mem_matches_base identical functions. To avoid code duplication move them to dram_helpers and make mctl_mem_matches use generic mctl_mem_matches_base. Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-03-05usb: xhci-dwc3: Fix support for dis_enblslpm_quirkJonas Karlman1-1/+1
No device tree in U-Boot or linux use the wrong spelling used in code. Use correct property name as defined in dwc3 bindings. Fixes: 062790f46131 ("usb: xhci-dwc3: Add USB2 PHY configuration") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Marek Vasut <marex@denx.de>
2024-03-04Merge tag 'u-boot-imx-master-20240304' of ↵WIP/04Mar2024Tom Rini13-25/+59
https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19817 - Fix i.MX93 OP-TEE support. - Use the container image for i.MX93 revision A1. - Fix display regression on opos6uldev.
2024-03-04video: mxsfb: add back imx6ul/imx6ull supportSébastien Szymanski1-0/+1
Because of commit bf947d2a4b15 ("imx6ul: synchronise device tree with linux"), the compatible property of lcdif in imx6ul.dtsi went from compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; to compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; without updating the mxsfb driver to match that change. Add "fsl,imx6sx-lcdif" as a compatible id to fix that. Fixes: bf947d2a4b15 ("imx6ul: synchronise device tree with linux") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2024-03-04opos6uldev: make the LCD work againSébastien Szymanski3-10/+22
Commit 5d7a95f49999 ("imx6ul/imx6ull: synchronise device trees with linux") removed the display timings from the board device tree whereas they are still needed by the mxsfb driver. Add the timings back (the correct ones) in the imx6ul-opos6uldev-u-boot.dtsi file and remove them from the opos6uldev.env file. Update the opos6uldev_defconfig file so that the LCD turns on at boot. Fixes: 5d7a95f49999 ("imx6ul/imx6ull: synchronise device trees with linux") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2024-03-04imx9: Update to mx93 A1 chip revision.Mathieu Othacehe4-13/+13
Use the latest, mx93a1-ahab-container.img that is compatible with the i.MX93 A1 revision. Using mx93a1-ahab-container.img on an A0 chip and conversely causes a boot failure without any traces on the UART. Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-03-04tools: imx9_image: Reword warning message.Mathieu Othacehe1-1/+1
If the optional `tee.bin` OP-TEE binary is missing, the image will still be functional. Adapt the warning message accordingly. Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-03-04imx9: Fix OP-TEE supportMathieu Othacehe4-1/+22
This fixes OP-TEE support by: - Adding tee.bin to container.cfg - Starting ELE RNG in SPL Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
2024-03-03sunxi: H616: Add OrangePi Zero 2W board supportAndre Przywara3-0/+36
The OrangePi Zero 2W is a tiny development board featuring the Allwinner H618 SoC, shipping with up to 4GB of LPDDR4 DRAM, a mini-HDMI connector, two USB Type-C sockets and a 16MB SPI NOR flash. There is an FPC connector to connect an expansion board, which sports two more USB Type-A sockets and a 100MBit Ethernet port. Support for the expansion board is not in the DT yet, probably a DT overlay would cover this in the future. Add a defconfig file selecting the right drivers and DRAM options. Since the .dts file was synced from the Linux kernel repo already, we just need to add one line to the Makefile to actually build the .dtb. The DRAM parameters were derived from the values found in the BSP DRAM drivers on the SPI NOR flash. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2024-03-03sunxi: sun4i: add missing sdelay() to clock_init_safe()Ludwig Kormann1-0/+2
This delay is required after switching the clock source. See “A20 Reference manual v1.4” Page 50 / section “1.5.4.16. CPU/AHB/APB0 CLOCK RATIO”: “If the clock source is changed, at most to wait for 8 present running clock cycles.” This is already implemented in clock_set_pll1(), but was still missing in clock_init_safe(). Signed-off-by: Ludwig Kormann <ludwig.kormann@ict42.de> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit v1.1 at 2024-08-05 18:36:09 +0000