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2019-12-27rockchip: mkimage: support packing optional second level boot-loaderJeffy Chen6-115/+231
Support packing optional second level boot-loader: $ ./tools/mkimage -n rk3399 -T rksd -d \ rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v Adding Image rk3399_ddr_800MHz_v1.24.bin Size 116492(pad to 116736) Adding Image rk3399_miniloader_v1.19.bin Size 88060(pad to 88064) Image Type: Rockchip RK33 (SD/MMC) boot image Init Data Size: 116736 bytes Boot Data Size: 88064 bytes Mainly parse init file and boot file from datafile option, copy them to the image with 2KB alignment. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27doc: rockchip: Fix reference the wrong defconfig name of ROC-CC-RK3308Andy Yan1-2/+2
The defconfig file for ROC-CC-RK3308 is roc-cc-rk3308_defconfig. Fixes: 7f08bfb74f04 ("doc: rockchip: Add documentation for rk3308 based boards") Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: rk3308: allow loading larger kernel ImageAndy Yan1-1/+1
When compile the curren mainline linux kernel(Linux 5.5-rc3) with defconfig, the final Image is 29M, it's much larger than Linux 5.4. On the current u-boot side on rk3308, the gap between kernel and fdt is 25M, the fdt will overwrite kernel Image, so move ftd to a higher memory to give 34M gab for them. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: add description for TPL_ROCKCHIP_COMMON_BOARDThomas Hebb1-1/+1
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but this one doesn't for some reason. Add a description to make the menu easier to read. Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: px30-firefly add standalone dtsKever Yang4-3/+619
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot proper will use the dts setting to do the IOMUX init, and a separate dts is needed for px30-firefly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: firefly-px30: Fix the MACRO for CONFIG_DEBUG_UART2_CHANNELKever Yang1-1/+1
The Macro has update without update the defconfig, update the defconfig to make Mcaro correct. Fixes: ec4fafdf1f ("rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to...") Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: make_fit_atf: explicitly use python3Jack Mitchell1-1/+1
On a distribution with no python2 installed and no python->python3 symlink the script will fail to execute. Specify python3 explicitly as it's already a requirement to build u-boot. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: rk3288-evb: update config to support OPTEEKever Yang1-0/+5
Upstream kernel and rockchip kernel has default enable PSCI which needs OPTEE in trust word, enable OPTEE support for evb by default and SPL_FIT option to pack OPTEE with U-Boot proper. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: rk3288-evb: update CONFIG_NR_DRAM_BANKS to 2Kever Yang1-1/+1
The OPTEE will use the ram start at 0x8400000 which make the DRAM be two banks. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config with rk3399Kever Yang1-2/+2
Update the SPL_STACK_R_MALLOC_SIMPLE_LEN which also including space for STACK and the size may not enough when loding FIT image in SPL. If the size is not enough, you can see log like this when loding FIT: U-Boot TPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53 +0800) Trying to boot from MMC2 And if enable the DEBUG for everyting in SPL, the log will hang at dwmmc sending CMD16 for 'uboot' loadables binary because this step need a large stack cost(about 0x2d00). External data: dst=8400000, offset=72638, size=b3580 Image OS is Trusted Execution Environment board_fit_config_name_match: rk3288-evb Selecting config 'rk3288-evb'loadables: 'uboot' blk_find_device: if_type=6, devnum=1: dwmmc@ff0c0000.blk, 6, 0 blk_find_device: if_type=6, devnum=1: dwmmc@ff0f0000.blk, 6, 1 Sending CMD16 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: fit_spl_optee: get text and optee base from buildKever Yang1-3/+9
Instead of hardcode the base address, we can get them from the build output, eg. get the SYS_TEXT_BASE from .config and get optee base from DRAM_BASE. We can use this script for SoCs with DRAM base not from 0x60000000(rk3229 and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-22Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini4-16/+19
- dwc3 and cdns3 bug fixes
2019-12-22Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-netTom Rini3-3/+21
- Fix phy_connect() call in two drivers - fw_setenv bugfix
2019-12-21usb: dwc3: Fix UTMI/UTMIW phy interface initializationJagan Teki2-16/+16
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-21MAINTAINERS: assign usb.c and and usb_kbd.cHeinrich Schuchardt1-0/+2
Marek is already maintaining USB. Assign files common/usb.c and common/usb_kbd.c to him. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-21usb: cdns3: ep0: Fix build warnings related to cache opsVignesh Raghavendra1-0/+1
Since, commit 62f9b6544728 ("common: Move older CPU functions to their own header") cache ops functions are declared in a separate header. Include the same to avoid build warnings. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-20fw_setenv: avoid writing environment when nothing has changedRasmus Villemoes1-1/+19
In the case where one deletes an already-non-existing variable, or sets a variable to the value it already has, there is no point in writing the environment back, thus reducing wear on the underlying storage device. In the case of redundant environments, if the two environments differ (e.g. because one is corrupt), make sure that any call of fw_setenv causes the two to become synchronized, even if the fw_setenv call does not change anything in the good copy. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-20drivers: net: bcm-sf2: pass -1 to phy_connect()Alex Marginean1-1/+1
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or is scanning the bus, passing -1 here should keep it functional either way. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Cc: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-20net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYsMarek Vasut1-1/+1
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to phy_connect(). Passing 0 used to work before be accident, but does no longer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-18Merge tag 'u-boot-stm32-20191218' of ↵Tom Rini4-5/+4
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Fix stm32mp1 crash (bootstage) and warning (cls)
2019-12-18stm32mp1: configs: Resync with savedefconfigPatrick Delaunay3-3/+3
Rsync all defconfig files using moveconfig.py Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-18stm32mp1: remove the imply BOOTSTAGEPatrick Delaunay1-2/+0
This patch is only a temporarily workaround for crash introduced by commit ac9cd4805c8b ("bootstage: Correct relocation algorithm"). The crash occurs because the bootstage struct is not correctly aligned when BOOTSTAGE feature is activated. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-18stm32mp1: imply CMD_CLSPatrick Delaunay1-0/+1
Activate by default the command CLS (clear screen); this command used in pxe or sysboot command (DISTRO support) when the "menu background" keyword is present. This patch avoid the warning "Unknown command 'cls'" with extlinux.conf: # Generic Distro Configuration file generated by OpenEmbedded menu title Select the boot mode MENU BACKGROUND /splash.bmp TIMEOUT 20 DEFAULT stm32mp157c-ev1-emmc LABEL stm32mp157c-ev1-emmc KERNEL /uImage FDT /stm32mp157c-ev1.dtb APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200 ... Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf 614 bytes read in 36 ms (16.6 KiB/s) Retrieving file: /splash.bmp 46180 bytes read in 40 ms (1.1 MiB/s) Unknown command 'cls' - try 'help' Select the boot mode 1: stm32mp157c-ev1-sdcard ... Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-16Prepare v2020.01-rc5v2020.01-rc5Tom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-13Merge branch '2019-12-13-master-imports'Tom Rini15-80/+125
- Assorted minor fixes
2019-12-13arm: ti: dra7: move BOOTP_DNS2 and PHY_TI in defconfigGrygorii Strashko4-2/+6
Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to dra7xx_evm_defconfig. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-12-13common: remove duplicate typedef for ucharHeinrich Schuchardt1-1/+0
With commit 37db55b7e9db ("linux/types.h: fix typo unchar") we have a duplicate typedef for uchar. As linux/types.h is included in common.h we don't need another typedef for uchar there. Fixes: 37db55b7e9db ("linux/types.h: fix typo unchar") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-13doc: fitImage: example of a signature nodeHeinrich Schuchardt1-0/+62
Describe that a signature node can be added to a binary device tree using the mkimage tool. Provide an example device tree node. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-13mailmap: Update mail address for Boris BrezillonHeinrich Schuchardt1-0/+2
Boris' email address has changed. Copy two entries from the Linux .mailmap file. Boris confirmed the new email address: https://lists.denx.de/pipermail/u-boot/2019-December/393774.html Cc: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-13doc: really get rid of Documentation/ directoryRasmus Villemoes3-74/+48
Commit 656d8da9d2 (doc: Remove duplicated documentation directory) got rid of most of Documentation/. But there's still an obviously useless .gitignore left behind. Also, there's a copy of the linux kernel's net/ethernet.txt binding imported from v5.0, while the existing one in doc/ is from 4.0-rc1. So replace the latter by the former, and making Documentation/ finally empty. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-12-13sysreset_mpc83xx: fix mcp83xx -> mpc83xx typoRasmus Villemoes3-3/+3
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-12-13dts: am335x-brsmarc1/xre1: insert phy_id againHannes Schmelzer2-0/+4
commit 3b3e8a37d36e ("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id") did sync with recent linux kernel and replaced therefore the 'phy_id' property with a phy-handle pointing to the mdio. This is OK for linux, but introduces trouble with the already running vxWorks on this target. So this commit here re-inerts the phy_id property beside the phy-handle property to be compatible with both. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-12-11Merge tag 'rpi-next-2020.01.2' of ↵Tom Rini2-5/+8
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - fix DRAM bank detection for unified binary - fix 32bit RPi4 config
2019-12-11Merge tag 'fix-for-2020.01' of ↵Tom Rini1-1/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-i2c i2c bugfixes for 2020.01 - i2c: i2c_cdns: fix write timeout on fifo boundary fixes timout issue when writting number of bytes is multiple of the FIFO depth.
2019-12-11Merge tag 'u-boot-atmel-fixes-2020.01-a' of ↵Tom Rini7-10/+34
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel - First set of u-boot-atmel fixes for 2020.01 cycle: This set includes a small fix for gpio bank names, one for removing unused headers (also touches some other boards), and a fix for the QSPI env read on one of the boards.
2019-12-11ARM: defconfig: Fix 32bit config for RPi4Matthias Brugger1-1/+1
The rpi_4_32b_defconfig states that only one DRAM bank is present. This leads to a wrong configuration of the available DRAM. Fix this by setting the DRAM bank config accordingly. Fixes: 193279d784 ("RPI: Add defconfigs for rpi4 (32/64)") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-12-11rpi: Enable DRAM bank initialization on arm64Matthias Brugger1-2/+0
Up to now we only update the DRAM banks when we are define CONFIG_BCM2711. But our one binary approach uses a config that supports BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on Raspberry Pi 4, even if it has more RAM. Fix this by calling dram_init_banksize. Fixes: 5694090670 ("ARM: defconfig: add unified config for RPi3 and RPi4") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-12-11rpi: fix dram bank initializationMatthias Brugger1-2/+7
To update the dram bank information from device-tree we use fdtdec_decode_ram_size() which expectes the the size-cells and address-cells to be defined in the memory node. For normal system RAM these values are defined in the root node. When the values differ from the default values defined in the spec, we can end up with wrong RAM bank information. Switch to the "standard" way to update the RAM bank information to avoid this. Fixes: 9de5b89e4c ("rpi4: enable dram bank initialization") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-12-11i2c: i2c_cdns: fix write timeout on fifo boundaryMichael Auchter1-1/+1
This fixes an issue that would cause I2C writes to timeout when the number of bytes is a multiple of the FIFO depth (i.e. 16 bytes). Within the transfer loop, after writing the data register with a new byte to transfer, if the transfer size equals the FIFO depth, the loop pauses until the INTERRUPT_COMP bit asserts to indicate data has been sent. This same check is performed after the loop as well to ensure data has been transferred prior to returning. In the case where the amount of data to be written is a multiple of the FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to assert after writing the final byte, and then wait for this bit to assert once more. However, since the transfer has finished at this point, no new data has been written to the data register, and hence INTERRUPT_COMP will never assert. Fix this by only waiting for INTERRUPT_COMP in the transfer loop if there's still data to be written. Signed-off-by: Michael Auchter <michael.auchter@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-12-10Merge tag 'fixes-for-2020.01' of ↵Tom Rini108-16/+195
https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix crash and board reset when drawing RLE8 bitmaps bigger than the framebuffer resolution - reduce dead code in video and console uclass routines (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1, stm32f746-disco, stm32f769-disco and wandboard)
2019-12-10configs: sama5d27_som1_ek: Add default config to read ENV from QSPISwapna Gurumani1-0/+8
In the initial SPI flash setup, the default bus mode being used was 3, which is incorrect, causing a CRC error when the ENV was being read from QSPI. Setting the default bus mode to 0 which is the correct mode. Signed-off-by: Swapna Gurumani <swapna.gurumani@microchip.com>
2019-12-09Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini33-73/+1057
- Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
2019-12-10spl: opensbi: wait for ack from secondary harts before entering OpenSBILukas Auer1-1/+11
At the start, OpenSBI relocates itself to its link address. If the link address ranges of U-Boot SPL and OpenSBI overlap, the relocation can lead to code corruption if a hart is still running U-Boot SPL during relocation. To avoid this problem, the main hart is specified as the preferred boot hart to perform the relocation. This fixes the code corruption problems based on the assumption that since the main hart schedules the secondary harts to enter OpenSBI, it will be the last to enter OpenSBI. However it was reported that this assumption is not always correct. To make sure the assumption always holds true, wait for all secondary harts to acknowledge the call-function request before entering OpenSBI on the main hart. Reported-by: Rick Chen <rick@andestech.com> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-12-10riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer6-13/+29
Add a wait option to smp_call_function() to wait for the secondary harts to acknowledge the call-function request. The request is considered to be acknowledged once each secondary hart has cleared the corresponding IPI. As part of the call-function request, the secondary harts invalidate the instruction cache after clearing the IPI. This adds a delay between acknowledgment (clear IPI) and fulfillment (call function) of the request. We want to use the acknowledgment to be able to judge when the request has been completed. Remove the delay by clearing the IPI after cache invalidation and just before calling the function from the request. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-12-10riscv: add functions for reading the IPI statusLukas Auer4-0/+43
Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2019-12-10spl: opensbi: specify main hart as preferred boot hartLukas Auer2-1/+18
OpenSBI uses a relocation lottery to determine the hart to relocate OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart schedules the secondary harts to enter OpenSBI before doing so itself. One of the secondary harts will therefore always be the winner of the relocation lottery. This is problematic if the link address ranges of OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore overwrite U-Boot SPL while some harts may still run it, leading to code corruption. Avoid this problem by specifying the main hart as the preferred boot hart to perform the OpenSBI relocation. The main hart will be the last hart to enter OpenSBI, relocation can therefore occur safely. The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC info structure. The header file include/opensbi.h is synchronized with include/sbi/fw_dynamic.h from the OpenSBI project to update the info structure. The header file is recent as of commit 7a13beb21326 ("firmware: Add preferred boot HART field in struct fw_dynamic_info"). Reported-by: Rick Chen <rick@andestech.com> Suggested-by: Anup Patel <Anup.Patel@wdc.com> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-12-10doc: update AX25-AE350 RISC-V documentationRick Chen1-3/+206
Add descriptions about U-Boot SPL feature and how to build and run. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-12-10riscv: dts: Add #address-cells and #size-cells in nor nodeRick Chen2-2/+6
Those are required for cfi-flash driver to get correct address information. Also modify size description correctly. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-12-10riscv: dts: Support four cores SMPRick Chen2-6/+108
Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
2019-12-10riscv: Fix clear bss loop in the start-up codeRick Chen3-4/+4
For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>
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