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2016-03-17x86: Move Intel Management Engine code to a common placeSimon Glass10-369/+418
Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass3-5/+5
This same name is used in USB. Add a prefix to distinguish it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common CPU code to its own placeSimon Glass6-76/+162
Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move common LPC code to its own placeSimon Glass7-85/+167
Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add the root-complex block to common intel registersSimon Glass4-7/+9
This is similar to MCH in that it is used in various drivers. Add it to the common header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Create a common header for Intel register accessSimon Glass6-6/+22
There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense. An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package). Add a new header file for these registers, and move MCH into it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move microcode code to a common locationSimon Glass6-4/+8
This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Move cache-as-RAM code into a common locationSimon Glass4-1/+8
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new intel_common directory and move it in there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: cpu: Add functions to return the family and steppingSimon Glass2-0/+24
These two identifiers can be useful for drivers which need to adjust their behaviour depending on the CPU family or stepping (revision). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Allow use of serial soon after relocationSimon Glass2-1/+8
At present on x86 machines with use cache-as-RAM, the memory goes away just before board_init_r() is called. This means that serial drivers are no-longer unavailable, until initr_dm() it called, etc. Any attempt to use printf() within this period will cause a hang. To fix this, mark the serial devices as 'unavailable' when it is no-longer available. Bring it back when serial_initialize() is called. This means that the debug UART will be used instead for this period. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17input: i8042: Make sure the keyboard is enabledSimon Glass2-0/+5
Add one more step into the init sequence. This fixes the keyboard on samus, which otherwise does not work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17syscon: Avoid returning a device on failureSimon Glass1-0/+1
If the device cannot be probed, syscon_get_by_driver_data() will still return a useful value in its devp parameter. Ensure that it returns NULL instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17dm: timer: Correct timer init ordering after relocationSimon Glass1-1/+3
Commit 1057e6c broke use of the timer with driver model. If the timer is used before relocation, then it becomes broken after relocation. This prevents some x86 boards from booting. Fix it. Fixes: 1057e6c (timer: Set up the real timer after driver model is available) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: broadwell: Add a few microcode filesSimon Glass2-0/+2272
Add two microcode files for broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add comments to the SIPI vectorSimon Glass2-0/+2
The Intel SIPI (start-up inter-processor interrupt) vector is the entry point for each secondary CPU (also called an AP - applications processor). The assembler and C code are linked, so add comments to indicate this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Tidy up mp_init to reduce duplicationSimon Glass1-53/+26
The timeout step is always 50us. By updating apic_wait_timeout() to print the debug messages we can simplify the code. Also tidy up a few messages and comments while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Correct duplicate POST valuesSimon Glass1-2/+2
Two power-on-self-test values are the same. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add a script to aid code conversion from corebootSimon Glass2-0/+26
It is useful to automate the process of converting code from coreboot a little. Add a sed script which performs some common transformations. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: gpio: Correct GPIO setup orderingSimon Glass2-1/+8
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO is probed. However, it assumes that the first GPIO to be probed is in the first GPIO bank. If this is not the case then the init will write to the wrong registers. Fix this. Also add a note that this code is deprecated. We should move to using device tree instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: dts: link: Add board ID GPIOsSimon Glass1-0/+2
At present the board ID GPIOs are hard-coded. Move them to the device tree so that we can use general SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: dts: link: Move SPD info into the memory controllerSimon Glass1-111/+110
The SDRAM SPD (Serial Presence Detect) information should be contained with the SDRAM controller. This makes it easier for the controller to access it and removes the need for a separate compatible string. As a first step, move the information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: link: Add required GPIO propertiesSimon Glass1-3/+9
In order to use GPIO phandles we need to add some GPIO properties as specified by the GPIO bindings. Add these for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add some more common MSR indexesSimon Glass3-20/+43
Many of the model-specific indexes are common to several Intel CPUs. Add some more common ones, and remove them from the ivybridge-specific header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: cpu: Make the vendor table constSimon Glass1-1/+1
This does not need to be modified at run-time, so make it const. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17malloc_simple: Add a little more debuggingSimon Glass1-2/+5
Output the pointer returned by each call to malloc(). This can be useful when debugging memory problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17pci: Correct a few comments and nitsSimon Glass2-3/+4
Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17pci: Add functions to update PCI configuration registersSimon Glass2-0/+80
It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17gpio: Use const where possibleSimon Glass2-10/+10
Some functions do not change the struct gpio_desc parameter. Update these to use const so this is clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17gpio: Add a function to obtain a GPIO vector valueSimon Glass2-0/+30
We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO is assigned a single bit and can be set high or low on the circuit board. We already have a legacy function for reading these values. Add one that supports driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17cpu: Add support for microcode version and CPU IDSimon Glass2-0/+12
Some CPUs use microcode and each core can have a different version of microcode loaded. Also some CPUs support the concept of an integer ID used for identification purposes. Add support for these in the CPU uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17video: Allow simple-panel to be used without regulatorsSimon Glass1-8/+10
At present simple-panel requires regulator support and will not build without it. But some panels do not have a power supply, or at least not one that can be controlled. Update the implementation to cope with this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
2016-03-17x86: Document how to play with SeaBIOSBin Meng1-2/+55
Boting SeaBIOS is done via U-Boot's bootelf command. Document this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: qemu: Enable ACPI table generation by defaultBin Meng1-0/+1
Now that ACPI is supported on QEMU, enable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Support booting SeaBIOSBin Meng3-0/+28
SeaBIOS is an open source implementation of a 16-bit x86 BIOS. It can run in an emulator or natively on x86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Implement functions for writing coreboot tableBin Meng3-0/+147
To prepare generating coreboot table from U-Boot, implement functions to handle the writing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Support writing configuration tables in high areaBin Meng1-0/+11
For those secondary bootloaders like SeaBIOS who want to live in the F segment, which conflicts the configuration table address, now we allow write_tables() to write the configuration tables in high area (malloc'ed memory). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Simplify codes in write_tables()Bin Meng1-27/+34
Given all table write routines have the same signature, we can simplify the codes by using a function table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Change write_acpi_tables() signature a little bitBin Meng3-6/+5
Change the parameter and return value of write_acpi_tables() to u32 to conform with other table write routines. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Use a macro for ROM table alignmentBin Meng2-5/+7
Define ROM_TABLE_ALIGN instead of using 1024 directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Change to use start/end address pair in write_tables()Bin Meng1-6/+12
Add a new variable rom_table_start and pass it to ROM table write routines. This reads better than previous single rom_table_end. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Clean up coreboot_tables.hBin Meng1-73/+80
Clean up this file a little bit: - Remove inclusion of <linux/compiler.h> - Use tab in the macro definition Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Move sysinfo related to sysinfo.hBin Meng2-4/+2
coreboot_tables.h should not include sysinfo related stuff. Move those to asm/arch-coreboot/sysinfo.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng5-4/+1
Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that coreboot table definitions can be used by other x86 builds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-16spl: arm: Make sure to include all of the u_boot_list entriesTom Rini5-15/+9
Starting with 96e5b03 we use a linker list for partition table information. However since we use this in SPL we need to make sure that the SPL linker scripts include these as well. While doing this, it's best to simply include all linker lists to future proof ourselves. Cc: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16mvebu: ds414: Move cmd_syno into ds414 directoryTom Rini3-8/+4
When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case as we don't have other common code nor other Synology borads, move the cmd_syno.c file (which claims to be ds414 specific anyways!) into the ds414 directory and only build it for non-SPL builds. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XXTom Rini1-1/+7
On OMAP4 platforms that also need to calculate their DDR settings we are now getting very close to the linker limit size. Since OMAP44XX is only seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we will know that we don't have it for OMAP44XX. Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16lpc32xx: work_92105: Rework MakefileTom Rini1-3/+5
When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case change things so that we only build the right objects for SPL or non-SPL Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16cmd: scsi: Group the command portion together, guard with !CONFIG_SPL_BUILDTom Rini1-21/+22
When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case, the SCSI code needs a lot of attention so for now just guard the command portions. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16ARM: keystone2: Only link cmd_ddr3.o on non-SPL buildsTom Rini1-1/+2
When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case simply move cmd_ddr3.o over to the list with the rest. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-16ARM: keystone2: Switch to using the poweroff commandTom Rini4-29/+30
Now that we have a standard way to power off the hardware, switch to using that rather than our own command. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-07-14 01:56:26 +0000