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2017-11-30rockchip: rk3036: update clock driver for ddrKever Yang1-9/+6
After the MASK MACRO update, we need to update the driver at the same time. This is a fix to: 37943aa rockchip: rk3036: clean mask definition for cru reg Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3036: fix pll config for correct frequencyKever Yang1-2/+3
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, so we need to double to pll output and then ddr can work in correct frequency. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: board: evb-rk3128: add empty MakefilePhilipp Tomsich2-0/+5
Even if the board-specific directory Makefile doesn't have any targets, it still needs to exist. This adds a minimal Makefile for the board/rockchip/evb_rk3128 directory and a evk-rk3128.c (as built-in.o needs to be built for every directory that a Makefile gets run for). Fixes: c7a6866 ("rockchip: rk3128: add evb-rk3128 support") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add sdram driverKever Yang2-0/+60
RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width. This patch is only used for U-Boot, but not for SPL which will comes later, maybe after we merge all the common code into a common file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add defconfig for evb-rk3128Kever Yang1-0/+56
Enable board config for evb-rk3128. Serial output and eMMC works in this version. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add evb-rk3128 supportKever Yang4-0/+60
evb-rk3128 is an evb from Rockchip based on rk3128 SoC: - 2 USB2.0 Host port; - 1 HDMI port; - 2 10/100M eth port; - 2GB ddr; - 16GB eMMC; - UART to USB debug port; Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add pinctrl driverKever Yang4-2/+750
Add rk3128 pinctrl driver and grf/iomux structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add clock driverKever Yang5-1/+843
Add rk3128 clock driver and cru structure definition. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add soc basic supportKever Yang8-0/+250
RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host and device, HDMI/LVDS/MIPI display. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: rk3128: add device tree fileKever Yang4-0/+1090
Add dts binding header for rk3128, files origin from kernel. Series-Changes: 2 - fix i2c address - add saradc and usb phy node - emmc using fifo mode for there is no dma support in rk3128 emmc - add some clock id in cru.h Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30rockchip: board: evb_rv1108: update READMEAndy Yan1-3/+2
After commit d962e5dadc2c("rockchip: mkimage: use spl_boot0 for all Rockchip SoCs"), the mkimage will not pad the Tag memroy, so we shoud pass a Taged ddr.bin/spl.bin to it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30MAINTAINERS: update maintained files for RockchipPhilipp Tomsich1-0/+12
With some of the recent cleanups (e.g. moving the DRAM controller drivers for Rockchip devices to drivers/ram/rockchip), the files and paths listed in MAINTAINERS no longer covered what really is looked after as part of the Rockchip port. This commit updates the files/paths listed in MAINTAINERS for the Rockchip port. I am certain, though, that this will have missed some additional paths that should have been included... Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-30Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini43-12847/+787
2017-11-30Merge git://git.denx.de/u-boot-marvellTom Rini10-14/+52
2017-11-30Merge git://git.denx.de/u-boot-x86Tom Rini9-43/+123
2017-11-30ARM: rmobile: Rework the ULCB CPLD driverMarek Vasut5-107/+129
Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-11-30arm: mvebu: correct comments around cas_wl/cas_lChris Packham5-6/+6
The order of members in struct hws_topology_map is cas_wl, cas_l. The comments in the original db-88f6820-gp.c had this wrong and have been copied to other Armada-385 based boards. Practically this hasn't made a difference since all these boards set both cas_wl and cas_l to 0 (autodetect) but if there were ever a board that did need to set these explicitly they would run into unexpected issued. Update the comments to reflect the correct order of structure members. Reported-by: Tobi Wulff <tobi.wulff@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30arm64: mvebu: armada-7k/8k: drop useless #ifdefBaruch Siach1-5/+0
CONFIG_ENV_IS_IN_NAND has been removed in commit 2be296538e2e (Convert CONFIG_ENV_IS_IN_MMC/NAND/UBI and NOWHERE to Kconfig). CONFIG_ENV_IS_IN_SPI_FLASH has been removed in commit 91c868fe7cd (Convert CONFIG_ENV_IS_IN_SPI_FLASH to Kconfig). The environment #ifdef is now empty. Remove it. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30arm: mvebu: enable boot from NANDSean Nyekjaer2-2/+15
Check if we are booting from NAND and let the bootrom continue to load the rest of the bootloader Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30arm: mvebu: fix boot from UART when in fallback modeSean Nyekjaer2-0/+15
It's the first 8 bits of the bootrom error register that contain the boot error/fallback error code. Let's check that and continue to boot from UART. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30arm: mvebu: add nand pinsSean Nyekjaer1-1/+14
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30fix: nand: pxa3xx: fix defined but not used warningsSean Nyekjaer1-0/+2
bbt_mirror_descr and bbt_main_descr is defined but not used when compiling without CONFIG_SYS_NAND_USE_FLASH_BBT set. Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
2017-11-30x86: lib: Implement standalone __udivdi3 etc instead of libgcc onesStefan Roese4-39/+114
This patch removes the inclusion of the libgcc math functions and replaces them by functions coded in C, taken from the coreboot project. This makes U-Boot building more independent from the toolchain installed / available on the build system. The code taken from coreboot is authored from Vadim Bendebury <vbendeb@chromium.org> on 2014-11-28 and committed with commit ID e63990ef [libpayload: provide basic 64bit division implementation] (coreboot git repository located here [1]). I modified the code so that its checkpatch clean without any functional changes. [1] git://github.com/coreboot/coreboot.git Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30distro bootcmd: define bootloader name for x86Heinrich Schuchardt1-0/+4
Currently X86 does not properly support distro defaults. This patch is only a partial fix. It provides the name of the bootloader EFI application for the X86 architecture. The architecture dependent file names are defined in the UEFI specification. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30Revert "x86: bootm: Fix FIT image booting on x86"Anatolij Gustschin1-1/+1
This reverts commit 13c531e52a09b4e6ffa8b5a1457199b0a574cb27. The error message with FIT style image mentioned in the above commit only happens when booting using FIT image containing bzImage kernel and without setup node (setup.bin). The current documentation for x86 FIT support in doc/uImage.FIT/x86-fit-boot.txt mentions that kernel's setup.bin file is required for building x86 FIT images. The above commit breaks FIT images generated as described in the documentation. Revert it to allow booting with images built in the documented way. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30x86: don't compare pointers to 0Heinrich Schuchardt1-2/+2
x86_vendor_name is defined as static const char *const x86_vendor_name[] So its elements should not be compared to 0. Remove superfluous paranthesis. Problem identified with Coccinelle. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30x86: conga-qeval20-qa3-e3845: Adjust VGA rom addressAnatolij Gustschin1-0/+1
Adjust VGA rom address to 0xfffb0000 so that u-boot.rom image can be built again. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-30x86: qemu: Move Cache-As-RAM memory from area mapped to ROMAnton Gerasimov1-1/+1
ROM has been made read-only in qemu recently (namely commit 208fa0e4: "pc: make 'pc.rom' readonly when machine has PCI enabled"). So this patch restores compatibility between U-Boot and qemu. Signed-off-by: Anton Gerasimov <anton@advancedtelematic.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: mention qemu commit title in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-29fat: Use cache aligned buffers for fat_opendirNeil Armstrong1-1/+3
Before this patch one could receive following errors when executing "fatls" command on machine with cache enabled (ex i.MX6Q) : => fatls mmc 0:1 CACHE: Misaligned operation at range [4f59dfc8, 4f59e7c8] CACHE: Misaligned operation at range [4f59dfc8, 4f59e7c8] ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x4f59dfc8 ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x4f59e7c8 CACHE: Misaligned operation at range [4f59dfc8, 4f59e7c8] CACHE: Misaligned operation at range [4f59dfc8, 4f59e7c8] ERROR: v7_outer_cache_inval_range - start address is not aligned - 0x4f59dfc8 ERROR: v7_outer_cache_inval_range - stop address is not aligned - 0x4f59e7c8 To alleviate this problem - the calloc()s have been replaced with malloc_cache_aligned() and memset(). After those changes the buffers are properly aligned (with both start address and size) to SoC cache line. Fixes: 09fa964bba80 ("fs/fat: Fix 'CACHE: Misaligned operation at range' warnings") Suggested-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2017-11-29board: laird: add WB50N CPU moduleBen Whitten7-0/+407
This board is based on the Atmel sama5d3 eval boards. Supporting the following features: - Boot from NAND Flash - Ethernet - FIT - SPL Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
2017-11-29board: laird: add WB45N CPU moduleBen Whitten8-0/+419
This board is based on the Atmel 9x5 eval board. Supporting the following features: - Boot from NAND Flash - Ethernet - FIT - SPL Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com> Signed-off-by: Dan Kephart <dan.kephart@lairdtech.com>
2017-11-29env: suppress a spurious warning with GCC 7.1Philipp Tomsich1-1/+1
GCC 7.1 seems to be smart enough to track val through the various static inline functions, but not smart enough to see that val will always be initialised when no error is returned. This triggers the following warning: env/mmc.c: In function 'mmc_get_env_addr': env/mmc.c:121:12: warning: 'val' may be used uninitialized in this function [-Wmaybe-uninitialized] To make it easier for compiler to understand what is going on, let's initialise val. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-29spl: make CONFIG_OF_EMBED pass dts through fdtgrepGoldschmidt Simon4-22/+38
Building spl with CONFIG_OF_EMBED enabled results in an error message on my board: "SPL image too big". This is because the fdtgrep build step is only executed for CONFIG_OF_SEPARATE. Fix this by moving the fdtgrep build step ('cmd_fdtgreo') from scripts/Makefile.spl to dts/Makefile so that the reduced dtb is available for all kinds of spl builds. The resulting variable name for the embedded device tree blob changes, too, which is why common.h and fdtdec.c have tiny changes. Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-11-29ARM: dts: Rename logicpd-toredp-37xx-devkit in U-BootAdam Ford1-0/+2
In U-Boot, this device tree is compatible with both the Torpedo and SOM-LV kits. Let's rename it in the device tree since the U-Boot code and show a more generic OMAP3 name. The code auto detects between the two and loads the proper DTB file for Linux. This would eliminate the SOM-LV showing the name Torpedo during boot and hopefully eliminate some confusion. Signed-off-by: Adam Ford <aford173@gmail.com>
2017-11-29fs: avoid possible NULL dereference in fs_devreadHeinrich Schuchardt1-1/+2
It is unwise to first dereference a variable and then to check if it was NULL. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-29cmd: blk: remove unreachable codeHeinrich Schuchardt1-2/+0
Remove an unreachable return statement. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-11-29common: command: tempory buffer should have size of command line bufHeinrich Schuchardt1-1/+1
When copying the command line buffer the target array should at least have the same size. Cf. definition of console_buffer in common/cli_readline.c. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-11-29disk: efi: correct the allocation size for mbr header in stackPatrick Delaunay1-2/+2
use ALLOC_CACHE_ALIGN_BUFFER_PAD for mbr header allocation in stack to fix alloc issue in is_gpt_valid() this patch fix also issue for GPT partition handling with blocksize != 512 in set_protective_mbr() Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2017-11-29board: atmel: add sama5d2_ptc_ek boardLudovic Desroches17-488/+554
Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board which was a prototype. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29ARM: at91: add sama5d2 smc headerLudovic Desroches1-0/+76
Add a header for SAMA5D2 SMC since it's not compatible with SAMA5D3 one. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> [wenyou: fix the wrong base address of the SMC register] Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29mmc: atmel_sdhci: not on capabilities to set gck rateLudovic Desroches1-10/+2
The capabilities have default values which doesn't reflect the reality when it concerns the base clock and the mul value. Use a fixe rate for the gck. 240 MHz is an arbitrary choice, it is a multiple of the maximum SD clock frequency handle by the controller and it allows to get a 400 kHz clock for the card initialisation. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29clk: at91: clk-generated: fix incorrect index of clk sourceWenyou Yang1-6/+8
Differentiate the generic clock source selection value from the parent clock index to fix the incorrect assignment of the generic clock source selection. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29clk: at91: clk-generated: select absolute closest rateLudovic Desroches1-3/+1
To get the same behavior as the Linux driver, instead of selecting the closest inferior rate, select the closest inferior or superior rate Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29clk: at91: Kconfig: fix the dependency of AT91_UTMIWenyou Yang1-3/+3
What the AT91_UTMI depends on SPL_DM isn't right. AT91_UTMI is not only used in SPL, also in other place, even if SPL_DM isn't enabled. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-11-29mach-stm32: Factorize MPU's region config for STM32 SoCsPatrice Chotard8-116/+16
MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family and used a common MPU's region config. Only one exception for STM32H7 which doesn't have device area located at 0xA000 0000. For STM32F4, configure_clocks() need to be moved from arch_cpu_init() to board_early_init_f(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29stm32: migrate clock structs in include/stm32_rcc.hPatrice Chotard7-96/+42
In order to factorize code between STM32F4 and STM32F7 migrate all structs related to RCC clocks in include/stm32_rcc.h Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: clk_stm32fx: add clock configuration for mmc usagePatrice Chotard4-1/+103
MMC block needs 48Mhz source clock, for that we choose to select the SAI PLL. Update also stm32_clock_get_rate() to retrieve the MMC clock source needed in MMC driver. STM32F4 uses a different RCC variant than STM32F7. For STM32F4 sdmmc clocks bit are located into dckcfgr register whereas there are located into dckcfgr2 registers on STM32F7. In both registers, bits CK48MSEL and SDMMC1SEL are located at the same position. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29dm: misc: bind STM32F4/F7 clock from rcc MFD driverPatrice Chotard3-46/+102
Like STM32H7, now STM32F4/F7 clock drivers are binded by MFD stm32_rcc driver. This also allows to add reset support to STM32F4/F7 SoCs family. As Reset driver is not part of SPL supported drivers, don't bind it in case of SPL to avoid that stm32_rcc_bind() returns an error. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29configs: stm32f746-disco: enable MISC/DM_RESET/STM32_RESET and STM32_RCCPatrice Chotard1-0/+4
This allows to add rcc MFD support to stm32f746-disco board This rcc MFD driver manages clock and reset for STM32 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2017-11-29clk: stm32fx: migrate define from rcc.h to driverPatrice Chotard2-32/+18
STM32F4 doesn't get rcc.h file, to avoid compilation issue, migrate RCC related defines from rcc.h to driver file and remove rcc.h file. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
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