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2021-08-02Merge https://source.denx.de/u-boot/custodians/u-boot-x86WIP/02Aug2021Tom Rini37-135/+120
- Fixed broken ICH SPI driver in software sequencer mode - Added "m25p,fast-read" to SPI flash node for x86 boards - Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds - Define a default TSC timer frequency for all x86 boards - x86 MTRR MSR programming codes bug fixes - x86 "hob" command bug fixes - Don't program MTRR for DRAM for FSP1 - Move INIT_PHASE_END_FIRMWARE to FSP2 - Use external graphics card by default on Intel Crown Bay - tangier: Fix DMA controller IRQ polarity in CSRT
2021-08-02Merge branch '2021-08-02-numeric-input-cleanups'Tom Rini254-948/+1169
- Merge in a series that cleans up and makes more consistent how we deal with numeric input on the CLI. This saves a few bytes in a lot of places.
2021-08-02lib: Allow using 0x when a decimal value is requestedSimon Glass4-17/+37
U-Boot mostly uses hex for value input, largely because addresses are much easier to understand in hex. But in some cases a decimal value is requested, such as where the value is small or hex does not make sense in the context. In these cases it is sometimes useful to be able to provide a hex value in any case, if only to resolve any ambiguity. Add this functionality, for increased flexibility. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02doc: Add a note about number representationSimon Glass1-0/+31
Mention the default base of U-Boot in the command-line section. Add examples for decimal and octal. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02doc: Convert command-line info to rSTSimon Glass3-41/+57
Take this part of the README and put it into rST format. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02lib: Move common digit-parsing code into a functionSimon Glass1-7/+24
The code to convert a character into a digit is repeated twice in this file. Factor it out into a separate function. This also makes the code a little easier to read. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02lib: Add octal tests for simple_strtoul/l()Simon Glass1-0/+10
This function support decoding octal but no tests are included yet. Add some. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02lib: Add tests for simple_strtoull()Simon Glass1-0/+61
Add some tests that check the behaviour of this function. These are the same as for simple_strtoul() but with a few longer values. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02lib: Drop unnecessary check for hex digitSimon Glass2-1/+3
If we see 0x then we can assume this is the start of a hex value. It does not seem necessary to check for a hex digit after that since it will happen when parsing the value anyway. Drop this check to simplify the code and reduce size. Add a few more test cases for when a 0x prefix is used. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02lib: Comment the base parameter with simple_strtoul/l()Simon Glass1-2/+8
This parameter is not documented properly since it does not cover the meaning when the base is 0. Update this in both functions. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02global: Convert simple_strtoul() with decimal to dectoul()Simon Glass111-230/+255
It is a pain to have to specify the value 10 in each call. Add a new dectoul() function and update the code to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02global: Convert simple_strtoul() with hex to hextoul()Simon Glass183-659/+692
It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02hash: Ensure verification hex pairs are terminatedSimon Glass1-1/+1
This function seems to assume that the chr[] variable contains zeros at the start, which is not always true. Use strlcpy() to be safe. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-03x86: crownbay: Use external graphics card by defaultBin Meng1-2/+1
The board routes the Integrated Graphics Device (IGD) to an LVDS panel, which is less popular than a PCIe based graphics card. Disable the IGD so that it does not show up in the PCI configuration space as a VGA display controller, so we can use an external PCIe graphics card with whatever cable we have. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-03x86: queensbay: Return directly if IGD / SDVO were already disabledBin Meng1-11/+9
Initialize 'igd' and 'sdvo' to NULL so that we just need to test them against NULL later, to be compatible with that case that IGD and SDVO devices were already in disabled state. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-03x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWAREBin Meng2-16/+17
For FSP1, there is no such INIT_PHASE_END_FIRMWARE. Move board_final_cleanup() to fsp2 directory. Fixes: 7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-03x86: fsp: Don't program MTRR for DRAM for FSP1Bin Meng1-4/+23
There are several outstanding issues as to why this does not apply to FSP1: * For FSP1, the system memory and reserved memory used by FSP are already programmed in the MTRR by FSP. * The 'mtrr_top' mistakenly includes TSEG memory range that has the same RES_MEM_RESERVED resource type. Its address is programmed and reported by FSP to be near the top of 4 GiB space, which is not what we want for SDRAM. * The call to mtrr_add_request() is not guaranteed to have its size to be exactly the power of 2. This causes reserved bits of the IA32_MTRR_PHYSMASK register to be written which generates #GP. For FSP2, it seems this is necessary as without this, U-Boot boot process on Chromebook Coral goes very slowly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02Merge tag 'efi-2021-10-rc2' of ↵Tom Rini9-46/+54
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc2 Documentation: * handle 'make htmldocs' warnings as errors * add missing board/ti/index.rst Bug fixes: * avoid buffer overrun in TrueType console * lib: disable CONFIG_SPL_HEXDUMP by default
2021-08-02Merge tag 'mmc-2021-7-30' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini3-29/+38
pl180_mmci update and cleanup fix rpmb routing memory alignment
2021-08-02x86: cmd: hob: Fix display of resource type for system memoryBin Meng1-1/+1
The resource type for system memory is currently displayed as "unknown", which is wrong. Fixes: 51af144eb7a0 ("x86: Allow showing details about a HOB entry") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: cmd: hob: Fix the command usage and help messagesBin Meng1-4/+3
At present the hob command usage and help messages are messed up in a single line. They should be separated. This was a regression introduced when [seq] and [-v] were added to the command. Fixes: d11544dfa9f4 ("x86: hob: Add way to show a single hob entry") Fixes: 51af144eb7a0 ("x86: Allow showing details about a HOB entry") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: mtrr: Abort if requested size is not power of 2Bin Meng2-3/+11
The size parameter of mtrr_add_request() and mtrr_set_next_var() shall be power of 2, otherwise the logic creates a mask that does not meet the requirement of IA32_MTRR_PHYSMASK register. Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: mtrr: Skip MSRs that were already programmed in mtrr_commit()Bin Meng1-1/+1
At present mtrr_commit() programs the MTRR MSRs starting from index 0, which may overwrite MSRs that were already programmed by previous boot stage or FSP. Switch to call mtrr_set_next_var() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: mtrr: Do not clear the unused ones in mtrr_commit()Bin Meng1-4/+0
Current mtrr_commit() logic assumes that MTRR MSRs are programmed consecutively from index 0 to its maximum number, and whenever it detects an unused one, it clears all other MTRRs starting from that one. However this may not always be the case. In fact, the clear is not much helpful because these MTRRs come out of reset as disabled already. Drop the clear codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: dts: Define a default TSC timer frequencyBin Meng20-43/+25
If for some reason, TSC timer frequency cannot be determined from hardware, nor is it specified in the device tree, U-Boot will panic resulting in endless reset during boot. Let's define a default TSC timer frequency using the Kconfig value CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of /include/ otherwise the macro is not pre-processed). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQBin Meng4-9/+10
Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROMBin Meng4-35/+2
These 2 options are no longer needed as now binman is used to build u-boot.rom. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: crownbay: Adjust VGA rom addressBin Meng1-0/+1
binman complains when binary blobs are present: Node '/binman/rom/intel-vga': Offset 0xfff90000 (4294508544) overlaps with previous entry '/binman/rom/u-boot-dtb-with-ucode' ending at 0xfff9204c (4294516812) Adjust VGA rom address to 0xfffa0000 so that u-boot.rom image can be successfully built again. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: tangier: Fix DMA controller IRQ polarity in CSRTAndy Shevchenko1-2/+2
IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh. Note, in DSDT (see southcluster.asl) it's described correctly. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: dts: Add "m25p,fast-read" to SPI flash nodeBin Meng11-0/+11
Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should have "m25p,fast-read" property present in their DT nodes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPSBin Meng1-0/+1
Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") SPI flash on Intel Crown Bay board does not work anymore. Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to the spi-nor core. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02spi: ich: Limit slave->max_read_sizeBin Meng1-2/+4
Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") (in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller in software sequencer mode. ICH controller can only transfer a small number of bytes at once. Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes is limited to slave->max_write_size but after commit 43c145b8b3ee data.nbytes is no longer limited because slave->max_read_size is not initialized with a valid number. Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02efi_loader: typo cerificateHeinrich Schuchardt1-1/+1
%s/cerificate/certificate/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-08-01doc: add graphviz imagemagick as build dependenciesHeinrich Schuchardt1-3/+3
'make htmldocs' requires graphviz and imagemagick (at least with Sphinx 3.5.4). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-08-01doc: handle 'make htmldocs' warnings as errorsHeinrich Schuchardt1-1/+1
Parameter -W for sphinx-build turns build warnings into errors. This helps us to avoid bad patches passing Gitlab CI. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-08-01doc: add missing board/ti/index.rstHeinrich Schuchardt1-0/+9
Commit 8baeeecbe305 ("doc: board: Move j721e document to doc/board/ti/ directory") introduced 'make htmldocs' build errors due to a missing file board/ti/index.rst. Fixes: 8baeeecbe305 ("doc: board: Move j721e document to doc/board/ti/ directory") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-08-01Merge tag 'dm-pull-1aug21' of https://source.denx.de/u-boot/custodians/u-boot-dmWIP/01Aug2021Tom Rini27-514/+997
sandbox TPM-emulator improvements rST documentation and fixes for moveconfig handle empty 'ranges' property in dtoc patman warning for invalid tag clean-ups to 'fdt add' command
2021-08-01dtoc: Support widening a bool valueSimon Glass6-2/+38
At present if we see 'ranges' property (with no value) we assume it is a boolean, as per the devicetree spec. But another node may define 'ranges' with a value, forcing us to widen it to an int array. At present this is not supported and causes an error. Fix this and add some test cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Tom Rini <trini@konsulko.com>
2021-08-01dtoc: Fix widening an int array to an intSimon Glass4-14/+22
An int array can hold a single int so we should not need to do anything in the widening operation. However due to a quirk in the code, an int[3] widened with an int produced an int[4]. Fix this and add a test. Fix a comment typo while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Tom Rini <trini@konsulko.com>
2021-08-01dtoc: Rename is_wider_than() to reduce confusionSimon Glass1-6/+9
The current name is confusing because the logic is actually backwards from what you might expect. Rename it to needs_widening() and update the comments. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-01sandbox: Reduce keyed autoboot delaySimon Glass6-3/+73
The autoboot tests are a recent addition to U-Boot, providing much-needed coverage in this area. A side effect of the keyed autoboot test is that this feature is enabled in sandbox always. This changes the autoboot prompt and confuses the pytests. Some tests become slower, for example the vboot tests take about 27s now instead of 3s. We don't actually need this feature enabled to be able to run the tests. Add a switch to allow sandbox to turn it on and off as needed. Use this in the one test that needs it. Add a command-line flag in case this is desired in normal use. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 25c8b9f298e ("test: add first autoboot unit tests") Reviewed-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2021-08-01moveconfig: Update to newer kconfiglibSimon Glass1-12/+12
Some of the more advanced features of this tool don't work anymore since kconfiglib was update. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-01doc: Fix up outdated moveconfig docsSimon Glass1-36/+22
The examples here are a bit messed up since the command does not match the documentation. Use a different example instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-01doc: Add docs for the moveconfig toolSimon Glass3-290/+298
Move these docs into htmldocs so they can be read there. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-01doc: Move coccinelle into its own sectionSimon Glass1-1/+8
This tool has nothing to do with testing. It is for refactoring code automatically using a 'semantic patch' tool. Create a new section for 'refactoring' and move it into there. It is likely that other topics may fall under the same heading, such as using moveconfig and search/replace tools. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-01doc: Create an intro section for testingSimon Glass2-3/+5
At present this information is hidden away. Make it more visible by putting it first, in an intro section. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-08-01patman: add warning for invalid tagPatrick Delaunay2-0/+20
Add a error in patman tool when the commit message contents an invalid tag "Serie-.*" instead of "Series-.*". Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-01fdt: Show the type of devicetree with fdt addrSimon Glass1-2/+3
It seems useful to show whether the address of the Control or Working devicetree is being shown. Add support for this. Drop the confusing 0x prefix since the command itself only accepts hex. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-01fdt: Tidy up the code a bit with fdt addrSimon Glass1-24/+13
Clean up the code a little before changing it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-01sandbox: tpm: Support extending a PCR multiple timesSimon Glass2-15/+27
It is fairly easy to handle this case and it makes the emulator more useful, since PCRs are commonly extended several times. Add support for this, using U-Boot's sha256 support. For now sandbox only supports a single PCR, but that is enough for the tests that currently exist. Signed-off-by: Simon Glass <sjg@chromium.org>
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