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2017-05-08aspeed: Refactor AST2500 RAM Driver and Sysreset Drivermaxims@google.com6-112/+24
This change switches all existing users of ast2500 Watchdog to Driver Model based Watchdog driver. To perform system reset Sysreset Driver uses first Watchdog device found via uclass_first_device call. Since the system is going to be reset anyway it does not make much difference which watchdog is used. Instead of using Watchdog to reset itself, SDRAM driver now uses Reset driver to do that. These were the only users of the old Watchdog API, so that API is removed. This all is done in one change to avoid having to maintain dual API for watchdog in between. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Device Tree configuration for Reset Drivermaxims@google.com3-0/+70
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Reset Drivermaxims@google.com4-0/+145
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to perform resets and thus depends on it. The actual Watchdog device used needs to be configured in Device Tree using "aspeed,wdt" property, which must be WDT phandle, for example: rst: reset-controller { compatible = "aspeed,ast2500-reset"; aspeed,wdt = <&wdt1>; } Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Make SCU lock/unlock functions part of SCU APImaxims@google.com3-16/+31
Make functions for locking and unlocking SCU part of SCU API. Many drivers need to modify settings in SCU and thus need to unlock it first. This change makes it possible. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Watchdog Timer Drivermaxims@google.com5-13/+217
This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08dm: Simple Watchdog uclassmaxims@google.com11-1/+333
This is a simple uclass for Watchdog Timers. It has four operations: start, restart, reset, stop. Drivers must implement start, restart and stop operations, while implementing reset is optional: It's default implementation expires watchdog timer in one clock tick. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Update ast2500 Device Treemaxims@google.com1-1/+880
Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08ARM: DT: STM32F746: add u-boot, dm-pre-reloc property to sub nodesVikas Manocha1-0/+24
This patch is required for correct SPL device tree creation by fdtgrep as fdtgrep looks for u-boot,dm-pre-reloc property of the node to include it in the spl device tree. Not adding it in these subnodes ignores the pin muxing of peripherals which is almost always in the subnodes. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08README: remove CONFIG_CMD_DATEChris Packham1-1/+0
CONFIG_CMD_DATE was recently moved to Kconfig. Remove the now duplicate description of the option. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08tools: moveconfig: cleanup README entiresChris Packham1-0/+41
The Kconfig description replaces the description in the README file so as options are migrated they can be removed from the README. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08tools: moveconfig: cleanup whitelist entriesChris Packham1-0/+20
After moving to KConfig and removing from all headers options should be removed from config_whitelist.txt so the build starts complaining if someone adds them back. Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08tools: moveconfig: extract helper function for user confirmationChris Packham1-19/+18
Avoid repetitive code dealing with asking the user for confirmation. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08rtc: Add DM support to ds1307Chris Packham2-20/+196
Add an implementation of the ds1307 driver that uses the driver model i2c APIs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08igep003x: Add netboot supportPau Pajuelo1-1/+12
netboot allows to boot an external image using TFTP and NFS protocols Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08igep003x: Add support for IGEP SMARC AM335xPau Pajuelo5-19/+133
The IGEP SMARC AM335x is an industrial processor module with following highlights: o AM3352 TI processor (Up to AM3359) o Cortex-A8 ARM CPU o SMARC form factor module o Up to 512 MB DDR3 SDRAM / 512 MB FLASH o WiFi a/b/g/n and Bluetooth v4.0 on-board o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08igep003x: UBIizeLadislav Michl3-18/+48
Convert IGEP board to use UBI volumes for U-Boot, its environment and kernel. With exception of first four sectors read by SoC BootROM whole NAND is UBI managed. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher<hs@denx.de> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08igep0033: Rename to igep003xLadislav Michl10-16/+16
Rename igep0033 to igep003x as IGEP SMARC AM335x module (igep0034) can use the same source files. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08mtd: nand: Consolidate nand spl loaders implementationLadislav Michl4-171/+110
nand_spl_load_image implementation was copied over into three different drivers and now with nand_spl_read_block used for ubispl situation gets even worse. For now use least intrusive solution and #include the same implementation to nand drivers. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08ARM: am33xx: define BOOT_DEVICE_ONENANDLadislav Michl1-0/+1
am33xx does not support OneNAND, but we need this define anyway to let UBI SPL code compile. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08ARM: am33xx: fix typo in spl.hLadislav Michl1-1/+1
Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08stm32f7: remove not needed configuration from board configVikas Manocha1-3/+0
This patch removes: - CONFIG_CMD_MEM: enabled by default - CONFIG_DESIGNWARE_ETH : not being used anywhere. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: add support for stm32f769 disco boardVikas Manocha2-1/+257
This board support stm32f7 family device stm32f769-I with 2MB internal Flash & 512KB RAM. STM32F769 lines offer the performance of the Cortex-M7 core (with double precision floating point unit) running up to 216 MHz. To compile for stm32f769 board, use same defconfig as stm32f746-disco, the only difference is to pass "DEVICE_TREE=stm32f769-disco". Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: move board specific pin muxing to dtsVikas Manocha2-86/+90
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: increase the max no of pin configuration to 70Vikas Manocha1-1/+2
The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: sdram: correct sdram configuration as per micron sdramVikas Manocha4-51/+33
Actually the sdram memory on stm32f746 discovery board is micron part MT48LC_4M32_B2B5_6A. This patch does the modification required in the device tree node & driver for the same. Also we are passing here all the timing parameters in terms of clock cycles, so no need to convert time(ns or ms) to cycles. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: enable board info read from device treeVikas Manocha1-0/+1
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: stm32f746-disco: read memory info from device treeVikas Manocha3-18/+31
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f746: to switch on user LED1 & read user buttonVikas Manocha3-0/+48
All discovery boards have one user button & one user LED. Here we are just reading the button status & switching ON the user LED. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: use stm32f7 gpio driver supporting driver modelVikas Manocha6-109/+15
With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08ARM: DT: stm32f7: add gpio device tree nodesVikas Manocha2-0/+123
Also created alias for gpios for stm32f7 discovery board. Based on these aliases, it would be possible to get gpio devices by sequence. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08dm: gpio: Add driver for stm32f7 gpio controllerVikas Manocha5-5/+198
This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-08stm32f7: sdram: use sdram device tree node to configure sdram controllerVikas Manocha3-53/+135
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: use clock driver to enable sdram controller clockVikas Manocha3-2/+16
This patch also removes the sdram/fmc clock enable from board specific code. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: use driver model for sdram initializationVikas Manocha1-70/+19
As driver model takes care of pin control configuraion, this patch also removes the sdram/fmc pin configuration. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08ARM: DT: stm32f7: add sdram pin contol nodeVikas Manocha3-0/+114
Also added DT binding doc for stm32 fmc(flexible memory controller). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: dm: add driver model support for sdramVikas Manocha1-0/+31
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: sdram: move sdram driver code to ram drivers areaVikas Manocha5-112/+135
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: use clock driver to enable qspi controller clockVikas Manocha2-1/+16
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08spl: make image arg or fdt blob address reconfigurableVikas Manocha6-23/+17
At present fdt blob or argument address being passed to kernel is fixed at compile time using macro CONFIG_SYS_SPL_ARGS_ADDR. FDT blob from different media like nand, nor flash are copied to the address pointed by the macro. The problem is, it makes args/fdt blob compulsory to copy which is not required in cases like for NOR Flash. This patch removes this limitation. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-05-08arm: am57xx: cl-som-am57x: enable USB commandsUri Mashiach1-0/+1
Add CONFIG_CMD_USB to the defconfig file. Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08arm: am57xx: cl-som-am57x: enable USB storageUri Mashiach1-0/+1
Add CONFIG_USB_STORAGE to the defconfig file. Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08arm: am57xx: cl-som-am57x: fix USB scanUri Mashiach1-2/+2
USB bus scan attempt: ----------------------------------cut---------------------------------- => usb start starting USB... USB0: Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... data abort pc : [<fff6240e>] lr : [<fff623b3>] reloc pc : [<8081b40e>] lr : [<8081b3b3>] sp : fdf42930 ip : fdf42960 fp : 00000000 r10: 00000001 r9 : fdf42ef0 r8 : 48890020 r7 : 00000002 r6 : fffa5840 r5 : fff8b140 r4 : fdf429c0 r3 : 00000000 r2 : 00000004 r1 : 00000000 r0 : 00000000 Flags: nZcv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... ----------------------------------cut---------------------------------- Fix by enabling USB configuration in the SPL. Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Igor Grinberg <grinberg@compulab.co.il>
2017-05-08arm: am57xx: cl-som-am57x: invoke clock API to enable/disable clocksUri Mashiach2-10/+2
Invoke enable_usb_clocks during board_usb_init and disable_usb_clocks during board_usb_exit to enable and disable clocks respectively. Modifications: * Enable USB clocks in the OMAP version of the function board_usb_init. * Disable USB clocks in the OMAP version of the function board_usb_cleanup. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08usb: host: xhci-omap: fix double weak board_usb_init functionsUri Mashiach5-9/+22
A weak version of the function board_usb_init is implemented in: common/usb.c drivers/usb/host/xhci-omap.c To fix the double implementations: * Convert the board_usb_init function in drivers/usb/host/xhci-omap.c normal (not weak). * The function board_usb_init in drivers/usb/host/xhci-omap.c calls to the weak function omap_xhci_board_usb_init. * Rename board version of the function board_usb_init to omap_xhci_board_usb_init. Done only for boards that defines CONFIG_USB_XHCI_OMAP. To achieve the same flexibility with the function board_usb_cleanup: * Add a normal (not weak) implementation of the function board_usb_cleanup in drivers/usb/host/xhci-omap.c * The function board_usb_cleanup in drivers/usb/host/xhci-omap.c calls to the weak function omap_xhci_board_usb_cleanup. * Rename board version of the function board_usb_cleanup to omap_xhci_board_usb_cleanup. Done only for boards that defines CONFIG_USB_XHCI_OMAP. Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Roger Quadros <rogerq@ti.com>
2017-05-08arm: usb: dra7xx: xHCI registers based on USB port indexUri Mashiach4-2/+15
Modify the determination of the base address of xHCI registers of DRA7XX targets. Before the commit: by the target. After the commit: by the USB port index. Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Roger Quadros <rogerq@ti.com> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
2017-05-08arm: dra7xx: move CONFIG_DRA7XX to KconfigUri Mashiach5-7/+8
The symbol CONFIG_DRA7XX is needed for Kconfig conditions. Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08Prepare v2017.05v2017.05Tom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-05board/BuR/common: incorrect check of dtbxypron.glpk@gmx.de1-3/+3
The logical expression to check the dtb is incorrect in load_devicetree. The problem was indicated by cppcheck. The inconsistent variable name dtppart is changed to dtbpart. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at> Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at>
2017-05-05tools: sunxi: avoid read after end of stringxypron.glpk@gmx.de1-1/+1
The evaluation of option -c is incorrect: According to the C99 standard endptr in the first strtol is always set as &endptr is not NULL. So the first part of the or condition is always true. If all digits in optarg are valid endptr will point to the closing \0 and the second strtol will read beyond the end of the string optarg points to. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-05-05relocate-rela: add missing va_end()xypron.glpk@gmx.de1-2/+4
va_start must always be matched by va_end. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
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