diff options
Diffstat (limited to 'src/arm64/mediatek/mt8192.dtsi')
| -rw-r--r-- | src/arm64/mediatek/mt8192.dtsi | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/arm64/mediatek/mt8192.dtsi b/src/arm64/mediatek/mt8192.dtsi index 6dd32db..84cbdf6 100644 --- a/src/arm64/mediatek/mt8192.dtsi +++ b/src/arm64/mediatek/mt8192.dtsi @@ -1164,6 +1164,14 @@ #address-cells = <1>; #size-cells = <1>; + socinfo-data1@44 { + reg = <0x044 0x4>; + }; + + socinfo-data2@50 { + reg = <0x050 0x4>; + }; + lvts_e_data1: data1@1c0 { reg = <0x1c0 0x58>; }; @@ -1456,6 +1464,7 @@ reg = <0 0x14001000 0 0x1000>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; @@ -1814,7 +1823,7 @@ mediatek,scp = <&scp>; power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; clocks = <&vencsys CLK_VENC_SET1_VENC>; - clock-names = "venc-set1"; + clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; }; |