diff options
Diffstat (limited to 'include')
510 files changed, 449 insertions, 6347 deletions
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e550703..16fd305 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -277,7 +277,7 @@ struct global_data { */ void *trace_buff; #endif -#if defined(CONFIG_SYS_I2C_LEGACY) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) /** * @cur_i2c_bus: currently used I2C bus */ @@ -447,12 +447,6 @@ struct global_data { */ fdt_addr_t translation_offset; #endif -#if CONFIG_IS_ENABLED(WDT) - /** - * @watchdog_dev: watchdog device - */ - struct udevice *watchdog_dev; -#endif #ifdef CONFIG_GENERATE_ACPI_TABLE /** * @acpi_ctx: ACPI context pointer diff --git a/include/clock_legacy.h b/include/clock_legacy.h index b0a8333..29261b6 100644 --- a/include/clock_legacy.h +++ b/include/clock_legacy.h @@ -11,4 +11,15 @@ int get_clocks(void); unsigned long get_bus_freq(unsigned long dummy); int get_serial_clock(void); +/* + * If we have CONFIG_DYNAMIC_DDR_CLK_FREQ then there will be an + * implentation of get_board_ddr_clk() somewhere. Otherwise we have + * a static value to use now. + */ +#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ +unsigned long get_board_ddr_clk(void); +#else +#define get_board_ddr_clk() CONFIG_DDR_CLK_FREQ +#endif + #endif diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index aaf016c..167d44e 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -46,10 +46,4 @@ #define CONFIG_SYS_MAXARGS 16 #endif -#if CONFIG_IS_ENABLED(DM_I2C) -# ifdef CONFIG_SYS_I2C_LEGACY -# error "Cannot define CONFIG_SYS_I2C_LEGACY when CONFIG_DM_I2C is used" -# endif -#endif - #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 3ffc744..709a449 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -47,7 +47,6 @@ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN 0x20000 /* * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above @@ -57,10 +56,5 @@ * (which is common practice). */ -/* - * MISC - */ -#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */ -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index 3f065ff..f7ad7ef 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -47,7 +47,6 @@ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN 0x20000 /* * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above @@ -57,10 +56,5 @@ * (which is common practice). */ -/* - * MISC - */ -#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */ -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 1b8312b..e0c8d36 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -40,11 +40,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_UDP_CHECKSUM @@ -71,8 +66,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ #define CONFIG_SYS_PLL_ODR 0x36 #define CONFIG_SYS_PLL_FDR 0x7D @@ -108,7 +101,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -138,7 +130,6 @@ env/embedded.o(.text*); /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index d061f45..f983281 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -49,11 +49,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_i2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) @@ -83,8 +78,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) - #define CONFIG_SYS_CLK 75000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 @@ -116,7 +109,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -154,7 +146,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 1a1a110..7015f79 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -31,8 +31,6 @@ */ #undef CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - /* * Clock configuration: enable only one of the following options */ @@ -78,7 +76,6 @@ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -104,7 +101,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 8ac0086..d892cbb 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -70,18 +70,11 @@ #define CONFIG_HOSTNAME "M5253DEMO" /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) #define CONFIG_SYS_I2C_PINMUX_SET (0) -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ #define CONFIG_SYS_FAST_CLK #ifdef CONFIG_SYS_FAST_CLK @@ -124,7 +117,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) /* @@ -160,7 +152,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 2cdd436..01c8ac6 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -75,7 +75,6 @@ "save\0" \ "" -#define CONFIG_SYS_LOAD_ADDR 0x20000 #define CONFIG_SYS_CLK 66000000 /* @@ -111,7 +110,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -134,7 +132,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index eb7823a..3504861 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -59,18 +59,11 @@ #endif /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) -#define CONFIG_SYS_LOAD_ADDR 0x800000 - #define CONFIG_BOOTCOMMAND "bootm ffe40000" #ifdef CONFIG_MCFFEC @@ -124,7 +117,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -147,7 +139,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 6a50a25..fde1084 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -72,8 +72,6 @@ "save\0" \ "" -#define CONFIG_SYS_LOAD_ADDR 0x20000 - #define CONFIG_SYS_CLK 64000000 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ @@ -116,7 +114,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -142,7 +139,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index a063b92..2e5b82a 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -55,11 +55,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_UDP_CHECKSUM @@ -86,8 +81,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 @@ -124,7 +117,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -158,7 +150,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 4fc6d38..e3e7d8b 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -49,11 +49,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_UDP_CHECKSUM @@ -80,8 +75,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 @@ -120,7 +113,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -165,7 +157,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 7a9240a..256a66f 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -51,11 +51,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_UDP_CHECKSUM @@ -82,8 +77,6 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 @@ -122,7 +115,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -167,7 +159,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 48e9ecd..65c1638 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -60,8 +60,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x200000 - #define CONFIG_SYS_HZ 1000 /* Definitions for initial stack pointer and data area (in DPRAM) */ @@ -86,7 +84,6 @@ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) #define CONFIG_SYS_MONITOR_LEN (320 << 10) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Environment Configuration */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index b4e1cae..dd11e98 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -22,8 +22,6 @@ /* * DDR Setup */ -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ /* @@ -35,26 +33,11 @@ #define SPD_EEPROM_ADDRESS2 0x51 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#undef CONFIG_DDR_2T_TIMING - /* * DDRCDR - DDR Control Driver Register */ @@ -70,21 +53,6 @@ * Manually set up DDR parameters */ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x47d00432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#else #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10) @@ -93,17 +61,10 @@ #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ -#if defined(CONFIG_DDR_32BIT) -/* set burst length to 8 for 32-bit data path */ - /* DLL,normal,seq,4/2.5, 8 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000023 -#else /* the default burst length is 4 - for 64-bit data path */ /* DLL,normal,seq,4/2.5, 4 burst len */ #define CONFIG_SYS_DDR_MODE 0x00000022 #endif -#endif -#endif /* * SDRAM on the Local Bus @@ -149,7 +110,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Serial Port @@ -165,14 +125,6 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* SPI */ @@ -218,9 +170,6 @@ #if defined(CONFIG_PCI) -#define CONFIG_83XX_PCI_STREAMING - - #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xFIXME #define PCI_ENET0_MEMADDR 0xFIXME @@ -280,7 +229,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -320,8 +268,6 @@ #define CONFIG_ROOTPATH "/nfsroot/rootfs" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=mpc8349emds\0" \ @@ -346,7 +292,7 @@ "fdtfile=mpc834x_mds.dtb\0" \ "" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ @@ -356,7 +302,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 7924cbc..2a53b14 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -22,8 +22,6 @@ /* * DDR Setup */ -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ /* @@ -35,26 +33,11 @@ #define SPD_EEPROM_ADDRESS2 0x51 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#undef CONFIG_DDR_2T_TIMING - /* * DDRCDR - DDR Control Driver Register */ @@ -70,21 +53,6 @@ * Manually set up DDR parameters */ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x47d00432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#else #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10) @@ -93,17 +61,10 @@ #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ -#if defined(CONFIG_DDR_32BIT) -/* set burst length to 8 for 32-bit data path */ - /* DLL,normal,seq,4/2.5, 8 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000023 -#else /* the default burst length is 4 - for 64-bit data path */ /* DLL,normal,seq,4/2.5, 4 burst len */ #define CONFIG_SYS_DDR_MODE 0x00000022 #endif -#endif -#endif /* * SDRAM on the Local Bus @@ -146,7 +107,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. @@ -220,14 +180,6 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* SPI */ @@ -273,9 +225,6 @@ #if defined(CONFIG_PCI) -#define CONFIG_83XX_PCI_STREAMING - - #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xFIXME #define PCI_ENET0_MEMADDR 0xFIXME @@ -335,7 +284,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -377,8 +325,6 @@ #define CONFIG_ROOTPATH "/nfsroot/rootfs" #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=mpc8349emds\0" \ @@ -403,7 +349,7 @@ "fdtfile=mpc834x_mds.dtb\0" \ "" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ @@ -413,7 +359,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a13b178..26c6180 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -66,9 +66,6 @@ #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ /* @@ -113,17 +110,9 @@ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */ -#if defined(CONFIG_DDR_2T_TIMING) -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE \ - | SDRAM_CFG_2T_EN) - /* 0x43088000 */ -#else #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2) /* 0x43000000 */ -#endif #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ | (0x0442 << SDRAM_MODE_SD_SHIFT)) @@ -147,7 +136,6 @@ #endif #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup @@ -203,11 +191,6 @@ #define CONFIG_FSL_SERDES2 0xe3100 /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* @@ -329,7 +312,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -361,9 +343,6 @@ #define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_FDTFILE "mpc8379_rdb.dtb" - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 800000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" CONFIG_NETDEV "\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ @@ -390,7 +369,7 @@ "$netdev:off " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv rootdev /dev/nfs;" \ "run setbootargs;" \ "run setipargs;" \ @@ -398,7 +377,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv rootdev /dev/ram;" \ "run setbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 549fbfa..fc9d949 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -61,7 +61,6 @@ /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -189,7 +188,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -205,11 +203,6 @@ /* * I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* RapidIO MMU */ @@ -286,7 +279,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -321,8 +313,6 @@ #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ @@ -331,7 +321,7 @@ "fdtaddr=400000\0" \ "fdtfile=your.fdt.dtb\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -340,7 +330,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -348,6 +338,6 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index d3e5da0..f7d05ff 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -45,10 +45,7 @@ extern unsigned long get_clock_freq(void); /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ @@ -278,7 +275,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -295,23 +291,13 @@ extern unsigned long get_clock_freq(void); * I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #else #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 #endif -#define CONFIG_SYS_I2C_FSL /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_CCID -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * General PCI @@ -420,7 +406,6 @@ extern unsigned long get_clock_freq(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -455,8 +440,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ @@ -478,7 +461,7 @@ extern unsigned long get_clock_freq(void); "fdtaddr=1e00000\0" \ "fdtfile=mpc8548cds.dtb\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -487,7 +470,7 @@ extern unsigned long get_clock_freq(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -495,6 +478,6 @@ extern unsigned long get_clock_freq(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 5254936..e1e0717 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -28,7 +28,6 @@ */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* @@ -62,7 +61,6 @@ /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -190,7 +188,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ @@ -202,11 +199,6 @@ /* * I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* RapidIO MMU */ @@ -258,50 +250,6 @@ #endif /* CONFIG_TSEC_ENET */ -#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ - -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif - /* * Environment */ @@ -319,7 +267,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ @@ -338,7 +285,7 @@ /* * Environment Configuration */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 @@ -355,8 +302,6 @@ #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyCPM\0" \ @@ -365,7 +310,7 @@ "fdtaddr=400000\0" \ "fdtfile=mpc8560ads.dtb\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -374,7 +319,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -382,6 +327,6 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index b7e44d1..02b0b71 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -153,7 +153,6 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ #define CONFIG_HWCONFIG @@ -168,7 +167,6 @@ /* DDR Setup */ #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 @@ -443,7 +441,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ /* * Config the L2 Cache as L2 SRAM @@ -497,38 +494,19 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif #define I2C_PCA9557_ADDR1 0x18 #define I2C_PCA9557_ADDR2 0x19 #define I2C_PCA9557_BUS_NUM 0 -#define CONFIG_SYS_I2C_FSL /* I2C EEPROM */ #if defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ID_EEPROM #ifdef CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #endif -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ #endif /* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* RTC */ #define CONFIG_RTC_PT7C4338 @@ -632,7 +610,6 @@ extern unsigned long get_sdram_size(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -660,9 +637,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \ @@ -715,7 +689,7 @@ extern unsigned long get_sdram_size(void); "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" #endif -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs; " \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -723,7 +697,7 @@ extern unsigned long get_sdram_size(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#define CONFIG_BOOTCOMMAND RAMBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 4ef0613..6da44e7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -14,8 +14,6 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -88,11 +86,8 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * DDR Setup @@ -104,8 +99,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -240,7 +233,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -259,19 +251,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_FSL /* @@ -478,7 +457,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -499,9 +477,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -525,14 +500,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); "fdtfile=p2041rdb/p2041rdb.dtb\0" \ "bdev=sda3\0" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -541,7 +516,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -549,7 +524,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT +#define CONFIG_BOOTCOMMAND HDBOOT #include <asm/fsl_secure_boot.h> diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index ded494c..fc6167c 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -11,7 +11,6 @@ */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg /* additions for new ARM relocation support */ @@ -38,15 +37,6 @@ * for your console driver. */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - #define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" #define MTDPARTS_MTDOOPS "errlog" #define CONFIG_DOS_PARTITION @@ -60,13 +50,7 @@ */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /* size in bytes reserved for initial data */ @@ -89,6 +73,4 @@ #define CONFIG_PHY_BASE_ADR 0x01 #endif /* CONFIG_CMD_NET */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ - #endif /* _CONFIG_SBX81LIFKW_H */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 06bbd86..06be63e 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -11,7 +11,6 @@ */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg /* additions for new ARM relocation support */ @@ -38,15 +37,6 @@ * for your console driver. */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - #define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" #define MTDPARTS_MTDOOPS "errlog" #define CONFIG_DOS_PARTITION @@ -60,7 +50,6 @@ */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ /* * For booting Linux, the board info and command line data @@ -89,6 +78,4 @@ #define CONFIG_PHY_BASE_ADR 0x01 #endif /* CONFIG_CMD_NET */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ - #endif /* _CONFIG_SBX81LIFXCAT_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 1873044..3ae8a14 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -26,7 +26,6 @@ #endif #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -43,11 +42,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg -#endif #endif #ifdef CONFIG_SPIFLASH @@ -60,11 +54,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg -#endif #endif #ifdef CONFIG_SDCARD @@ -76,11 +65,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -134,11 +118,9 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 /* * These can be toggled for performance analysis, otherwise use default. @@ -147,9 +129,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -170,13 +150,8 @@ unsigned long get_board_ddr_clk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * DDR Setup @@ -187,7 +162,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -392,7 +366,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -422,20 +395,7 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ #define I2C_PCA6408_BUS_NUM 1 #define I2C_PCA6408_ADDR 0x20 @@ -615,7 +575,6 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -635,7 +594,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ #define __USB_PHY_TYPE utmi #ifdef CONFIG_ARCH_T1024 @@ -668,7 +626,7 @@ unsigned long get_board_ddr_clk(void); "fdtaddr=1e00000\0" \ "bdev=sda3\0" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -676,7 +634,7 @@ unsigned long get_board_ddr_clk(void); "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -685,7 +643,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index fb215bb..910baef 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -15,14 +15,6 @@ #include <asm/config_mpc85xx.h> #ifdef CONFIG_RAMBOOT_PBL - -#ifndef CONFIG_NXP_ESBC -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg -#else -#define CONFIG_SYS_FSL_PBL_PBI \ - $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg -#endif - #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -49,26 +41,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg -#endif #endif #ifdef CONFIG_SPIFLASH @@ -81,26 +53,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg -#endif #endif #ifdef CONFIG_SDCARD @@ -112,26 +64,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg -#endif #endif #endif @@ -164,7 +96,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 66666666 /* * These can be toggled for performance analysis, otherwise use default. @@ -173,9 +104,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -211,8 +140,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 @@ -421,7 +348,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -452,26 +378,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C3_SPEED 400000 -#define CONFIG_SYS_FSL_I2C4_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x8 @@ -676,7 +583,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -701,9 +607,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" @@ -746,7 +649,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg "fdtfile=" __stringify(FDTFILE) "\0" \ "bdev=sda3\0" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -754,14 +657,14 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -770,7 +673,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -778,7 +681,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index f61b40f..315d1f7 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -29,8 +29,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg - #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -47,9 +45,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg -#endif #endif #ifdef CONFIG_SPIFLASH @@ -62,9 +57,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg -#endif #endif #ifdef CONFIG_SDCARD @@ -76,9 +68,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg -#endif #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -101,19 +90,15 @@ */ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* * Config the L3 Cache as L3 SRAM @@ -130,11 +115,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* * DDR Setup @@ -144,7 +126,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 @@ -352,7 +333,6 @@ unsigned long get_board_ddr_clk(void); GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* * Serial Port @@ -370,23 +350,6 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C3_SPEED 100000 -#define CONFIG_SYS_FSL_I2C4_SPEED 100000 -#endif - -#define CONFIG_SYS_I2C_FSL #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ @@ -613,7 +576,6 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -635,8 +597,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -664,7 +624,7 @@ unsigned long get_board_ddr_clk(void); * For emulation this causes u-boot to jump to the start of the * proof point app code automatically */ -#define CONFIG_PROOF_POINTS \ +#define PROOF_POINTS \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "cpu 1 release 0x29000000 - - -;" \ @@ -676,11 +636,11 @@ unsigned long get_board_ddr_clk(void); "cpu 7 release 0x29000000 - - -;" \ "go 0x29000000" -#define CONFIG_HVBOOT \ +#define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" -#define CONFIG_ALU \ +#define ALU \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "cpu 1 release 0x01000000 - - -;" \ @@ -692,7 +652,7 @@ unsigned long get_board_ddr_clk(void); "cpu 7 release 0x01000000 - - -;" \ "go 0x01000000" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -700,14 +660,14 @@ unsigned long get_board_ddr_clk(void); "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -716,7 +676,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -724,7 +684,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 601e67c..6824be9 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg - #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_PAD_TO 0x40000 #define CONFIG_SPL_MAX_SIZE 0x28000 @@ -42,7 +40,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg #endif #ifdef CONFIG_SPIFLASH @@ -55,7 +52,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg #endif #ifdef CONFIG_SDCARD @@ -67,7 +63,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -90,19 +85,15 @@ */ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ 66660000 -#define CONFIG_DDR_CLK_FREQ 133330000 /* * Config the L3 Cache as L3 SRAM @@ -119,11 +110,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * DDR Setup @@ -133,7 +121,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 @@ -304,7 +291,6 @@ unsigned long get_board_ddr_clk(void); GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* * Serial Port @@ -322,26 +308,6 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C3_SPEED 100000 -#define CONFIG_SYS_FSL_I2C4_SPEED 100000 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif - -#define CONFIG_SYS_I2C_FSL #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ @@ -565,7 +531,6 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -587,8 +552,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -616,7 +579,7 @@ unsigned long get_board_ddr_clk(void); * For emulation this causes u-boot to jump to the start of the * proof point app code automatically */ -#define CONFIG_PROOF_POINTS \ +#define PROOF_POINTS \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "cpu 1 release 0x29000000 - - -;" \ @@ -628,11 +591,11 @@ unsigned long get_board_ddr_clk(void); "cpu 7 release 0x29000000 - - -;" \ "go 0x29000000" -#define CONFIG_HVBOOT \ +#define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" -#define CONFIG_ALU \ +#define ALU \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "cpu 1 release 0x01000000 - - -;" \ @@ -644,7 +607,7 @@ unsigned long get_board_ddr_clk(void); "cpu 7 release 0x01000000 - - -;" \ "go 0x01000000" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -652,14 +615,14 @@ unsigned long get_board_ddr_clk(void); "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -668,7 +631,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -676,7 +639,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index c796b1d..54db021 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -18,7 +18,6 @@ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg #ifndef CONFIG_SDCARD #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc @@ -38,7 +37,6 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_SYS_MPC85XX_NO_RESETVEC #endif -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg #endif #ifdef CONFIG_SPL_BUILD @@ -50,8 +48,6 @@ #endif #endif /* CONFIG_RAMBOOT_PBL */ -#define CONFIG_DDR_ECC - /* High Level Configuration Options */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ @@ -72,7 +68,6 @@ #define CONFIG_SYS_CACHE_STASHING #define CONFIG_BTB /* toggle branch predition */ #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -102,8 +97,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD - /* * IFC Definitions */ @@ -135,7 +128,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -154,18 +146,6 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif - -#define CONFIG_SYS_I2C_FSL /* * General PCI @@ -225,7 +205,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -246,19 +225,14 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_HVBOOT \ +#define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" #define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ 133333333 #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif /* @@ -429,8 +403,6 @@ unsigned long get_board_ddr_clk(void); #endif /* I2C */ -#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ @@ -600,11 +572,11 @@ unsigned long get_board_ddr_clk(void); "fdtfile=t4240rdb/t4240rdb.dtb\0" \ "bdev=sda3\0" -#define CONFIG_HVBOOT \ +#define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ "bootm 0x01000000 - 0x00f00000" -#define CONFIG_LINUX \ +#define LINUXBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "setenv ramdiskaddr 0x02000000;" \ @@ -612,14 +584,14 @@ unsigned long get_board_ddr_clk(void); "setenv loadaddr 0x1000000;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -628,7 +600,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -636,7 +608,7 @@ unsigned long get_board_ddr_clk(void); "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_LINUX +#define CONFIG_BOOTCOMMAND LINUXBOOTCOMMAND #include <asm/fsl_secure_boot.h> diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h index a7adb59..b6a78b1 100644 --- a/include/configs/adp-ae3xx.h +++ b/include/configs/adp-ae3xx.h @@ -15,8 +15,6 @@ */ #define CONFIG_USE_INTERRUPT -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_SKIP_TRUNOFF_WATCHDOG #define CONFIG_ARCH_MAP_SYSMEM @@ -86,7 +84,6 @@ * Size of malloc() pool */ /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* * Physical Memory Map @@ -105,14 +102,6 @@ GENERATED_GBL_DATA_SIZE) /* - * Load address and memory test area should agree with - * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x300000 - -/* memtest works on 63 MB in DRAM */ - -/* * Static memory controller configuration */ #define CONFIG_FTSMC020 diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index afec9ba..3e78d5c 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -15,8 +15,6 @@ */ #define CONFIG_USE_INTERRUPT -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_ARCH_MAP_SYSMEM #define CONFIG_BOOTP_SERVERIP @@ -85,12 +83,6 @@ */ /* - * Size of malloc() pool - */ -/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - -/* * AHB Controller configuration */ #define CONFIG_FTAHBC020S @@ -217,14 +209,6 @@ #endif /* CONFIG_MEM_REMAP */ /* - * Load address and memory test area should agree with - * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x300000 - -/* memtest works on 63 MB in DRAM */ - -/* * Static memory controller configuration */ #define CONFIG_FTSMC020 diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ad5616d..0f6ffd9 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_BOOTM_LEN SZ_16M -#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -168,10 +166,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /* PMIC support */ #define CONFIG_POWER_TPS65217 #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index c161b93..d93db09 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -22,8 +22,6 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifndef CONFIG_SPL_BUILD #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 387d50d..584b025 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -223,10 +223,4 @@ #endif #define CONFIG_NET_RETRY_COUNT 10 - -/* I2C configuration */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 1 #endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 16849d8..dff9468 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_BOOTM_LEN (16 << 20) -/*#define CONFIG_MACH_TYPE 3589 Until the next sync */ - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -55,10 +53,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /* PMIC support */ #define CONFIG_POWER_TPS65217 #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index a9c14a1..edfd890 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -14,8 +14,6 @@ #include <configs/ti_omap3_common.h> -#define CONFIG_REVISION_TAG - /* Hardware drivers */ /* diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 31a1c7e..ff1949e 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -21,15 +21,8 @@ #endif /* I2C Configuration */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Power */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#endif #define CONFIG_POWER_TPS65218 #define CONFIG_POWER_TPS62362 @@ -42,14 +35,6 @@ #define CONFIG_SYS_PL310_BASE 0x48242000 /* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* * When building U-Boot such that there is no previous loader * we need to call board_early_init_f. This is taken care of in * s_init when we have SPL used. @@ -74,7 +59,7 @@ #define CONFIG_AM437X_USB2PHY2_HOST #endif -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_ETHER) +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_GADGET) #undef CONFIG_USB_DWC3_PHY_OMAP #undef CONFIG_USB_DWC3_OMAP #undef CONFIG_USB_DWC3 diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c47ffcc..5396586 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -22,10 +22,6 @@ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - #define CONFIG_SYS_OMAP_ABE_SYSCK #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 57cd520..9962408 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -22,10 +22,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif -#ifndef CONFIG_CPU_V7R -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #if defined(CONFIG_TARGET_AM642_A53_EVM) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index d4514a0..55fa641 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -49,10 +49,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" #endif -#ifndef CONFIG_CPU_V7R -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #define CONFIG_SYS_BOOTM_LEN SZ_64M diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 641d8fd..4fd02cd 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -28,10 +28,6 @@ "erase 0xfff00000 0xffffffff; " \ "cp.b 0x20000 0xfff00000 ${filesize}\0" -/* undef to save memory */ - -#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ - #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 45000000 @@ -58,7 +54,6 @@ /* reserve 128-4KB */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) #define LDS_BOARD_TEXT \ @@ -75,7 +70,6 @@ * This is a single unified instruction/data cache. * sdram - single region - no masks */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 4902d07..fb2a0b3 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -12,11 +12,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x40000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 diff --git a/include/configs/ap143.h b/include/configs/ap143.h index c79e050..bb9544b 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -12,11 +12,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x40000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 0d2c484..766f10b 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -12,11 +12,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x40000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index b04a03f..8059454 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -18,8 +18,6 @@ #define USDHC2_BASE_ADDR 0x5b020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Networking */ #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 @@ -70,9 +68,6 @@ "${blkcnt}; fi\0" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -83,9 +78,6 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h index 2ad4ca3..cd00223 100644 --- a/include/configs/apalis-imx8x.h +++ b/include/configs/apalis-imx8x.h @@ -17,8 +17,6 @@ #define USDHC2_BASE_ADDR 0x5b020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 @@ -97,9 +95,6 @@ "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" /* Link Definitions */ -#define CONFIG_LOADADDR 0x89000000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -112,9 +107,6 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 12de010..23fca1e 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -14,8 +14,6 @@ #undef CONFIG_DISPLAY_BOARDINFO -#define CONFIG_MACH_TYPE 4886 - #include <asm/arch/imx-regs.h> #include <asm/mach-imx/gpio.h> @@ -23,25 +21,8 @@ #include "imx6_spl.h" #endif -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - #define CONFIG_MXC_UART_BASE UART1_BASE -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -80,8 +61,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#define CONFIG_LOADADDR 0x12000000 - #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ @@ -162,7 +141,7 @@ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "vidargs=mxc_hdmi.only_cea=1 fbmem=32M\0" /* Miscellaneous configurable options */ @@ -171,8 +150,6 @@ #undef CONFIG_SYS_MAXARGS #define CONFIG_SYS_MAXARGS 48 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 9e5f523..eab4f22 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -23,8 +23,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30 - /* PCI networking support */ #define CONFIG_E1000_NO_NVM diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 78fa1a9..b73b0d5 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -28,7 +28,6 @@ #include "mx6_common.h" -#define CONFIG_MACH_TYPE 4501 #define CONFIG_MMCROOT "/dev/mmcblk0p1" /* MMC Configs */ @@ -93,13 +92,13 @@ #endif #if (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ +#define EXTRA_ENV_BOARD_SETTINGS \ "dead=while true; do; " \ "led led_red on; sleep 1;" \ "led led_red off; sleep 1;" \ "done\0" #elif (CONFIG_SYS_BOARD_VERSION == 6) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ +#define EXTRA_ENV_BOARD_SETTINGS \ "dead=while true; do; " \ "led led_red on; led led_red2 on; sleep 1;" \ "led led_red off; led led_red2 off;; sleep 1;" \ @@ -414,7 +413,7 @@ "run main_rescue_boot;" \ "fi; \0"\ HAB_EXTRA_SETTINGS \ - CONFIG_EXTRA_ENV_BOARD_SETTINGS + EXTRA_ENV_BOARD_SETTINGS #define CONFIG_ARP_TIMEOUT 200UL diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 06704e5..73f63c5 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -44,12 +44,9 @@ #define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) #define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - 64 * 1024 * 1024) #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index df0f5d2..5177bf2 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -13,9 +13,6 @@ #include <asm/arch/platform.h> /* Misc CPU related */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG #define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE @@ -32,8 +29,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN (32 << 20) - /* * NS16550 Configuration */ diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h index 88e1bf1..4a25d56 100644 --- a/include/configs/aspenite.h +++ b/include/configs/aspenite.h @@ -14,8 +14,6 @@ */ #define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ #define CONFIG_ARMADA100 1 /* SOC Family Name */ -#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * There is no internal RAM in ARMADA100, using DRAM diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 2ea33e5..077af08 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -22,17 +22,17 @@ * set the card type to actually compile for; either of * the possibilities listed below has to be used! */ -#define CONFIG_ASTRO_V532 1 +#define ASTRO_V532 1 -#if CONFIG_ASTRO_V532 +#if ASTRO_V532 #define ASTRO_ID 0xF8 -#elif CONFIG_ASTRO_V512 +#elif ASTRO_V512 #define ASTRO_ID 0xFA -#elif CONFIG_ASTRO_TWIN7S2 +#elif ASTRO_TWIN7S2 #define ASTRO_ID 0xF9 -#elif CONFIG_ASTRO_V912 +#elif ASTRO_V912 #define ASTRO_ID 0xFC -#elif CONFIG_ASTRO_COFDMDUOS2 +#elif ASTRO_COFDMDUOS2 #define ASTRO_ID 0xFB #else #error No card type defined! @@ -58,11 +58,6 @@ #define CONFIG_MCFTMR /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR /* @@ -149,7 +144,7 @@ #ifdef CONFIG_MONITOR_IS_IN_RAM #define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ #else -#if CONFIG_ASTRO_V532 +#if ASTRO_V532 #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ "run xilinxload&&run alteraload&&bootm 0x80000;"\ "update;reset" @@ -159,9 +154,6 @@ #endif #endif -/* default RAM address for user programs */ -#define CONFIG_SYS_LOAD_ADDR 0x20000 - #define CONFIG_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 @@ -240,8 +232,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) -/* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* * For booting Linux, the board info and command line data @@ -272,7 +262,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index ba21149..9a73e3a 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -15,10 +15,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - /* * BOOTP options */ @@ -54,7 +50,4 @@ #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 780bf0c..d09a5db 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -35,10 +35,6 @@ #endif /* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -68,24 +64,6 @@ (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -/* - * The (arm)linux board id set by generic code depending on configured board - * (see boards.cfg for different boards) - */ -#ifdef CONFIG_AT91SAM9G20 - /* the sam9g20 variants have two different board ids */ -# ifdef CONFIG_AT91SAM9G20EK_2MMC - /* we may be setup for the 2MMC variant of at91sam9g20ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC -# else - /* or the normal at91sam9g20ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK -# endif -#else - /* otherwise default to good old at91sam9260ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK -#endif - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -106,8 +84,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -134,9 +110,4 @@ "fatload mmc 0:1 0x22000000 uImage; bootm" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index c3fe416..fb4695c 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -22,12 +22,6 @@ #include <asm/hardware.h> -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_ATMEL_LEGACY /* @@ -93,8 +87,6 @@ #endif #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -115,9 +107,4 @@ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 51ecf41..f8df5b0 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -22,12 +22,7 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - #ifndef CONFIG_SYS_USE_BOOT_NORFLASH -#define CONFIG_SKIP_LOWLEVEL_INIT #else #define CONFIG_SYS_USE_NORFLASH #endif @@ -209,8 +204,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -224,9 +217,4 @@ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index b4aaf59..78ff577 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -18,11 +18,6 @@ #define CONFIG_AT91SAM9M10G45EK -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -67,8 +62,6 @@ #define CONFIG_RESET_PHY_R #define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env in nandflash */ @@ -83,11 +76,6 @@ "bootz 0x72000000 - 0x71000000" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE 0x010000 #define CONFIG_SPL_STACK 0x310000 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index fe99253..4ae6b66 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -14,10 +14,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT /* LCD */ #define LCD_BPP LCD_COLOR16 @@ -61,9 +57,6 @@ "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" -/* Ethernet */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* USB host */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_ATMEL @@ -102,11 +95,6 @@ #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x6000 #define CONFIG_SPL_STACK 0x308000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 92b87a2..c703276 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -16,12 +16,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - #define CONFIG_ATMEL_LEGACY /* @@ -62,10 +56,6 @@ /* Ethernet - not present */ -/* USB - not supported */ - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SYS_USE_DATAFLASH /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -87,10 +77,4 @@ "fatload mmc 0:1 0x22000000 zImage; " \ "bootz 0x22000000 - 0x21000000" #endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 6a95b39..33481dc 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -12,11 +12,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -65,8 +60,6 @@ #endif #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_BOOTCOMMAND "nand read " \ @@ -85,11 +78,6 @@ "bootm 0x22000000" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x6000 #define CONFIG_SPL_STACK 0x308000 diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index bd9c371..bf3f34e 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -12,7 +12,7 @@ #define CONFIG_SPL_BSS_START_ADDR 0x04000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" #endif #endif @@ -47,12 +47,6 @@ */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* - * Size of malloc() pool - * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough - */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - /* DT blob (fdt) address */ #define CONFIG_SYS_FDT_BASE 0x800f0000 @@ -79,20 +73,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ GENERATED_GBL_DATA_SIZE) -/* - * Load address and memory test area should agree with - * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */ - -/* - * memtest works on 512 MB in DRAM - */ - -/* - * FLASH and environment organization - */ - /* use CFI framework */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 0c5a3af..c02d25c 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -27,9 +27,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * UART configuration @@ -63,7 +61,6 @@ * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* * Console configuration diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 42a5abd..2fe6c86 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -19,8 +19,6 @@ #include <linux/sizes.h> #include <configs/ti_am335x_common.h> -#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -204,10 +202,6 @@ #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index f72d62e..d799ffd 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -15,8 +15,6 @@ #define CONFIG_SYS_TEXT_BASE 0x10100000 #define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 -#define CONFIG_SYS_MALLOC_LEN ((40 * 1024) << 10) /* 40 MiB */ - #include "bcmstb.h" #define BCMSTB_TIMER_LOW 0xf0412008 diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index ce865cb..989482e 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -15,8 +15,6 @@ #define CONFIG_SYS_TEXT_BASE 0x80100000 #define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 -#define CONFIG_SYS_MALLOC_LEN ((10 * 1024) << 10) /* 10 MiB */ - #include "bcmstb.h" #define BCMSTB_TIMER_LOW 0xf0412008 diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 14275ab..be60fe7 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -16,7 +16,6 @@ #define PHYS_SDRAM_1 V2M_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x80000) /* * Initial SP before reloaction is placed at end of first DRAM bank, @@ -26,7 +25,6 @@ */ #define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x80000000) /* 12MB Malloc size */ -#define CONFIG_SYS_MALLOC_LEN (SZ_8M + SZ_4M) /* console configuration */ #define CONFIG_SYS_NS16550_CLK 25000000 diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index d7f9e5b..c3c28ea 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -10,7 +10,6 @@ #ifndef __BCMSTB_H #define __BCMSTB_H -#include "version.h" #include <linux/sizes.h> #ifndef __ASSEMBLY__ @@ -36,7 +35,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * CPU configuration. */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* * Memory configuration. @@ -88,7 +86,6 @@ extern phys_addr_t prior_stage_fdt_address; #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* * CONFIG_SYS_LOAD_ADDR - 1 MiB. @@ -121,7 +118,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * Informational display configuration. */ -#define CONFIG_REVISION_TAG /* * Command configuration. diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 0daa20e..8be491e 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -20,8 +20,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER - /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h index b541236..d9599b8 100644 --- a/include/configs/bg0900.h +++ b/include/configs/bg0900.h @@ -20,8 +20,6 @@ /* Boot Linux */ #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTCOMMAND "bootm" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 2abbe7b..84ea032 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -60,14 +60,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M) - /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -81,8 +73,6 @@ #define CONFIG_SYS_FSL_QSPI_LE #endif -#define CONFIG_LOADADDR 0x82000000 - /* We boot from the gfxRAM area of the OCRAM. */ #define CONFIG_BOARD_SIZE_LIMIT 520192 @@ -230,10 +220,6 @@ "source to NAND\0" \ "active_workset=1\0" -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical memory map */ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (SZ_512M) diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index 573ff3e..66c23cd 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -15,10 +15,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 45eb931..412471a 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index eed321e..8caddf3 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index c78099a..892a3e2 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index 38dd9e3..6eaca1c 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -15,10 +15,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index 547cf85..5bfbcb7 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -22,10 +22,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 116e970..f8c81f6 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index e5e8b15..92ab0ba 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 4d4403f..7d321e1 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -24,10 +24,8 @@ #endif /* CONFIG_USB_OHCI_HCD */ /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index f1ff054..481dfc2 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -15,10 +15,8 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_OFFSET SZ_8K #endif diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 3cb2d40..0f63239 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -18,7 +18,6 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K #define CONFIG_SYS_CBSIZE SZ_512 diff --git a/include/configs/boston.h b/include/configs/boston.h index b9a9965e..cd70e7b 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -33,10 +33,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) - -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) - /* * Console */ diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h index 238ae9c..6bdca17 100644 --- a/include/configs/broadcom_bcm963158.h +++ b/include/configs/broadcom_bcm963158.h @@ -14,7 +14,6 @@ 230400, 500000, 1500000 } /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) /* @@ -26,9 +25,6 @@ /* U-Boot */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm968360bg.h b/include/configs/broadcom_bcm968360bg.h index 77690ff..66c1267 100644 --- a/include/configs/broadcom_bcm968360bg.h +++ b/include/configs/broadcom_bcm968360bg.h @@ -14,7 +14,6 @@ 230400, 500000, 1500000 } /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* * 6858 @@ -25,9 +24,6 @@ /* U-Boot */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h index febe6c0..ba5c3d8 100644 --- a/include/configs/broadcom_bcm968580xref.h +++ b/include/configs/broadcom_bcm968580xref.h @@ -14,7 +14,6 @@ 230400, 500000, 1500000 } /* Memory usage */ #define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* * 6858 @@ -25,9 +24,6 @@ /* U-Boot */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT #ifdef CONFIG_MTD_RAW_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index f9a0632..9fb861b 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -16,7 +16,6 @@ #include <linux/stringify.h> /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) #define CONFIG_SYS_BOOTM_LEN SZ_32M /* Clock Defines */ @@ -25,13 +24,6 @@ #define CONFIG_POWER_TPS65217 -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -/*#define CONFIG_MACH_TYPE 3589*/ -#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ - /* * When we have NAND flash we expect to be making use of mtdparts, * both for ease of use in U-Boot and for passing information on to diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 333d3f4..3f54baf 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -20,20 +20,12 @@ #define CONFIG_BOARD_POSTCLK_INIT #define CONFIG_MXC_GPT_HCLK -#define CONFIG_LOADADDR 0x10700000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* MMC */ #define CONFIG_FSL_USDHC /* Boot */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_MACH_TYPE 0xFFFFFFFF /* misc */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* Environment */ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index d0cc08b..f1e6dbf 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -18,15 +18,12 @@ /* ------------------------------------------------------------------------- */ /* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_MACH_TYPE 3589 - #ifndef CONFIG_SPL_BUILD /* Default environment */ @@ -61,11 +58,6 @@ BUR_COMMON_ENV \ " bootm ${loadaddr} - ${dtbaddr}\0" #endif /* !CONFIG_SPL_BUILD*/ -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* SPI Flash */ /* Environment */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index d6a7af1..d917976 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -18,14 +18,11 @@ #define LCD_BPP LCD_COLOR32 /* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_MACH_TYPE 3589 - #ifndef CONFIG_SPL_BUILD /* Default environment */ @@ -58,11 +55,6 @@ BUR_COMMON_ENV \ #define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default" -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* Environment */ #endif /* __CONFIG_BRXRE1_H__ */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 51585fc..9b2e8b5 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -19,8 +19,6 @@ #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#define CONFIG_SYS_I2C_LEGACY - #endif /* CONFIG_DM */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ @@ -47,14 +45,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* !CONFIG_SPL_BUILD, ... */ -/* - * Our DDR memory always starts at 0x80000000 and U-Boot shall have - * relocated itself to higher in memory by the time this value is used. - */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* * ---------------------------------------------------------------------------- * DDR information. We say (for simplicity) that we have 1 bank, diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index b310e6c..59e827e 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -51,7 +51,6 @@ /* I2C Configuration */ #ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_I2C_SPEED 400000 /* EEPROM */ #define EEPROM_I2C_BUS 0 /* I2C0 */ #define EEPROM_I2C_ADDR 0x50 @@ -128,17 +127,12 @@ "reset;" /* Default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x80280000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 /* On CCP board, USDHC1 is for eMMC */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 8e8b106..f3416b5 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -24,8 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU - /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 15c5027..304c876 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -50,8 +50,6 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Boot M4 */ #define M4_BOOT_ENV \ "m4_0_image=m4_0.bin\0" \ @@ -147,9 +145,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -158,9 +153,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 6e46d29..1d4503b 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_CI20_H__ #define __CONFIG_CI20_H__ -#define CONFIG_SKIP_LOWLEVEL_INIT - /* Ingenic JZ4780 clock configuration. */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_MHZ 1200 @@ -18,13 +16,10 @@ /* Memory configuration */ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index b8928ba..ebfe356 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -12,9 +12,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* Network */ #define CONFIG_FEC_MXC #define CONFIG_FEC_XCV_TYPE RGMII @@ -25,22 +22,9 @@ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -/* I2C configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define SYS_I2C_BUS_SOM 0 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM - #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } @@ -108,7 +92,6 @@ "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ "echo USB boot attempt ...; run usbbootscript; " -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index a496a80..a22fd0e 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -14,7 +14,6 @@ /* Machine config */ #define CONFIG_SYS_LITTLE_ENDIAN -#define CONFIG_MACH_TYPE 4273 /* MMC */ #define CONFIG_SYS_FSL_USDHC_NUM 3 @@ -43,9 +42,9 @@ "initrd_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ "ramdisk_addr_r=0x13000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=undefined\0" \ "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ @@ -165,19 +164,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 - /* SATA */ #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_LBA48 @@ -186,10 +172,8 @@ /* Boot */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -#define CONFIG_SERIAL_TAG /* misc */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) /* SPL */ #include "imx6_spl.h" @@ -201,10 +185,5 @@ #define CONFIG_VIDEO_BMP_LOGO /* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 #endif /* __CONFIG_CM_FX6_H */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 342cc7f..4ca4f35 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -17,8 +17,6 @@ #undef CONFIG_MAX_RAM_BANK_SIZE #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ -#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 - /* Clock Defines */ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -83,9 +81,6 @@ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ /* I2C Configuration */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 0 /* SPL */ @@ -128,11 +123,6 @@ /* Status LED polarity is inversed, so init it in the "off" state */ /* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 #ifndef CONFIG_SPL_BUILD /* diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 73205d0..a290cf0 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -50,8 +50,6 @@ #define CONFIG_AM437X_USB2PHY2_HOST /* Power */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_TPS65218 /* Enabling L2 Cache */ @@ -62,9 +60,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_HSMMC2_8BIT @@ -114,10 +109,5 @@ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 #endif /* __CONFIG_CM_T43_H */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index c859616..efc6b5b 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -135,9 +135,6 @@ enter a valid image address in flash */ #endif -#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address -from which user programs will be started */ - /*---*/ /* @@ -217,7 +214,6 @@ from which user programs will be started */ #endif #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -237,7 +233,6 @@ from which user programs will be started */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 2fa3485..d95c838 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -15,9 +15,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* ENET1 */ #define IMX_FEC_BASE ENET2_BASE_ADDR @@ -25,9 +22,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 1 -/* I2C configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 @@ -106,11 +100,10 @@ "fatload ${interface} 0:1 ${loadaddr} " \ "${board}/flash_blk.img && source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ "vidargs=video=mxsfb:640x480M-16@60" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index cb22b3c..e823497c 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -19,8 +19,6 @@ #define USDHC2_BASE_ADDR 0x5b020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 @@ -102,9 +100,6 @@ "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -117,9 +112,6 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 804a144..44135b2 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -21,25 +21,8 @@ #include "imx6_spl.h" #endif -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - #define CONFIG_MXC_UART_BASE UART1_BASE -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -68,8 +51,6 @@ #undef CONFIG_SERVERIP #define CONFIG_SERVERIP 192.168.10.1 -#define CONFIG_LOADADDR 0x12000000 - #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ @@ -142,7 +123,7 @@ "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ "source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "vidargs=fbmem=8M\0" /* Miscellaneous configurable options */ @@ -151,8 +132,6 @@ #undef CONFIG_SYS_MAXARGS #define CONFIG_SYS_MAXARGS 48 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 2fffaa3..6509366 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -13,9 +13,6 @@ #include "mx7_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND @@ -24,10 +21,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 @@ -171,13 +164,12 @@ "fatload ${interface} 0:1 ${loadaddr} " \ "${board}/flash_blk.img && source ${loadaddr}\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ "updlevel=2\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 6889e8b..0878676 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -19,7 +19,6 @@ /* * Environment settings */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_BOOTCOMMAND \ "if fatload mmc 0 0xa0000000 uImage; then " \ "bootm 0xa0000000; " \ @@ -29,8 +28,6 @@ "fi; " \ "bootm 0xc0000;" #define CONFIG_TIMESTAMP -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS /* * Serial Console Configuration @@ -41,11 +38,10 @@ */ /* I2C support */ -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) #define CONFIG_SYS_I2C_PXA #define CONFIG_PXA_STD_I2C #define CONFIG_PXA_PWR_I2C -#define CONFIG_SYS_I2C_SPEED 100000 #endif /* LCD support */ @@ -83,7 +79,6 @@ #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 158bb09..e947b58 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -15,8 +15,6 @@ #define CONFIG_TEGRA_UARTA_SDIO1 #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2 - /* LCD support */ #define CONFIG_LCD_LOGO diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 30b48c5..324e607 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -24,8 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30 - /* Increase console I/O buffer size */ #undef CONFIG_SYS_CBSIZE #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 5bd440f..f9d0d92 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_SKIP_LOWLEVEL_INIT - #ifdef CONFIG_VIDEO_FSL_DCU_FB #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -27,9 +25,6 @@ #define DCU_LAYER_MAX_NUM 64 #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -38,7 +33,6 @@ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_SERVERIP 192.168.10.1 -#define CONFIG_LOADADDR 0x80008000 #define CONFIG_FDTADDR 0x84000000 /* We boot from the gfxRAM area of the OCRAM. */ @@ -117,7 +111,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical memory map */ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 3b17f75..efd04c6 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -12,16 +12,12 @@ */ #define CONFIG_CUSTOMER_BOARD_SUPPORT -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - /* * TEXT_BASE needs to be below 16MiB, since this area is scrubbed * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_LOADADDR 1000000 - /* * SATA/SCSI/AHCI configuration */ @@ -85,7 +81,7 @@ #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD /* SPL related MMC defines */ -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #ifdef CONFIG_SPL_BUILD #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ #endif @@ -134,7 +130,7 @@ " gpio clear ${gpio1}; gpio set ${gpio2};" \ " fi; sleep 0.12; done\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ @@ -142,7 +138,7 @@ "tftpboot ${bootfile_addr} ${bootfile}; " \ "bootm ${bootfile_addr}" -#define CONFIG_MMCBOOTCOMMAND \ +#define MMCBOOTCOMMAND \ "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ "console=${consoledev},${baudrate} ${othbootargs}; " \ "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c877f3c..2a0a6be 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -25,16 +25,6 @@ #else #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#if defined(CONFIG_TARGET_P3041DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg -#elif defined(CONFIG_TARGET_P4080DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg -#elif defined(CONFIG_TARGET_P5020DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg -#elif defined(CONFIG_TARGET_P5040DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg -#endif #endif #endif @@ -73,9 +63,7 @@ #define CONFIG_BACKSIDE_L2_CACHE #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -101,11 +89,8 @@ #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* * DDR Setup @@ -117,8 +102,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -250,7 +233,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -269,19 +251,6 @@ #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_FSL /* * RapidIO @@ -488,7 +457,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -509,9 +477,6 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #ifdef CONFIG_TARGET_P4080DS #define __USB_PHY_TYPE ulpi #else @@ -539,14 +504,14 @@ "fdtfile=p4080ds/p4080ds.dtb\0" \ "bdev=sda3\0" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -555,7 +520,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ @@ -563,7 +528,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT +#define CONFIG_BOOTCOMMAND HDBOOT #include <asm/fsl_secure_boot.h> diff --git a/include/configs/corvus.h b/include/configs/corvus.h index bd4d6e8..32f4a10 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -29,11 +29,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ @@ -83,20 +78,12 @@ /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 - /* bootstrap + u-boot + env in nandflash */ #define CONFIG_BOOTCOMMAND \ "nand read 0x70000000 0x200000 0x300000;" \ "bootm 0x70000000" -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - SZ_4M, 0x1000) - /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) #define CONFIG_SPL_STACK (SZ_16K) diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 883cbc9..34683f6 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) @@ -31,7 +30,6 @@ /* * Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ @@ -173,16 +171,12 @@ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) /* * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTCOMMAND \ "run envboot; " \ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 18d9ba1..2a020e9 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -17,8 +17,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE - /* Environment in eMMC, at the end of 2nd "boot sector" */ /* SPI */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index dccfa03..6f861a0 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -29,9 +29,6 @@ #endif #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Environment settings */ /* Environment in SD */ @@ -47,15 +44,9 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 18f4707..95f5cf0 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -17,11 +17,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 1ab4232..6bae063 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -11,11 +11,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* * SATA/SCSI/AHCI configuration diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index dd0c3cb..9f5e665 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -18,11 +18,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 33d71a7..c2340b2 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -12,36 +12,18 @@ #include <linux/sizes.h> #include <asm/arch/cpu.h> -#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 - -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - /* * Memory configurations */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_64M -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - GENERATED_GBL_DATA_SIZE) /* * DMA */ -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_DMA_LPC32XX -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SPEED 100000 /* * GPIO @@ -125,14 +107,7 @@ * U-Boot Commands */ -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 /* * SPL specific defines diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 87da441..a2a1d93 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -15,7 +15,6 @@ #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM @@ -34,12 +33,6 @@ #include <configs/ti_omap3_common.h> -#define CONFIG_REVISION_TAG 1 - -/* Size of malloc() pool */ -#undef CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* Hardware drivers */ /* DM9000 */ #define CONFIG_NET_RETRY_COUNT 20 diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index d9be1c3..7af8fce 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -27,14 +27,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) - /* Bootcounter */ #define CONFIG_SYS_BOOTCOUNT_BE @@ -81,9 +73,6 @@ #define CONFIG_HW_WATCHDOG #endif -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/display5.h b/include/configs/display5.h index 40bb3b5..27854df 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -47,14 +47,6 @@ #include "imx6_spl.h" -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - #define CONFIG_MXC_UART_BASE UART5_BASE /* I2C Configs */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 8990efb..18ff1bb 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -13,16 +13,10 @@ #define _CONFIG_DNS325_H /* - * Machine number definition - */ -#define CONFIG_MACH_TYPE MACH_TYPE_DNS325 - -/* * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 04dd0f6..75a2476 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -16,7 +16,6 @@ */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index cc18bce..4613834 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -31,10 +31,6 @@ #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - #define CONFIG_SYS_OMAP_ABE_SYSCK #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/draco.h b/include/configs/draco.h index 396eb7d..29ce3a5 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -12,8 +12,6 @@ #ifndef __CONFIG_DRACO_H #define __CONFIG_DRACO_H -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO - #include "siemens-am33x-common.h" #define DDR_PLL_FREQ 303 @@ -29,13 +27,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - #define CONFIG_FACTORYSET /* Define own nand partitions */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 6474e57..624f611 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -20,7 +20,6 @@ #define PHYS_SDRAM_1_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) #define CONFIG_SYS_BOOTM_LEN SZ_64M /* UART */ @@ -82,9 +81,6 @@ REFLASH(dragonboard/u-boot.img, 8)\ "pxefile_addr_r=0x90100000\0"\ BOOTENV -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 64 /* max command args */ diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 4256e6f..e71dd24 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Generic Timer Definitions */ @@ -50,9 +49,6 @@ "pxefile_addr_r=0x90100000\0"\ BOOTENV -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 65962ee..5b71f70 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -15,7 +15,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG #include "mv-plug-common.h" diff --git a/include/configs/ds109.h b/include/configs/ds109.h index f232abe..62fe144 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -11,9 +11,6 @@ #ifndef _CONFIG_DS109_H #define _CONFIG_DS109_H -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 527 - /* * High Level Configuration Options (easy to change) */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 5d40128..58ecc5f 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -6,9 +6,6 @@ #ifndef _CONFIG_SYNOLOGY_DS414_H #define _CONFIG_SYNOLOGY_DS414_H -/* Vendor kernel expects this MACH_TYPE */ -#define CONFIG_MACH_TYPE 3036 - /* * High Level Configuration Options (easy to change) */ @@ -20,11 +17,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* PCIe support */ #ifndef CONFIG_SPL_BUILD @@ -67,11 +60,7 @@ #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) -/* DS414 bus width is 32bits */ -#define CONFIG_DDR_32BIT - /* Default Environment */ -#define CONFIG_LOADADDR 0x80000 #define CONFIG_BOOTCOMMAND \ "sf probe; " \ "sf read ${loadaddr} 0xd0000 0x2d0000; " \ diff --git a/include/configs/durian.h b/include/configs/durian.h index fa48e5c..1dec09b 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -13,11 +13,6 @@ #define PHYS_SDRAM_1_SIZE 0x7B000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) - -/* Size of Malloc Pool */ -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) - #define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000) /* PCI CONFIG */ diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h index c1a37c8..220c3c4 100644 --- a/include/configs/ea-lpc3250devkitv2.h +++ b/include/configs/ea-lpc3250devkitv2.h @@ -13,20 +13,16 @@ /* * SoC and board defines */ -#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */ /* * RAM */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE /* * cmd */ -#define CONFIG_SYS_LOAD_ADDR 0x80100000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) /* diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 77584fa..6a5e1d3 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -47,8 +47,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x20000 - /*#define CONFIG_SYS_DRAM_TEST 1 */ #undef CONFIG_SYS_DRAM_TEST @@ -104,7 +102,6 @@ #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 #define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 /* @@ -135,7 +132,6 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) @@ -194,15 +190,8 @@ * I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL - -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0 - #ifdef CONFIG_CMD_DATE #define CONFIG_RTC_DS1338 #define CONFIG_I2C_RTC_ADDR 0x68 diff --git a/include/configs/edison.h b/include/configs/edison.h index 0e1205b..3ec35db 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Memory */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 #define CONFIG_PHYSMEM #define CONFIG_SYS_STACK_SIZE (32 * 1024) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 7e0a0ea..fbe4680 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -94,15 +94,6 @@ /* auto boot */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ /* @@ -153,11 +144,7 @@ * I2C related stuff */ #ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 #endif /* @@ -165,15 +152,9 @@ */ /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ - -/* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Enable command line editing */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index b117176..279d712 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -14,9 +14,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - #ifdef CONFIG_SPL #include "imx6_spl.h" #endif @@ -25,17 +22,7 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* I2C config */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 @@ -55,9 +42,9 @@ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 401b50d..9769155 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -17,17 +17,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index a872d48..c99222d 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -15,14 +15,10 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) -#define CONFIG_SYS_MALLOC_LEN SZ_64K -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - /* * Environment */ #define CONFIG_BOOTFILE "app.bin" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_EXTRA_ENV_SETTINGS \ "upgrade_image=u-boot.bin\0" \ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 880149f..47617c2 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -86,10 +86,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 3f26654..80108fc 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -14,10 +14,6 @@ /* The first stage boot loader expects u-boot running at this address. */ /* The first stage boot loader takes care of low level initialization. */ -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Set our official architecture number. */ -#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 /* CPU information */ @@ -34,9 +30,6 @@ /* 128MB SDRAM in 1 bank */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE (128 << 20) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) /* 512kB on-chip NOR flash */ # define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -97,11 +90,6 @@ /* I2C */ #define CONFIG_SYS_MAX_I2C_BUS 1 -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 - #define I2C_SOFT_DECLARATIONS #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 @@ -131,9 +119,6 @@ /* File systems */ /* Boot command */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ "sf read 0x22000000 0xc6000 0x294000; " \ "bootm 0x22000000" diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index 0ff01af..dc032c1 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -13,7 +13,4 @@ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* Memory Info */ -#define CONFIG_SYS_LOAD_ADDR 0x83000000 - #endif /* __CONFIG_H */ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index e7975bf..177a52e 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -10,7 +10,4 @@ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* Memory Info */ -#define CONFIG_SYS_LOAD_ADDR 0x83000000 - #endif /* __CONFIG_H */ diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 8adaf29..95aaa74 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -16,21 +16,12 @@ #include <linux/sizes.h> #include <linux/stringify.h> -#define CONFIG_SKIP_LOWLEVEL_INIT - /* Keep L2 Cache Disabled */ /* input clock of PLL: 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - /* select serial console configuration */ /* PWM */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 5e2aca3..52dcf7a 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -14,8 +14,6 @@ #define CONFIG_BOARD_COMMON -#define CONFIG_REVISION_TAG - /* SD/MMC configuration */ #define CONFIG_MMC_DEFAULT_DEV 0 @@ -32,7 +30,7 @@ #define CONFIG_USB_GADGET_DWC2_OTG_PHY /* Common environment variables */ -#define CONFIG_EXTRA_ENV_ITB \ +#define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ "${kernelname}\0" \ "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 9297fbd..e492396 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -45,12 +45,6 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -/* specific .lds file */ - -/* Boot Argument Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - #define CONFIG_RD_LVL #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE @@ -96,11 +90,6 @@ #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) -/* I2C */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 - /* SPI */ /* Ethernet Controllor Driver */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 65da381..36c3a61 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -13,8 +13,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 - #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) #define CONFIG_IRAM_STACK 0x02050000 diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 2d362f3..7762c77 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -12,9 +12,6 @@ #define CONFIG_EXYNOS5_DT -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 8002 - #define CONFIG_VAR_SIZE_SPL #define CONFIG_IRAM_TOP 0x02074000 diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 6c0aa9b..4a1ecbb 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -16,9 +16,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <linux/sizes.h> -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ @@ -42,8 +39,6 @@ /* select serial console configuration */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) diff --git a/include/configs/falcon.h b/include/configs/falcon.h index 5ecbd1d..67931fe 100644 --- a/include/configs/falcon.h +++ b/include/configs/falcon.h @@ -11,14 +11,13 @@ #include "rcar-gen3-common.h" -/* Generic Interrupt Controller Definitions */ -#ifdef CONFIG_GICV2 -#undef CONFIG_GICV2 +/* + * Generic Interrupt Controller Definitions. Undefine v2 locations and define + * v3 locations. + */ #undef GICD_BASE #undef GICC_BASE #undef GICR_BASE -#endif -#define CONFIG_GICV3 #define GICD_BASE 0xF1000000 #define GICR_BASE 0xF1060000 diff --git a/include/configs/flea3.h b/include/configs/flea3.h index c345fb2..6c3b2c4 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -17,32 +17,14 @@ /* High Level Configuration Options */ #define CONFIG_MX35 -#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 - /* Set TEXT at the beginning of the NOR flash */ /* This is required to setup the ESDC controller */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - /* * Hardware drivers */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ -#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe /* * UART (console) @@ -55,9 +37,6 @@ #define CONFIG_NET_RETRY_COUNT 100 - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - /* * Ethernet on SOC (FEC) */ @@ -75,8 +54,6 @@ /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* * Physical Memory Map */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 007cbb0..72852a0 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -17,11 +17,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -32,8 +27,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - /* NAND flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -45,8 +38,6 @@ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x7000 #define CONFIG_SPL_STACK 0x308000 diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 1b26466..d287942 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -12,14 +12,9 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 - #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 @@ -31,7 +26,7 @@ #define CONFIG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -46,7 +41,6 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 560d6a3..12d108d 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -27,7 +27,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup @@ -60,7 +59,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -84,8 +82,6 @@ #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - /* TODO: Turn into string option and migrate to Kconfig */ #define CONFIG_HOSTNAME "gazerbeam" #define CONFIG_ROOTPATH "/opt/nfsroot" @@ -105,7 +101,7 @@ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -114,13 +110,13 @@ "tftp ${fdt_addr} $fdtfile;" \ "bootm ${kernel_addr} - ${fdt_addr}" -#define CONFIG_MMCBOOTCOMMAND \ +#define MMCBOOTCOMMAND \ "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ "console=$consoledev,$baudrate $othbootargs;" \ "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ "bootm ${kernel_addr} - ${fdt_addr}" -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND +#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 7db6afd..1a5db24 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -15,9 +15,6 @@ #include "imx6_spl.h" #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* PWM */ #define CONFIG_IMX6_PWM_PER_CLK 66000000 diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 5be3a49..0eeffd4 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -19,12 +19,6 @@ #include "mx6_common.h" #include <linux/sizes.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* SATA Configs */ #ifdef CONFIG_CMD_SATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 @@ -33,10 +27,6 @@ #define CONFIG_LBA48 #endif -/* Serial Flash */ - -#define CONFIG_LOADADDR 0x12000000 - #ifdef CONFIG_CMD_NFS #define NETWORKBOOT \ "setnetworkboot=" \ @@ -53,7 +43,7 @@ "nfs ${loadaddr} /srv/nfs/fitImage; " \ "bootm ${loadaddr}\0" \ -#define CONFIG_NETWORKBOOTCOMMAND \ +#define NETWORKBOOTCOMMAND \ "run networkboot; " \ #else @@ -108,21 +98,16 @@ "run doboot; " \ "run failbootcmd\0" \ -#define CONFIG_MMCBOOTCOMMAND \ +#define MMCBOOTCOMMAND \ "run doquiet; " \ "run tryboot; " \ #ifdef CONFIG_CMD_NFS -#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND +#define CONFIG_BOOTCOMMAND NETWORKBOOTCOMMAND #else -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND +#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND #endif - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 2e89d72..43027a5 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -19,7 +19,6 @@ */ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * Default GPIO configuration and LED status diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 4d5eab0..29a446c 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -13,18 +13,13 @@ /* Miscellaneous */ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_CMDLINE_TAG /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) -#define CONFIG_SYS_LOAD_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) -/* Malloc */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Network interface */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 4f27273..f028958 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -24,14 +24,6 @@ #include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" -#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ - -/* Serial ATAG */ -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* Serial */ #define CONFIG_MXC_UART_BASE UART2_BASE @@ -42,12 +34,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_GSC 0 #define CONFIG_I2C_EDID @@ -74,8 +60,6 @@ /* * PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define CONFIG_POWER_LTC3676 diff --git a/include/configs/harmony.h b/include/configs/harmony.h index b2464f9..5a1e72c 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -23,8 +23,6 @@ #define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE #endif -#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY - /* NAND support */ #define CONFIG_TEGRA_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/highbank.h b/include/configs/highbank.h index ff92c4f..4ef3a46 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -12,11 +12,6 @@ #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) #define CONFIG_SYS_TIMER_COUNTS_DOWN -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - #define CONFIG_PL011_CLOCK 150000000 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ @@ -36,7 +31,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x800000 #define CONFIG_SYS_64BIT_LBA /* Environment data setup @@ -46,7 +40,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_SP_ADDR 0x01000000 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 659fbee..387971c 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -13,7 +13,6 @@ #include <linux/sizes.h> -#define CONFIG_POWER #define CONFIG_POWER_HI6553 #define CONFIG_REMAKE_ELF @@ -35,8 +34,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) - /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 19000000 @@ -44,13 +41,6 @@ #define GICD_BASE 0xf6801000 #define GICC_BASE 0xf6802000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - -#ifdef CONFIG_USB_DWC2 -#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO -#endif - #define CONFIG_HIKEY_GPIO /* BOOTP options */ diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 04d4587..f446ecb 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) - /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 19000000 @@ -33,9 +31,6 @@ #define GICD_BASE 0xe82b1000 #define GICC_BASE 0xe82b2000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) #include <config_distro_bootcmd.h> diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 5678f0a..21a984a 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -29,9 +29,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * UART configuration @@ -107,7 +105,6 @@ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* Cli configuration */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 3cc3b8c..c8c28bb 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -28,9 +28,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * UART configuration @@ -106,7 +104,6 @@ setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* Cli configuration */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index ba859a9..4bd3494 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -13,7 +13,6 @@ */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index c99490b..1a716df 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -13,12 +13,6 @@ */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Machine type - */ -#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT #include "mv-common.h" diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 19d3fbf..e759db2 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -163,11 +163,6 @@ /* * I2C setup */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* @@ -217,7 +212,6 @@ */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) /* * Environment Configuration @@ -229,7 +223,6 @@ #define CONFIG_BOOTFILE "ids8313/uImage" #define CONFIG_UBOOTPATH "ids8313/u-boot.bin" #define CONFIG_FDTFILE "ids8313/ids8313.dtb" -#define CONFIG_LOADADDR 0x400000 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" /* Initial Memory map for Linux*/ @@ -241,7 +234,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x100000 #define CONFIG_LOADS_ECHO #define CONFIG_TIMESTAMP #define CONFIG_BOOTCOMMAND "run boot_cramfs" @@ -284,7 +276,7 @@ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ "\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv rootdev /dev/nfs;" \ "run setipargs;run addmtd;" \ "tftp ${loadaddr} ${bootfile};" \ diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index fcf1b7f..fc27ca4 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -11,7 +11,6 @@ #define __XILFPGA_CONFIG_H /* BootROM + MIG is pretty smart. DDR and Cache initialized */ -#define CONFIG_SKIP_LOWLEVEL_INIT /*-------------------------------------------- * CPU configuration @@ -29,9 +28,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ /*---------------------------------------------------------------------- * Commands diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 8c5c061..27aab38 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -15,10 +15,6 @@ #define CONFIG_MX27 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - /* * Lowlevel configuration */ @@ -67,8 +63,6 @@ /* * Memory Info */ -/* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) /* memtest start address */ #define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ @@ -120,9 +114,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index bfe83b8..cf46b54 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -13,9 +13,6 @@ #include <linux/stringify.h> #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Total Size of Environment Sector */ /* Environment */ @@ -30,7 +27,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=uImage\0" \ "fit_image=fit.itb\0" \ "fdt_high=0xffffffff\0" \ @@ -103,7 +100,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 #ifdef CONFIG_MX6UL @@ -174,7 +170,7 @@ # ifdef CONFIG_ENV_IS_IN_NAND # define CONFIG_SPL_NAND_SUPPORT # else -# define CONFIG_SPL_MMC_SUPPORT +# define CONFIG_SPL_MMC # endif # include "imx6_spl.h" diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 6b992f9..e493703 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -17,9 +17,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -36,7 +33,7 @@ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x14000000\0" \ "ramdisk_addr_r=0x14080000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index ede81cc..234aacb 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -54,12 +54,12 @@ #endif /* MMC support */ -#if defined(CONFIG_SPL_MMC_SUPPORT) +#if defined(CONFIG_SPL_MMC) #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ #endif /* SATA support */ -#if defined(CONFIG_SPL_SATA_SUPPORT) +#if defined(CONFIG_SPL_SATA) #define CONFIG_SPL_SATA_BOOT_DEVICE 0 #define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 #endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 4027f32..367f78d 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -13,9 +13,6 @@ #include <linux/sizes.h> #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - /* Total Size of Environment Sector */ /* Environment */ @@ -65,7 +62,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 4a3706d..270c44e 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -12,9 +12,6 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - #define CONFIG_ETHPRIME "FEC" #undef CONFIG_SYS_AUTOLOAD @@ -75,7 +72,6 @@ #define CONFIG_BOOTCOMMAND "run boot${boot-mode}" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h index abf3dd5..01d1cd8 100644 --- a/include/configs/imx7_spl.h +++ b/include/configs/imx7_spl.h @@ -31,7 +31,7 @@ #define CONFIG_SPL_PAD_TO 0x11000 /* MMC support */ -#if defined(CONFIG_SPL_MMC_SUPPORT) +#if defined(CONFIG_SPL_MMC) #define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ #endif diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index faeee21..9b86e0a 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -140,9 +140,6 @@ #endif /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -153,9 +150,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ @@ -178,8 +172,6 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 94f4a12..2bdcc0a 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -93,9 +93,6 @@ "fi;" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -104,9 +101,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ @@ -128,9 +122,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* FEC*/ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 8f3dd8f..a03a7a7 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -44,8 +44,8 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=Image\0" \ "console=ttymxc1,115200\0" \ "fdt_addr_r=0x43000000\0" \ @@ -57,9 +57,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -70,9 +67,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ @@ -94,8 +88,6 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index af5be68..4b22ba1 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -56,8 +56,6 @@ BOOTENV /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M @@ -66,8 +64,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ @@ -94,7 +90,4 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - #endif /* __IMX8MM_ICORE_MX8MM_H */ diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 9166925..63f02bf 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -37,8 +37,6 @@ "scriptaddr=0x46000000\0" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Enable Distro Boot */ #ifndef CONFIG_SPL_BUILD @@ -87,8 +85,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ @@ -112,9 +108,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* FEC */ #define CONFIG_ETHPRIME "eth0" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 9ce60fd..cb85c35 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -108,9 +108,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -121,9 +118,6 @@ #define CONFIG_ENV_OVERWRITE -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 985bec8..1e18a87 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -44,8 +44,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "console=ttymxc1,115200\0" \ "fdt_addr_r=0x43000000\0" \ "boot_fit=no\0" \ @@ -56,9 +56,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 @@ -69,9 +66,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ @@ -93,6 +87,4 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 - #endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index a6569d5..bec6c1d 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -30,15 +30,9 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC -#undef CONFIG_DM_PMIC_PFUZE100 -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PCA9450 -#define CONFIG_SYS_I2C_LEGACY - #endif #if defined(CONFIG_CMD_NET) @@ -68,8 +62,8 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=Image\0" \ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ "fdt_addr_r=0x43000000\0" \ @@ -81,9 +75,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -94,9 +85,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - /* Totally 6GB DDR */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -120,6 +108,4 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 - #endif diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 9db3bd5..9b78662 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -65,9 +65,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -78,9 +75,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index af81a43..9b9d6fd 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -28,7 +28,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_GPIO -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #define CONFIG_SPL_BSS_START_ADDR 0x00180000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 @@ -41,18 +41,7 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC -#undef CONFIG_DM_PMIC_PFUZE100 -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif @@ -99,9 +88,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -112,9 +98,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ @@ -139,13 +122,6 @@ #define CONFIG_MXC_GPIO -/* I2C Configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_OF_SYSTEM_SETUP -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_PMIC -#endif - #endif diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 8038abc..0ec1f69 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -25,7 +25,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_GPIO -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #define CONFIG_SPL_BSS_START_ADDR 0x00180000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 @@ -38,18 +38,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC -#undef CONFIG_DM_PMIC_PFUZE100 - -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#define CONFIG_POWER -#define CONFIG_POWER_I2C #endif #define CONFIG_REMAKE_ELF @@ -142,9 +130,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -155,9 +140,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ @@ -184,13 +166,6 @@ #define CONFIG_MXC_GPIO -/* I2C Configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_OF_SYSTEM_SETUP -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_PMIC -#endif - #endif diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 99e73a9..152fa6f 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -42,8 +42,6 @@ #define USDHC2_BASE_ADDR 0x5B020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -145,9 +143,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -159,9 +154,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index fcbf8ee..89b4554 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -24,7 +24,6 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* FUSE command */ /* Boot M4 */ @@ -122,9 +121,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -146,9 +142,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ #define CONFIG_SYS_FSL_USDHC_NUM 3 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index a7d623a..a7ca48f 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -41,8 +41,6 @@ #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else @@ -144,9 +142,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 @@ -158,9 +153,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 32f8773..8e9a159 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -33,8 +33,6 @@ #endif -#define CONFIG_SERIAL_TAG - #define CONFIG_REMAKE_ELF #define CONFIG_BOARD_EARLY_INIT_F @@ -63,8 +61,8 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "image=Image\0" \ "console=ttyLP1,115200 earlycon\0" \ "fdt_addr_r=0x83000000\0" \ @@ -76,9 +74,6 @@ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ /* Link Definitions */ -#define CONFIG_LOADADDR 0x80480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -88,9 +83,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_MMCROOT "/dev/mmcblk2p2" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_16M) - #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index 4fb4477..64c0f5e 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -11,13 +11,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x20240000 -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SYS_LOAD_ADDR 0x20209000 -#else -#define CONFIG_SYS_LOAD_ADDR 0x80000000 -#define CONFIG_LOADADDR 0x80000000 -#endif - #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 @@ -31,7 +24,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) /* For SPL */ #ifdef CONFIG_SUPPORT_SPL diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index c8d661f..1b67542 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -11,13 +11,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x20280000 -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SYS_LOAD_ADDR 0x20209000 -#else -#define CONFIG_SYS_LOAD_ADDR 0x80000000 -#define CONFIG_LOADADDR 0x80000000 -#endif - #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 1 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1 @@ -42,7 +35,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) /* For SPL */ #ifdef CONFIG_SUPPORT_SPL diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 89ab0da..b573bdc 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -7,11 +7,6 @@ */ #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS /* * There are various dependencies on the core module (CM) fitted @@ -48,7 +43,6 @@ * image to run at reset/power up * e.g. whether the ARM Boot Monitor runs before U-Boot */ -/* #define CONFIG_SKIP_LOWLEVEL_INIT */ /* * The ARM boot monitor does not relocate U-Boot. diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index 1ba69d9..a1b8c06 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -57,9 +57,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) -#define CONFIG_SYS_MALLOC_LEN SZ_64K #define CONFIG_SYS_BOOTM_LEN SZ_128K -#define CONFIG_SYS_LOAD_ADDR SRAM_BASE #define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K @@ -75,6 +73,5 @@ * Environment */ #define CONFIG_BOOTFILE "app.bin" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #endif /* _CONFIG_IOT_DEVKIT_H_ */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 716ae3b..35439c0 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -23,7 +23,7 @@ #endif /* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ +#define ENV_KS2_BOARD_SETTINGS \ DEFAULT_FW_INITRAMFS_BOOT_ENV \ DEFAULT_SEC_BOOT_ENV \ "boot=ubi\0" \ @@ -47,6 +47,4 @@ #define CONFIG_KSNET_CPSW_NUM_PORTS 9 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE -#define CONFIG_DDR_SPD - #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 4471eb4..17245ab 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -16,7 +16,7 @@ #define CONFIG_SOC_K2G /* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ +#define ENV_KS2_BOARD_SETTINGS \ DEFAULT_MMC_TI_ARGS \ DEFAULT_PMMC_BOOT_ENV \ DEFAULT_FW_INITRAMFS_BOOT_ENV \ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index d90b264..f5a20ce 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -23,7 +23,7 @@ #endif /* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ +#define ENV_KS2_BOARD_SETTINGS \ DEFAULT_FW_INITRAMFS_BOOT_ENV \ DEFAULT_SEC_BOOT_ENV \ "boot=ubi\0" \ @@ -46,6 +46,4 @@ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 -#define CONFIG_DDR_SPD - #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 152cea0..97512c9 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -23,7 +23,7 @@ #endif /* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ +#define ENV_KS2_BOARD_SETTINGS \ DEFAULT_FW_INITRAMFS_BOOT_ENV \ DEFAULT_SEC_BOOT_ENV \ "boot=ubi\0" \ diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h index e710c04..ff97c6c 100644 --- a/include/configs/km/km-mpc8309.h +++ b/include/configs/km/km-mpc8309.h @@ -8,7 +8,6 @@ /* * System Clock Setup */ -#define CONFIG_83XX_CLKIN 66000000 #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 @@ -123,7 +122,6 @@ #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 /* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h index 22dfb5d..537a9d5 100644 --- a/include/configs/km/km-mpc832x.h +++ b/include/configs/km/km-mpc832x.h @@ -6,7 +6,6 @@ /* * System Clock Setup */ -#define CONFIG_83XX_CLKIN 66000000 #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 @@ -72,5 +71,4 @@ #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 /* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index 798b126..92e046d 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -67,7 +67,6 @@ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 /* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * PAXE on the local bus CS3 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index ecf4378..45db5cf 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -18,7 +18,6 @@ /* * Manually set up DDR parameters */ -#define CONFIG_DDR_II #define CONFIG_SYS_DDR_SIZE 2048 /* MB */ /* @@ -62,17 +61,8 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } /* I2C */ -#define CONFIG_SYS_I2C_LEGACY #define CONFIG_SYS_NUM_I2C_BUSES 4 #define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 3be926c..a9a6a41 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -11,13 +11,6 @@ /* EEprom support 24C08, 24C16, 24C64 */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* Reserve 4 MB for malloc */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) /* Increase max size of compressed kernel */ #define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 179e145..cca624e 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -25,23 +25,16 @@ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD - #define CONFIG_NAND_ECC_BCH /* include common defines/options for all Keymile boards */ #include "keymile-common.h" -/* Reserve 4 MB for malloc */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* Increase max size of compressed kernel */ #define CONFIG_SYS_BOOTM_LEN (32 << 20) #include "asm/arch/config.h" -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ - /* architecture specific default bootargs */ #define CONFIG_KM_DEF_BOOT_ARGS_CPU \ "bootcountaddr=${bootcountaddr} ${mtdparts}" \ @@ -59,17 +52,6 @@ "appended one; fi\0" \ "" -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - /* * NAND Flash configuration */ @@ -90,8 +72,6 @@ * I2C related stuff */ #undef CONFIG_I2C_MVTWSI -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ #define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ @@ -125,16 +105,8 @@ extern void __set_direction(unsigned pin, int high); #define I2C_DELAY udelay(1) #define I2C_SOFT_DECLARATIONS -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x0 -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 - /* EEprom support 24C128, 24C256 valid for environment eeprom */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * Environment variables configurations @@ -142,8 +114,6 @@ extern void __set_direction(unsigned pin, int high); #if defined CONFIG_KM_ENV_IS_IN_SPI_NOR #define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ #else -#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 -#define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_EEPROM_WREN #define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ #endif @@ -165,9 +135,9 @@ extern void __set_direction(unsigned pin, int high); "newenv=setenv addr 0x100000 && " \ "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \ "mw.b ${addr} 0 4 && " \ - "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ + "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \ " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \ - "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ + "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \ " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" #endif diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index a4cc477..75d109a 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -8,16 +8,9 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_SKIP_LOWLEVEL_INIT - /* include common defines/options for all Keymile boards */ #include "keymile-common.h" -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE @@ -26,12 +19,6 @@ CONFIG_KM_RESERVED_PRAM) >> 10) #define CONFIG_SYS_CLK_FREQ 66666666 -/* - * Take into account default implementation where DDR_FDBK_MULTI is consider as - * configured for DDR_PLL = 2*MEM_PLL_RAT. - * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT. - */ -#define CONFIG_DDR_CLK_FREQ (100000000 >> 1) #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) @@ -42,8 +29,6 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 @@ -191,9 +176,7 @@ /* * I2C */ -#define CONFIG_SYS_I2C_LEGACY #define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_MAX_HOPS 1 @@ -224,8 +207,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 51a01d8..bf876df 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -177,21 +177,14 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DDR_CLK_FREQ 66666666 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x54 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /****************************************************************************** * (PRAM usage) * ... ------------------------------------------------------- @@ -366,8 +359,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - /* * Serial Port - controlled on board with jumper J8 * open - index 2 diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index cdfb280..60fe4ae 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -27,7 +27,6 @@ /* * System Clock Setup */ -#define CONFIG_83XX_CLKIN 66000000 #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index bfb4e67..438a189 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -16,8 +16,6 @@ #endif /* DDR */ -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_VERY_BIG_RAM @@ -42,9 +40,6 @@ /* generic timer */ #define COUNTER_FREQUENCY 25000000 -/* size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* early heap for SPL DM */ #define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE @@ -53,7 +48,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) /* ethernet */ @@ -71,7 +65,6 @@ /* environment */ /* see include/configs/ti_armv7_common.h */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 #define ENV_MEM_LAYOUT_SETTINGS \ "loadaddr=0x82000000\0" \ "kernel_addr_r=0x82000000\0" \ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index c948828..c1db6ea 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -12,20 +12,11 @@ #define CONFIG_SYS_FSL_CLK -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - /* Command definition */ -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc1,115200\0" \ @@ -77,7 +68,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 749e880..8471dff 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -16,13 +16,6 @@ #include "imx6_spl.h" /* common IMX6 SPL configuration */ /* Miscellaneous configurable options */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) /* FEC ethernet */ #define CONFIG_ARP_TIMEOUT 200UL @@ -37,11 +30,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ #endif -/* Watchdog */ - -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 059c54e..c3f690c 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -8,14 +8,9 @@ #define __KZM9G_H #define CONFIG_SH73A0 -#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G #include <asm/arch/rmobile.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* MEMORY */ #define KZM_SDRAM_BASE (0x40000000) #define PHYS_SDRAM KZM_SDRAM_BASE @@ -46,10 +41,8 @@ #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) #define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 @@ -82,23 +75,4 @@ #define CONFIG_NFS_TIMEOUT 10000UL -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 -#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 -#define CONFIG_SYS_I2C_SH_SPEED0 100000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 -#define CONFIG_SYS_I2C_SH_SPEED1 100000 -#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 -#define CONFIG_SYS_I2C_SH_SPEED2 100000 -#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 -#define CONFIG_SYS_I2C_SH_SPEED3 100000 -#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 -#define CONFIG_SYS_I2C_SH_SPEED4 100000 -#define CONFIG_SH_I2C_8BIT -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ - #endif /* __KZM9G_H */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 88f784f..146d8ad 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -7,27 +7,6 @@ #define _CONFIG_LACIE_KW_H /* - * Machine number definition - */ -#if defined(CONFIG_INETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 -#elif defined(CONFIG_NETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 -#elif defined(CONFIG_NETSPACE_LITE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2 -#elif defined(CONFIG_NETSPACE_MINI_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2 -#elif defined(CONFIG_NETSPACE_MAX_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 -#elif defined(CONFIG_D2NET_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 -#elif defined(CONFIG_NET2BIG_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 -#else -#error "Unknown board" -#endif - -/* * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ @@ -37,7 +16,6 @@ #else #define CONFIG_KW88F6281 #endif -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * SDRAM configuration @@ -99,9 +77,6 @@ */ #ifdef CONFIG_CMD_I2C /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ #if defined(CONFIG_NET2BIG_V2) #define CONFIG_SYS_I2C_G762_ADDR 0x3e #endif diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 8c2c8e1..6928179 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -22,12 +22,10 @@ #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT /* * Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ @@ -47,7 +45,6 @@ /* * I2C Configuration */ -#define CONFIG_SYS_I2C_LEGACY #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ @@ -57,15 +54,12 @@ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) /* * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_SETUP_INITRD_TAG #define CONFIG_BOOTCOMMAND \ "if mmc rescan; then " \ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index e7a7ae3..aa2542f 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -12,14 +12,9 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 - #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 @@ -31,7 +26,7 @@ #define CONFIG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -47,7 +42,6 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 5adbe1c..dc6f15a 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -16,9 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -104,8 +101,6 @@ "else run netboot; fi" /* Miscellaneous configurable options */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 670b55d..1edea0a 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -6,22 +6,17 @@ #ifndef __LS1012A_COMMON_H #define __LS1012A_COMMON_H -#define CONFIG_GICV2 - #include <asm/arch/config.h> #include <asm/arch/stream_id_lsch2.h> #include <linux/sizes.h> #define CONFIG_SYS_CLK_FREQ 125000000 -#define CONFIG_SKIP_LOWLEVEL_INIT - #ifdef CONFIG_TFABOOT #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) #endif -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -34,9 +29,6 @@ /* CSU */ #define CONFIG_LAYERSCAPE_NS_ACCESS -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (5 * SZ_1M) - /* PFE */ #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000 @@ -55,12 +47,6 @@ CONFIG_SYS_SCSI_MAX_LUN) /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif /* GPIO */ #ifdef CONFIG_DM_GPIO diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 3e5fdad..a5900f2 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -54,13 +54,8 @@ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Voltage monitor on channel 2*/ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 4c448c6..7a7640a 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -11,16 +11,10 @@ #define CONFIG_SYS_FSL_CLK -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 /* * DDR: 800 MHz ( 1600 MT/s data rate ) @@ -53,21 +47,13 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1021aiot/ls102xa_pbi.cfg -#endif - #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_I2C #define CONFIG_SPL_WATCHDOG -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -98,23 +84,9 @@ * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* * MMC @@ -175,8 +147,6 @@ #define CONFIG_PCI_SCAN_SHOW #endif -#define CONFIG_CMDLINE_TAG - #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 @@ -196,8 +166,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 598f6c6..a164796 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,45 +11,23 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_DEEP_SLEEP -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_QIXIS_I2C_ACCESS #else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#endif - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg #endif #ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg -#endif - #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SPL_PAD_TO 0x1c000 @@ -63,8 +41,6 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg - #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SPL_PAD_TO 0x1c000 @@ -82,7 +58,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -95,9 +70,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -330,16 +303,6 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* GPIO */ #ifdef CONFIG_DM_GPIO @@ -349,13 +312,8 @@ unsigned long get_board_ddr_clk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * I2C bus multiplexer @@ -429,8 +387,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCI_SCAN_SHOW #endif -#define CONFIG_CMDLINE_TAG - #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 @@ -461,8 +417,6 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 58c2d97..afac6ec 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -12,9 +12,6 @@ #define CONFIG_DEEP_SLEEP -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE @@ -22,7 +19,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -51,15 +47,7 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - "board/freescale/ls1021atsn/ls102xa_pbi.cfg" -#endif - #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) #endif /* ifdef CONFIG_NXP_ESBC */ @@ -104,23 +92,10 @@ #define CONFIG_SYS_NS16550_CLK get_serial_clock() /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* QSPI */ #define FSL_QSPI_FLASH_SIZE (1 << 24) @@ -220,8 +195,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index ba308c5..067d4f7 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,19 +11,12 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_DEEP_SLEEP -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -52,19 +45,7 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg -#endif - #ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg -#endif - #ifdef CONFIG_NXP_ESBC /* * HDR would be appended at end of image and copied to DDR along @@ -208,16 +189,6 @@ /* * I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* GPIO */ #ifdef CONFIG_DM_GPIO @@ -227,13 +198,8 @@ #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * MMC @@ -267,8 +233,6 @@ #define CONFIG_PCI_SCAN_SHOW #endif -#define CONFIG_CMDLINE_TAG - #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 @@ -431,8 +395,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_LS102XA_STREAM_ID #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index cbcf30e..50edefb 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -16,8 +16,6 @@ /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -33,9 +31,6 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* GPIO */ #ifdef CONFIG_DM_GPIO #ifndef CONFIG_MPC8XXX_GPIO @@ -44,9 +39,6 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#endif /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -56,7 +48,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 @@ -103,13 +94,8 @@ #define I2C_MUX_CH_DEFAULT 0x8 /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* DisplayPort */ #define DP_PWD_EN_DEFAULT_MASK 0x8 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 9ae37b9..fe20363 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -9,7 +9,6 @@ #include "ls1028a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) /* DDR */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 1a80cb9..348db1e 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -9,7 +9,6 @@ #include "ls1028a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) #define CONFIG_SYS_RTC_BUS_NUM 0 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 834c3e6..f6909d0 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -27,7 +27,6 @@ #endif #define CONFIG_REMAKE_ELF -#define CONFIG_GICV2 #include <asm/arch/stream_id_lsch2.h> #include <asm/arch/config.h> @@ -39,8 +38,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) #endif -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -52,9 +49,6 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -149,16 +143,6 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif /* PCIe */ #ifndef SPL_NO_PCIE @@ -217,7 +201,6 @@ #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 1636f0b..4ef4cac 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -10,13 +10,9 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -24,13 +20,10 @@ unsigned long get_board_ddr_clk(void); /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -53,23 +46,6 @@ unsigned long get_board_ddr_clk(void); #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg -#endif -#endif - /* LPUART */ #ifdef CONFIG_LPUART #define CONFIG_LPUART_32B_REG @@ -79,13 +55,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SCSI_AHCI_PLAT /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_SATA AHCI_BASE_ADDR @@ -191,7 +162,6 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT #endif /* @@ -395,8 +365,6 @@ unsigned long get_board_ddr_clk(void); * Environment */ -#define CONFIG_CMDLINE_TAG - #include <asm/fsl_secure_boot.h> #endif /* __LS1043AQDS_H__ */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 84b83e6..906cd09 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -9,7 +9,6 @@ #include "ls1043a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -21,20 +20,10 @@ #ifndef CONFIG_SPL #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg -#endif - #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 @@ -228,13 +217,8 @@ /* EEPROM */ #ifndef SPL_NO_EEPROM -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #endif /* diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 289acc0..1d8adf9 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -27,7 +27,6 @@ #endif #define CONFIG_REMAKE_ELF -#define CONFIG_GICV2 #include <asm/arch/config.h> #include <asm/arch/stream_id_lsch2.h> @@ -39,8 +38,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) #endif -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -52,9 +49,6 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -108,7 +102,6 @@ #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_WATCHDOG #define CONFIG_SPL_I2C -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_DRIVERS_MISC @@ -133,16 +126,6 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif /* PCIe */ #define CONFIG_PCIE1 /* PCIE controller 1 */ @@ -195,7 +178,6 @@ #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index fade815..7da0860 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -9,7 +9,6 @@ #include "ls1046a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -74,13 +73,8 @@ #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define I2C_RETIMER_ADDR 0x18 /* I2C bus multiplexer */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 9102c81..b6bbc01 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -10,13 +10,9 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -24,13 +20,10 @@ unsigned long get_board_ddr_clk(void); /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -55,26 +48,6 @@ unsigned long get_board_ddr_clk(void); #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1046aqds/ls1046aqds_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg -#endif -#endif - /* IFC */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC @@ -103,13 +76,8 @@ unsigned long get_board_ddr_clk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* * IFC Definitions @@ -209,7 +177,6 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT #endif /* @@ -410,8 +377,6 @@ unsigned long get_board_ddr_clk(void); * Environment */ -#define CONFIG_CMDLINE_TAG - #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index dddaa25..d3f5d8c 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -10,7 +10,6 @@ #include "ls1046a_common.h" #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -18,27 +17,12 @@ /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg -#ifdef CONFIG_EMMC_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg -#endif -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg +#if defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_UBOOT_BASE 0x40100000 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 #endif @@ -135,20 +119,11 @@ #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define I2C_RETIMER_ADDR 0x18 /* PMIC */ -#define CONFIG_POWER -#ifdef CONFIG_POWER -#define CONFIG_POWER_I2C -#endif /* * Environment diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 3f0679c..f39f031 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -37,8 +37,6 @@ /* Link Definitions */ #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 @@ -50,9 +48,6 @@ */ #define CPU_RELEASE_ADDR secondary_boot_addr -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* GPIO */ #ifdef CONFIG_DM_GPIO #ifndef CONFIG_MPC8XXX_GPIO @@ -61,9 +56,6 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#endif /* Serial Port */ @@ -147,7 +139,6 @@ unsigned long long get_qixis_addr(void); #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* SATA */ #ifdef CONFIG_SCSI diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 78ccc2d..a7d8cb5 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -11,7 +11,6 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_TFABOOT @@ -23,14 +22,9 @@ unsigned long get_board_ddr_clk(void); #define SYS_NO_FLASH #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #else #define CONFIG_QIXIS_I2C_ACCESS -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_EARLY_INIT -#endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #endif #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) @@ -38,9 +32,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -335,13 +326,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index ad3043b..4a61345 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -17,18 +17,12 @@ #endif #define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -#define CONFIG_DDR_SPD #ifdef CONFIG_EMU #define CONFIG_SYS_FSL_DDR_EMU -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 #else -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif #define SPD_EEPROM_ADDRESS 0x51 @@ -241,13 +235,8 @@ #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4527336..770f2aa 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -8,7 +8,6 @@ #define __LS2_COMMON_H #define CONFIG_REMAKE_ELF -#define CONFIG_GICV3 #include <asm/arch/stream_id_lsch3.h> #include <asm/arch/config.h> @@ -24,8 +23,6 @@ /* Link Definitions */ -#define CONFIG_SKIP_LOWLEVEL_INIT - #ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_DDR_RAW_TIMING #endif @@ -63,9 +60,6 @@ */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* GPIO */ #ifdef CONFIG_DM_GPIO #ifndef CONFIG_MPC8XXX_GPIO @@ -74,9 +68,6 @@ #endif /* I2C */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#endif /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -157,7 +148,6 @@ unsigned long long get_qixis_addr(void); #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* Physical Memory Map */ /* fixme: these need to be checked against the board */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 8bfe4b9..e831d37 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -11,25 +11,17 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FSL_QSPI #define CONFIG_QIXIS_I2C_ACCESS -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_EARLY_INIT -#endif #define CONFIG_SYS_I2C_IFDR_DIV 0x7e #endif #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -304,13 +296,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index bfbde1d..5568a48 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -13,9 +13,6 @@ #ifdef CONFIG_TARGET_LS2081ARDB #define CONFIG_QIXIS_I2C_ACCESS #endif -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_EARLY_INIT -#endif #endif #define I2C_MUX_CH_VOL_MONITOR 0xa @@ -39,12 +36,8 @@ unsigned long get_board_sys_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ 133333333 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -286,13 +279,8 @@ unsigned long get_board_sys_clk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_FSL_MEMAC diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index a4a4739..7294a3c 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -12,10 +12,8 @@ */ #if defined(CONFIG_LSCHLV2) #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg -#define CONFIG_MACH_TYPE 3006 #elif defined(CONFIG_LSXHL) #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg -#define CONFIG_MACH_TYPE 2663 #else #error "unknown board" #endif @@ -26,8 +24,6 @@ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - #define CONFIG_KIRKWOOD_GPIO #include "mv-common.h" @@ -45,7 +41,6 @@ /* * Default environment variables */ -#define CONFIG_LOADADDR 0x00800000 #if defined(CONFIG_LSXHL) #define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1ae7d37..4db19e2 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -12,15 +12,12 @@ #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 #define CONFIG_FSL_MEMAC #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SKIP_LOWLEVEL_INIT - /* DDR */ #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ @@ -30,9 +27,6 @@ #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 @@ -49,7 +43,6 @@ #define CONFIG_SYS_MONITOR_LEN (936 * 1024) /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* SMP Definitinos */ #define CPU_RELEASE_ADDR secondary_boot_addr @@ -62,9 +55,6 @@ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - /* Serial Port */ #define CONFIG_PL01X_SERIAL #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) @@ -110,13 +100,8 @@ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Qixis */ #define CONFIG_FSL_QIXIS @@ -157,11 +142,9 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) #define CONFIG_HWCONFIG diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index ea1b163..30b044b 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -34,13 +34,8 @@ u8 qixis_esdhc_detect_quirk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 097f122..ebe5004 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -30,13 +30,8 @@ #define I2C_EMC2305_PWM 0x80 /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 847534c..7fa3c25 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -38,13 +38,8 @@ u8 qixis_esdhc_detect_quirk(void); #endif /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index bd117da..813d326 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -11,7 +11,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_REVISION_TAG #define CONFIG_SYS_FSL_CLK #define CONFIG_TIMESTAMP /* Print image info with timestamp */ @@ -24,7 +23,6 @@ #define PHYS_SDRAM_2 CSD1_BASE_ADDR #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) @@ -84,17 +82,7 @@ #define CONFIG_ETHPRIME "FEC0" #endif -/* - * I2C - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ -#endif /* * RTC @@ -141,14 +129,8 @@ /* * Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTFILE "boot/fitImage" -#define CONFIG_LOADADDR 0x70800000 #define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* * NAND SPL diff --git a/include/configs/malta.h b/include/configs/malta.h index 9602773..8ace0cc 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -38,9 +38,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000) - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index fc23932..53ba649 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -6,6 +6,8 @@ #ifndef _CONFIG_DB_MV7846MP_GP_H #define _CONFIG_DB_MV7846MP_GP_H +#include <linux/sizes.h> + /* * High Level Configuration Options (easy to change) */ @@ -17,11 +19,7 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* SPI NOR flash default params, used by sf commands */ @@ -65,7 +63,7 @@ /* SPL related SPI defines */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ +#define CONFIG_SYS_SDRAM_SIZE SZ_1G #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 0c383e9..a080322 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -25,9 +25,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "fitImage" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index f43a841..ac9a75b 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -14,10 +14,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index bd4bac7..3457c59 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -32,12 +32,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ /* Misc CPU related */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ /* * Hardware drivers @@ -58,8 +52,6 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) - /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, * leaving the correct space for initial global data structure above @@ -100,10 +92,4 @@ #define CONFIG_SYS_CBSIZE 512 -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - 128*1024, 0x1000) - #endif diff --git a/include/configs/meson64.h b/include/configs/meson64.h index f9bb024..b779363 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -32,14 +32,10 @@ #define CONFIG_CPU_ARMV8 #define CONFIG_REMAKE_ELF #define CONFIG_SYS_MAXARGS 32 -#ifndef CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_MALLOC_LEN (32 << 20) -#endif #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_SYS_INIT_SP_ADDR 0x20000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index 358e0a5..fb3ccc3 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -11,8 +11,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_MALLOC_LEN SZ_128M - #ifndef BOOT_PARTITION #define BOOT_PARTITION "boot" #endif diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 59b20cf..e7882fb 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -24,8 +24,6 @@ /* setting reset address */ /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ -#define CONFIG_SYS_MALLOC_LEN 0xC0000 - /* Stack location before relocation */ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_F_LEN) @@ -55,8 +53,6 @@ #define CONFIG_SYS_CBSIZE 512 /* max number of command args */ #define CONFIG_SYS_MAXARGS 15 -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0 #define CONFIG_HOSTNAME "microblaze-generic" diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 2499037..655c8d6 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -12,10 +12,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index 4d074a3..b05ac0a 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -13,11 +13,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x100000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x80010000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 @@ -30,9 +28,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index f015d10..97fcf2f 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_CBSIZE SZ_1K #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Uboot definition */ @@ -27,10 +25,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ GENERATED_GBL_DATA_SIZE) -/* UBoot -> Kernel */ -#define CONFIG_LOADADDR 0x4007ff28 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 9895279..6023f81 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -12,9 +12,6 @@ #include <linux/sizes.h> /* Miscellaneous configurable options */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG #define CONFIG_SYS_MAXARGS 8 #define CONFIG_SYS_BOOTM_LEN SZ_64M @@ -22,8 +19,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ @@ -32,10 +27,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ GENERATED_GBL_DATA_SIZE) -/* UBoot -> Kernel */ -#define CONFIG_LOADADDR 0x84000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* MMC */ #define MMC_SUPPORTS_TUNING diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index c6752f4..e53e6a0 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -13,11 +13,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x100000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x80010000 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 @@ -27,7 +25,7 @@ #define CONFIG_SYS_CBSIZE 1024 /* Serial SPL */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 #define CONFIG_SYS_NS16550_REG_SIZE -4 @@ -39,9 +37,6 @@ 230400, 460800, 921600 } /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 08a4d01..c58545b 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -12,9 +12,6 @@ #include <linux/sizes.h> /* Miscellaneous configurable options */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG #define CONFIG_SYS_MAXARGS 8 #define CONFIG_SYS_BOOTM_LEN SZ_64M @@ -22,8 +19,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_NONCACHED_MEMORY SZ_1M /* Environment */ @@ -43,8 +38,6 @@ /* UBoot -> Kernel */ #define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000 -#define CONFIG_LOADADDR 0x42007f1c -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index 8e7afbb..ebd2b32 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -11,9 +11,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN SZ_4M - #define CONFIG_CPU_ARMV8 #define COUNTER_FREQUENCY 13000000 diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index 7cd388f..8882a5a 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -17,10 +17,6 @@ #define COUNTER_FREQUENCY 13000000 -#define CONFIG_SYS_LOAD_ADDR 0x41000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Uboot definition */ diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index a1c5d81..12840b8 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -11,9 +11,6 @@ #include <linux/sizes.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN SZ_4M - #define CONFIG_CPU_ARMV8 #define COUNTER_FREQUENCY 13000000 diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 4e32442..593c6a1 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -21,10 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_SYS_LOAD_ADDR 0x41000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_BOOTM_LEN SZ_64M /* Uboot definition */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 6036bf4..e460f69 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -50,26 +50,11 @@ /* auto boot */ -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */ - -/* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h index 486650f..d38d987 100644 --- a/include/configs/mv-plug-common.h +++ b/include/configs/mv-plug-common.h @@ -11,7 +11,6 @@ * High Level Configuration Options (easy to change) */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index c8c34d7..755f59e 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -25,26 +25,11 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - -/* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x06000000 /* default load adr */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ @@ -55,7 +40,6 @@ * I2C */ #define CONFIG_I2C_MV -#define CONFIG_SYS_I2C_SLAVE 0x0 /* * Environment diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 493e3de..beecf18 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -19,26 +19,11 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - -/* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 2ee41ae..b0c78d3 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -5,9 +5,6 @@ #ifndef __CONFIGS_MX23_OLINUXINO_H__ #define __CONFIGS_MX23_OLINUXINO_H__ -/* System configurations */ -#define CONFIG_MACH_TYPE 4105 - /* U-Boot Commands */ /* Memory configuration */ @@ -27,8 +24,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 3f13e60..1f40d98 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -8,9 +8,6 @@ #ifndef __CONFIGS_MX23EVK_H__ #define __CONFIGS_MX23EVK_H__ -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK - /* U-Boot Commands */ /* Memory configuration */ @@ -36,8 +33,6 @@ /* Boot Linux */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 21f3277..10292c8 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -10,9 +10,6 @@ #ifndef __CONFIGS_MX28EVK_H__ #define __CONFIGS_MX28EVK_H__ -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK - /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ @@ -50,8 +47,6 @@ /* Boot Linux */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3574d65..9cc297d 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -16,17 +16,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - /* * Hardware drivers */ @@ -35,7 +24,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ -#define CONFIG_POWER #define CONFIG_POWER_SPI #define CONFIG_POWER_FSL #define CONFIG_FSL_PMIC_BUS 0 @@ -61,8 +49,6 @@ #define CONFIG_ETHPRIME "FEC0" -#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -140,8 +126,6 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 93158fb..f03e425 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -14,17 +14,8 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #define CONFIG_SYS_FSL_CLK -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - -#define CONFIG_REVISION_TAG - #define CONFIG_MXC_UART_BASE UART2_BASE #define CONFIG_FPGA_COUNT 1 @@ -43,8 +34,6 @@ /* Command definition */ -#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ @@ -72,8 +61,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index e69130d..b026c6f 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -9,21 +9,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO - #include <asm/arch/imx-regs.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #define CONFIG_SYS_FSL_CLK -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_REVISION_TAG - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -35,16 +24,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - /* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_DIALOG_POWER #define CONFIG_POWER_FSL #define CONFIG_POWER_FSL_MC13892 @@ -56,8 +36,6 @@ #define CONFIG_ETHPRIME "FEC0" -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -132,8 +110,6 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index b1e6a56..b623242 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -11,17 +11,8 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #define CONFIG_SYS_FSL_CLK -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_REVISION_TAG - /* USB Configs */ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX @@ -33,8 +24,6 @@ /* Command definition */ -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ - #define PPD_CONFIG_NFS \ "nfsserver=192.168.252.95\0" \ "gatewayip=192.168.252.95\0" \ @@ -102,11 +91,11 @@ "video-mode=" \ "lcd:800x480-24@60,monitor=lcd\0" \ -#define CONFIG_MMCBOOTCOMMAND \ +#define MMCBOOTCOMMAND \ "run doquiet; " \ "run tryboot; " \ -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND +#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND #define CONFIG_ARP_TIMEOUT 200UL @@ -116,8 +105,6 @@ #define CONFIG_SYS_MAXARGS 48 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ /* Physical Memory Map */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index a4504ee..5c0b729 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -33,22 +33,6 @@ #define CONFIG_SYS_FSL_CLK -/* ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Boot options */ -#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ - defined(CONFIG_MX6SX) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define CONFIG_LOADADDR 0x82000000 -#else -#define CONFIG_LOADADDR 0x12000000 -#endif -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 32 diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 9e5083b..da25336 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -13,8 +13,6 @@ #include "imx6_spl.h" -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR @@ -46,9 +44,9 @@ "fdtfile=undefined\0" \ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 120297d..42d5e24 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -13,8 +13,6 @@ #include "mx6_common.h" #include "imx6_spl.h" -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) - #ifdef CONFIG_SERIAL_CONSOLE_UART1 #if defined(CONFIG_MX6SL) #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index ac579f3..51f6b3a 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -12,9 +12,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -52,7 +49,7 @@ "dfu_alt_info=spl raw 0x400\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 626dbd5..5cd51a4 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -12,7 +12,6 @@ #include "imx6_spl.h" #endif -#define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" @@ -50,14 +49,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -67,8 +58,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 9546887..9a9f588 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -12,7 +12,6 @@ #include "imx6_spl.h" #endif -#define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" @@ -37,17 +36,7 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ab32f4e..e8fd212 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -14,23 +14,11 @@ #include "imx6_spl.h" #endif -#define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index a38ce4d..f2bddd1 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -10,20 +10,8 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE -/* I2C Configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 58cc3f0..62b8de3 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -10,9 +10,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -106,13 +103,6 @@ /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 036881f..1237dde 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -16,9 +16,6 @@ #include "imx6_spl.h" #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX @@ -140,13 +137,6 @@ /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* Network */ #define CONFIG_FEC_MXC diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 7d36c1e..ff2ad09 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -18,9 +18,6 @@ /* SPL options */ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -36,14 +33,6 @@ #endif -/* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -56,7 +45,7 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ @@ -135,7 +124,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 23f6de9..247d5e1 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -16,9 +16,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -33,14 +30,6 @@ #endif #endif -/* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -132,7 +121,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 3d87690..eeb535e 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -28,8 +28,6 @@ /* Enable iomux-lpsr support */ #define CONFIG_IOMUX_LPSR -#define CONFIG_LOADADDR 0x80800000 - /* Miscellaneous configurable options */ #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 32 @@ -49,10 +47,5 @@ * launched by OPTEE, because of that we shall skip all the low level * initialization since it was already done by ATF or OPTEE */ -#if (CONFIG_OPTEE_TZDRAM_SIZE != 0) -#ifndef CONFIG_OPTEE -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#endif #endif diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 5801da0..42b729b 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -14,16 +14,9 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #ifdef CONFIG_IMX_BOOTAUX @@ -79,11 +72,11 @@ "fdtfile=imx7d-sdb.dtb\0" \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x83100000\0" \ "ramdiskaddr=0x83100000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ BOOTENV @@ -94,7 +87,6 @@ #include <config_distro_bootcmd.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 28672c4..48172de 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -32,13 +32,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -47,8 +40,6 @@ #define PHYS_SDRAM 0x60000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_LOADADDR 0x60800000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "console=ttyLP0\0" \ @@ -74,8 +65,6 @@ "run mmcboot; " \ "fi; " \ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 0c31030..567a037 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -22,19 +22,9 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -/*#define CONFIG_REVISION_TAG*/ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - /* UART */ #define LPUART_BASE LPUART4_RBASE -#define CONFIG_SYS_CACHELINE_SIZE 64 - /* Miscellaneous configurable options */ #define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 512 @@ -47,8 +37,6 @@ #define PHYS_SDRAM_SIZE SZ_1G #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_LOADADDR 0x60800000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -125,7 +113,6 @@ "fi" #define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE SZ_256K diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 325c3ee..64f017a 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -50,7 +50,6 @@ #endif /* Memory sizes */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 @@ -85,10 +84,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot argument buffer size */ -/* Booting Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - /* * Drivers */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 5ef16fb..04c9879 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -15,16 +15,12 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 1fd5471..be02220 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -12,16 +12,10 @@ #define _CONFIG_NAS220_H /* - * Machine type ID - */ -#define CONFIG_MACH_TYPE MACH_TYPE_RD88F6192_NAS - -/* * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ #define CONFIG_KW88F6192 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ /* power-on led, regulator, sata0, sata1 */ #define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 0c40750..cd53c49 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -11,22 +11,11 @@ #include "mx6_common.h" -#define CONFIG_MACH_TYPE 3769 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - #define CONFIG_USBD_HS #define CONFIG_MXC_UART_BASE UART2_BASE /* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID /* MMC Configs */ @@ -90,14 +79,6 @@ #define DISTRO_BOOT_DEV_DHCP(func) #endif - -#if defined(CONFIG_SABRELITE) -#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0" -#else -/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */ -#define FDTFILE -#endif - #define BOOT_TARGET_DEVICES(func) \ DISTRO_BOOT_DEV_MMC(func) \ DISTRO_BOOT_DEV_SATA(func) \ @@ -113,10 +94,10 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ - FDTFILE \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" __stringify(CONFIG_DEFAULT_DEVICE_TREE) ".dtb\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ "ip_dyn=yes\0" \ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 7ef25ea..b37e054 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -23,8 +23,6 @@ */ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ -#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 - #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> #include <asm/arch/mem.h> @@ -34,19 +32,7 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */ - -#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */ -#define CONFIG_INITRD_TAG /* enable passing initrd */ -#define CONFIG_REVISION_TAG /* enable passing revision tag*/ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - -/* - * Size of malloc() pool - */ #define CONFIG_UBI_SIZE (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ - (128 << 10)) /* * Hardware drivers @@ -188,9 +174,6 @@ int rx51_kp_getc(struct stdio_dev *sdev); "run attachboot;" \ "echo" -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - /* * OMAP3 has 12 GP timers, they can be driven by the system clock * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). diff --git a/include/configs/novena.h b/include/configs/novena.h index 3876412..46c5301 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -41,8 +41,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) - /* SPL */ #include "imx6_spl.h" /* common IMX6 SPL configuration */ @@ -52,20 +50,10 @@ #endif /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_SPD_BUS_NUM 0 /* I2C EEPROM */ -#ifdef CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 -#endif /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 @@ -80,8 +68,6 @@ #endif /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 @@ -115,9 +101,9 @@ "bootdev=/dev/mmcblk0p1\0" \ "rootdev=/dev/mmcblk0p2\0" \ "netdev=eth0\0" \ - "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ - "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ - "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "pxefile_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "scriptaddr="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ "ramdisk_addr_r=0x28000000\0" \ "fdt_addr_r=0x18000000\0" \ "fdtfile=imx6q-novena.dtb\0" \ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 3be9b8f..70e2898 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -15,9 +15,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 -/* Size of malloc() poll */ -#define CONFIG_SYS_MALLOC_LEN SZ_2M - /* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE @@ -26,7 +23,6 @@ #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 23cf94e..950549c 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -13,7 +13,6 @@ #define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ #define CONFIG_KW88F6192 1 /* SOC Name */ #define CONFIG_KW88F6702 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/nsim.h b/include/configs/nsim.h index 61217bb..62169af 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -20,15 +20,12 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_2M #define CONFIG_SYS_BOOTM_LEN SZ_32M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* * Console configuration diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 394fb15..3584d9a 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -26,9 +26,6 @@ /* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) -#undef CONFIG_LOADADDR -#define CONFIG_LOADADDR 0x82408000 - #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index b9746b9..72515a3 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -6,7 +6,6 @@ #include "mx6_common.h" -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 109ef40..23bb4f6 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -8,19 +8,15 @@ #define __OCTEON_COMMON_H__ #if defined(CONFIG_RAM_OCTEON) -#define CONFIG_SYS_MALLOC_LEN (16 << 20) #define CONFIG_SYS_INIT_SP_OFFSET 0x20100000 #else /* No DDR init -> run in L2 cache with limited resources */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 #endif #define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20)) - #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 2800896..5e1c007 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -18,11 +18,6 @@ /** Stack starting address */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) -/** Heap size for U-Boot */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - #define CONFIG_LAST_STAGE_INIT /* Allow environment variable to be overwritten */ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 0e4a176..3ceedef 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -44,9 +44,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) /** Heap size for U-Boot */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Allow environment variable to be overwritten */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 1367d13..281922a 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -19,8 +19,6 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif -#define CONFIG_MACH_TYPE 4289 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE @@ -28,9 +26,6 @@ #define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) #define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - #include <linux/sizes.h> #define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" @@ -174,6 +169,4 @@ */ #define CONFIG_MISC_COMMON -#undef CONFIG_REVISION_TAG - #endif /* __CONFIG_H */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index fc70dc6..70481b5 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -75,7 +75,6 @@ /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ #define CONFIG_ODROID_REV_AIN 9 -#define CONFIG_REVISION_TAG /* * Need to override existing one (smdk5420) with odroid so set_board_info will diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 6563335..5d300b1 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -18,11 +18,6 @@ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 2ce3c86..b12e3a4 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -23,11 +23,6 @@ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 8dc30be..0fee2ed 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -16,8 +16,6 @@ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). */ -#define CONFIG_REVISION_TAG 1 - /* TPS65950 */ #define PBIASLITEVMODE1 (1 << 8) diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index dd0ea2d..886f2e9 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -20,15 +20,9 @@ * order to allow for BCH8 to fit in. */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - /* Hardware drivers */ /* I2C */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ #ifdef CONFIG_SPL_BUILD #undef CONFIG_USB_EHCI_OMAP diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 462aa4a..fb210ce 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -15,7 +15,6 @@ /* * High Level Configuration Options */ -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP #include <configs/ti_omap4_common.h> diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index a37359e..f60d15b 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -23,12 +23,10 @@ #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* * Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ @@ -161,7 +159,6 @@ #define CONFIG_BOOTFILE "zImage" /* Boot file name */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) /* * USB Configs @@ -173,9 +170,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_BOOTCOMMAND \ "run envboot; " \ "run mmcboot; " diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 42c64f3..a24b134 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -16,8 +16,6 @@ /* Environment options */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32M) -#define CONFIG_SYS_LOAD_ADDR 0x87000000 -#define CONFIG_SYS_MALLOC_LEN SZ_256M #define CONFIG_SYS_BOOTM_LEN SZ_256M #ifdef CONFIG_SPL diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 03b9393..56bfe87 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -18,7 +18,6 @@ */ #define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ #define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 2fb1634..33bc30e 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -18,9 +18,6 @@ #endif #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 << 20) - /* Miscellaneous configurable options */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR @@ -78,7 +75,7 @@ "mmcrootfstype=ext4 rootwait\0" \ "kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \ "splashpos=0,0\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ "check_env=if test -n ${flash_env_version}; " \ "then env default env_version; " \ diff --git a/include/configs/origen.h b/include/configs/origen.h index 8a0e145..881df2d 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -19,11 +19,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN - #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ #define CONFIG_SYS_MONITOR_BASE 0x00000000 diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index 4ef9e8e..9645321 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -16,10 +16,7 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY (24000000) /* 24MHz */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - /* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0) /* * This is the initial SP which is used only briefly for relocating the u-boot diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 54c82b4..49dbbf0 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -157,7 +157,6 @@ #else #define CONFIG_SYS_CLK_FREQ 66666666 #endif -#define CONFIG_DDR_CLK_FREQ 66666666 #define CONFIG_HWCONFIG /* @@ -179,7 +178,6 @@ /* DDR Setup */ #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 @@ -346,7 +344,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ #define CONFIG_SYS_CPLD_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT @@ -464,36 +461,20 @@ /* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 #endif -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ /* * I2C2 EEPROM */ -#undef CONFIG_ID_EEPROM #define CONFIG_RTC_PT7C4338 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 /* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #if defined(CONFIG_PCI) /* @@ -607,7 +588,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -629,9 +609,6 @@ #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #ifdef __SW_BOOT_NOR #define __NOR_RST_CMD \ norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ @@ -691,7 +668,7 @@ __stringify(__SD_RST_CMD)"\0" \ __stringify(__NAND_RST_CMD)"\0" \ __stringify(__PCIE_RST_CMD)"\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ @@ -700,7 +677,7 @@ __stringify(__PCIE_RST_CMD)"\0" "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_HDBOOT \ +#define HDBOOT \ "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ "console=$consoledev,$baudrate $othbootargs;" \ "usb start;" \ @@ -733,7 +710,7 @@ __stringify(__PCIE_RST_CMD)"\0" "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ "bootm $norbootaddr - $norfdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs " \ "ramdisk_size=$ramdisk_size;" \ @@ -742,6 +719,6 @@ __stringify(__PCIE_RST_CMD)"\0" "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT +#define CONFIG_BOOTCOMMAND HDBOOT #endif /* __CONFIG_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 7a09ac0..c12f4d0 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -19,8 +19,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 4f4d501..f29f6dc 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -24,9 +24,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE @@ -36,7 +33,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 6009521..c1da1a0 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -18,9 +18,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - /* Environment settings */ /* Environment in SD */ @@ -36,14 +33,9 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 960ff98..5b2e084 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -12,21 +12,11 @@ #include <linux/sizes.h> #include <linux/stringify.h> -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_LOADADDR 0x82000000 - /* We boot from the gfxRAM area of the OCRAM. */ #define CONFIG_BOARD_SIZE_LIMIT 520192 @@ -139,8 +129,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Physical memory map */ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index bc48e80..3ca0377 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -14,9 +14,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - /* Enable NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 53342ce..3d18747 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -14,9 +14,6 @@ /* Using 32K of volatile storage for environment */ -#define MACH_TYPE_PDU001 5075 -#define CONFIG_MACH_TYPE MACH_TYPE_PDU001 - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index 4a347fe..4925fcc 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -14,8 +14,6 @@ #include <configs/ti_am335x_common.h> -#define CONFIG_MACH_TYPE MACH_TYPE_SBC_PHYCORE_AM335X - #ifdef CONFIG_MTD_RAW_NAND #define NANDARGS \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index fd69dc4..8d1fd15 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -82,8 +82,6 @@ "fi;" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K @@ -94,8 +92,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM SZ_1G @@ -117,9 +113,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* ENET1 */ #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 58ead45..874c94e 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -29,12 +29,8 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PCA9450 -#define CONFIG_SYS_I2C_LEGACY - #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -84,8 +80,6 @@ "fi;" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K @@ -96,8 +90,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 @@ -117,7 +109,4 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* I2C */ -#define CONFIG_SYS_I2C_SPEED 100000 - #endif /* __PHYCORE_IMX8MP_H */ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index d50edc7..a83e49f 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -28,13 +28,11 @@ /* SDRAM Configuration (for final code, data, stack, heap) */ #define CONFIG_SYS_SDRAM_BASE 0x88000000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) #define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (192 << 10) -#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */ #define CONFIG_SYS_ENV_ADDR 0x88300000 #define CONFIG_SYS_FDT_ADDR 0x89d00000 diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 6199f0d..4e72caa 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -24,9 +24,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ @@ -94,11 +91,11 @@ "run base_boot;" \ "fi; \0" \ "base_boot=run findfdt; run finduuid; run distro_bootcmd\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 04a2531..7e36cee 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -33,9 +33,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1 #define CONFIG_FEC_XCV_TYPE RMII -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - #define CONFIG_MXC_UART_BASE UART6_BASE_ADDR /* MMC Configs */ @@ -82,11 +79,11 @@ BOOTMENU_ENV \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x83000000\0" \ "ramdiskaddr=0x83000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "mmcautodetect=yes\0" \ CONFIG_DFU_ENV_SETTINGS \ "findfdt=" \ @@ -111,7 +108,6 @@ #include <config_distro_bootcmd.h> #include <linux/stringify.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -126,10 +122,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - /* environment organization */ /* Environment starts at 768k = 768 * 1024 = 786432 */ /* diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index f5d2c23..36c5792 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -24,9 +24,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ @@ -74,7 +71,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "console=ttymxc4\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -82,11 +79,11 @@ "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x83000000\0" \ "ramdiskaddr=0x83000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ CONFIG_DFU_ENV_SETTINGS \ "findfdt=" \ "if test $fdtfile = ask ; then " \ @@ -110,7 +107,6 @@ #include <config_distro_bootcmd.h> #include <linux/stringify.h> -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -125,18 +121,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* I2C configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 89b3d27..d858a7e 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -25,7 +25,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_GPIO -#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_MMC #define CONFIG_SPL_BSS_START_ADDR 0x00180000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 @@ -38,17 +38,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE #undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC - -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#define CONFIG_POWER -#define CONFIG_POWER_I2C #endif #define CONFIG_REMAKE_ELF @@ -121,9 +110,6 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 @@ -134,9 +120,6 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ @@ -163,15 +146,8 @@ #define CONFIG_MXC_GPIO -/* I2C Configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - #define CONFIG_OF_SYSTEM_SETUP -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_PMIC -#endif - #define CONFIG_SYS_BOOTM_LEN SZ_128M #endif diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 382d19a..d530107 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -25,10 +25,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" - -#define CONFIG_MACH_TYPE MACH_TYPE_PM9261 - /* clocks */ /* CKGR_MOR - enable main osc. */ #define CONFIG_SYS_MOR_VAL \ @@ -128,12 +124,6 @@ AT91_WDT_MR_WDDIS | \ AT91_WDT_MR_WDD(0xfff)) -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#undef CONFIG_SKIP_LOWLEVEL_INIT - /* * Hardware drivers */ @@ -182,8 +172,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - #undef CONFIG_SYS_USE_DATAFLASH_CS0 #undef CONFIG_SYS_USE_NANDFLASH #define CONFIG_SYS_USE_FLASH 1 @@ -233,12 +221,6 @@ #error "Undefined memory device" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ GENERATED_GBL_DATA_SIZE) diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index e825270..c13f8de 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -25,10 +25,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" - -#define CONFIG_MACH_TYPE MACH_TYPE_PM9263 - /* clocks */ #define CONFIG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ @@ -140,11 +136,6 @@ AT91_WDT_MR_WDDIS | \ AT91_WDT_MR_WDD(0xfff)) -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#undef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_USER_LOWLEVEL_INIT 1 /* @@ -213,8 +204,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #define CONFIG_SYS_USE_FLASH 1 #undef CONFIG_SYS_USE_DATAFLASH #undef CONFIG_SYS_USE_NANDFLASH @@ -266,11 +255,6 @@ #error "Undefined memory device" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ GENERATED_GBL_DATA_SIZE) diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 452fbda..c22f698 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -19,11 +19,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -57,8 +52,6 @@ #define CONFIG_RESET_PHY_R #define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_NAND_BOOT /* bootstrap + u-boot + env in nandflash */ @@ -73,12 +66,6 @@ "bootz 0x72000000 - 0x71000000" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - 128 * 1024, 0x1000) - /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE 0x010000 #define CONFIG_SPL_STACK 0x310000 diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index cbe5022..f49bcfb 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -13,16 +13,10 @@ #define _CONFIG_POGO_E02_H /* - * Machine type definition and ID - */ -#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02 - -/* * High Level Configuration Options (easy to change) */ #define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ #define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #include "mv-common.h" diff --git a/include/configs/poplar.h b/include/configs/poplar.h index 9763218..222a14b 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -18,8 +18,6 @@ /* SYS */ #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_SYS_INIT_SP_ADDR 0x200000 -#define CONFIG_SYS_LOAD_ADDR 0x800000 -#define CONFIG_SYS_MALLOC_LEN SZ_32M /* ATF bl33.bin load address (must match) */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 3f92621..8606eb1 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -23,13 +23,9 @@ /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE * does not yet support DT. Thus define it here. */ -#define CONFIG_GICV2 #define GICD_BASE 0xf7011000 #define GICC_BASE 0xf7012000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) - #define CONFIG_SYS_TIMER_BASE 0xf4321000 /* Use external clock source */ @@ -48,7 +44,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000) #define CONFIG_LAST_STAGE_INIT /* SDRAM Bank #1 */ diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h index f52ea01..23de326 100644 --- a/include/configs/puma_rk3399.h +++ b/include/configs/puma_rk3399.h @@ -10,6 +10,4 @@ #define SDRAM_BANK_SIZE (2UL << 30) -#define CONFIG_SERIAL_TAG - #endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 76d6ab1..0992387 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_NS16550_MEM32 @@ -20,7 +19,6 @@ #define CONFIG_IRAM_BASE 0xff020000 #define CONFIG_SYS_INIT_SP_ADDR 0x00400000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0x00400000 #define CONFIG_SPL_MAX_SIZE 0x20000 #define CONFIG_SPL_BSS_START_ADDR 0x4000000 diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 4673390..a333326 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_PXM2_H #define __CONFIG_PXM2_H -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2 - #include "siemens-am33x-common.h" #define DDR_IOCTRL_VAL 0x18b @@ -32,10 +30,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - #define CONFIG_FACTORYSET #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 273fa1a..bb4240a 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -14,8 +14,6 @@ /* The DTB generated by QEMU is placed at start of RAM, stay away from there */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_MALLOC_LEN SZ_16M #define CONFIG_SYS_BOOTM_LEN SZ_64M diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index b2e1204..f79e0fe 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -69,7 +69,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) #define CONFIG_LBA48 @@ -85,7 +84,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -102,9 +100,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - #define CONFIG_BOOTCOMMAND \ "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr\0" diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index bbeea96..ae57f68 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -21,10 +21,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 61b6fb4..36930fa 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -15,12 +15,9 @@ #define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) /* Address of u-boot image in Flash */ #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_MONITOR_LEN (256 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 7f12844..de8ea8b 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -34,10 +34,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index f94e9d8..595482c 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -10,10 +10,6 @@ #include <asm/arch/rmobile.h> -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #ifdef CONFIG_SPL #define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" #endif @@ -28,12 +24,9 @@ #define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x50000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) /* ENV setting */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 99ef27b..2b3e1bb 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -21,12 +21,7 @@ /* boot option */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 #define GICD_BASE 0xF1010000 #define GICC_BASE 0xF1020000 @@ -45,14 +40,11 @@ #define DRAM_RSV_SIZE 0x08000000 #define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x58000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_SYS_MONITOR_BASE 0x00000000 #define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* The HF/QSPI layout permits up to 1 MiB large bootloader blob */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 7f148ef..b133d8e 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 @@ -17,7 +16,6 @@ #define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SPL_STACK 0x10081fff #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 7c064a0..8b7a0bb 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 @@ -20,7 +19,6 @@ #define CONFIG_IRAM_BASE 0x10080000 #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 3bcc048..e7c0964 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -6,19 +6,15 @@ #ifndef __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #define CONFIG_SYS_CBSIZE 1024 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ #endif #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) #define CONFIG_ROCKCHIP_CHIP_TAG "RK31" diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 7e0c831..a46b1ff 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,7 +8,6 @@ #include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ @@ -18,7 +17,6 @@ #define CONFIG_SYS_HZ_CLOCK 24000000 #define CONFIG_SYS_INIT_SP_ADDR 0x61100000 -#define CONFIG_SYS_LOAD_ADDR 0x61800800 #define CONFIG_SPL_MAX_SIZE 0x100000 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index addad7a..abbb273 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */ -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 @@ -23,7 +22,6 @@ /* Bootrom will load u-boot binary to 0x0 once return from SPL */ #endif #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 #define CONFIG_IRAM_BASE 0xff700000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index bd9ac82..edaf78a 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -25,7 +24,6 @@ #define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 #define CONFIG_IRAM_BASE 0xfff80000 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 -#define CONFIG_SYS_LOAD_ADDR 0x00C00800 #define CONFIG_SPL_STACK 0x00400000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 0538da7..c1e26a0 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -14,10 +14,8 @@ #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0x00400000 #define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_BSS_START_ADDR 0x2000000 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index fbbb8cf..8b239ca 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -8,15 +8,12 @@ #include "rockchip-common.h" -#define CONFIG_SYS_CACHELINE_SIZE 64 - #include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h> #define CONFIG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 #define COUNTER_FREQUENCY 24000000 @@ -24,7 +21,6 @@ #define CONFIG_IRAM_BASE 0xff8c0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_MAX_SIZE 0x40000 #define CONFIG_SPL_BSS_START_ADDR 0x400000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 6d710da..ed72c8b 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define COUNTER_FREQUENCY 24000000 #define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 @@ -17,7 +16,6 @@ #define CONFIG_IRAM_BASE 0xff8c0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) #define CONFIG_SPL_STACK 0x00400000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index b656891..afe5050 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define COUNTER_FREQUENCY 24000000 #define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020 @@ -17,7 +16,6 @@ #define CONFIG_IRAM_BASE 0xfdcc0000 #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 -#define CONFIG_SYS_LOAD_ADDR 0x00c00800 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ #define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 522b41c..55768a4 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -13,10 +13,6 @@ #include <asm/arch/base.h> #endif -#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - /* Architecture, CPU, etc.*/ /* Use SoC timer for AArch32, but architected timer for AArch64 */ @@ -26,21 +22,6 @@ (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) #endif -/* - * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, - * so 2708 has historically been used rather than a dedicated 2835 ID. - * - * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation - * chose to use someone else's previously registered machine ID (3139, MX51_GGC) - * rather than obtaining a valid ID:-/ - * - * For the bcm2837, hopefully a machine type is not needed, since everything - * is DT. - */ -#ifdef CONFIG_BCM2835 -#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 -#endif - /* Memory layout */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE @@ -54,8 +35,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ CONFIG_SYS_SDRAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_LOADADDR 0x00200000 #ifdef CONFIG_ARM64 #define CONFIG_SYS_BOOTM_LEN SZ_64M @@ -88,15 +67,9 @@ #define CONFIG_SYS_CBSIZE 1024 /* Environment */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* Shell */ -/* ATAGs support for bootm/bootz */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial,usbkbd\0" \ diff --git a/include/configs/rut.h b/include/configs/rut.h index 6694003..68d68d0 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_RUT_H #define __CONFIG_RUT_H -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT - #include "siemens-am33x-common.h" #define RUT_IOCTRL_VAL 0x18b @@ -23,14 +21,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ - #define CONFIG_FACTORYSET /* Watchdog */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 758e85e..d0f70b0 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -11,7 +11,6 @@ #define CONFIG_IRAM_BASE 0x10080000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ @@ -20,7 +19,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) /* rockchip ohci host driver */ #define CONFIG_USB_OHCI_NEW diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 1e2180b..c482de1 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -60,12 +60,9 @@ */ #define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - #define BMP_LOAD_ADDR 0x78000000 /* kernel load address */ -#define CONFIG_SYS_LOAD_ADDR 0x71080000 #define INITRD_START 0x79000000 #define KERNEL_DTB_ADDR 0x7A000000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 6af6009..b4a3cc0 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -26,14 +26,6 @@ /* Text Base */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_INITRD_TAG - -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - /* MMC */ #define SDHCI_MAX_HOSTS 4 @@ -138,8 +130,6 @@ "dfu_alt_info=" CONFIG_DFU_ALT "\0" #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) /* Goni has 3 banks of DRAM, but swap the bank */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 0b679f4..ff29de0 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -31,9 +31,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ #define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT @@ -44,16 +41,6 @@ ",100M(swap)"\ ",-(UMS)\0" -#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7" -#define CONFIG_BOOTBLOCK "10" -#define CONFIG_UBIBLOCK "9" - -#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc " -#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \ - "${mtdparts}" - -#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" - #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ @@ -71,18 +58,20 @@ "lpj=lpj=3981312\0" \ "ubifsboot=" \ "set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \ - CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ - CONFIG_ENV_COMMON_BOOT "; run bootk\0" \ + "ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7 " \ + "rootflags=bulk_read,no_chk_data_crc ${mtdparts} ${opts} " \ + "${lcdinfo} ${console} ${meminfo}; run bootk\0" \ "tftpboot=" \ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ - CONFIG_ENV_COMMON_BOOT \ + "ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7 " \ + "rootflags=bulk_read,no_chk_data_crc ${mtdparts} ${opts} " \ + "${lcdinfo} ${console} ${meminfo}" \ "; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \ "nfsboot=" \ "set bootargs root=/dev/nfs rw " \ "nfsroot=${nfsroot},nolock,tcp " \ "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ + "${netmask}:generic:usb0:off ${console} ${meminfo}" \ "; run bootk\0" \ "ramfsboot=" \ "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \ @@ -102,8 +91,8 @@ "mbrparts=" MBRPARTS_DEFAULT \ "meminfo=crashkernel=32M@0x50000000\0" \ "nfsroot=/nfsroot/arm\0" \ - "bootblock=" CONFIG_BOOTBLOCK "\0" \ - "ubiblock=" CONFIG_UBIBLOCK" \0" \ + "bootblock=10\0" \ + "ubiblock=9\0" \ "ubi=enabled\0" \ "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ "mmcdev=0\0" \ diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 6a6f1de..774ecb4 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -14,11 +14,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ @@ -54,8 +49,6 @@ #define CONFIG_SYS_NAND_ONFI_DETECTION #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #ifdef CONFIG_SD_BOOT /* bootstrap + u-boot + env + linux in sd card */ #define CONFIG_BOOTCOMMAND \ @@ -78,9 +71,4 @@ "bootz 0x22000000 - 0x21000000" #endif -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - #endif diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 8942d15..1c30e44 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -14,26 +14,20 @@ #undef CONFIG_SYS_AT91_MAIN_CLOCK #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x8000000 - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR 0x218000 #else #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_SD_BOOT /* bootstrap + u-boot + env in sd card */ -#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 " \ +#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 " \ CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \ - "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" + "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \ + "bootz 0x23000000 - 0x22000000" #endif /* SPL */ diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 8bea764..09ebf48 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -26,8 +26,6 @@ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SPL */ #define CONFIG_SPL_TEXT_BASE 0x200000 #define CONFIG_SPL_MAX_SIZE 0x10000 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index 9be6d4f..e7ccfea 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -27,8 +27,6 @@ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* NAND flash */ /* SPI flash */ diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index f42e26a..1001bbc 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -22,8 +22,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* NAND Flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 4f5ceca..da573bc 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -11,19 +11,13 @@ #include "at91-sama5_common.h" -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR 0x218000 #else #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + (0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SerialFlash */ #ifdef CONFIG_SD_BOOT @@ -31,18 +25,18 @@ /* bootstrap + u-boot + env in sd card */ #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d2_xplained.dtb; " \ - "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" +#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 at91-sama5d2_xplained.dtb; " \ + "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x23000000 zImage; " \ + "bootz 0x23000000 - 0x22000000" #elif CONFIG_SPI_BOOT /* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */ #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x21000000 /boot/at91-sama5d2_xplained.dtb; " \ - "ext4load mmc 0:1 0x22000000 /boot/zImage; " \ - "bootz 0x22000000 - 0x21000000" +#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x22000000 /boot/at91-sama5d2_xplained.dtb; " \ + "ext4load mmc 0:1 0x23000000 /boot/zImage; " \ + "bootz 0x23000000 - 0x22000000" #endif @@ -51,9 +45,9 @@ #undef CONFIG_BOOTCOMMAND #define CONFIG_ENV_SPI_BUS 1 #define CONFIG_BOOTCOMMAND "sf probe 1:0; " \ - "sf read 0x21000000 0x180000 0x80000; " \ - "sf read 0x22000000 0x200000 0x600000; "\ - "bootz 0x22000000 - 0x21000000" + "sf read 0x22000000 0x180000 0x80000; " \ + "sf read 0x23000000 0x200000 0x600000; "\ + "bootz 0x23000000 - 0x22000000" #endif diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 4c25964..20d1d34 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -56,8 +56,6 @@ #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x18000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 44c1952..ac52e27 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -69,8 +69,6 @@ #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SPL */ #define CONFIG_SPL_MAX_SIZE 0x18000 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 80809df..3032297 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -22,8 +22,6 @@ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 2fb4764..4e8fe86 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -22,8 +22,6 @@ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 96db82e..9b7cc2c 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -24,9 +24,7 @@ GENERATED_GBL_DATA_SIZE) #endif -#define CONFIG_SYS_LOAD_ADDR 0x62000000 /* load address */ - -#undef CONFIG_BOOTCOMMAND +#ifndef CONFIG_BOOTCOMMAND #ifdef CONFIG_SD_BOOT /* u-boot env in sd/mmc card */ @@ -34,10 +32,11 @@ #define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x61000000 at91-sama7g5ek.dtb; " \ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x62000000 zImage; " \ "bootz 0x62000000 - 0x61000000" +#else +#define CONFIG_BOOTCOMMAND "Place your bootcommand here" #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#endif #define CONFIG_ARP_TIMEOUT 200 #define CONFIG_NET_RETRY_COUNT 50 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 8eeccdd..24c9a84 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -24,11 +24,7 @@ #define CONFIG_HOST_MAX_DEVICES 4 -/* - * Size of malloc() pool, before and after relocation - */ #define CONFIG_MALLOC_F_ADDR 0x0010000 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -38,8 +34,6 @@ #define CONFIG_I2C_EDID -/* Memory things - we don't really want a memory test */ -#define CONFIG_SYS_LOAD_ADDR 0x00000000 #define CONFIG_SYS_FDT_LOAD_ADDR 0x100 #define CONFIG_PHYSMEM diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 5b5aa1b..c51517a 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -24,8 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD - /* Environment in eMMC, at the end of 2nd "boot sector" */ /* NAND support */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index a4b4c48..6ccba95 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -18,15 +18,6 @@ #define CONFIG_DMA_COHERENT #define CONFIG_DMA_COHERENT_SIZE (1 << 20) -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) -#ifdef CONFIG_SIEMENS_MACH_TYPE -#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE -#endif - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* commands to include */ #ifndef CONFIG_SPL_BUILD @@ -53,8 +44,6 @@ * start addr of ram disk */ -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - /* Physical Memory Map */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ @@ -73,7 +62,6 @@ /* I2C Configuration */ -#define CONFIG_SYS_I2C_LEGACY /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ @@ -125,9 +113,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #ifndef CONFIG_SPL_BUILD /* diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index b6c29f8..8535678 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -28,10 +28,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index bea0eeb..f68d7d7 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -28,18 +28,12 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - #define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 /* Environment options */ @@ -85,9 +79,5 @@ #endif /* CONFIG_SPL_BUILD */ #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 0x1 - -#define CONFIG_ID_EEPROM #endif /* __SIFIVE_UNMATCHED_H */ diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 0fbe8a5..1f74702 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -8,11 +8,8 @@ #include <linux/sizes.h> -#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* Start just below the second bank so we don't clobber it during reloc */ #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF -#define CONFIG_SYS_MALLOC_LEN SZ_128K -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_SIZE SZ_8M diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 5e8637e..5bcc3a6 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -40,16 +40,11 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ /* misc settings */ -#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ -#define CONFIG_INITRD_TAG /* pass initrd param to kernel */ -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */ /* We set the max number of command args high to avoid HUSH bugs. */ #define CONFIG_SYS_MAXARGS 32 /* setting board specific options */ -#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB #define CONFIG_SYS_AUTOLOAD "yes" #define CONFIG_RESET_TO_RETRY @@ -69,10 +64,6 @@ * till the beginning of the U-Boot position in RAM. */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000) - /* NAND flash settings */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 @@ -101,7 +92,7 @@ /* BOOTP and DHCP options */ #define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv autoload yes; setenv autoboot yes; " \ "setenv bootargs ${basicargs} ${mtdparts} " \ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ @@ -130,12 +121,6 @@ #define CONFIG_SYS_CBSIZE 512 /* - * RAM Memory address where to put the - * Linux Kernel befor starting. - */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - -/* * The NAND Flash partitions: */ #define CONFIG_ENV_RANGE (SZ_512K) diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 77773cd..a5edf04 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -29,16 +29,6 @@ /* Text Base */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - * 1MB = 0x100000, 0x100000 = 1024 * 1024 - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - /* * select serial console configuration */ @@ -105,8 +95,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index fc2f6ec..4a6b625 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -12,14 +12,10 @@ #undef CONFIG_BOARD_COMMON #undef CONFIG_USB_GADGET_DWC2_OTG_PHY -#undef CONFIG_REVISION_TAG /* High Level Configuration Options */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ -/* Mach Type */ -#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* Handling Sleep Mode*/ @@ -28,14 +24,10 @@ #define S5P_CHECK_LPA 0xABAD0000 /* MMC SPL */ -#define CONFIG_SKIP_LOWLEVEL_INIT #define COPY_BL2_FNPTR_ADDR 0x00002488 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - /* SMDKV310 has 4 bank of DRAM */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 6f7b46e..cf80801 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -14,9 +14,6 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -45,7 +42,6 @@ "run mmcboot; " \ "fi; " \ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 529976e..32abeb0 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -20,11 +20,6 @@ /* CPU */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ @@ -73,10 +68,6 @@ #endif /* I2C - Bit-bashed */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F #define CONFIG_SOFT_I2C_READ_REPEATED_START #define I2C_INIT do { \ at91_set_gpio_output(AT91_PIN_PA23, 1); \ @@ -100,7 +91,6 @@ #define I2C_DELAY udelay(2) /* Boot options */ -#define CONFIG_SYS_LOAD_ADDR 0x23000000 #define CONFIG_BOOTP_BOOTFILESIZE @@ -108,7 +98,4 @@ /* Console settings */ -/* U-Boot memory settings */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - #endif /* __CONFIG_H */ diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 077e9d6..b13584d 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -19,10 +19,6 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* CPU */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* SDRAM */ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 @@ -64,7 +60,6 @@ /* UARTs/Serial console */ /* Boot options */ -#define CONFIG_SYS_LOAD_ADDR 0x23000000 #define CONFIG_BOOTP_BOOTFILESIZE @@ -92,7 +87,4 @@ /* Console settings */ -/* U-Boot memory settings */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - #endif /* __CONFIG_H */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 6ef96df..7c563b7 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -12,16 +12,6 @@ #include <asm/arch/omap.h> /* - * CPU - */ - -#define CONFIG_ARM_ARCH_CP15_ERRATA - -/* - * Board - */ - -/* * Clocks */ @@ -47,13 +37,10 @@ #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) - /* * I2C */ -#define CONFIG_SYS_I2C_LEGACY #define CONFIG_I2C_MULTI_BUS /* @@ -112,21 +99,9 @@ "bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0" /* - * ATAGs - */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* * Boot */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - #define CONFIG_BOOTCOMMAND \ "setenv boot_mmc_part ${kernel_mmc_part}; " \ "if test reboot-${reboot-mode} = reboot-r; then " \ diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 645e66e..ebb3e8c 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -8,10 +8,6 @@ #include <asm/arch/base_addr_a10.h> -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* * U-Boot general configurations */ diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index c25d6bd..0b37efe 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -43,7 +43,6 @@ "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \ "saveenv && saveenv && boot;" -#define CONFIG_CMDLINE_TAG #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Environment settings */ @@ -57,9 +56,6 @@ #define CONFIG_BOOT_RETRY_TIME 45 #define CONFIG_RESET_TO_RETRY -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_KM_KERNEL_ADDR - /* * FPGA Remote Update related environment * diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index af6137a..ca2d782 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c5e4292..ed3aac7 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -18,7 +18,6 @@ * Memory configurations */ #define PHYS_SDRAM_1 0x0 -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE @@ -186,7 +185,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif /* SPL SDMMC boot support */ -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 028db2a..c23ba23 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h index bffedcb..137da2f 100644 --- a/include/configs/socfpga_dbm_soc1.h +++ b/include/configs/socfpga_dbm_soc1.h @@ -13,8 +13,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Environment is in MMC */ diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 21108e3..a5e6511 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h index d85f98f..dfc22cf 100644 --- a/include/configs/socfpga_de10_nano.h +++ b/include/configs/socfpga_de10_nano.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h index 9919d29..4b58bc4 100644 --- a/include/configs/socfpga_de1_soc.h +++ b/include/configs/socfpga_de1_soc.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index c4da594..06337d4 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -13,8 +13,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "zImage" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index 50c5961..1456214 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -13,8 +13,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Environment is in MMC */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index a0453e5..4a0235d 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -15,8 +15,6 @@ * U-Boot general configurations */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_LOADADDR 0x2000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_REMAKE_ELF /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ #define CPU_RELEASE_ADDR 0xFFD12210 @@ -47,7 +45,6 @@ + 0x100000) #endif #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) /* * U-Boot environment configurations @@ -116,11 +113,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); "socfpga_legacy_reset_compat=1\0" /* - * Generic Interrupt Controller Definitions - */ -#define CONFIG_GICV2 - -/* * External memory configurations */ #define PHYS_SDRAM_1 0x0 diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 9729999..a4aece9 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index 7faea15..f482005 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index ccaa050..62c1bc7 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -10,10 +10,6 @@ /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Ethernet on SoC (EMAC) */ #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII /* The PHY is autodetected, so no MII PHY address is needed here */ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 38a7753..d9d0a4a 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -14,8 +14,6 @@ #define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTCOMMAND "run selboot" #define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" diff --git a/include/configs/socrates.h b/include/configs/socrates.h index da60546..400cea4 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -57,9 +57,7 @@ /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 @@ -72,7 +70,6 @@ /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ -#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ /* Hardcoded values, to use instead of SPD */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f @@ -126,7 +123,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ /* FPGA and NAND */ #define CONFIG_SYS_FPGA_BASE 0xc0000000 @@ -146,8 +142,6 @@ #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 - /* * General PCI * Memory space is mapped 1-1. @@ -201,7 +195,6 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ /* * For booting Linux, the board info and command line data @@ -214,7 +207,6 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ #endif -#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 945d0ec..6af908a 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -16,9 +16,6 @@ /* SPL options */ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ @@ -71,7 +68,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index b94ef91..e5571b2 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -13,17 +13,37 @@ * low-level initialization and rely on configuration provided by the Samsung * bootloader. New images are loaded at the same address for compatibility. */ -#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MALLOC_LEN SZ_2M /* FIXME: This should be loaded from device tree... */ #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0xa0412000 -/* Generate initrd atag for downstream kernel (others are copied in stemmy.c) */ -#define CONFIG_INITRD_TAG +/* Linux does not boot if FDT / initrd is loaded to end of RAM */ +#define BOOT_ENV \ + "fdt_high=0x6000000\0" \ + "initrd_high=0x6000000\0" + +#define CONSOLE_ENV \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define FASTBOOT_ENV \ + "fastboot_partition_alias_boot=Kernel\0" \ + "fastboot_partition_alias_recovery=Kernel2\0" \ + "fastboot_partition_alias_system=SYSTEM\0" \ + "fastboot_partition_alias_cache=CACHEFS\0" \ + "fastboot_partition_alias_hidden=HIDDEN\0" \ + "fastboot_partition_alias_userdata=DATAFS\0" + +#define BOOTCMD_ENV \ + "fastbootcmd=echo '*** FASTBOOT MODE ***'; fastboot usb 0\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOT_ENV \ + CONSOLE_ENV \ + FASTBOOT_ENV \ + BOOTCMD_ENV #endif diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 33b34ee..b1917c9 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -13,7 +13,6 @@ #define PHYS_SDRAM_1 0x40000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */ #define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ @@ -25,7 +24,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_BOOTM_LEN SZ_16M #define BOOT_TARGET_DEVICES(func) \ @@ -45,10 +43,6 @@ /* Extra Commands */ -#define CONFIG_SETUP_MEMORY_TAGS - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN 0x1800000 #define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ CONFIG_SYS_MALLOC_LEN - \ @@ -59,8 +53,6 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SKIP_LOWLEVEL_INIT - /* USB Configs */ #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 9d029fb..525a527 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -14,8 +14,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_LOAD_ADDR 0x90400000 -#define CONFIG_LOADADDR 0x90400000 #define CONFIG_SYS_MAX_FLASH_SECT 12 #define CONFIG_SYS_MAX_FLASH_BANKS 2 @@ -27,15 +25,8 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MALLOC_LEN (2 << 20) - #define CONFIG_BOOTCOMMAND \ "run bootcmd_romfs" diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index fefdb2d..609b4c2 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -19,8 +19,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 -#define CONFIG_LOADADDR 0x00400000 #define CONFIG_SYS_MAX_FLASH_SECT 12 #define CONFIG_SYS_MAX_FLASH_BANKS 2 @@ -29,15 +27,8 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index ba9f05a..a8f6fbf 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -19,8 +19,6 @@ /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 -#define CONFIG_LOADADDR 0x00400000 #define CONFIG_SYS_MAX_FLASH_SECT 12 #define CONFIG_SYS_MAX_FLASH_BANKS 2 @@ -29,15 +27,8 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 08d050a..c76d290 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -15,13 +15,6 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SYS_LOAD_ADDR 0x08008000 -#else -#define CONFIG_SYS_LOAD_ADDR 0xC0400000 -#define CONFIG_LOADADDR 0xC0400000 -#endif - /* * Configuration of the external SDRAM memory */ @@ -36,15 +29,8 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index 6e10dbd..c43b0d8 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -16,21 +16,9 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0xD0400000 -#define CONFIG_LOADADDR 0xD0400000 - #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 268d39c..d838449 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -16,21 +16,9 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0xD0400000 -#define CONFIG_LOADADDR 0xD0400000 - #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index 3fd5461..db17939 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -16,21 +16,9 @@ #define CONFIG_SYS_FLASH_BASE 0x90000000 #define CONFIG_SYS_INIT_SP_ADDR 0x24040000 -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0xC1800000 -#define CONFIG_LOADADDR 0xC1800000 - #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index b372838..4ccaab5 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -28,17 +28,6 @@ #define CONFIG_SYS_CBSIZE SZ_1K /* - * default load address used for command tftp, bootm , loadb, ... - */ -#define CONFIG_LOADADDR 0xc2000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index da162cb..5516ecf 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -73,7 +73,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) #define CONFIG_SYS_MBAR 0xFC000000 /* @@ -111,8 +110,6 @@ #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* * For booting Linux, the board info and command line data @@ -132,7 +129,6 @@ #endif /* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 8) #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 0058dcd..d380884 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -13,13 +13,10 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x00198000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) - /* user interface */ #define CONFIG_SYS_CBSIZE 1024 /* MISC */ -#define CONFIG_SYS_LOAD_ADDR 0x00000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 #define CONFIG_SYS_INIT_SP_OFFSET \ diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 6033760..0e1baa9 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -16,6 +16,4 @@ */ #include <configs/sunxi-common.h> -#define CONFIG_MACH_TYPE (4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - #endif /* __CONFIG_H */ diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index ee42af8..ada18de 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -16,6 +16,4 @@ */ #include <configs/sunxi-common.h> -#define CONFIG_MACH_TYPE (4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - #endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index d2fd586..803a751 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -20,6 +20,4 @@ */ #include <configs/sunxi-common.h> -#define CONFIG_MACH_TYPE (4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - #endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 958b850..f7d0a7e 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -15,22 +15,6 @@ #include <asm/arch/cpu.h> #include <linux/stringify.h> -#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT -/* - * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the - * expense of restricting some features, so the regular machine id values can - * be used. - */ -# define CONFIG_MACH_TYPE_COMPAT_REV 0 -#else -/* - * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. - * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass - * beyond the machine id check. - */ -# define CONFIG_MACH_TYPE_COMPAT_REV 1 -#endif - #ifdef CONFIG_ARM64 #define CONFIG_SYS_BOOTM_LEN (32 << 20) #endif @@ -61,7 +45,6 @@ #ifdef CONFIG_MACH_SUN9I #define SDRAM_OFFSET(x) 0x2##x #define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here * since it needs to fit in with the other values. By also #defining it * we get warnings if the Kconfig value mismatches. */ @@ -70,7 +53,6 @@ #else #define SDRAM_OFFSET(x) 0x4##x #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ /* V3s do not have enough memory to place code at 0x4a000000 */ /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here * since it needs to fit in with the other values. By also #defining it @@ -107,11 +89,6 @@ #define CONFIG_SYS_64BIT_LBA #endif -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_SERIAL_TAG - #ifdef CONFIG_NAND_SUNXI #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 #define CONFIG_SYS_NAND_ONFI_DETECTION @@ -137,14 +114,6 @@ #define CONFIG_SYS_MMC_MAX_DEVICE 4 #endif -#ifndef CONFIG_MACH_SUN8I_V3S -/* 64MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) -#else -/* 2MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) -#endif - /* * Miscellaneous configurable options */ @@ -194,21 +163,7 @@ /* I2C */ -#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ - defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ - defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE -#define CONFIG_SYS_I2C_MVTWSI -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7f -#endif -#endif - -#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 +#if defined(CONFIG_VIDEO_LCD_PANEL_I2C) /* We use pin names in Kconfig and sunxi_name_to_gpio() */ #define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda #define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 4503cf3..225d017 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -24,8 +24,6 @@ * Boot info */ #define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ -#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */ /* * Hardware drivers support diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 41efb64..166b839 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -20,16 +20,6 @@ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ - 2 * 1024 * 1024) /* * DDR related */ @@ -56,9 +46,6 @@ /* EHCI */ #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 /* @@ -78,10 +65,6 @@ #define CONFIG_SYS_MAXARGS 32 /* max number of command */ /* args */ -/* memtest works on */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ /* * AM3517 has 12 GP timers, they can be driven by the system clock @@ -249,7 +232,7 @@ struct tam3517_module_info { #define TAM3517_READ_EEPROM(info, ret) \ do { \ - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ (void *)info, sizeof(*info))) \ ret = 1; \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 6e86946..23f1e378 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -33,11 +33,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ @@ -102,9 +97,6 @@ /* SPL related */ #endif -/* load address */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - /* bootstrap in spi flash , u-boot + env + linux in nandflash */ #ifndef CONFIG_SPL_BUILD @@ -157,11 +149,6 @@ "upgrade_available=0\0" #endif #endif /* #ifndef CONFIG_SPL_BUILD */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000) /* Defines for SPL */ #define CONFIG_SPL_MAX_SIZE (31 * SZ_512) diff --git a/include/configs/tb100.h b/include/configs/tb100.h index f42b0df..6e31bd5 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -20,9 +20,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_128K #define CONFIG_SYS_BOOTM_LEN SZ_32M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 /* * UART configuration @@ -51,7 +49,6 @@ * Environment configuration */ #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR /* * Console configuration diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index a2e59ce..0438b5a 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -12,8 +12,6 @@ /* General configuration */ -#define CONFIG_MACH_TYPE 3980 - #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -26,8 +24,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) - #define CONFIG_SYS_BOOTMAPSZ 0x10000000 /* Serial console */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 2bc531c..f8e741a 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -22,11 +22,6 @@ #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH_SIZE (4 << 20) -/* Tag support */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index dd7a75a..7cb8d64 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -7,17 +7,6 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H -/* - * Size of malloc() pool - */ -#ifdef CONFIG_DFU_OVER_USB -#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \ - CONFIG_SYS_DFU_DATA_BUF_SIZE + \ - CONFIG_SYS_DFU_MAX_FILE_SIZE) -#else -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ -#endif - #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ #ifndef CONFIG_SPL_BUILD @@ -81,8 +70,6 @@ #define BOARD_EXTRA_ENV_SETTINGS #endif -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - #ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS #define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS #endif @@ -111,13 +98,6 @@ /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -/* remove I2C support */ -#ifdef CONFIG_SYS_I2C_TEGRA -#undef CONFIG_SYS_I2C_TEGRA -#endif - /* remove USB */ #ifdef CONFIG_USB_EHCI_TEGRA #undef CONFIG_USB_EHCI_TEGRA diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 432ecea..673056c 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -22,8 +22,6 @@ #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE #endif -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ - /* Environment */ /* diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 9d751b6..f714c52 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -45,11 +45,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 0eb8f92..4a92954 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -47,11 +47,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index d5f21e0..9685016 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -17,9 +17,6 @@ * Physical Memory Map */ -/* Generic Interrupt Controller */ -#define CONFIG_GICV2 - #undef FDTFILE #define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ @@ -50,11 +47,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x80080000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index fdd8996..e99e65f 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -46,11 +46,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x01000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x10000000\0" \ "pxefile_addr_r=0x10100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x03000000\0" \ "ramdisk_addr_r=0x03100000\0" diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 2226eff..b9e0414 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -14,9 +14,6 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Generic Interrupt Controller */ -#define CONFIG_GICV2 - /* * Memory layout for where various images get loaded by boot scripts: * @@ -41,11 +38,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x80080000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83200000\0" diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 6c5dc24..0ee13a2 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -42,11 +42,10 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 760713d..64b7f25 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -6,6 +6,8 @@ #ifndef _CONFIG_THEADORABLE_H #define _CONFIG_THEADORABLE_H +#include <linux/sizes.h> + /* * High Level Configuration Options (easy to change) */ @@ -23,12 +25,8 @@ */ /* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI @@ -93,6 +91,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ +#define CONFIG_SYS_SDRAM_SIZE SZ_2G #endif /* _CONFIG_THEADORABLE_H */ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 15a8469..d45ff7d 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -27,10 +27,6 @@ /* Physical Memory Map */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 4d3c58d..1ce0347 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -25,9 +25,6 @@ /* Generic Timer Definitions */ #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 @@ -42,7 +39,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) /* Physical Memory Map */ #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 67bcc0c..ee63ce3 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -18,13 +18,6 @@ #include <asm/arch/omap.h> -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG /* for ramdisk support */ - /* commands to include */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -87,8 +80,6 @@ /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ - /** * Physical Memory Map */ @@ -137,9 +128,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* Ethernet */ #define CONFIG_NET_RETRY_COUNT 10 diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 44fdc4c..cffa794 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -12,8 +12,6 @@ #include <configs/ti_armv7_omap.h> #include <asm/arch/omap.h> -#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM - #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ @@ -92,9 +90,6 @@ /* Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* * Disable MMC DM for SPL build and can be re-enabled after adding diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index c57b20a..10da123 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -46,9 +46,6 @@ * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* * When building U-Boot such that there is no previous loader diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 4fcf741..fa48cd2 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -16,19 +16,6 @@ #ifndef __CONFIG_TI_ARMV7_COMMON_H__ #define __CONFIG_TI_ARMV7_COMMON_H__ -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Our DDR memory always starts at 0x80000000 and U-Boot shall have - * relocated itself to higher in memory by the time this value is used. - * However, set this to a 32MB offset to allow for easier Linux kernel - * booting as the default is often used as the kernel load address. - */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - /* * We setup defaults based on constraints from the Linux kernel, which should * also be safe elsewhere. We have the default load at 32MB into DDR (for @@ -87,9 +74,6 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ /* If DM_I2C, enable non-DM I2C support */ -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#endif /* * The following are general good-enough settings for U-Boot. We set a @@ -100,7 +84,6 @@ * we are on so we do not need to rely on the command prompt. We set a * console baudrate of 115200 and use the default baud rate table. */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M /* As stated above, the following choices are optional. */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index cfc2be7..690ef0e 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -12,7 +12,6 @@ #define CONFIG_SOC_KEYSTONE /* U-Boot Build Configuration */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ /* SoC Configuration */ #define CONFIG_SPL_TARGET "u-boot-spi.gph" @@ -120,11 +119,6 @@ #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ /* EEPROM definitions */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_ENV_EEPROM_IS_ON_I2C /* NAND Configuration */ #define CONFIG_KEYSTONE_RBL_NAND @@ -155,7 +149,6 @@ #define CONFIG_TIMESTAMP /* EDMA3 */ -#define CONFIG_TI_EDMA3 #define KERNEL_MTD_PARTS \ "mtdparts=" \ @@ -187,7 +180,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ - CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + ENV_KS2_BOARD_SETTINGS \ DFUARGS \ "bootdir=/boot\0" \ "tftp_root=/\0" \ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 1e6f038..b5ccfdc 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -118,7 +118,6 @@ #ifdef CONFIG_SPL_BUILD /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ -#undef CONFIG_SYS_I2C_LEGACY #endif #endif /* __CONFIG_TI_OMAP4_COMMON_H */ diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index cc93f19..bbeedaf 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -18,14 +18,10 @@ #define UART0_BASE 0x7ff80000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) - /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 7372800 /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x90000000 /* Physical Memory Map */ #define PHYS_SDRAM_1 0x80000000 @@ -34,9 +30,7 @@ #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_ARM_PL180_MMCI_BASE 0x001c050000 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 -#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 12000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index f25f6dc..32689e1 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -12,12 +12,9 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x40000 #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 #define CONFIG_SYS_SDRAM_BASE 0xa0000000 -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index b58c475..1efe9d5 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -36,17 +36,12 @@ /* I2C Configs */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C EEPROM (M24C64) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ #define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 #if !defined(CONFIG_DM_PMIC) -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 @@ -65,9 +60,6 @@ #define CONFIG_ARP_TIMEOUT 200UL -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - #if defined(CONFIG_TQMA6X_MMC_BOOT) #define TQMA6_UBOOT_OFFSET SZ_1K diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index aa98a51..e68e96d 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -30,6 +30,5 @@ #define CONFIG_SYS_BOOTCOUNT_BE /* I2C */ -#define CONFIG_SYS_I2C_LEGACY #endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index a44792d..396e9f2 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -26,11 +26,6 @@ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -#define CONFIG_MACH_TYPE MACH_TYPE_TRATS - #define CONFIG_BOOTCOMMAND "run autoboot" #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ @@ -40,9 +35,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_BOOTBLOCK "10" -#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" - /* Tizen - partitions definitions */ #define PARTS_CSA "csa-mmc" #define PARTS_BOOT "boot" @@ -94,7 +86,7 @@ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=${nfsroot},nolock,tcp " \ "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ + "${netmask}:generic:usb0:off ${console} ${meminfo}" \ "; run bootk\0" \ "ramfsboot=" \ "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ @@ -112,7 +104,7 @@ "console=console=ttySAC2,115200n8\0" \ "meminfo=crashkernel=32M@0x50000000\0" \ "nfsroot=/nfsroot/arm\0" \ - "bootblock=" CONFIG_BOOTBLOCK "\0" \ + "bootblock=10\0" \ "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ "${fdtfile}\0" \ @@ -141,7 +133,7 @@ "setenv spl_imgsize;" \ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ - CONFIG_EXTRA_ENV_ITB \ + ENV_ITB \ "fdtaddr=40800000\0" \ /* Falcon mode definitions */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 4b1eff0..114dd8e 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -24,8 +24,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* memtest works on */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) #define CONFIG_BOOTCOMMAND "run autoboot" @@ -125,7 +123,7 @@ "setenv spl_imgsize;" \ "setenv spl_imgaddr;" \ "setenv spl_addr_tmp;\0" \ - CONFIG_EXTRA_ENV_ITB \ + ENV_ITB \ "fdtaddr=40800000\0" \ /* GPT */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b914e44..b562d44 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -18,8 +18,6 @@ #define CONFIG_TEGRA_UARTA_GPU #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE - /* SPI */ /* Environment in SPI */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 6712839..0bbc984 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -30,26 +30,11 @@ 4000000, 4500000, 5000000, 5500000, \ 6000000 } -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ /* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - -/* * Other required minimal configurations */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ @@ -60,7 +45,6 @@ * I2C */ #define CONFIG_I2C_MV -#define CONFIG_SYS_I2C_SLAVE 0x0 /* Environment in SPI NOR flash */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 2983693..fe6ea68 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -12,12 +12,6 @@ #include "imx6_spl.h" -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 4800 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART2_BASE /* SATA Configs */ @@ -43,10 +37,10 @@ "setenv fdtfile imx6dl-udoo.dtb; fi; " \ "if test ${fdtfile} = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 813e743..b06abc9 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -14,9 +14,6 @@ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR @@ -45,10 +42,10 @@ "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \ "if test $fdtfile = UNDEFINED; then " \ "echo WARNING: Could not determine dtb to use; fi\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x84000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ @@ -70,15 +67,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* I2C configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define PFUZE3000_I2C_BUS 0 diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 12028e5..d419db1 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -39,8 +39,6 @@ #define BOOTENV #endif -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - #define CONFIG_TIMESTAMP #define CONFIG_SYS_MONITOR_BASE 0 @@ -69,7 +67,6 @@ #define CONFIG_GATEWAYIP 192.168.11.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SYS_LOAD_ADDR 0x85000000 #define CONFIG_SYS_BOOTM_LEN (32 << 20) #if defined(CONFIG_ARM64) @@ -84,7 +81,7 @@ #endif #define CONFIG_ROOTPATH "/nfs/root/path" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs $bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 73bf2d1..c12e536 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -20,14 +20,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT - /* * Hardware drivers */ @@ -71,16 +63,9 @@ #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #endif -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - /* bootstrap + u-boot + env + linux in dataflash on CS0 */ #define CONFIG_BOOTCOMMAND "nboot 21000000 0" #define CONFIG_EXTRA_ENV_SETTINGS \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - #endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 648232b..6f5a1c8 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -31,19 +31,9 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* I2C */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ - /* Fuse */ #define CONFIG_FSL_IIM -/* U-Boot memory offsets */ -#define CONFIG_LOADADDR 0x72000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Linux boot */ #define CONFIG_HOSTNAME "usbarmory" #define CONFIG_BOOTCOMMAND \ @@ -89,6 +79,4 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - #endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 82a8fa7..3b86309 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -10,8 +10,6 @@ /* Onboard devices */ -#define CONFIG_SYS_MALLOC_LEN 0x1F0000 -#define CONFIG_SYS_LOAD_ADDR 0x00100000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 #if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL) diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 21f90f3..0bd5a1e 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -17,8 +17,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 7be5e5d..0f9ec66 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -37,9 +37,6 @@ "ramdisk_addr_r=0x46400000\0" \ "scriptaddr=0x46000000\0" -#define CONFIG_LOADADDR 0x40480000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - /* Enable Distro Boot */ #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ @@ -88,8 +85,6 @@ /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M #define CONFIG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ @@ -110,7 +105,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_SYS_I2C_SPEED 100000 /* ENET */ #define CONFIG_ETHPRIME "FEC" diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 54b5967..df22584 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -85,9 +85,6 @@ #endif #endif /* !CONFIG_GICV3 */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) - #ifndef CONFIG_TARGET_VEXPRESS64_JUNO /* The Vexpress64 simulators use SMSC91C111 */ #define CONFIG_SMC91111 1 @@ -105,7 +102,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) /* Physical Memory Map */ #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h new file mode 100644 index 0000000..ba3f979 --- /dev/null +++ b/include/configs/vexpress_ca9x4.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2011 Linaro + * Ryan Harkin, <ryan.harkin@linaro.org> + * + * Configuration for Versatile Express. Parts were derived from other ARM + * configurations. + */ + +#ifndef __VEXPRESS_CA9X4_H +#define __VEXPRESS_CA9X4_H + +#define VEXPRESS_ORIGINAL_MEMORY_MAP +#include "vexpress_common.h" + +#endif /* VEXPRESS_CA9X4_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index b131480..02fd963 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -15,7 +15,7 @@ * Definitions copied from linux kernel: * arch/arm/mach-vexpress/include/mach/motherboard.h */ -#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP +#ifdef VEXPRESS_ORIGINAL_MEMORY_MAP /* CS register bases for the original memory map. */ #define V2M_PA_CS0 0x40000000 #define V2M_PA_CS1 0x44000000 @@ -56,7 +56,6 @@ /* Common peripherals relative to CS7. */ #define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4)) -#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5)) #define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6)) #define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7)) @@ -109,15 +108,8 @@ /* Board info register */ #define SYS_ID V2M_SYSREGS -#define CONFIG_REVISION_TAG 1 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_SYS_L2CACHE_OFF 1 -#define CONFIG_INITRD_TAG 1 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */ #define SCTL_BASE V2M_SYSCTL #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) @@ -135,15 +127,12 @@ #define CONFIG_SYS_SERIAL0 V2M_UART0 #define CONFIG_SYS_SERIAL1 V2M_UART1 -#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI #define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 -#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 /* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) /* Physical Memory Map */ @@ -169,29 +158,10 @@ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#define CONFIG_PLATFORM_ENV_SETTINGS \ - "loadaddr=0x80008000\0" \ - "ramdisk_addr_r=0x61000000\0" \ - "kernel_addr=0x44100000\0" \ - "ramdisk_addr=0x44800000\0" \ - "maxramdisk=0x1800000\0" \ - "pxefile_addr_r=0x88000000\0" \ - "scriptaddr=0x88000000\0" \ - "kernel_addr_r=0x80008000\0" -#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) -#define CONFIG_PLATFORM_ENV_SETTINGS \ - "loadaddr=0xa0008000\0" \ - "ramdisk_addr_r=0x81000000\0" \ - "kernel_addr=0x0c100000\0" \ - "ramdisk_addr=0x0c800000\0" \ - "maxramdisk=0x1800000\0" \ - "pxefile_addr_r=0xa8000000\0" \ - "scriptaddr=0xa8000000\0" \ - "kernel_addr_r=0xa0008000\0" -#endif #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS \ + "kernel_addr_r=0x60100000\0" \ + "fdt_addr_r=0x60000000\0" \ + "bootargs=console=tty0 console=ttyAMA0,38400n8\0" \ BOOTENV \ "console=ttyAMA0,38400n8\0" \ "dram=1024M\0" \ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 4f11018..49053ce 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -13,16 +13,6 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_MACH_TYPE 4146 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - /* NAND support */ #define CONFIG_SYS_NAND_ONFI_DETECTION @@ -42,15 +32,8 @@ #define CONFIG_FEC_MXC_PHYADDR 0 /* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_SPD_BUS_NUM 0 - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - /* We boot from the gfxRAM area of the OCRAM. */ #define CONFIG_BOARD_SIZE_LIMIT 520192 diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 496c228..7397d3e 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -30,8 +30,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - /* SerialFlash */ #ifdef CONFIG_CMD_SF diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index e90eaf3..dcdaffc 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -14,9 +14,6 @@ #include "imx6_spl.h" #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ @@ -42,16 +39,7 @@ /* MMC Configuration */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -/* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index dfdb8fc..58888d4 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -12,14 +12,9 @@ /* RAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 - #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_BSS_START_ADDR 0x80010000 @@ -41,7 +36,6 @@ /* Memory usage */ #define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) #define CONFIG_SYS_CBSIZE 512 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index bd64893..ece762e 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -12,11 +12,6 @@ #include "imx6_spl.h" -#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - #define CONFIG_MXC_UART_BASE UART1_BASE /* SATA Configs */ @@ -45,7 +40,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "fdtfile=undefined\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ @@ -85,11 +80,11 @@ "setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi; \0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/warp.h b/include/configs/warp.h index e3beee0..11a9b31 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -14,9 +14,6 @@ #include "mx6_common.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ @@ -53,15 +50,8 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 /* I2C Configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a5d52e3..0822eaf 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -13,17 +13,11 @@ #define PHYS_SDRAM_SIZE SZ_512M -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -/* Switch on SERIAL_TAG */ -#define CONFIG_SERIAL_TAG - #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ @@ -107,7 +101,6 @@ "fi; " \ "fi" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ @@ -135,10 +128,6 @@ */ #define CONFIG_BOARD_SIZE_LIMIT 785408 -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - /* environment organization */ #define CONFIG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index f96178b..83b24a7 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -14,24 +14,11 @@ #include <asm/arch/cpu.h> /* - * Define work_92105 machine type by hand -- done only for compatibility - * with original board code - */ -#define CONFIG_MACH_TYPE 736 - -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* * Memory configurations */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - GENERATED_GBL_DATA_SIZE) @@ -43,24 +30,6 @@ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ -/* - * I2C driver - */ - -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_SPEED 350000 - -/* - * I2C EEPROM - */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * I2C RTC - */ - #define CONFIG_RTC_DS1374 /* @@ -105,12 +74,8 @@ /* * Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG #define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 /* * SPL diff --git a/include/configs/x530.h b/include/configs/x530.h index 64d6827..1e5d738 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -61,8 +61,6 @@ /* NAND */ #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MALLOC_LEN (4 << 20) - #include <asm/arch/config.h> /* @@ -75,7 +73,6 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -#define CONFIG_SYS_LOAD_ADDR 0x1000000 #define CONFIG_UBI_PART user #define CONFIG_UBIFS_VOLUME user diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index ab39b0b..4b39faa 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -53,15 +53,12 @@ */ #define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_LOAD_ADDR 0x20000000 - /*----------------------------------------------------------------------- * CPU Features */ #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x200000 /*----------------------------------------------------------------------- * Environment configuration @@ -82,7 +79,6 @@ #define CONFIG_ROOTPATH "/opt/nfsroot" #define CONFIG_HOSTNAME "x86" #define CONFIG_BOOTFILE "bzImage" -#define CONFIG_LOADADDR 0x1000000 #define CONFIG_RAMDISK_ADDR 0x4000000 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) #define CONFIG_OTHBOOTARGS "othbootargs=\0" @@ -109,7 +105,7 @@ "ramdiskfile=initramfs.gz\0" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ @@ -117,7 +113,7 @@ "tftpboot $ramdisk_addr_r $ramdiskfile;" \ "zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ diff --git a/include/configs/xea.h b/include/configs/xea.h index 1207f75..5081cc8 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -43,8 +43,6 @@ /* Booting Linux */ #define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Extra Environment */ #define CONFIG_HOSTNAME "xea" diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index d76ce13..c5e3d16 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -20,12 +20,8 @@ * This can be any arbitrary address as we are using PIE, but * please note, that CONFIG_SYS_TEXT_BASE must match the below. */ -#define CONFIG_SYS_LOAD_ADDR 0x40000000 #define CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_SYS_LOAD_ADDR -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MAXARGS 64 diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 62680ad..4348645 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -36,7 +36,6 @@ #define CONFIG_BOOTP_MAY_FAIL /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* Monitor Command Prompt */ /* Console I/O Buffer Size */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 42758ba..e10d90c 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -15,7 +15,6 @@ /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ /* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 #define GICD_BASE 0xF9010000 #define GICC_BASE 0xF9020000 @@ -26,9 +25,6 @@ # define COUNTER_FREQUENCY 100000000 #endif -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x4000000) - /* Serial setup */ #define CONFIG_CPU_ARMV8 @@ -49,7 +45,6 @@ #endif /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 #if defined(CONFIG_ZYNQMP_USB) #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index ef9c768..c106443 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -17,7 +17,6 @@ /* Undef unneeded configs */ #undef CONFIG_BOOTCOMMAND #undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_MALLOC_LEN #undef CONFIG_SYS_INIT_SP_ADDR /* BOOTP options */ diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h index a7ae30d..57c40d6 100644 --- a/include/configs/xilinx_zynqmp_mini_emmc.h +++ b/include/configs/xilinx_zynqmp_mini_emmc.h @@ -13,6 +13,5 @@ #include <configs/xilinx_zynqmp_mini.h> #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x800000 #endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index 692f6e5..782e696 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -15,6 +15,5 @@ #define CONFIG_SYS_SDRAM_SIZE 0x1000000 #define CONFIG_SYS_SDRAM_BASE 0x0 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) -#define CONFIG_SYS_MALLOC_LEN 0x800000 #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h index 205ddb4..3091bae 100644 --- a/include/configs/xilinx_zynqmp_mini_qspi.h +++ b/include/configs/xilinx_zynqmp_mini_qspi.h @@ -13,6 +13,5 @@ #include <configs/xilinx_zynqmp_mini.h> #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) -#define CONFIG_SYS_MALLOC_LEN 0x1a00 #endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index c0cd72e..6d5b81e 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -17,12 +17,9 @@ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Boot configuration */ -#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_MALLOC_LEN 0x1400000 - #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ @@ -32,6 +29,4 @@ /* Extend size of kernel image for uncompression */ #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) -#define CONFIG_SKIP_LOWLEVEL_INIT - #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index e4678e3..1e2b6c0 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -13,25 +13,13 @@ /* SPL options */ #include "imx6_spl.h" -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 << 20) - #define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* I2C configs */ -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ -#define CONFIG_SYS_I2C_SPEED 100000 - /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 /* Physical Memory Map */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 516a608..b69834a 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -65,8 +65,6 @@ # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ #endif -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ - /* Linux boot param area in RAM (used only when booting linux) */ #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) @@ -98,9 +96,6 @@ #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) -/* Used by tftpboot; env var 'loadaddr' */ -#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) - /*==============================*/ /* U-Boot general configuration */ /*==============================*/ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 8b571da..d7cbb0f 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_TIMER_COUNTER \ (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) -#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 /* * Environment settings */ @@ -26,10 +25,6 @@ "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ "bootm 0x81000000; bootelf 0x81000000\0" -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* * Hardware drivers */ @@ -80,12 +75,4 @@ * CFI FLASH driver setup */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) - #endif /* __CONFIG_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 7859b77..9b4c54b 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -65,7 +65,6 @@ /* enable preboot to be loaded before CONFIG_BOOTDELAY */ /* Boot configuration */ -#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ #ifdef CONFIG_SPL_BUILD #define BOOTENV diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 0491cf5..7eafdfd 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_ZYNQ_CSE_H #define __CONFIG_ZYNQ_CSE_H -#define CONFIG_SKIP_LOWLEVEL_INIT - #include <configs/zynq-common.h> /* Undef unneeded configs */ diff --git a/include/dm/device.h b/include/dm/device.h index 0a9718a..ef6241b 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -738,7 +738,7 @@ int device_find_next_child(struct udevice **devp); * * @parent: Parent device to search * @uclass_id: Uclass to look for - * @devp: Returns device found, if any + * @devp: Returns device found, if any, else NULL * @return 0 if found, else -ENODEV */ int device_find_first_inactive_child(const struct udevice *parent, @@ -750,7 +750,7 @@ int device_find_first_inactive_child(const struct udevice *parent, * * @parent: Parent device to search * @uclass_id: Uclass to look for - * @devp: Returns first child device in that uclass, if any + * @devp: Returns first child device in that uclass, if any, else NULL * @return 0 if found, else -ENODEV */ int device_find_first_child_by_uclass(const struct udevice *parent, diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index e7edd40..3768432 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -54,6 +54,7 @@ enum uclass_id { UCLASS_FIRMWARE, /* Firmware */ UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ + UCLASS_HASH, /* Hash device */ UCLASS_HWSPINLOCK, /* Hardware semaphores */ UCLASS_I2C, /* I2C bus */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ diff --git a/include/dm/uclass.h b/include/dm/uclass.h index da0c1bf..15e5f9e 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -354,7 +354,7 @@ int uclass_next_device(struct udevice **devp); * The device returned is probed if necessary, and ready for use * * @devp: On entry, pointer to device to lookup. On exit, returns pointer - * to the next device in the uclass if no error occurred, or -ENODEV if + * to the next device in the uclass if no error occurred, or NULL if * there is no next device. * @return 0 if found, -ENODEV if not found, other -ve on error */ diff --git a/include/dt-bindings/mfd/atmel-flexcom.h b/include/dt-bindings/mfd/atmel-flexcom.h new file mode 100644 index 0000000..4e2fc32 --- /dev/null +++ b/include/dt-bindings/mfd/atmel-flexcom.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides macros for Atmel Flexcom DT bindings. + * + * Copyright (C) 2015 Cyrille Pitchen <cyrille.pitchen@atmel.com> + */ + +#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ +#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ + +#define ATMEL_FLEXCOM_MODE_USART 1 +#define ATMEL_FLEXCOM_MODE_SPI 2 +#define ATMEL_FLEXCOM_MODE_TWI 3 + +#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ diff --git a/include/eeprom.h b/include/eeprom.h index 6820844..f9c6542 100644 --- a/include/eeprom.h +++ b/include/eeprom.h @@ -21,8 +21,4 @@ int eeprom_write(uint dev_addr, uint offset, uchar *buffer, uint cnt); #define eeprom_write(dev_addr, offset, buffer, cnt) (-ENOSYS) #endif -#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) -# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR -#endif - #endif diff --git a/include/env_default.h b/include/env_default.h index 1ddd64b..66e203e 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -82,8 +82,8 @@ const uchar default_environment[] = { #ifdef CONFIG_BOOTFILE "bootfile=" CONFIG_BOOTFILE "\0" #endif -#ifdef CONFIG_LOADADDR - "loadaddr=" __stringify(CONFIG_LOADADDR) "\0" +#ifdef CONFIG_SYS_LOAD_ADDR + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0" #endif #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0" diff --git a/include/i2c.h b/include/i2c.h index 3d9ecab..a35e99b 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -610,6 +610,10 @@ extern struct acpi_ops i2c_acpi_ops; */ int acpi_i2c_of_to_plat(struct udevice *dev); +#ifdef CONFIG_SYS_I2C_EARLY_INIT +void i2c_early_init_f(void); +#endif + #if !CONFIG_IS_ENABLED(DM_I2C) /* @@ -743,26 +747,13 @@ extern struct i2c_bus_hose i2c_bus[]; #endif /* - * Many boards/controllers/drivers don't support an I2C slave interface so - * provide a default slave address for them for use in common code. A real - * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does - * support a slave interface. - */ -#ifndef CONFIG_SYS_I2C_SLAVE -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - -/* * Initialization, must be called once on start up, may be called * repeatedly to change the speed and slave addresses. */ -#ifdef CONFIG_SYS_I2C_EARLY_INIT -void i2c_early_init_f(void); -#endif void i2c_init(int speed, int slaveaddr); void i2c_init_board(void); -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) /* * i2c_get_bus_num: * @@ -942,7 +933,7 @@ unsigned int i2c_get_bus_speed(void); * only for backwardcompatibility, should go away if we switched * completely to new multibus support. */ -#if defined(CONFIG_SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) # if !defined(CONFIG_SYS_MAX_I2C_BUS) # define CONFIG_SYS_MAX_I2C_BUS 2 # endif diff --git a/include/i8042.h b/include/i8042.h index 8d69fa1..6876320 100644 --- a/include/i8042.h +++ b/include/i8042.h @@ -20,12 +20,12 @@ #define STATUS_IBF (1 << 1) /* Configuration byte bit defines */ -#define CONFIG_KIRQ_EN (1 << 0) -#define CONFIG_MIRQ_EN (1 << 1) -#define CONFIG_SET_BIST (1 << 2) -#define CONFIG_KCLK_DIS (1 << 4) -#define CONFIG_MCLK_DIS (1 << 5) -#define CONFIG_AT_TRANS (1 << 6) +#define CFG_KIRQ_EN (1 << 0) +#define CFG_MIRQ_EN (1 << 1) +#define CFG_SET_BIST (1 << 2) +#define CFG_KCLK_DIS (1 << 4) +#define CFG_MCLK_DIS (1 << 5) +#define CFG_AT_TRANS (1 << 6) /* i8042 commands */ #define CMD_RD_CONFIG 0x20 /* read configuration byte */ diff --git a/include/lmb.h b/include/lmb.h index 3c4afdf..1984291 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -122,6 +122,7 @@ lmb_size_bytes(struct lmb_region *type, unsigned long region_nr) void board_lmb_reserve(struct lmb *lmb); void arch_lmb_reserve(struct lmb *lmb); +void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end, ulong align); /* Low level functions */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 71cffa1..0275b31 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1372,7 +1372,7 @@ #endif /* !CONFIG_MPC83XX_SDRAM */ /* - * CONFIG_ADDRESS - PCI Config Address Register + * PCI_CONFIG_ADDRESS - PCI Config Address Register */ #define PCI_CONFIG_ADDRESS_EN 0x80000000 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 diff --git a/include/netdev.h b/include/netdev.h index 00a0993..fb18f09 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -29,7 +29,6 @@ int board_interface_eth_init(struct udevice *dev, int cpu_eth_init(struct bd_info *bis); /* Driver initialization prototypes */ -int at91emac_register(struct bd_info *bis, unsigned long iobase); int ax88180_initialize(struct bd_info *bis); int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num); int bfin_EMAC_initialize(struct bd_info *bis); diff --git a/include/os.h b/include/os.h index 7b20d60..770d76e 100644 --- a/include/os.h +++ b/include/os.h @@ -52,6 +52,14 @@ off_t os_lseek(int fd, off_t offset, int whence); #define OS_SEEK_END 2 /** + * os_filesize() - Calculate the size of a file + * + * @fd: File descriptor as returned by os_open() + * Return: file size or negative error code + */ +int os_filesize(int fd); + +/** * Access to the OS open() system call * * @pathname: Pathname of file to open @@ -398,6 +406,19 @@ int os_write_file(const char *name, const void *buf, int size); */ int os_read_file(const char *name, void **bufp, int *sizep); +/** + * os_map_file() - Map a file from the host filesystem into memory + * + * This can be useful when to provide a backing store for an emulated device + * + * @pathname: File pathname to map + * @os_flags: Flags, like OS_O_RDONLY, OS_O_RDWR + * @bufp: Returns buffer containing the file + * @sizep: Returns size of data + * Return: 0 if OK, -ve on error + */ +int os_map_file(const char *pathname, int os_flags, void **bufp, int *sizep); + /* * os_find_text_base() - Find the text section in this running process * diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index 82fe350..cf476c8 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -154,7 +154,7 @@ enum { OPMODE_ON, }; -#ifdef CONFIG_POWER +#if CONFIG_IS_ENABLED(POWER_LEGACY) int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV); int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode); int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV); diff --git a/include/power/pmic.h b/include/power/pmic.h index be9de6b..97f855c 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -17,7 +17,8 @@ enum { PMIC_I2C, PMIC_SPI, PMIC_NONE}; -#ifdef CONFIG_POWER +/* TODO: Change to !CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ +#if CONFIG_IS_ENABLED(POWER_LEGACY) enum { I2C_PMIC, I2C_NUM, }; enum { PMIC_READ, PMIC_WRITE, }; enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, }; @@ -82,8 +83,9 @@ struct pmic { struct pmic *parent; struct list_head list; }; -#endif /* CONFIG_POWER */ +#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ +/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ #ifdef CONFIG_DM_PMIC /** * U-Boot PMIC Framework @@ -306,9 +308,12 @@ struct uc_pmic_priv { uint trans_len; }; -#endif /* CONFIG_DM_PMIC */ +#endif /* DM_PMIC */ -#ifdef CONFIG_POWER +/* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ +#if CONFIG_IS_ENABLED(POWER_LEGACY) + +/* Legacy API, do not use */ int pmic_init(unsigned char bus); int power_init_board(void); int pmic_dialog_init(unsigned char bus); @@ -319,7 +324,7 @@ int pmic_probe(struct pmic *p); int pmic_reg_read(struct pmic *p, u32 reg, u32 *val); int pmic_reg_write(struct pmic *p, u32 reg, u32 val); int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on); -#endif +#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ #define pmic_i2c_addr (p->hw.i2c.addr) #define pmic_i2c_tx_num (p->hw.i2c.tx_num) diff --git a/include/radeon.h b/include/radeon.h deleted file mode 100644 index da6c26b..0000000 --- a/include/radeon.h +++ /dev/null @@ -1,1988 +0,0 @@ -#ifndef _RADEON_H -#define _RADEON_H - - -#define RADEON_REGSIZE 0x4000 - - -#define MM_INDEX 0x0000 -#define MM_DATA 0x0004 -#define BUS_CNTL 0x0030 -#define HI_STAT 0x004C -#define BUS_CNTL1 0x0034 -#define I2C_CNTL_1 0x0094 -#define CONFIG_CNTL 0x00E0 -#define CONFIG_MEMSIZE 0x00F8 -#define CONFIG_APER_0_BASE 0x0100 -#define CONFIG_APER_1_BASE 0x0104 -#define CONFIG_APER_SIZE 0x0108 -#define CONFIG_REG_1_BASE 0x010C -#define CONFIG_REG_APER_SIZE 0x0110 -#define PAD_AGPINPUT_DELAY 0x0164 -#define PAD_CTLR_STRENGTH 0x0168 -#define PAD_CTLR_UPDATE 0x016C -#define PAD_CTLR_MISC 0x0aa0 -#define AGP_CNTL 0x0174 -#define BM_STATUS 0x0160 -#define CAP0_TRIG_CNTL 0x0950 -#define CAP1_TRIG_CNTL 0x09c0 -#define VIPH_CONTROL 0x0C40 -#define VENDOR_ID 0x0F00 -#define DEVICE_ID 0x0F02 -#define COMMAND 0x0F04 -#define STATUS 0x0F06 -#define REVISION_ID 0x0F08 -#define REGPROG_INF 0x0F09 -#define SUB_CLASS 0x0F0A -#define BASE_CODE 0x0F0B -#define CACHE_LINE 0x0F0C -#define LATENCY 0x0F0D -#define HEADER 0x0F0E -#define BIST 0x0F0F -#define REG_MEM_BASE 0x0F10 -#define REG_IO_BASE 0x0F14 -#define REG_REG_BASE 0x0F18 -#define ADAPTER_ID 0x0F2C -#define BIOS_ROM 0x0F30 -#define CAPABILITIES_PTR 0x0F34 -#define INTERRUPT_LINE 0x0F3C -#define INTERRUPT_PIN 0x0F3D -#define MIN_GRANT 0x0F3E -#define MAX_LATENCY 0x0F3F -#define ADAPTER_ID_W 0x0F4C -#define PMI_CAP_ID 0x0F50 -#define PMI_NXT_CAP_PTR 0x0F51 -#define PMI_PMC_REG 0x0F52 -#define PM_STATUS 0x0F54 -#define PMI_DATA 0x0F57 -#define AGP_CAP_ID 0x0F58 -#define AGP_STATUS 0x0F5C -#define AGP_COMMAND 0x0F60 -#define AIC_CTRL 0x01D0 -#define AIC_STAT 0x01D4 -#define AIC_PT_BASE 0x01D8 -#define AIC_LO_ADDR 0x01DC -#define AIC_HI_ADDR 0x01E0 -#define AIC_TLB_ADDR 0x01E4 -#define AIC_TLB_DATA 0x01E8 -#define DAC_CNTL 0x0058 -#define DAC_CNTL2 0x007c -#define CRTC_GEN_CNTL 0x0050 -#define MEM_CNTL 0x0140 -#define MC_CNTL 0x0140 -#define EXT_MEM_CNTL 0x0144 -#define MC_TIMING_CNTL 0x0144 -#define MC_AGP_LOCATION 0x014C -#define MEM_IO_CNTL_A0 0x0178 -#define MEM_REFRESH_CNTL 0x0178 -#define MEM_INIT_LATENCY_TIMER 0x0154 -#define MC_INIT_GFX_LAT_TIMER 0x0154 -#define MEM_SDRAM_MODE_REG 0x0158 -#define AGP_BASE 0x0170 -#define MEM_IO_CNTL_A1 0x017C -#define MC_READ_CNTL_AB 0x017C -#define MEM_IO_CNTL_B0 0x0180 -#define MC_INIT_MISC_LAT_TIMER 0x0180 -#define MEM_IO_CNTL_B1 0x0184 -#define MC_IOPAD_CNTL 0x0184 -#define MC_DEBUG 0x0188 -#define MC_STATUS 0x0150 -#define MEM_IO_OE_CNTL 0x018C -#define MC_CHIP_IO_OE_CNTL_AB 0x018C -#define MC_FB_LOCATION 0x0148 -/* #define MC_FB_LOCATION 0x0188 */ -#define HOST_PATH_CNTL 0x0130 -#define MEM_VGA_WP_SEL 0x0038 -#define MEM_VGA_RP_SEL 0x003C -#define HDP_DEBUG 0x0138 -#define SW_SEMAPHORE 0x013C -#define CRTC2_GEN_CNTL 0x03f8 -#define CRTC2_DISPLAY_BASE_ADDR 0x033c -#define SURFACE_CNTL 0x0B00 -#define SURFACE0_LOWER_BOUND 0x0B04 -#define SURFACE1_LOWER_BOUND 0x0B14 -#define SURFACE2_LOWER_BOUND 0x0B24 -#define SURFACE3_LOWER_BOUND 0x0B34 -#define SURFACE4_LOWER_BOUND 0x0B44 -#define SURFACE5_LOWER_BOUND 0x0B54 -#define SURFACE6_LOWER_BOUND 0x0B64 -#define SURFACE7_LOWER_BOUND 0x0B74 -#define SURFACE0_UPPER_BOUND 0x0B08 -#define SURFACE1_UPPER_BOUND 0x0B18 -#define SURFACE2_UPPER_BOUND 0x0B28 -#define SURFACE3_UPPER_BOUND 0x0B38 -#define SURFACE4_UPPER_BOUND 0x0B48 -#define SURFACE5_UPPER_BOUND 0x0B58 -#define SURFACE6_UPPER_BOUND 0x0B68 -#define SURFACE7_UPPER_BOUND 0x0B78 -#define SURFACE0_INFO 0x0B0C -#define SURFACE1_INFO 0x0B1C -#define SURFACE2_INFO 0x0B2C -#define SURFACE3_INFO 0x0B3C -#define SURFACE4_INFO 0x0B4C -#define SURFACE5_INFO 0x0B5C -#define SURFACE6_INFO 0x0B6C -#define SURFACE7_INFO 0x0B7C -#define SURFACE_ACCESS_FLAGS 0x0BF8 -#define SURFACE_ACCESS_CLR 0x0BFC -#define GEN_INT_CNTL 0x0040 -#define GEN_INT_STATUS 0x0044 -#define CRTC_EXT_CNTL 0x0054 -#define RB3D_CNTL 0x1C3C -#define WAIT_UNTIL 0x1720 -#define ISYNC_CNTL 0x1724 -#define RBBM_GUICNTL 0x172C -#define RBBM_STATUS 0x0E40 -#define RBBM_STATUS_alt_1 0x1740 -#define RBBM_CNTL 0x00EC -#define RBBM_CNTL_alt_1 0x0E44 -#define RBBM_SOFT_RESET 0x00F0 -#define RBBM_SOFT_RESET_alt_1 0x0E48 -#define NQWAIT_UNTIL 0x0E50 -#define RBBM_DEBUG 0x0E6C -#define RBBM_CMDFIFO_ADDR 0x0E70 -#define RBBM_CMDFIFO_DATAL 0x0E74 -#define RBBM_CMDFIFO_DATAH 0x0E78 -#define RBBM_CMDFIFO_STAT 0x0E7C -#define CRTC_STATUS 0x005C -#define GPIO_VGA_DDC 0x0060 -#define GPIO_DVI_DDC 0x0064 -#define GPIO_MONID 0x0068 -#define GPIO_CRT2_DDC 0x006c -#define PALETTE_INDEX 0x00B0 -#define PALETTE_DATA 0x00B4 -#define PALETTE_30_DATA 0x00B8 -#define CRTC_H_TOTAL_DISP 0x0200 -#define CRTC_H_SYNC_STRT_WID 0x0204 -#define CRTC_H_SYNC_POL (1 << 23) -#define CRTC_V_TOTAL_DISP 0x0208 -#define CRTC_V_SYNC_STRT_WID 0x020C -#define CRTC_V_SYNC_POL (1 << 23) -#define CRTC_VLINE_CRNT_VLINE 0x0210 -#define CRTC_CRNT_FRAME 0x0214 -#define CRTC_GUI_TRIG_VLINE 0x0218 -#define CRTC_DEBUG 0x021C -#define CRTC_OFFSET_RIGHT 0x0220 -#define CRTC_OFFSET 0x0224 -#define CRTC_OFFSET_CNTL 0x0228 -#define CRTC_PITCH 0x022C -#define OVR_CLR 0x0230 -#define OVR_WID_LEFT_RIGHT 0x0234 -#define OVR_WID_TOP_BOTTOM 0x0238 -#define DISPLAY_BASE_ADDR 0x023C -#define SNAPSHOT_VH_COUNTS 0x0240 -#define SNAPSHOT_F_COUNT 0x0244 -#define N_VIF_COUNT 0x0248 -#define SNAPSHOT_VIF_COUNT 0x024C -#define FP_CRTC_H_TOTAL_DISP 0x0250 -#define FP_CRTC_V_TOTAL_DISP 0x0254 -#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 -#define CRT_CRTC_V_SYNC_STRT_WID 0x025C -#define CUR_OFFSET 0x0260 -#define CUR_HORZ_VERT_POSN 0x0264 -#define CUR_HORZ_VERT_OFF 0x0268 -#define CUR_CLR0 0x026C -#define CUR_CLR1 0x0270 -#define FP_HORZ_VERT_ACTIVE 0x0278 -#define CRTC_MORE_CNTL 0x027C -#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) -#define DAC_EXT_CNTL 0x0280 -#define FP_GEN_CNTL 0x0284 -#define FP_HORZ_STRETCH 0x028C -#define FP_VERT_STRETCH 0x0290 -#define FP_H_SYNC_STRT_WID 0x02C4 -#define FP_V_SYNC_STRT_WID 0x02C8 -#define AUX_WINDOW_HORZ_CNTL 0x02D8 -#define AUX_WINDOW_VERT_CNTL 0x02DC -/* #define DDA_CONFIG 0x02e0 */ -/* #define DDA_ON_OFF 0x02e4 */ -#define DVI_I2C_CNTL_1 0x02e4 -#define GRPH_BUFFER_CNTL 0x02F0 -#define GRPH2_BUFFER_CNTL 0x03F0 -#define VGA_BUFFER_CNTL 0x02F4 -#define OV0_Y_X_START 0x0400 -#define OV0_Y_X_END 0x0404 -#define OV0_PIPELINE_CNTL 0x0408 -#define OV0_REG_LOAD_CNTL 0x0410 -#define OV0_SCALE_CNTL 0x0420 -#define OV0_V_INC 0x0424 -#define OV0_P1_V_ACCUM_INIT 0x0428 -#define OV0_P23_V_ACCUM_INIT 0x042C -#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 -#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 -#define OV0_BASE_ADDR 0x043C -#define OV0_VID_BUF0_BASE_ADRS 0x0440 -#define OV0_VID_BUF1_BASE_ADRS 0x0444 -#define OV0_VID_BUF2_BASE_ADRS 0x0448 -#define OV0_VID_BUF3_BASE_ADRS 0x044C -#define OV0_VID_BUF4_BASE_ADRS 0x0450 -#define OV0_VID_BUF5_BASE_ADRS 0x0454 -#define OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define OV0_AUTO_FLIP_CNTRL 0x0470 -#define OV0_DEINTERLACE_PATTERN 0x0474 -#define OV0_SUBMIT_HISTORY 0x0478 -#define OV0_H_INC 0x0480 -#define OV0_STEP_BY 0x0484 -#define OV0_P1_H_ACCUM_INIT 0x0488 -#define OV0_P23_H_ACCUM_INIT 0x048C -#define OV0_P1_X_START_END 0x0494 -#define OV0_P2_X_START_END 0x0498 -#define OV0_P3_X_START_END 0x049C -#define OV0_FILTER_CNTL 0x04A0 -#define OV0_FOUR_TAP_COEF_0 0x04B0 -#define OV0_FOUR_TAP_COEF_1 0x04B4 -#define OV0_FOUR_TAP_COEF_2 0x04B8 -#define OV0_FOUR_TAP_COEF_3 0x04BC -#define OV0_FOUR_TAP_COEF_4 0x04C0 -#define OV0_FLAG_CNTRL 0x04DC -#define OV0_SLICE_CNTL 0x04E0 -#define OV0_VID_KEY_CLR_LOW 0x04E4 -#define OV0_VID_KEY_CLR_HIGH 0x04E8 -#define OV0_GRPH_KEY_CLR_LOW 0x04EC -#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 -#define OV0_KEY_CNTL 0x04F4 -#define OV0_TEST 0x04F8 -#define SUBPIC_CNTL 0x0540 -#define SUBPIC_DEFCOLCON 0x0544 -#define SUBPIC_Y_X_START 0x054C -#define SUBPIC_Y_X_END 0x0550 -#define SUBPIC_V_INC 0x0554 -#define SUBPIC_H_INC 0x0558 -#define SUBPIC_BUF0_OFFSET 0x055C -#define SUBPIC_BUF1_OFFSET 0x0560 -#define SUBPIC_LC0_OFFSET 0x0564 -#define SUBPIC_LC1_OFFSET 0x0568 -#define SUBPIC_PITCH 0x056C -#define SUBPIC_BTN_HLI_COLCON 0x0570 -#define SUBPIC_BTN_HLI_Y_X_START 0x0574 -#define SUBPIC_BTN_HLI_Y_X_END 0x0578 -#define SUBPIC_PALETTE_INDEX 0x057C -#define SUBPIC_PALETTE_DATA 0x0580 -#define SUBPIC_H_ACCUM_INIT 0x0584 -#define SUBPIC_V_ACCUM_INIT 0x0588 -#define DISP_MISC_CNTL 0x0D00 -#define DAC_MACRO_CNTL 0x0D04 -#define DISP_PWR_MAN 0x0D08 -#define DISP_TEST_DEBUG_CNTL 0x0D10 -#define DISP_HW_DEBUG 0x0D14 -#define DAC_CRC_SIG1 0x0D18 -#define DAC_CRC_SIG2 0x0D1C -#define OV0_LIN_TRANS_A 0x0D20 -#define OV0_LIN_TRANS_B 0x0D24 -#define OV0_LIN_TRANS_C 0x0D28 -#define OV0_LIN_TRANS_D 0x0D2C -#define OV0_LIN_TRANS_E 0x0D30 -#define OV0_LIN_TRANS_F 0x0D34 -#define OV0_GAMMA_0_F 0x0D40 -#define OV0_GAMMA_10_1F 0x0D44 -#define OV0_GAMMA_20_3F 0x0D48 -#define OV0_GAMMA_40_7F 0x0D4C -#define OV0_GAMMA_380_3BF 0x0D50 -#define OV0_GAMMA_3C0_3FF 0x0D54 -#define DISP_MERGE_CNTL 0x0D60 -#define DISP_OUTPUT_CNTL 0x0D64 -#define DISP_LIN_TRANS_GRPH_A 0x0D80 -#define DISP_LIN_TRANS_GRPH_B 0x0D84 -#define DISP_LIN_TRANS_GRPH_C 0x0D88 -#define DISP_LIN_TRANS_GRPH_D 0x0D8C -#define DISP_LIN_TRANS_GRPH_E 0x0D90 -#define DISP_LIN_TRANS_GRPH_F 0x0D94 -#define DISP_LIN_TRANS_VID_A 0x0D98 -#define DISP_LIN_TRANS_VID_B 0x0D9C -#define DISP_LIN_TRANS_VID_C 0x0DA0 -#define DISP_LIN_TRANS_VID_D 0x0DA4 -#define DISP_LIN_TRANS_VID_E 0x0DA8 -#define DISP_LIN_TRANS_VID_F 0x0DAC -#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 -#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 -#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 -#define RMX_HORZ_PHASE 0x0DBC -#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 -#define DAC_BROAD_PULSE 0x0DC4 -#define DAC_SKEW_CLKS 0x0DC8 -#define DAC_INCR 0x0DCC -#define DAC_NEG_SYNC_LEVEL 0x0DD0 -#define DAC_POS_SYNC_LEVEL 0x0DD4 -#define DAC_BLANK_LEVEL 0x0DD8 -#define CLOCK_CNTL_INDEX 0x0008 -#define CLOCK_CNTL_DATA 0x000C -#define CP_RB_CNTL 0x0704 -#define CP_RB_BASE 0x0700 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define SCRATCH_REG0 0x15E0 -#define GUI_SCRATCH_REG0 0x15E0 -#define SCRATCH_REG1 0x15E4 -#define GUI_SCRATCH_REG1 0x15E4 -#define SCRATCH_REG2 0x15E8 -#define GUI_SCRATCH_REG2 0x15E8 -#define SCRATCH_REG3 0x15EC -#define GUI_SCRATCH_REG3 0x15EC -#define SCRATCH_REG4 0x15F0 -#define GUI_SCRATCH_REG4 0x15F0 -#define SCRATCH_REG5 0x15F4 -#define GUI_SCRATCH_REG5 0x15F4 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DP_BRUSH_FRGD_CLR 0x147C -#define DP_BRUSH_BKGD_CLR 0x1478 -#define DST_LINE_START 0x1600 -#define DST_LINE_END 0x1604 -#define SRC_OFFSET 0x15AC -#define SRC_PITCH 0x15B0 -#define SRC_TILE 0x1704 -#define SRC_PITCH_OFFSET 0x1428 -#define SRC_X 0x1414 -#define SRC_Y 0x1418 -#define SRC_X_Y 0x1590 -#define SRC_Y_X 0x1434 -#define DST_Y_X 0x1438 -#define DST_WIDTH_HEIGHT 0x1598 -#define DST_HEIGHT_WIDTH 0x143c -#define DST_OFFSET 0x1404 -#define SRC_CLUT_ADDRESS 0x1780 -#define SRC_CLUT_DATA 0x1784 -#define SRC_CLUT_DATA_RD 0x1788 -#define HOST_DATA0 0x17C0 -#define HOST_DATA1 0x17C4 -#define HOST_DATA2 0x17C8 -#define HOST_DATA3 0x17CC -#define HOST_DATA4 0x17D0 -#define HOST_DATA5 0x17D4 -#define HOST_DATA6 0x17D8 -#define HOST_DATA7 0x17DC -#define HOST_DATA_LAST 0x17E0 -#define DP_SRC_ENDIAN 0x15D4 -#define DP_SRC_FRGD_CLR 0x15D8 -#define DP_SRC_BKGD_CLR 0x15DC -#define SC_LEFT 0x1640 -#define SC_RIGHT 0x1644 -#define SC_TOP 0x1648 -#define SC_BOTTOM 0x164C -#define SRC_SC_RIGHT 0x1654 -#define SRC_SC_BOTTOM 0x165C -#define DP_CNTL 0x16C0 -#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 -#define DP_DATATYPE 0x16C4 -#define DP_MIX 0x16C8 -#define DP_WRITE_MSK 0x16CC -#define DP_XOP 0x17F8 -#define CLR_CMP_CLR_SRC 0x15C4 -#define CLR_CMP_CLR_DST 0x15C8 -#define CLR_CMP_CNTL 0x15C0 -#define CLR_CMP_MSK 0x15CC -#define DSTCACHE_MODE 0x1710 -#define DSTCACHE_CTLSTAT 0x1714 -#define DEFAULT_PITCH_OFFSET 0x16E0 -#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 -#define DEFAULT_SC_TOP_LEFT 0x16EC -#define SRC_PITCH_OFFSET 0x1428 -#define DST_PITCH_OFFSET 0x142C -#define DP_GUI_MASTER_CNTL 0x146C -#define SC_TOP_LEFT 0x16EC -#define SC_BOTTOM_RIGHT 0x16F0 -#define SRC_SC_BOTTOM_RIGHT 0x16F4 -#define RB2D_DSTCACHE_MODE 0x3428 -#define RB2D_DSTCACHE_CTLSTAT 0x342C -#define LVDS_GEN_CNTL 0x02d0 -#define LVDS_PLL_CNTL 0x02d4 -#define FP2_GEN_CNTL 0x0288 -#define TMDS_CNTL 0x0294 -#define TMDS_CRC 0x02a0 -#define TMDS_TRANSMITTER_CNTL 0x02a4 -#define MPP_TB_CONFIG 0x01c0 -#define PAMAC0_DLY_CNTL 0x0a94 -#define PAMAC1_DLY_CNTL 0x0a98 -#define PAMAC2_DLY_CNTL 0x0a9c -#define FW_CNTL 0x0118 -#define FCP_CNTL 0x0910 -#define VGA_DDA_ON_OFF 0x02ec -#define TV_MASTER_CNTL 0x0800 - -/* #define BASE_CODE 0x0f0b */ -#define BIOS_0_SCRATCH 0x0010 -#define BIOS_1_SCRATCH 0x0014 -#define BIOS_2_SCRATCH 0x0018 -#define BIOS_3_SCRATCH 0x001c -#define BIOS_4_SCRATCH 0x0020 -#define BIOS_5_SCRATCH 0x0024 -#define BIOS_6_SCRATCH 0x0028 -#define BIOS_7_SCRATCH 0x002c - -#define HDP_SOFT_RESET (1 << 26) - -#define TV_DAC_CNTL 0x088c -#define GPIOPAD_MASK 0x0198 -#define GPIOPAD_A 0x019c -#define GPIOPAD_EN 0x01a0 -#define GPIOPAD_Y 0x01a4 -#define ZV_LCDPAD_MASK 0x01a8 -#define ZV_LCDPAD_A 0x01ac -#define ZV_LCDPAD_EN 0x01b0 -#define ZV_LCDPAD_Y 0x01b4 - -/* PLL Registers */ -#define CLK_PIN_CNTL 0x0001 -#define PPLL_CNTL 0x0002 -#define PPLL_REF_DIV 0x0003 -#define PPLL_DIV_0 0x0004 -#define PPLL_DIV_1 0x0005 -#define PPLL_DIV_2 0x0006 -#define PPLL_DIV_3 0x0007 -#define VCLK_ECP_CNTL 0x0008 -#define HTOTAL_CNTL 0x0009 -#define M_SPLL_REF_FB_DIV 0x000a -#define AGP_PLL_CNTL 0x000b -#define SPLL_CNTL 0x000c -#define SCLK_CNTL 0x000d -#define MPLL_CNTL 0x000e -#define MDLL_CKO 0x000f -#define MDLL_RDCKA 0x0010 -#define MCLK_CNTL 0x0012 -#define AGP_PLL_CNTL 0x000b -#define PLL_TEST_CNTL 0x0013 -#define CLK_PWRMGT_CNTL 0x0014 -#define PLL_PWRMGT_CNTL 0x0015 -#define MCLK_MISC 0x001f -#define P2PLL_CNTL 0x002a -#define P2PLL_REF_DIV 0x002b -#define PIXCLKS_CNTL 0x002d -#define SCLK_MORE_CNTL 0x0035 - -/* MCLK_CNTL bit constants */ -#define FORCEON_MCLKA (1 << 16) -#define FORCEON_MCLKB (1 << 17) -#define FORCEON_YCLKA (1 << 18) -#define FORCEON_YCLKB (1 << 19) -#define FORCEON_MC (1 << 20) -#define FORCEON_AIC (1 << 21) - -/* SCLK_CNTL bit constants */ -#define DYN_STOP_LAT_MASK 0x00007ff8 -#define CP_MAX_DYN_STOP_LAT 0x0008 -#define SCLK_FORCEON_MASK 0xffff8000 - -/* SCLK_MORE_CNTL bit constants */ -#define SCLK_MORE_FORCEON 0x0700 - -/* BUS_CNTL bit constants */ -#define BUS_DBL_RESYNC 0x00000001 -#define BUS_MSTR_RESET 0x00000002 -#define BUS_FLUSH_BUF 0x00000004 -#define BUS_STOP_REQ_DIS 0x00000008 -#define BUS_ROTATION_DIS 0x00000010 -#define BUS_MASTER_DIS 0x00000040 -#define BUS_ROM_WRT_EN 0x00000080 -#define BUS_DIS_ROM 0x00001000 -#define BUS_PCI_READ_RETRY_EN 0x00002000 -#define BUS_AGP_AD_STEPPING_EN 0x00004000 -#define BUS_PCI_WRT_RETRY_EN 0x00008000 -#define BUS_MSTR_RD_MULT 0x00100000 -#define BUS_MSTR_RD_LINE 0x00200000 -#define BUS_SUSPEND 0x00400000 -#define LAT_16X 0x00800000 -#define BUS_RD_DISCARD_EN 0x01000000 -#define BUS_RD_ABORT_EN 0x02000000 -#define BUS_MSTR_WS 0x04000000 -#define BUS_PARKING_DIS 0x08000000 -#define BUS_MSTR_DISCONNECT_EN 0x10000000 -#define BUS_WRT_BURST 0x20000000 -#define BUS_READ_BURST 0x40000000 -#define BUS_RDY_READ_DLY 0x80000000 - -/* PIXCLKS_CNTL */ -#define PIX2CLK_SRC_SEL_MASK 0x03 -#define PIX2CLK_SRC_SEL_CPUCLK 0x00 -#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 -#define PIX2CLK_SRC_SEL_BYTECLK 0x02 -#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 -#define PIX2CLK_ALWAYS_ONb (1<<6) -#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) -#define PIXCLK_TV_SRC_SEL (1 << 8) -#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) -#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) - - -/* CLOCK_CNTL_INDEX bit constants */ -#define PLL_WR_EN 0x00000080 - -/* CONFIG_CNTL bit constants */ -#define CONFIG_SYS_VGA_RAM_EN 0x00000100 -#define CONFIG_SYS_ATI_REV_ID_MASK (0xf << 16) -#define CONFIG_SYS_ATI_REV_A11 (0 << 16) -#define CONFIG_SYS_ATI_REV_A12 (1 << 16) -#define CONFIG_SYS_ATI_REV_A13 (2 << 16) - -/* CRTC_EXT_CNTL bit constants */ -#define VGA_ATI_LINEAR 0x00000008 -#define VGA_128KAP_PAGING 0x00000010 -#define XCRT_CNT_EN (1 << 6) -#define CRTC_HSYNC_DIS (1 << 8) -#define CRTC_VSYNC_DIS (1 << 9) -#define CRTC_DISPLAY_DIS (1 << 10) -#define CRTC_CRT_ON (1 << 15) - - -/* DSTCACHE_CTLSTAT bit constants */ -#define RB2D_DC_FLUSH (3 << 0) -#define RB2D_DC_FLUSH_ALL 0xf -#define RB2D_DC_BUSY (1 << 31) - - -/* CRTC_GEN_CNTL bit constants */ -#define CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_CUR_EN 0x00010000 -#define CRTC_INTERLACE_EN (1 << 1) -#define CRTC_BYPASS_LUT_EN (1 << 14) -#define CRTC_EXT_DISP_EN (1 << 24) -#define CRTC_EN (1 << 25) -#define CRTC_DISP_REQ_EN_B (1 << 26) - -/* CRTC_STATUS bit constants */ -#define CRTC_VBLANK 0x00000001 - -/* CRTC2_GEN_CNTL bit constants */ -#define CRT2_ON (1 << 7) -#define CRTC2_DISPLAY_DIS (1 << 23) -#define CRTC2_EN (1 << 25) -#define CRTC2_DISP_REQ_EN_B (1 << 26) - -/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ -#define CUR_LOCK 0x80000000 - -/* GPIO bit constants */ -#define GPIO_A_0 (1 << 0) -#define GPIO_A_1 (1 << 1) -#define GPIO_Y_0 (1 << 8) -#define GPIO_Y_1 (1 << 9) -#define GPIO_EN_0 (1 << 16) -#define GPIO_EN_1 (1 << 17) -#define GPIO_MASK_0 (1 << 24) -#define GPIO_MASK_1 (1 << 25) -#define VGA_DDC_DATA_OUTPUT GPIO_A_0 -#define VGA_DDC_CLK_OUTPUT GPIO_A_1 -#define VGA_DDC_DATA_INPUT GPIO_Y_0 -#define VGA_DDC_CLK_INPUT GPIO_Y_1 -#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 -#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 - - -/* FP bit constants */ -#define FP_CRTC_H_TOTAL_MASK 000003ff -#define FP_CRTC_H_DISP_MASK 0x01ff0000 -#define FP_CRTC_V_TOTAL_MASK 0x00000fff -#define FP_CRTC_V_DISP_MASK 0x0fff0000 -#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -#define FP_H_SYNC_WID_MASK 0x003f0000 -#define FP_V_SYNC_STRT_MASK 0x00000fff -#define FP_V_SYNC_WID_MASK 0x001f0000 -#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_H_DISP_SHIFT 0x00000010 -#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_V_DISP_SHIFT 0x00000010 -#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -#define FP_H_SYNC_WID_SHIFT 0x00000010 -#define FP_V_SYNC_STRT_SHIFT 0x00000000 -#define FP_V_SYNC_WID_SHIFT 0x00000010 - -/* FP_GEN_CNTL bit constants */ -#define FP_FPON (1 << 0) -#define FP_TMDS_EN (1 << 2) -#define FP_PANEL_FORMAT (1 << 3) -#define FP_EN_TMDS (1 << 7) -#define FP_DETECT_SENSE (1 << 8) -#define R200_FP_SOURCE_SEL_MASK (3 << 10) -#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) -#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) -#define R200_FP_SOURCE_SEL_RMX (2 << 10) -#define R200_FP_SOURCE_SEL_TRANS (3 << 10) -#define FP_SEL_CRTC1 (0 << 13) -#define FP_SEL_CRTC2 (1 << 13) -#define FP_USE_VGA_HSYNC (1 << 14) -#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) -#define FP_CRTC_USE_SHADOW_VEND (1 << 18) -#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -#define FP_DFP_SYNC_SEL (1 << 21) -#define FP_CRTC_LOCK_8DOT (1 << 22) -#define FP_CRT_SYNC_SEL (1 << 23) -#define FP_USE_SHADOW_EN (1 << 24) -#define FP_CRT_SYNC_ALT (1 << 26) - -/* FP2_GEN_CNTL bit constants */ -#define FP2_BLANK_EN (1 << 1) -#define FP2_ON (1 << 2) -#define FP2_PANEL_FORMAT (1 << 3) -#define FP2_SOURCE_SEL_MASK (3 << 10) -#define FP2_SOURCE_SEL_CRTC2 (1 << 10) -#define FP2_SRC_SEL_MASK (3 << 13) -#define FP2_SRC_SEL_CRTC2 (1 << 13) -#define FP2_FP_POL (1 << 16) -#define FP2_LP_POL (1 << 17) -#define FP2_SCK_POL (1 << 18) -#define FP2_LCD_CNTL_MASK (7 << 19) -#define FP2_PAD_FLOP_EN (1 << 22) -#define FP2_CRC_EN (1 << 23) -#define FP2_CRC_READ_EN (1 << 24) -#define FP2_DV0_EN (1 << 25) -#define FP2_DV0_RATE_SEL_SDR (1 << 26) - - -/* LVDS_GEN_CNTL bit constants */ -#define LVDS_ON (1 << 0) -#define LVDS_DISPLAY_DIS (1 << 1) -#define LVDS_PANEL_TYPE (1 << 2) -#define LVDS_PANEL_FORMAT (1 << 3) -#define LVDS_EN (1 << 7) -#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 -#define LVDS_BL_MOD_LEVEL_SHIFT 8 -#define LVDS_BL_MOD_EN (1 << 16) -#define LVDS_DIGON (1 << 18) -#define LVDS_BLON (1 << 19) -#define LVDS_SEL_CRTC2 (1 << 23) -#define LVDS_STATE_MASK \ - (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) - -/* LVDS_PLL_CNTL bit constatns */ -#define HSYNC_DELAY_SHIFT 0x1c -#define HSYNC_DELAY_MASK (0xf << 0x1c) - -/* TMDS_TRANSMITTER_CNTL bit constants */ -#define TMDS_PLL_EN (1 << 0) -#define TMDS_PLLRST (1 << 1) -#define TMDS_RAN_PAT_RST (1 << 7) -#define TMDS_ICHCSEL (1 << 28) - -/* FP_HORZ_STRETCH bit constants */ -#define HORZ_STRETCH_RATIO_MASK 0xffff -#define HORZ_STRETCH_RATIO_MAX 4096 -#define HORZ_PANEL_SIZE (0x1ff << 16) -#define HORZ_PANEL_SHIFT 16 -#define HORZ_STRETCH_PIXREP (0 << 25) -#define HORZ_STRETCH_BLEND (1 << 26) -#define HORZ_STRETCH_ENABLE (1 << 25) -#define HORZ_AUTO_RATIO (1 << 27) -#define HORZ_FP_LOOP_STRETCH (0x7 << 28) -#define HORZ_AUTO_RATIO_INC (1 << 31) - - -/* FP_VERT_STRETCH bit constants */ -#define VERT_STRETCH_RATIO_MASK 0xfff -#define VERT_STRETCH_RATIO_MAX 4096 -#define VERT_PANEL_SIZE (0xfff << 12) -#define VERT_PANEL_SHIFT 12 -#define VERT_STRETCH_LINREP (0 << 26) -#define VERT_STRETCH_BLEND (1 << 26) -#define VERT_STRETCH_ENABLE (1 << 25) -#define VERT_AUTO_RATIO_EN (1 << 27) -#define VERT_FP_LOOP_STRETCH (0x7 << 28) -#define VERT_STRETCH_RESERVED 0xf1000000 - -/* DAC_CNTL bit constants */ -#define DAC_8BIT_EN 0x00000100 -#define DAC_4BPP_PIX_ORDER 0x00000200 -#define DAC_CRC_EN 0x00080000 -#define DAC_MASK_ALL (0xff << 24) -#define DAC_PDWN (1 << 15) -#define DAC_EXPAND_MODE (1 << 14) -#define DAC_VGA_ADR_EN (1 << 13) -#define DAC_RANGE_CNTL (3 << 0) -#define DAC_RANGE_CNTL_MASK 0x03 -#define DAC_BLANKING (1 << 2) -#define DAC_CMP_EN (1 << 3) -#define DAC_CMP_OUTPUT (1 << 7) - -/* DAC_CNTL2 bit constants */ -#define DAC2_EXPAND_MODE (1 << 14) -#define DAC2_CMP_EN (1 << 7) -#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) - -/* DAC_EXT_CNTL bit constants */ -#define DAC_FORCE_BLANK_OFF_EN (1 << 4) -#define DAC_FORCE_DATA_EN (1 << 5) -#define DAC_FORCE_DATA_SEL_MASK (3 << 6) -#define DAC_FORCE_DATA_MASK 0x0003ff00 -#define DAC_FORCE_DATA_SHIFT 8 - -/* GEN_RESET_CNTL bit constants */ -#define SOFT_RESET_GUI 0x00000001 -#define SOFT_RESET_VCLK 0x00000100 -#define SOFT_RESET_PCLK 0x00000200 -#define SOFT_RESET_ECP 0x00000400 -#define SOFT_RESET_DISPENG_XCLK 0x00000800 - -/* MEM_CNTL bit constants */ -#define MEM_CTLR_STATUS_IDLE 0x00000000 -#define MEM_CTLR_STATUS_BUSY 0x00100000 -#define MEM_SEQNCR_STATUS_IDLE 0x00000000 -#define MEM_SEQNCR_STATUS_BUSY 0x00200000 -#define MEM_ARBITER_STATUS_IDLE 0x00000000 -#define MEM_ARBITER_STATUS_BUSY 0x00400000 -#define MEM_REQ_UNLOCK 0x00000000 -#define MEM_REQ_LOCK 0x00800000 -#define MEM_NUM_CHANNELS_MASK 0x00000001 -#define MEM_USE_B_CH_ONLY 0x00000002 -#define RV100_MEM_HALF_MODE 0x00000008 -#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 -#define R300_MEM_USE_CD_CH_ONLY 0x00000004 - - -/* RBBM_SOFT_RESET bit constants */ -#define SOFT_RESET_CP (1 << 0) -#define SOFT_RESET_HI (1 << 1) -#define SOFT_RESET_SE (1 << 2) -#define SOFT_RESET_RE (1 << 3) -#define SOFT_RESET_PP (1 << 4) -#define SOFT_RESET_E2 (1 << 5) -#define SOFT_RESET_RB (1 << 6) -#define SOFT_RESET_HDP (1 << 7) - -/* SURFACE_CNTL bit consants */ -#define SURF_TRANSLATION_DIS (1 << 8) -#define NONSURF_AP0_SWP_16BPP (1 << 20) -#define NONSURF_AP0_SWP_32BPP (1 << 21) -#define NONSURF_AP1_SWP_16BPP (1 << 22) -#define NONSURF_AP1_SWP_32BPP (1 << 23) - -#define R200_SURF_TILE_COLOR_MACRO (1 << 16) - -/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ -#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) - -/* MM_INDEX bit constants */ -#define MM_APER 0x80000000 - -/* CLR_CMP_CNTL bit constants */ -#define COMPARE_SRC_FALSE 0x00000000 -#define COMPARE_SRC_TRUE 0x00000001 -#define COMPARE_SRC_NOT_EQUAL 0x00000004 -#define COMPARE_SRC_EQUAL 0x00000005 -#define COMPARE_SRC_EQUAL_FLIP 0x00000007 -#define COMPARE_DST_FALSE 0x00000000 -#define COMPARE_DST_TRUE 0x00000100 -#define COMPARE_DST_NOT_EQUAL 0x00000400 -#define COMPARE_DST_EQUAL 0x00000500 -#define COMPARE_DESTINATION 0x00000000 -#define COMPARE_SOURCE 0x01000000 -#define COMPARE_SRC_AND_DST 0x02000000 - - -/* DP_CNTL bit constants */ -#define DST_X_RIGHT_TO_LEFT 0x00000000 -#define DST_X_LEFT_TO_RIGHT 0x00000001 -#define DST_Y_BOTTOM_TO_TOP 0x00000000 -#define DST_Y_TOP_TO_BOTTOM 0x00000002 -#define DST_X_MAJOR 0x00000000 -#define DST_Y_MAJOR 0x00000004 -#define DST_X_TILE 0x00000008 -#define DST_Y_TILE 0x00000010 -#define DST_LAST_PEL 0x00000020 -#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 -#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 -#define DST_BRES_SIGN 0x00000100 -#define DST_HOST_BIG_ENDIAN_EN 0x00000200 -#define DST_POLYLINE_NONLAST 0x00008000 -#define DST_RASTER_STALL 0x00010000 -#define DST_POLY_EDGE 0x00040000 - - -/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ -#define DST_X_MAJOR_S 0x00000000 -#define DST_Y_MAJOR_S 0x00000001 -#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 -#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 -#define DST_X_RIGHT_TO_LEFT_S 0x00000000 -#define DST_X_LEFT_TO_RIGHT_S 0x80000000 - - -/* DP_DATATYPE bit constants */ -#define DST_8BPP 0x00000002 -#define DST_15BPP 0x00000003 -#define DST_16BPP 0x00000004 -#define DST_24BPP 0x00000005 -#define DST_32BPP 0x00000006 -#define DST_8BPP_RGB332 0x00000007 -#define DST_8BPP_Y8 0x00000008 -#define DST_8BPP_RGB8 0x00000009 -#define DST_16BPP_VYUY422 0x0000000b -#define DST_16BPP_YVYU422 0x0000000c -#define DST_32BPP_AYUV444 0x0000000e -#define DST_16BPP_ARGB4444 0x0000000f -#define BRUSH_SOLIDCOLOR 0x00000d00 -#define SRC_MONO 0x00000000 -#define SRC_MONO_LBKGD 0x00010000 -#define SRC_DSTCOLOR 0x00030000 -#define BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define BYTE_ORDER_LSB_TO_MSB 0x40000000 -#define DP_CONVERSION_TEMP 0x80000000 -#define HOST_BIG_ENDIAN_EN (1 << 29) - - -/* DP_GUI_MASTER_CNTL bit constants */ -#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 -#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 -#define GMC_SRC_CLIP_DEFAULT 0x00000000 -#define GMC_SRC_CLIP_LEAVE 0x00000004 -#define GMC_DST_CLIP_DEFAULT 0x00000000 -#define GMC_DST_CLIP_LEAVE 0x00000008 -#define GMC_BRUSH_8x8MONO 0x00000000 -#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 -#define GMC_BRUSH_8x1MONO 0x00000020 -#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 -#define GMC_BRUSH_1x8MONO 0x00000040 -#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 -#define GMC_BRUSH_32x1MONO 0x00000060 -#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 -#define GMC_BRUSH_32x32MONO 0x00000080 -#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 -#define GMC_BRUSH_8x8COLOR 0x000000a0 -#define GMC_BRUSH_8x1COLOR 0x000000b0 -#define GMC_BRUSH_1x8COLOR 0x000000c0 -#define GMC_BRUSH_SOLID_COLOR 0x000000d0 -#define GMC_DST_8BPP 0x00000200 -#define GMC_DST_15BPP 0x00000300 -#define GMC_DST_16BPP 0x00000400 -#define GMC_DST_24BPP 0x00000500 -#define GMC_DST_32BPP 0x00000600 -#define GMC_DST_8BPP_RGB332 0x00000700 -#define GMC_DST_8BPP_Y8 0x00000800 -#define GMC_DST_8BPP_RGB8 0x00000900 -#define GMC_DST_16BPP_VYUY422 0x00000b00 -#define GMC_DST_16BPP_YVYU422 0x00000c00 -#define GMC_DST_32BPP_AYUV444 0x00000e00 -#define GMC_DST_16BPP_ARGB4444 0x00000f00 -#define GMC_SRC_MONO 0x00000000 -#define GMC_SRC_MONO_LBKGD 0x00001000 -#define GMC_SRC_DSTCOLOR 0x00003000 -#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 -#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 -#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 -#define GMC_DP_SRC_RECT 0x02000000 -#define GMC_DP_SRC_HOST 0x03000000 -#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 -#define GMC_3D_FCN_EN_CLR 0x00000000 -#define GMC_3D_FCN_EN_SET 0x08000000 -#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 -#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 -#define GMC_AUX_CLIP_LEAVE 0x00000000 -#define GMC_AUX_CLIP_CLEAR 0x20000000 -#define GMC_WRITE_MASK_LEAVE 0x00000000 -#define GMC_WRITE_MASK_SET 0x40000000 -#define GMC_CLR_CMP_CNTL_DIS (1 << 28) -#define GMC_SRC_DATATYPE_COLOR (3 << 12) -#define ROP3_S 0x00cc0000 -#define ROP3_SRCCOPY 0x00cc0000 -#define ROP3_P 0x00f00000 -#define ROP3_PATCOPY 0x00f00000 -#define DP_SRC_SOURCE_MASK (7 << 24) -#define GMC_BRUSH_NONE (15 << 4) -#define DP_SRC_SOURCE_MEMORY (2 << 24) -#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 - -/* DP_MIX bit constants */ -#define DP_SRC_RECT 0x00000200 -#define DP_SRC_HOST 0x00000300 -#define DP_SRC_HOST_BYTEALIGN 0x00000400 - -/* MPLL_CNTL bit constants */ -#define MPLL_RESET 0x00000001 - -/* MDLL_CKO bit constants */ -#define MCKOA_SLEEP 0x00000001 -#define MCKOA_RESET 0x00000002 -#define MCKOA_REF_SKEW_MASK 0x00000700 -#define MCKOA_FB_SKEW_MASK 0x00007000 - -/* MDLL_RDCKA bit constants */ -#define MRDCKA0_SLEEP 0x00000001 -#define MRDCKA0_RESET 0x00000002 -#define MRDCKA1_SLEEP 0x00010000 -#define MRDCKA1_RESET 0x00020000 - -/* VCLK_ECP_CNTL constants */ -#define VCLK_SRC_SEL_MASK 0x03 -#define VCLK_SRC_SEL_CPUCLK 0x00 -#define VCLK_SRC_SEL_PSCANCLK 0x01 -#define VCLK_SRC_SEL_BYTECLK 0x02 -#define VCLK_SRC_SEL_PPLLCLK 0x03 -#define PIXCLK_ALWAYS_ONb 0x00000040 -#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 - -/* BUS_CNTL1 constants */ -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 -#define BUS_CNTL1_AGPCLK_VALID 0x80000000 - -/* PLL_PWRMGT_CNTL constants */ -#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 -#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 -#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 -#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 -#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 -#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 -#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 - -/* TV_DAC_CNTL constants */ -#define TV_DAC_CNTL_BGSLEEP 0x00000040 -#define TV_DAC_CNTL_DETECT 0x00000010 -#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 -#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 -#define TV_DAC_CNTL_BGADJ__SHIFT 16 -#define TV_DAC_CNTL_DACADJ__SHIFT 20 -#define TV_DAC_CNTL_RDACPD 0x01000000 -#define TV_DAC_CNTL_GDACPD 0x02000000 -#define TV_DAC_CNTL_BDACPD 0x04000000 - -/* DISP_MISC_CNTL constants */ -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) -#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) -#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) -#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) -#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) - -/* DISP_PWR_MAN constants */ -#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) -#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) -#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) -#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) -#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) -#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) -#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) -#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) -#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) -#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) -#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) -#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) -#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) - -/* masks */ - -#define CONFIG_MEMSIZE_MASK 0x1f000000 -#define MEM_CFG_TYPE 0x40000000 -#define DST_OFFSET_MASK 0x003fffff -#define DST_PITCH_MASK 0x3fc00000 -#define DEFAULT_TILE_MASK 0xc0000000 -#define PPLL_DIV_SEL_MASK 0x00000300 -#define PPLL_RESET 0x00000001 -#define PPLL_SLEEP 0x00000002 -#define PPLL_ATOMIC_UPDATE_EN 0x00010000 -#define PPLL_REF_DIV_MASK 0x000003ff -#define PPLL_FB3_DIV_MASK 0x000007ff -#define PPLL_POST3_DIV_MASK 0x00070000 -#define PPLL_ATOMIC_UPDATE_R 0x00008000 -#define PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 -#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) -#define R300_PPLL_REF_DIV_ACC_SHIFT 18 - -#define GUI_ACTIVE 0x80000000 - - -#define MC_IND_INDEX 0x01F8 -#define MC_IND_DATA 0x01FC - -/* PAD_CTLR_STRENGTH */ -#define PAD_MANUAL_OVERRIDE 0x80000000 - -/* pllCLK_PIN_CNTL */ -#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L -#define CLK_PIN_CNTL__OSC_EN 0x00000001L -#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L -#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L -#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L -#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L -#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L -#define CLK_PIN_CNTL__CG_SPARE 0x00004000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L -#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L -#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L - -/* pllCLK_PWRMGT_CNTL */ -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 -#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 -#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f -#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 -#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 -#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 -#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 -#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f - -/* pllP2PLL_CNTL */ -#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L -#define P2PLL_CNTL__P2PLL_RESET 0x00000001L -#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L -#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L -#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L -#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L -#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L -#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L -#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L -#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L -#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L -#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L -#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L - -/* pllPIXCLKS_CNTL */ -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 -#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f - - -/* pllPIXCLKS_CNTL */ -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L -#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L -#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) -#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) -#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) -#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) -#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) -#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) -#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) -#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) - - -/* pllP2PLL_DIV_0 */ -#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L -#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L - -/* pllSCLK_CNTL */ -#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L -#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L -#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L -#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L -#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L -#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L -#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L -#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L -#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L -#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L -#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L -#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L -#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L -#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 -#define SCLK_CNTL__FORCE_DISP2 0x00008000L -#define SCLK_CNTL__FORCE_CP 0x00010000L -#define SCLK_CNTL__FORCE_HDP 0x00020000L -#define SCLK_CNTL__FORCE_DISP1 0x00040000L -#define SCLK_CNTL__FORCE_TOP 0x00080000L -#define SCLK_CNTL__FORCE_E2 0x00100000L -#define SCLK_CNTL__FORCE_SE 0x00200000L -#define SCLK_CNTL__FORCE_IDCT 0x00400000L -#define SCLK_CNTL__FORCE_VIP 0x00800000L -#define SCLK_CNTL__FORCE_RE 0x01000000L -#define SCLK_CNTL__FORCE_PB 0x02000000L -#define SCLK_CNTL__FORCE_TAM 0x04000000L -#define SCLK_CNTL__FORCE_TDM 0x08000000L -#define SCLK_CNTL__FORCE_RB 0x10000000L -#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L -#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L -#define SCLK_CNTL__FORCE_OV0 0x80000000L -#define SCLK_CNTL__R300_FORCE_VAP (1<<21) -#define SCLK_CNTL__R300_FORCE_SR (1<<25) -#define SCLK_CNTL__R300_FORCE_PX (1<<26) -#define SCLK_CNTL__R300_FORCE_TX (1<<27) -#define SCLK_CNTL__R300_FORCE_US (1<<28) -#define SCLK_CNTL__R300_FORCE_SU (1<<30) -#define SCLK_CNTL__FORCEON_MASK 0xffff8000L - -/* pllSCLK_CNTL2 */ -#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) -#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) -#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) -#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) -#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) -#define SCLK_CNTL2__R300_FORCE_GA (1<<15) - -/* SCLK_MORE_CNTL */ -#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L -#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L -#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L -#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L -#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L -#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L -#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L -#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L -#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L -#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L -#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L -#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L -#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L -#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L -#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L -#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L -#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L -#define SCLK_MORE_CNTL__FORCEON 0x00000700L - -/* MCLK_CNTL */ -#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L -#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L -#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L -#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L -#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L -#define MCLK_CNTL__FORCE_MCLKA 0x00010000L -#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L -#define MCLK_CNTL__FORCE_MCLKB 0x00020000L -#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L -#define MCLK_CNTL__FORCE_YCLKA 0x00040000L -#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L -#define MCLK_CNTL__FORCE_YCLKB 0x00080000L -#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L -#define MCLK_CNTL__FORCE_MC 0x00100000L -#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L -#define MCLK_CNTL__FORCE_AIC 0x00200000L -#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L -#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L -#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L -#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L -#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) -#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) - -/* MCLK_MISC */ -#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L -#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L -#define MCLK_MISC__DLL_READY_LAT 0x00000100L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L -#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L -#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L -#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L -#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L -#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L - -/* VCLK_ECP_CNTL */ -#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L -#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L -#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L -#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L -#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L -#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L -#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L -#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L -#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) - -/* PLL_PWRMGT_CNTL */ -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L -#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L -#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L -#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L -#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L -#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L -#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L - -/* CLK_PWRMGT_CNTL */ -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L -#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L -#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L -#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L -#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L -#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L -#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L -#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L -#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L -#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L -#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L -#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L -#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L - -/* BUS_CNTL1 */ -#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L -#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L -#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L -#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L -#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L -#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L -#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L -#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L -#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L -#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L -#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L -#define BUS_CNTL1__AGPCLK_VALID 0x80000000L - -/* BUS_CNTL1 */ -#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 -#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 -#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 -#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b -#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a -#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c -#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f - -/* CRTC_OFFSET_CNTL */ -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L - -/* CRTC_GEN_CNTL */ -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L -#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L -#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L -#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L -#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L -#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L -#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L - -/* CRTC2_GEN_CNTL */ -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L -#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L -#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L -#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L - -/* AGP_CNTL */ -#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL -#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L -#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L -#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L -#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L -#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L -#define AGP_CNTL__EN_2X_STBB 0x00000400L -#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L -#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L -#define AGP_CNTL__SBA_DIS_MASK 0x00001000L -#define AGP_CNTL__SBA_DIS 0x00001000L -#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L -#define AGP_CNTL__AGP_REV_ID 0x00002000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L -#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L -#define AGP_CNTL__FORCE_INT_VREF 0x00010000L -#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L -#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L -#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L -#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L -#define AGP_CNTL__EN_RBFCALM 0x00800000L -#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L -#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L -#define AGP_CNTL__DIS_RBF_MASK 0x02000000L -#define AGP_CNTL__DIS_RBF 0x02000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L -#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L - -/* AGP_CNTL */ -#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 -#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 -#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 -#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a -#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b -#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c -#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d -#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f -#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 -#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 -#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 -#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 -#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 -#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 -#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 -#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a -#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b -#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e - -/* DISP_MISC_CNTL */ -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L -#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L -#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L -#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L -#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L -#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L - -/* DISP_PWR_MAN */ -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L -#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L -#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L -#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L -#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L -#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L -#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L -#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L - -/* MC_IND_INDEX */ -#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL -#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L -#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L - -/* MC_IND_DATA */ -#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL - -/* MC_CHP_IO_CNTL_A1 */ -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f - -/* MC_CHP_IO_CNTL_B1 */ -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f - -/* MC_CHP_IO_CNTL_A1 */ -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L - -/* MC_CHP_IO_CNTL_B1 */ -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L - -/* MEM_SDRAM_MODE_REG */ -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L - -/* MEM_SDRAM_MODE_REG */ -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f - -/* MEM_REFRESH_CNTL */ -#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L -#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L - -/* MC_STATUS */ -#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L -#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L -#define MC_STATUS__MC_IDLE_MASK 0x00000004L -#define MC_STATUS__MC_IDLE 0x00000004L -#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L -#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L -#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L -#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L -#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L -#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L -#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L -#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L -#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L -#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L - -/* MDLL_CKO */ -#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L -#define MDLL_CKO__MCKOA_SLEEP 0x00000001L -#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L -#define MDLL_CKO__MCKOA_RESET 0x00000002L -#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL -#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L -#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L -#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L -#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L -#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L -#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L -#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L -#define MDLL_CKO__MCKOB_SLEEP 0x00010000L -#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L -#define MDLL_CKO__MCKOB_RESET 0x00020000L -#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L -#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L -#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L -#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L -#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L -#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L -#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L - -/* MDLL_RDCKA */ -#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L -#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L -#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L -#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L -#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L -#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L - -/* MDLL_RDCKB */ -#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L -#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L -#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L -#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L -#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L -#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L - -#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L -#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L -#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L -#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L -#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L -#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L -#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L -#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L - -#define pllCLK_PIN_CNTL 0x0001 -#define pllPPLL_CNTL 0x0002 -#define pllPPLL_REF_DIV 0x0003 -#define pllPPLL_DIV_0 0x0004 -#define pllPPLL_DIV_1 0x0005 -#define pllPPLL_DIV_2 0x0006 -#define pllPPLL_DIV_3 0x0007 -#define pllVCLK_ECP_CNTL 0x0008 -#define pllHTOTAL_CNTL 0x0009 -#define pllM_SPLL_REF_FB_DIV 0x000A -#define pllAGP_PLL_CNTL 0x000B -#define pllSPLL_CNTL 0x000C -#define pllSCLK_CNTL 0x000D -#define pllMPLL_CNTL 0x000E -#define pllMDLL_CKO 0x000F -#define pllMDLL_RDCKA 0x0010 -#define pllMDLL_RDCKB 0x0011 -#define pllMCLK_CNTL 0x0012 -#define pllPLL_TEST_CNTL 0x0013 -#define pllCLK_PWRMGT_CNTL 0x0014 -#define pllPLL_PWRMGT_CNTL 0x0015 -#define pllCG_TEST_MACRO_RW_WRITE 0x0016 -#define pllCG_TEST_MACRO_RW_READ 0x0017 -#define pllCG_TEST_MACRO_RW_DATA 0x0018 -#define pllCG_TEST_MACRO_RW_CNTL 0x0019 -#define pllDISP_TEST_MACRO_RW_WRITE 0x001A -#define pllDISP_TEST_MACRO_RW_READ 0x001B -#define pllDISP_TEST_MACRO_RW_DATA 0x001C -#define pllDISP_TEST_MACRO_RW_CNTL 0x001D -#define pllSCLK_CNTL2 0x001E -#define pllMCLK_MISC 0x001F -#define pllTV_PLL_FINE_CNTL 0x0020 -#define pllTV_PLL_CNTL 0x0021 -#define pllTV_PLL_CNTL1 0x0022 -#define pllTV_DTO_INCREMENTS 0x0023 -#define pllSPLL_AUX_CNTL 0x0024 -#define pllMPLL_AUX_CNTL 0x0025 -#define pllP2PLL_CNTL 0x002A -#define pllP2PLL_REF_DIV 0x002B -#define pllP2PLL_DIV_0 0x002C -#define pllPIXCLKS_CNTL 0x002D -#define pllHTOTAL2_CNTL 0x002E -#define pllSSPLL_CNTL 0x0030 -#define pllSSPLL_REF_DIV 0x0031 -#define pllSSPLL_DIV_0 0x0032 -#define pllSS_INT_CNTL 0x0033 -#define pllSS_TST_CNTL 0x0034 -#define pllSCLK_MORE_CNTL 0x0035 - -#define ixMC_PERF_CNTL 0x0000 -#define ixMC_PERF_SEL 0x0001 -#define ixMC_PERF_REGION_0 0x0002 -#define ixMC_PERF_REGION_1 0x0003 -#define ixMC_PERF_COUNT_0 0x0004 -#define ixMC_PERF_COUNT_1 0x0005 -#define ixMC_PERF_COUNT_2 0x0006 -#define ixMC_PERF_COUNT_3 0x0007 -#define ixMC_PERF_COUNT_MEMCH_A 0x0008 -#define ixMC_PERF_COUNT_MEMCH_B 0x0009 -#define ixMC_IMP_CNTL 0x000A -#define ixMC_CHP_IO_CNTL_A0 0x000B -#define ixMC_CHP_IO_CNTL_A1 0x000C -#define ixMC_CHP_IO_CNTL_B0 0x000D -#define ixMC_CHP_IO_CNTL_B1 0x000E -#define ixMC_IMP_CNTL_0 0x000F -#define ixTC_MISMATCH_1 0x0010 -#define ixTC_MISMATCH_2 0x0011 -#define ixMC_BIST_CTRL 0x0012 -#define ixREG_COLLAR_WRITE 0x0013 -#define ixREG_COLLAR_READ 0x0014 -#define ixR300_MC_IMP_CNTL 0x0018 -#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 -#define ixR300_MC_CHP_IO_CNTL_A1 0x001a -#define ixR300_MC_CHP_IO_CNTL_B0 0x001b -#define ixR300_MC_CHP_IO_CNTL_B1 0x001c -#define ixR300_MC_CHP_IO_CNTL_C0 0x001d -#define ixR300_MC_CHP_IO_CNTL_C1 0x001e -#define ixR300_MC_CHP_IO_CNTL_D0 0x001f -#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 -#define ixR300_MC_IMP_CNTL_0 0x0021 -#define ixR300_MC_ELPIDA_CNTL 0x0022 -#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 -#define ixR300_MC_READ_CNTL_CD 0x0024 -#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 -#define ixR300_MC_DEBUG_CNTL 0x0026 -#define ixR300_MC_BIST_CNTL_0 0x0028 -#define ixR300_MC_BIST_CNTL_1 0x0029 -#define ixR300_MC_BIST_CNTL_2 0x002a -#define ixR300_MC_BIST_CNTL_3 0x002b -#define ixR300_MC_BIST_CNTL_4 0x002c -#define ixR300_MC_BIST_CNTL_5 0x002d -#define ixR300_MC_IMP_STATUS 0x002e -#define ixR300_MC_DLL_CNTL 0x002f -#define NB_TOM 0x15C - -#endif /* _RADEON_H */ diff --git a/include/stdio.h b/include/stdio.h index 039f7df..1939a48 100644 --- a/include/stdio.h +++ b/include/stdio.h @@ -10,9 +10,9 @@ int tstc(void); /* stdout */ #if !defined(CONFIG_SPL_BUILD) || \ - (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL_SUPPORT)) || \ + (defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL)) || \ (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && \ - defined(CONFIG_SPL_SERIAL_SUPPORT)) + defined(CONFIG_SPL_SERIAL)) void putc(const char c); void puts(const char *s); int __printf(1, 2) printf(const char *fmt, ...); diff --git a/include/test/ut.h b/include/test/ut.h index 656e25f..fb2e5fc 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -83,6 +83,21 @@ int ut_check_console_linen(struct unit_test_state *uts, const char *fmt, ...) int ut_check_skipline(struct unit_test_state *uts); /** + * ut_check_skip_to_line() - skip output until a line is found + * + * This creates a string and then checks it against the following lines of + * console output obtained with console_record_readline() until it is found. + * + * After the function returns, uts->expect_str holds the expected string and + * uts->actual_str holds the actual string read from the console. + * + * @uts: Test state + * @fmt: printf() format string to look for, followed by args + * @return 0 if OK, -ENOENT if not found, other value on error + */ +int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...); + +/** * ut_check_console_end() - Check there is no more console output * * After the function returns, uts->actual_str holds the actual string read @@ -286,6 +301,15 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes); return CMD_RET_FAILURE; \ } \ +/* Assert that a following console output line matches */ +#define ut_assert_skip_to_line(fmt, args...) \ + if (ut_check_skip_to_line(uts, fmt, ##args)) { \ + ut_failf(uts, __FILE__, __LINE__, __func__, \ + "console", "\nExpected '%s',\n got to '%s'", \ + uts->expect_str, uts->actual_str); \ + return CMD_RET_FAILURE; \ + } \ + /* Assert that there is no more console output */ #define ut_assert_console_end() \ if (ut_check_console_end(uts)) { \ diff --git a/include/u-boot/hash.h b/include/u-boot/hash.h new file mode 100644 index 0000000..f9d47a9 --- /dev/null +++ b/include/u-boot/hash.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2021 ASPEED Technology Inc. + */ +#ifndef _UBOOT_HASH_H +#define _UBOOT_HASH_H + +enum HASH_ALGO { + HASH_ALGO_CRC16_CCITT, + HASH_ALGO_CRC32, + HASH_ALGO_MD5, + HASH_ALGO_SHA1, + HASH_ALGO_SHA256, + HASH_ALGO_SHA384, + HASH_ALGO_SHA512, + + HASH_ALGO_NUM, + + HASH_ALGO_INVALID = 0xffffffff, +}; + +/* general APIs for hash algo information */ +enum HASH_ALGO hash_algo_lookup_by_name(const char *name); +ssize_t hash_algo_digest_size(enum HASH_ALGO algo); +const char *hash_algo_name(enum HASH_ALGO algo); + +/* device-dependent APIs */ +int hash_digest(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf); +int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz); +int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp); +int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen); +int hash_finish(struct udevice *dev, void *ctx, void *obuf); + +/* + * struct hash_ops - Driver model for Hash operations + * + * The uclass interface is implemented by all hash devices + * which use driver model. + */ +struct hash_ops { + /* progressive operations */ + int (*hash_init)(struct udevice *dev, enum HASH_ALGO algo, void **ctxp); + int (*hash_update)(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen); + int (*hash_finish)(struct udevice *dev, void *ctx, void *obuf); + + /* all-in-one operation */ + int (*hash_digest)(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf); + + /* all-in-one operation with watchdog triggering every chunk_sz */ + int (*hash_digest_wd)(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz); +}; + +#endif diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index 6d48592..d61364c 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -19,6 +19,10 @@ struct MD5Context { }; }; +void MD5Init(struct MD5Context *ctx); +void MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len); +void MD5Final(unsigned char digest[16], struct MD5Context *ctx); + /* * Calculate and store in 'output' the MD5 digest of 'len' bytes at * 'input'. 'output' must have enough space to hold 16 bytes. diff --git a/include/version.h b/include/version.h index 2d24451..5955b21 100644 --- a/include/version.h +++ b/include/version.h @@ -7,16 +7,8 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#include <timestamp.h> - #ifndef DO_DEPS_ONLY #include "generated/version_autogenerated.h" #endif -#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \ - U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING - -#ifndef __ASSEMBLY__ -extern const char version_string[]; -#endif /* __ASSEMBLY__ */ #endif /* __VERSION_H__ */ diff --git a/include/version_string.h b/include/version_string.h new file mode 100644 index 0000000..a89a6e4 --- /dev/null +++ b/include/version_string.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __VERSION_STRING_H__ +#define __VERSION_STRING_H__ + +extern const char version_string[]; + +#endif /* __VERSION_STRING_H__ */ diff --git a/include/wdt.h b/include/wdt.h index bc242c2..baaa9db 100644 --- a/include/wdt.h +++ b/include/wdt.h @@ -38,6 +38,14 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags); int wdt_stop(struct udevice *dev); /* + * Stop all registered watchdog devices. + * + * @return: 0 if ok, first error encountered otherwise (but wdt_stop() + * is still called on following devices) + */ +int wdt_stop_all(void); + +/* * Reset the timer, typically restoring the counter to * the value configured by start() * |