diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/configs/odroid_m1.h | 11 | ||||
-rw-r--r-- | include/configs/px30_common.h | 5 | ||||
-rw-r--r-- | include/dm/read.h | 21 | ||||
-rw-r--r-- | include/linux/usb/phy-rockchip-usbdp.h | 70 |
4 files changed, 105 insertions, 2 deletions
diff --git a/include/configs/odroid_m1.h b/include/configs/odroid_m1.h new file mode 100644 index 0000000..0d2e9fd --- /dev/null +++ b/include/configs/odroid_m1.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ODROID_M1_H +#define __ODROID_M1_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "cramfsaddr=0x0c000000\0" + +#include <configs/rk3568_common.h> + +#endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 6fbd267..13ed901 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -21,8 +21,9 @@ "pxefile_addr_r=0x00600000\0" \ "fdt_addr_r=0x08300000\0" \ "kernel_addr_r=0x00280000\0" \ - "kernel_addr_c=0x03e80000\0" \ - "ramdisk_addr_r=0x0a200000\0" + "ramdisk_addr_r=0x0a200000\0" \ + "kernel_comp_addr_r=0x03e80000\0" \ + "kernel_comp_size=0x2000000\0" #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/dm/read.h b/include/dm/read.h index 137f2a5..c2615f7 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -247,6 +247,20 @@ fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, fdt_size_t *size); /** + * dev_read_addr_size_index_ptr() - Get the indexed reg property of a device + * as a pointer + * + * @dev: Device to read from + * @index: the 'reg' property can hold a list of <addr, size> pairs + * and @index is used to select which one is required + * @size: place to put size value (on success) + * + * Return: pointer or NULL if not found + */ +void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index, + fdt_size_t *size); + +/** * dev_remap_addr_index() - Get the indexed reg property of a device * as a memory-mapped I/O pointer * @@ -952,6 +966,13 @@ static inline fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, return devfdt_get_addr_size_index(dev, index, size); } +static inline void *dev_read_addr_size_index_ptr(const struct udevice *dev, + int index, + fdt_size_t *size) +{ + return devfdt_get_addr_size_index_ptr(dev, index, size); +} + static inline fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name) { diff --git a/include/linux/usb/phy-rockchip-usbdp.h b/include/linux/usb/phy-rockchip-usbdp.h new file mode 100644 index 0000000..8acfa6d --- /dev/null +++ b/include/linux/usb/phy-rockchip-usbdp.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip USBDP Combo PHY with Samsung IP block driver + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __PHY_ROCKCHIP_USBDP_H_ +#define __PHY_ROCKCHIP_USBDP_H_ + +#include <linux/bitops.h> + +/* RK3588 USBDP PHY Register Definitions */ + +#define UDPHY_PCS 0x4000 +#define UDPHY_PMA 0x8000 + +/* VO0 GRF Registers */ +#define RK3588_GRF_VO0_CON0 0x0000 +#define RK3588_GRF_VO0_CON2 0x0008 +#define DP_SINK_HPD_CFG BIT(11) +#define DP_SINK_HPD_SEL BIT(10) +#define DP_AUX_DIN_SEL BIT(9) +#define DP_AUX_DOUT_SEL BIT(8) +#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) +#define DP_LANE_SEL_ALL GENMASK(7, 0) +#define PHY_AUX_DP_DATA_POL_NORMAL 0 +#define PHY_AUX_DP_DATA_POL_INVERT 1 + +/* PMA CMN Registers */ +#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ +#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) +#define CMN_DP_LANE_EN_N(n) BIT(n) +#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) +#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) +#define PHY_LANE_MUX_USB 0 +#define PHY_LANE_MUX_DP 1 + +#define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */ +#define CMN_DP_TX_LINK_BW GENMASK(6, 5) +#define CMN_DP_TX_LANE_SWAP_EN BIT(2) + +#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ +#define CMN_ROPLL_SSC_EN BIT(1) +#define CMN_LCPLL_SSC_EN BIT(0) + +#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ +#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) +#define CMN_ANA_LCPLL_AFC_DONE BIT(6) + +#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ +#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) +#define CMN_ANA_ROPLL_AFC_DONE BIT(0) + +#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ +#define CMN_DP_INIT_RSTN BIT(3) +#define CMN_DP_CMN_RSTN BIT(2) +#define CMN_CDR_WTCHDG_EN BIT(1) +#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) + +#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ +#define LN_ANA_TX_SER_TXCLK_INV BIT(1) + +#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ +#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) + +#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ +#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) + +#endif |