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-rw-r--r--include/configs/M5272C3.h20
-rw-r--r--include/configs/MPC8540ADS.h8
-rw-r--r--include/configs/MPC8548CDS.h17
-rw-r--r--include/configs/MPC8560ADS.h8
-rw-r--r--include/configs/P2041RDB.h18
-rw-r--r--include/configs/cobra5272.h30
-rw-r--r--include/configs/corenet_ds.h22
-rw-r--r--include/configs/p1_p2_rdb_pc.h19
-rw-r--r--include/configs/socrates.h9
9 files changed, 0 insertions, 151 deletions
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 1204aa0..2121b29 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -146,26 +146,6 @@
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
-#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
-#define CONFIG_SYS_BR1_PRELIM 0
-#define CONFIG_SYS_OR1_PRELIM 0
-#define CONFIG_SYS_BR2_PRELIM 0x30000001
-#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
-#define CONFIG_SYS_BR3_PRELIM 0
-#define CONFIG_SYS_OR3_PRELIM 0
-#define CONFIG_SYS_BR4_PRELIM 0
-#define CONFIG_SYS_OR4_PRELIM 0
-#define CONFIG_SYS_BR5_PRELIM 0
-#define CONFIG_SYS_OR5_PRELIM 0
-#define CONFIG_SYS_BR6_PRELIM 0
-#define CONFIG_SYS_OR6_PRELIM 0
-#define CONFIG_SYS_BR7_PRELIM 0x00000701
-#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
-
-/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_PACNT 0x00000000
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 9b6bf33..ab029aa 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -90,9 +90,7 @@
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
-#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@@ -131,8 +129,6 @@
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
-
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
@@ -147,8 +143,6 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@@ -176,8 +170,6 @@
/*
* 32KB, 8-bit wide for ADS config reg
*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8000801
-#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
#define CONFIG_SYS_INIT_RAM_LOCK 1
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 23c7fec..349b486 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -134,14 +134,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_BR0_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_BR1_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM 0xff806e65
-#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
@@ -185,10 +177,6 @@ extern unsigned long get_clock_freq(void);
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
- | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
-
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
@@ -203,8 +191,6 @@ extern unsigned long get_clock_freq(void);
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@@ -263,9 +249,6 @@ extern unsigned long get_clock_freq(void);
#else
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
-#define CONFIG_SYS_BR3_PRELIM \
- (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 102c945..2167dcd 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -90,9 +90,7 @@
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
-#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
-#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@@ -131,8 +129,6 @@
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
-
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
@@ -147,8 +143,6 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@@ -176,8 +170,6 @@
/*
* 32KB, 8-bit wide for ADS config reg
*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8000801
-#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
#define CONFIG_SYS_INIT_RAM_LOCK 1
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 1f10fb1..ef4bb0b 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -137,9 +137,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CPLD_BASE_PHYS CPLD_BASE
#endif
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
@@ -185,21 +182,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 7c4638f..be62caa 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -246,36 +246,6 @@ enter a valid image address in flash */
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
- * Memory bank definitions
- *
- * Please refer also to Motorola Coldfire user manual - Chapter XXX
- * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
- */
-#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
-#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
-
-#define CONFIG_SYS_BR1_PRELIM 0
-#define CONFIG_SYS_OR1_PRELIM 0
-
-#define CONFIG_SYS_BR2_PRELIM 0
-#define CONFIG_SYS_OR2_PRELIM 0
-
-#define CONFIG_SYS_BR3_PRELIM 0
-#define CONFIG_SYS_OR3_PRELIM 0
-
-#define CONFIG_SYS_BR4_PRELIM 0
-#define CONFIG_SYS_OR4_PRELIM 0
-
-#define CONFIG_SYS_BR5_PRELIM 0
-#define CONFIG_SYS_OR5_PRELIM 0
-
-#define CONFIG_SYS_BR6_PRELIM 0
-#define CONFIG_SYS_OR6_PRELIM 0
-
-#define CONFIG_SYS_BR7_PRELIM 0x00000701
-#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
-
-/*-----------------------------------------------------------------------
* LED config
*/
#define LED_STAT_0 0xffff /*all LEDs off*/
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 8ad28ad..a04e7f9 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -128,10 +128,6 @@
#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
-#define CONFIG_SYS_BR1_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS 0xfffdf0000ull
@@ -139,9 +135,6 @@
#define PIXIS_BASE_PHYS PIXIS_BASE
#endif
-#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
-
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
@@ -187,21 +180,6 @@
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 32d0d5d..365f61b 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -352,22 +352,6 @@
OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
OR_GPCM_EAD)
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#endif
-#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
-#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
-
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000"
@@ -385,9 +369,6 @@
OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
-#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
-#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
-
/* The size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 68bd254..b7296da 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -97,11 +97,6 @@
#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
-#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
-#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
-#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
-#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
-
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@@ -128,8 +123,6 @@
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_HMI_BASE 0xc0010000
-#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
-#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -137,8 +130,6 @@
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
-#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
#define CONFIG_SYS_SPD_BUS_NUM 0
generated by cgit v1.1 at 2024-07-13 19:51:33 +0000