diff options
Diffstat (limited to 'include')
116 files changed, 2773 insertions, 657 deletions
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 1f85de0..e67562e 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -80,7 +80,7 @@ struct acpi_rsdt { }; /* XSDT (Extended System Description Table) */ -struct acpi_xsdt { +struct __packed acpi_xsdt { struct acpi_table_header header; u64 entry[MAX_ACPI_TABLES]; }; @@ -228,10 +228,8 @@ struct __packed acpi_fadt { u8 reset_value; u16 arm_boot_arch; u8 minor_revision; - u32 x_firmware_ctl_l; - u32 x_firmware_ctl_h; - u32 x_dsdt_l; - u32 x_dsdt_h; + u64 x_firmware_ctrl; + u64 x_dsdt; struct acpi_gen_regaddr x_pm1a_evt_blk; struct acpi_gen_regaddr x_pm1b_evt_blk; struct acpi_gen_regaddr x_pm1a_cnt_blk; @@ -921,6 +919,15 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature); int acpi_fill_csrt(struct acpi_ctx *ctx); /** + * acpi_get_rsdp_addr() - get ACPI RSDP table address + * + * This routine returns the ACPI RSDP table address in the system memory. + * + * @return: ACPI RSDP table address + */ +ulong acpi_get_rsdp_addr(void); + +/** * write_acpi_tables() - Write out the ACPI tables * * This writes all ACPI tables to the given address diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e8c6412..fcc3c6e 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -553,7 +553,7 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #endif #ifdef CONFIG_SMBIOS -#define gd_smbios_start() gd->smbios_start +#define gd_smbios_start() gd->arch.smbios_start #define gd_set_smbios_start(addr) gd->arch.smbios_start = addr #else #define gd_smbios_start() 0UL @@ -697,6 +697,14 @@ enum gd_flags { * @GD_FLG_BLOBLIST_READY: bloblist is ready for use */ GD_FLG_BLOBLIST_READY = 0x800000, + /** + * @GD_FLG_HUSH_OLD_PARSER: Use hush old parser. + */ + GD_FLG_HUSH_OLD_PARSER = 0x1000000, + /** + * @GD_FLG_HUSH_MODERN_PARSER: Use hush 2021 parser. + */ + GD_FLG_HUSH_MODERN_PARSER = 0x2000000, }; #endif /* __ASSEMBLY__ */ diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 7a2f0db..13d99cf 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -105,5 +105,353 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) } #endif +/* + * __raw_{read,write}{b,w,l,q}() access memory in native endianness. + * + * On some architectures memory mapped IO needs to be accessed differently. + * On the simple architectures, we just read/write the memory location + * directly. + */ + +#ifndef __raw_readb +#define __raw_readb __raw_readb +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + return *(const volatile u8 __force *)addr; +} +#endif + +#ifndef __raw_readw +#define __raw_readw __raw_readw +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + return *(const volatile u16 __force *)addr; +} +#endif + +#ifndef __raw_readl +#define __raw_readl __raw_readl +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + return *(const volatile u32 __force *)addr; +} +#endif + +#ifdef CONFIG_64BIT +#ifndef __raw_readq +#define __raw_readq __raw_readq +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + return *(const volatile u64 __force *)addr; +} +#endif +#endif /* CONFIG_64BIT */ + +#ifndef __raw_writeb +#define __raw_writeb __raw_writeb +static inline void __raw_writeb(u8 value, volatile void __iomem *addr) +{ + *(volatile u8 __force *)addr = value; +} +#endif + +#ifndef __raw_writew +#define __raw_writew __raw_writew +static inline void __raw_writew(u16 value, volatile void __iomem *addr) +{ + *(volatile u16 __force *)addr = value; +} +#endif + +#ifndef __raw_writel +#define __raw_writel __raw_writel +static inline void __raw_writel(u32 value, volatile void __iomem *addr) +{ + *(volatile u32 __force *)addr = value; +} +#endif + +#ifdef CONFIG_64BIT +#ifndef __raw_writeq +#define __raw_writeq __raw_writeq +static inline void __raw_writeq(u64 value, volatile void __iomem *addr) +{ + *(volatile u64 __force *)addr = value; +} +#endif +#endif /* CONFIG_64BIT */ + +/* + * {read,write}s{b,w,l,q}() repeatedly access the same memory address in + * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). + */ +#ifndef readsb +#define readsb readsb +static inline void readsb(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + if (count) { + u8 *buf = buffer; + + do { + u8 x = __raw_readb(addr); + *buf++ = x; + } while (--count); + } +} +#endif + +#ifndef readsw +#define readsw readsw +static inline void readsw(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + if (count) { + u16 *buf = buffer; + + do { + u16 x = __raw_readw(addr); + *buf++ = x; + } while (--count); + } +} +#endif + +#ifndef readsl +#define readsl readsl +static inline void readsl(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + if (count) { + u32 *buf = buffer; + + do { + u32 x = __raw_readl(addr); + *buf++ = x; + } while (--count); + } +} +#endif + +#ifdef CONFIG_64BIT +#ifndef readsq +#define readsq readsq +static inline void readsq(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + if (count) { + u64 *buf = buffer; + + do { + u64 x = __raw_readq(addr); + *buf++ = x; + } while (--count); + } +} +#endif +#endif /* CONFIG_64BIT */ + +#ifndef writesb +#define writesb writesb +static inline void writesb(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u8 *buf = buffer; + + do { + __raw_writeb(*buf++, addr); + } while (--count); + } +} +#endif + +#ifndef writesw +#define writesw writesw +static inline void writesw(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u16 *buf = buffer; + + do { + __raw_writew(*buf++, addr); + } while (--count); + } +} +#endif + +#ifndef writesl +#define writesl writesl +static inline void writesl(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u32 *buf = buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} +#endif + +#ifdef CONFIG_64BIT +#ifndef writesq +#define writesq writesq +static inline void writesq(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u64 *buf = buffer; + + do { + __raw_writeq(*buf++, addr); + } while (--count); + } +} +#endif +#endif /* CONFIG_64BIT */ + +#ifndef PCI_IOBASE +#define PCI_IOBASE ((void __iomem *)0) +#endif + +/* + * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a + * single I/O port multiple times. + */ + +#ifndef insb +#define insb insb +static inline void insb(unsigned long addr, void *buffer, unsigned int count) +{ + readsb(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef insw +#define insw insw +static inline void insw(unsigned long addr, void *buffer, unsigned int count) +{ + readsw(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef insl +#define insl insl +static inline void insl(unsigned long addr, void *buffer, unsigned int count) +{ + readsl(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef outsb +#define outsb outsb +static inline void outsb(unsigned long addr, const void *buffer, + unsigned int count) +{ + writesb(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef outsw +#define outsw outsw +static inline void outsw(unsigned long addr, const void *buffer, + unsigned int count) +{ + writesw(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef outsl +#define outsl outsl +static inline void outsl(unsigned long addr, const void *buffer, + unsigned int count) +{ + writesl(PCI_IOBASE + addr, buffer, count); +} +#endif + +#ifndef ioread8_rep +#define ioread8_rep ioread8_rep +static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer, + unsigned int count) +{ + readsb(addr, buffer, count); +} +#endif + +#ifndef ioread16_rep +#define ioread16_rep ioread16_rep +static inline void ioread16_rep(const volatile void __iomem *addr, + void *buffer, unsigned int count) +{ + readsw(addr, buffer, count); +} +#endif + +#ifndef ioread32_rep +#define ioread32_rep ioread32_rep +static inline void ioread32_rep(const volatile void __iomem *addr, + void *buffer, unsigned int count) +{ + readsl(addr, buffer, count); +} +#endif + +#ifdef CONFIG_64BIT +#ifndef ioread64_rep +#define ioread64_rep ioread64_rep +static inline void ioread64_rep(const volatile void __iomem *addr, + void *buffer, unsigned int count) +{ + readsq(addr, buffer, count); +} +#endif +#endif /* CONFIG_64BIT */ + +#ifndef iowrite8_rep +#define iowrite8_rep iowrite8_rep +static inline void iowrite8_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesb(addr, buffer, count); +} +#endif + +#ifndef iowrite16_rep +#define iowrite16_rep iowrite16_rep +static inline void iowrite16_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesw(addr, buffer, count); +} +#endif + +#ifndef iowrite32_rep +#define iowrite32_rep iowrite32_rep +static inline void iowrite32_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesl(addr, buffer, count); +} +#endif + +#ifdef CONFIG_64BIT +#ifndef iowrite64_rep +#define iowrite64_rep iowrite64_rep +static inline void iowrite64_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesq(addr, buffer, count); +} +#endif +#endif /* CONFIG_64BIT */ + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_GENERIC_IO_H__ */ diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h index 66436b9..a115d6c 100644 --- a/include/atmel_lcd.h +++ b/include/atmel_lcd.h @@ -9,6 +9,8 @@ #ifndef _ATMEL_LCD_H_ #define _ATMEL_LCD_H_ +#include <linux/types.h> + /** * struct atmel_lcd_plat - platform data for Atmel LCDs with driver model * diff --git a/include/bloblist.h b/include/bloblist.h index 080cc46..84fc943 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -24,11 +24,11 @@ * which would add to code size. For Thumb-2 the code size needed in SPL is * approximately 940 bytes (e.g. for chromebook_bob). * - * 5. Bloblist uses 16-byte alignment internally and is designed to start on a - * 16-byte boundary. Its headers are multiples of 16 bytes. This makes it easier - * to deal with data structures which need this level of alignment, such as ACPI - * tables. For use in SPL and TPL the alignment can be relaxed, since it can be - * relocated to an aligned address in U-Boot proper. + * 5. Bloblist uses 8-byte alignment internally and is designed to start on a + * 8-byte boundary. Its headers are 8 bytes long. It is possible to achieve + * larger alignment (e.g. 16 bytes) by adding a dummy header, For use in SPL and + * TPL the alignment can be relaxed, since it can be relocated to an aligned + * address in U-Boot proper. * * 6. Bloblist is designed to be passed to Linux as reserved memory. While linux * doesn't understand the bloblist header, it can be passed the indivdual blobs. @@ -66,6 +66,7 @@ * * Copyright 2018 Google, Inc * Written by Simon Glass <sjg@chromium.org> + * Adjusted July 2023 to match Firmware handoff specification, Release 0.9 */ #ifndef __BLOBLIST_H @@ -74,14 +75,19 @@ #include <mapmem.h> enum { - BLOBLIST_VERSION = 0, - BLOBLIST_MAGIC = 0xb00757a3, - BLOBLIST_ALIGN = 16, + BLOBLIST_VERSION = 1, + BLOBLIST_MAGIC = 0x4a0fb10b, + + BLOBLIST_BLOB_ALIGN_LOG2 = 3, + BLOBLIST_BLOB_ALIGN = 1 << BLOBLIST_BLOB_ALIGN_LOG2, + + BLOBLIST_ALIGN_LOG2 = 3, + BLOBLIST_ALIGN = 1 << BLOBLIST_ALIGN_LOG2, }; /* Supported tags - add new ones to tag_name in bloblist.c */ enum bloblist_tag_t { - BLOBLISTT_NONE = 0, + BLOBLISTT_VOID = 0, /* * Standard area to allocate blobs used across firmware components, for @@ -89,42 +95,36 @@ enum bloblist_tag_t { * projects. */ BLOBLISTT_AREA_FIRMWARE_TOP = 0x1, + /* + * Devicetree for use by firmware. On some platforms this is passed to + * the OS also + */ + BLOBLISTT_CONTROL_FDT = 1, + BLOBLISTT_HOB_BLOCK = 2, + BLOBLISTT_HOB_LIST = 3, + BLOBLISTT_ACPI_TABLES = 4, + BLOBLISTT_TPM_EVLOG = 5, + BLOBLISTT_TPM_CRB_BASE = 6, /* Standard area to allocate blobs used across firmware components */ - BLOBLISTT_AREA_FIRMWARE = 0x100, + BLOBLISTT_AREA_FIRMWARE = 0x10, + BLOBLISTT_TPM2_TCG_LOG = 0x10, /* TPM v2 log space */ + BLOBLISTT_TCPA_LOG = 0x11, /* TPM log space */ /* * Advanced Configuration and Power Interface Global Non-Volatile * Sleeping table. This forms part of the ACPI tables passed to Linux. */ - BLOBLISTT_ACPI_GNVS = 0x100, - BLOBLISTT_INTEL_VBT = 0x101, /* Intel Video-BIOS table */ - BLOBLISTT_TPM2_TCG_LOG = 0x102, /* TPM v2 log space */ - BLOBLISTT_TCPA_LOG = 0x103, /* TPM log space */ - BLOBLISTT_ACPI_TABLES = 0x104, /* ACPI tables for x86 */ - BLOBLISTT_SMBIOS_TABLES = 0x105, /* SMBIOS tables for x86 */ - BLOBLISTT_VBOOT_CTX = 0x106, /* Chromium OS verified boot context */ - - /* - * Project-specific tags are permitted here. Projects can be open source - * or not, but the format of the data must be fuily documented in an - * open source project, including all fields, bits, etc. Naming should - * be: BLOBLISTT_<project>_<purpose_here> - */ - BLOBLISTT_PROJECT_AREA = 0x8000, - BLOBLISTT_U_BOOT_SPL_HANDOFF = 0x8000, /* Hand-off info from SPL */ - BLOBLISTT_VBE = 0x8001, /* VBE per-phase state */ - BLOBLISTT_U_BOOT_VIDEO = 0x8002, /* Video information from SPL */ + BLOBLISTT_ACPI_GNVS = 0x12, - /* - * Vendor-specific tags are permitted here. Projects can be open source - * or not, but the format of the data must be fuily documented in an - * open source project, including all fields, bits, etc. Naming should - * be BLOBLISTT_<vendor>_<purpose_here> - */ - BLOBLISTT_VENDOR_AREA = 0xc000, + /* Standard area to allocate blobs used for Trusted Firmware */ + BLOBLISTT_AREA_TF = 0x100, + BLOBLISTT_OPTEE_PAGABLE_PART = 0x100, - /* Tags after this are not allocated for now */ - BLOBLISTT_EXPANSION = 0x10000, + /* Other standard area to allocate blobs */ + BLOBLISTT_AREA_OTHER = 0x200, + BLOBLISTT_INTEL_VBT = 0x200, /* Intel Video-BIOS table */ + BLOBLISTT_SMBIOS_TABLES = 0x201, /* SMBIOS tables for x86 */ + BLOBLISTT_VBOOT_CTX = 0x202, /* Chromium OS verified boot context */ /* * Tags from here are on reserved for private use within a single @@ -133,9 +133,20 @@ enum bloblist_tag_t { * implementation, but cannot be used in upstream code. Allocate a * tag in one of the areas above if you want that. * - * This area may move in future. + * Project-specific tags are permitted here. Projects can be open source + * or not, but the format of the data must be fuily documented in an + * open source project, including all fields, bits, etc. Naming should + * be: BLOBLISTT_<project>_<purpose_here> + * + * Vendor-specific tags are also permitted. Projects can be open source + * or not, but the format of the data must be fuily documented in an + * open source project, including all fields, bits, etc. Naming should + * be BLOBLISTT_<vendor>_<purpose_here> */ - BLOBLISTT_PRIVATE_AREA = 0xffff0000, + BLOBLISTT_PRIVATE_AREA = 0xfff000, + BLOBLISTT_U_BOOT_SPL_HANDOFF = 0xfff000, /* Hand-off info from SPL */ + BLOBLISTT_VBE = 0xfff001, /* VBE per-phase state */ + BLOBLISTT_U_BOOT_VIDEO = 0xfff002, /* Video info from SPL */ }; /** @@ -156,33 +167,33 @@ enum bloblist_tag_t { * from the last. * * @magic: BLOBLIST_MAGIC + * @chksum: checksum for the entire bloblist allocated area. Since any of the + * blobs can be altered after being created, this checksum is only valid + * when the bloblist is finalized before jumping to the next stage of boot. + * This is the value needed to make all checksummed bytes sum to 0 * @version: BLOBLIST_VERSION * @hdr_size: Size of this header, normally sizeof(struct bloblist_hdr). The * first bloblist_rec starts at this offset from the start of the header - * @flags: Space for BLOBLISTF... flags (none yet) - * @size: Total size of the bloblist (non-zero if valid) including this header. - * The bloblist extends for this many bytes from the start of this header. - * When adding new records, the bloblist can grow up to this size. - * @alloced: Total size allocated so far for this bloblist. This starts out as + * @align_log2: Power of two of the maximum alignment required by this list + * @used_size: Size allocated so far for this bloblist. This starts out as * sizeof(bloblist_hdr) since we need at least that much space to store a * valid bloblist + * @total_size: The number of total bytes that the bloblist can occupy. + * Any blob producer must check if there is sufficient space before adding + * a record to the bloblist. + * @flags: Space for BLOBLISTF... flags (none yet) * @spare: Spare space (for future use) - * @chksum: CRC32 for the entire bloblist allocated area. Since any of the - * blobs can be altered after being created, this checksum is only valid - * when the bloblist is finalised before jumping to the next stage of boot. - * Note that chksum is last to make it easier to exclude it from the - * checksum calculation. */ struct bloblist_hdr { u32 magic; - u32 version; - u32 hdr_size; + u8 chksum; + u8 version; + u8 hdr_size; + u8 align_log2; + u32 used_size; + u32 total_size; u32 flags; - - u32 size; - u32 alloced; u32 spare; - u32 chksum; }; /** @@ -193,18 +204,25 @@ struct bloblist_hdr { * * NOTE: Only exported for testing purposes. Do not use this struct. * - * @tag: Tag indicating what the record contains - * @hdr_size: Size of this header, normally sizeof(struct bloblist_rec). The - * record's data starts at this offset from the start of the record + * @tag_and_hdr_size: Tag indicating what the record contains (bottom 24 bits), and + * size of this header (top 8 bits), normally sizeof(struct bloblist_rec). + * The record's data starts at this offset from the start of the record * @size: Size of record in bytes, excluding the header size. This does not * need to be aligned (e.g. 3 is OK). - * @spare: Spare space for other things */ struct bloblist_rec { - u32 tag; - u32 hdr_size; + u32 tag_and_hdr_size; u32 size; - u32 spare; +}; + +enum { + BLOBLISTR_TAG_SHIFT = 0, + BLOBLISTR_TAG_MASK = 0xffffffU << BLOBLISTR_TAG_SHIFT, + BLOBLISTR_HDR_SIZE_SHIFT = 24, + BLOBLISTR_HDR_SIZE_MASK = 0xffU << BLOBLISTR_HDR_SIZE_SHIFT, + + BLOBLIST_HDR_SIZE = sizeof(struct bloblist_hdr), + BLOBLIST_REC_HDR_SIZE = sizeof(struct bloblist_rec), }; /** @@ -249,11 +267,11 @@ void *bloblist_find(uint tag, int size); * * @tag: Tag to add (enum bloblist_tag_t) * @size: Size of the blob - * @align: Alignment of the blob (in bytes), 0 for default + * @align_log2: Alignment of the blob (in bytes log2), 0 for default * Return: pointer to the newly added block, or NULL if there is not enough * space for the blob */ -void *bloblist_add(uint tag, int size, int align); +void *bloblist_add(uint tag, int size, int align_log2); /** * bloblist_ensure_size() - Find or add a blob @@ -263,11 +281,11 @@ void *bloblist_add(uint tag, int size, int align); * @tag: Tag to add (enum bloblist_tag_t) * @size: Size of the blob * @blobp: Returns a pointer to blob on success - * @align: Alignment of the blob (in bytes), 0 for default + * @align_log2: Alignment of the blob (in bytes log2), 0 for default * Return: 0 if OK, -ENOSPC if it is missing and could not be added due to lack * of space, or -ESPIPE it exists but has the wrong size */ -int bloblist_ensure_size(uint tag, int size, int align, void **blobp); +int bloblist_ensure_size(uint tag, int size, int align_log2, void **blobp); /** * bloblist_ensure() - Find or add a blob @@ -313,10 +331,11 @@ int bloblist_resize(uint tag, int new_size); * @addr: Address of bloblist * @size: Initial size for bloblist * @flags: Flags to use for bloblist + * @align_log2: Log base 2 of maximum alignment provided by this bloblist * Return: 0 if OK, -EFAULT if addr is not aligned correctly, -ENOSPC is the * area is not large enough */ -int bloblist_new(ulong addr, uint size, uint flags); +int bloblist_new(ulong addr, uint size, uint flags, uint align_log2); /** * bloblist_check() - Check if a bloblist exists @@ -347,10 +366,10 @@ int bloblist_finish(void); * This returns useful information about the bloblist * * @basep: Returns base address of bloblist - * @sizep: Returns the number of bytes used in the bloblist - * @allocedp: Returns the total space allocated to the bloblist + * @tsizep: Returns the total number of bytes of the bloblist + * @usizep: Returns the number of used bytes of the bloblist */ -void bloblist_get_stats(ulong *basep, ulong *sizep, ulong *allocedp); +void bloblist_get_stats(ulong *basep, ulong *tsizep, ulong *usizep); /** * bloblist_get_base() - Get the base address of the bloblist @@ -367,6 +386,13 @@ ulong bloblist_get_base(void); ulong bloblist_get_size(void); /** + * bloblist_get_total_size() - Get the total size of the bloblist + * + * Return: the size in bytes + */ +ulong bloblist_get_total_size(void); + +/** * bloblist_show_stats() - Show information about the bloblist * * This shows useful information about the bloblist on the console diff --git a/include/bootdev.h b/include/bootdev.h index 35fa25a..2cee883 100644 --- a/include/bootdev.h +++ b/include/bootdev.h @@ -7,6 +7,7 @@ #ifndef __bootdev_h #define __bootdev_h +#include <dm/uclass-id.h> #include <linux/list.h> struct bootflow; diff --git a/include/bootflow.h b/include/bootflow.h index fede8f2..4211287 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -45,10 +45,12 @@ enum bootflow_state_t { * CONFIG_OF_HAS_PRIOR_STAGE is enabled * @BOOTFLOWF_STATIC_BUF: Indicates that @bflow->buf is statically set, rather * than being allocated by malloc(). + * @BOOTFLOWF_USE_BUILTIN_FDT : Indicates that current bootflow uses built-in FDT */ enum bootflow_flags_t { BOOTFLOWF_USE_PRIOR_FDT = 1 << 0, BOOTFLOWF_STATIC_BUF = 1 << 1, + BOOTFLOWF_USE_BUILTIN_FDT = 1 << 2, }; /** diff --git a/include/bootm.h b/include/bootm.h index 10a1bd6..9e0f8d6 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -16,6 +16,55 @@ struct cmd_tbl; #define BOOTM_ERR_OVERLAP (-2) #define BOOTM_ERR_UNIMPLEMENTED (-3) +/** + * struct bootm_info() - information used when processing images to boot + * + * These mirror the first three arguments of the bootm command. They are + * designed to handle any type of image, but typically it is a FIT. + * + * @addr_img: Address of image to bootm, as passed to + * genimg_get_kernel_addr_fit() for processing: + * + * NULL: Usees default load address, i.e. image_load_addr + * <addr>: Uses hex address + * + * For FIT: + * "[<addr>]#<conf>": Uses address (or image_load_addr) and also specifies + * the FIT configuration to use + * "[<addr>]:<subimage>": Uses address (or image_load_addr) and also + * specifies the subimage name containing the OS + * + * @conf_ramdisk: Address (or with FIT, the name) of the ramdisk image, as + * passed to boot_get_ramdisk() for processing, or NULL for none + * @conf_fdt: Address (or with FIT, the name) of the FDT image, as passed to + * boot_get_fdt() for processing, or NULL for none + * @boot_progress: true to show boot progress + * @images: images information + * @cmd_name: command which invoked this operation, e.g. "bootm" + * @argc: Number of arguments to the command (excluding the actual command). + * This is 0 if there are no arguments + * @argv: NULL-terminated list of arguments, or NULL if there are no arguments + */ +struct bootm_info { + const char *addr_img; + const char *conf_ramdisk; + const char *conf_fdt; + bool boot_progress; + struct bootm_headers *images; + const char *cmd_name; + int argc; + char *const *argv; +}; + +/** + * bootm_init() - Set up a bootm_info struct with useful defaults + * + * Set up the struct with default values for all members: + * @boot_progress is set to true and @images is set to the global images + * variable. Everything else is set to NULL except @argc which is 0 + */ +void bootm_init(struct bootm_info *bmi); + /* * Continue booting an OS image; caller already has: * - copied image header to global variable `header' @@ -25,21 +74,16 @@ struct cmd_tbl; * - disabled interrupts. * * @flag: Flags indicating what to do (BOOTM_STATE_...) - * @argc: Number of arguments. Note that the arguments are shifted down - * so that 0 is the first argument not processed by U-Boot, and - * argc is adjusted accordingly. This avoids confusion as to how - * many arguments are available for the OS. - * @images: Pointers to os/initrd/fdt + * bmi: Bootm information * Return: 1 on error. On success the OS boots so this function does * not return. */ -typedef int boot_os_fn(int flag, int argc, char *const argv[], - struct bootm_headers *images); +typedef int boot_os_fn(int flag, struct bootm_info *bmi); extern boot_os_fn do_bootm_linux; extern boot_os_fn do_bootm_vxworks; -int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_bootelf(struct cmd_tbl *cmdtp, int fglag, int argc, char *const argv[]); boot_os_fn *bootm_os_get_boot_func(int os); @@ -47,14 +91,33 @@ boot_os_fn *bootm_os_get_boot_func(int os); int bootm_host_load_images(const void *fit, int cfg_noffset); #endif -int boot_selected_os(int argc, char *const argv[], int state, - struct bootm_headers *images, boot_os_fn *boot_fn); +int boot_selected_os(int state, struct bootm_info *bmi, boot_os_fn *boot_fn); ulong bootm_disable_interrupts(void); -/* This is a special function used by booti/bootz */ -int bootm_find_images(int flag, int argc, char *const argv[], ulong start, - ulong size); +/** + * bootm_find_images() - find and locate various images + * + * @img_addr: Address of image being loaded + * @conf_ramdisk: Indicates the ramdisk to use (typically second arg of bootm) + * @conf_fdt: Indicates the FDT to use (typically third arg of bootm) + * @start: OS image start address + * @size: OS image size + * + * boot_find_images() will attempt to load an available ramdisk, + * flattened device tree, as well as specifically marked + * "loadable" images (loadables are FIT only) + * + * Note: bootm_find_images will skip an image if it is not found + * + * This is a special function used by booti/bootz + * + * Return: + * 0, if all existing images were loaded correctly + * 1, if an image is found but corrupted, or invalid + */ +int bootm_find_images(ulong img_addr, const char *conf_ramdisk, + const char *conf_fdt, ulong start, ulong size); /* * Measure the boot images. Measurement is the process of hashing some binary @@ -67,9 +130,82 @@ int bootm_find_images(int flag, int argc, char *const argv[], ulong start, */ int bootm_measure(struct bootm_headers *images); -int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[], int states, struct bootm_headers *images, - int boot_progress); +/** + * bootm_run_states() - Execute selected states of the bootm command. + * + * Note that if states contains more than one flag it MUST contain + * BOOTM_STATE_START, since this handles the addr_fit, conf_ramdisk and conf_fit + * members of @bmi + * + * Also note that aside from boot_os_fn functions and bootm_load_os, no other + * functions store the return value of in 'ret' may use a negative return + * value, without special handling. + * + * @bmi: bootm information + * @states Mask containing states to run (BOOTM_STATE_...) + * Return: 0 if ok, something else on error. Some errors will cause this + * function to perform a reboot! If states contains BOOTM_STATE_OS_GO + * then the intent is to boot an OS, so this function will not return + * unless the image type is standalone. + */ +int bootm_run_states(struct bootm_info *bmi, int states); + +/** + * boot_run() - Run the entire bootm/booti/bootz process + * + * This runs through the boot process from start to finish, with a base set of + * states, along with the extra ones supplied. + * + * This uses bootm_run_states(). + * + * Note that it is normally easier to use bootm_run(), etc. since they handle + * the extra states correctly. + * + * @bmi: bootm information + * @cmd: command being run, NULL if none + * @extra_states: Mask of extra states to use for the boot + * Return: 0 if ok, something else on error + */ +int boot_run(struct bootm_info *bmi, const char *cmd, int extra_states); + +/** + * bootm_run() - Run the entire bootm process + * + * This runs through the bootm process from start to finish, using the default + * set of states. + * + * This uses bootm_run_states(). + * + * @bmi: bootm information + * Return: 0 if ok, something else on error + */ +int bootm_run(struct bootm_info *bmi); + +/** + * bootz_run() - Run the entire bootz process + * + * This runs through the bootz process from start to finish, using the default + * set of states. + * + * This uses bootm_run_states(). + * + * @bmi: bootm information + * Return: 0 if ok, something else on error + */ +int bootz_run(struct bootm_info *bmi); + +/** + * booti_run() - Run the entire booti process + * + * This runs through the booti process from start to finish, using the default + * set of states. + * + * This uses bootm_run_states(). + * + * @bmi: bootm information + * Return: 0 if ok, something else on error + */ +int booti_run(struct bootm_info *bmi); void arch_preboot_os(void); diff --git a/include/bootstage.h b/include/bootstage.h index affb0e5..f4e77b0 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -12,7 +12,9 @@ #define _BOOTSTAGE_H #include <linux/types.h> +#ifdef USE_HOSTCC #include <linux/kconfig.h> +#endif /* Flags for each bootstage record */ enum bootstage_flags { @@ -147,7 +149,6 @@ enum bootstage_id { BOOTSTAGE_ID_FIT_CONFIG = 110, BOOTSTAGE_ID_FIT_TYPE, - BOOTSTAGE_ID_FIT_KERNEL_INFO, BOOTSTAGE_ID_FIT_COMPRESSION, BOOTSTAGE_ID_FIT_OS, diff --git a/include/bootstd.h b/include/bootstd.h index 7802564..99ce7b6 100644 --- a/include/bootstd.h +++ b/include/bootstd.h @@ -94,4 +94,13 @@ int bootstd_get_priv(struct bootstd_priv **stdp); */ void bootstd_clear_glob(void); +/** + * bootstd_prog_boot() - Run standard boot in a fully programmatic mode + * + * Attempts to boot without making any use of U-Boot commands + * + * Returns: -ve error value (does not return except on failure to boot) + */ +int bootstd_prog_boot(void); + #endif diff --git a/include/cli_hush.h b/include/cli_hush.h index 2bd3567..007b8d6 100644 --- a/include/cli_hush.h +++ b/include/cli_hush.h @@ -12,11 +12,58 @@ #define FLAG_REPARSING (1 << 2) /* >=2nd pass */ #define FLAG_CONT_ON_NEWLINE (1 << 3) /* continue when we see \n */ +#if CONFIG_IS_ENABLED(HUSH_OLD_PARSER) extern int u_boot_hush_start(void); -extern int parse_string_outer(const char *, int); +extern int parse_string_outer(const char *str, int flag); extern int parse_file_outer(void); - int set_local_var(const char *s, int flg_export); +#else +static inline int u_boot_hush_start(void) +{ + return 0; +} + +static inline int parse_string_outer(const char *str, int flag) +{ + return 1; +} + +static inline int parse_file_outer(void) +{ + return 0; +} + +static inline int set_local_var(const char *s, int flg_export) +{ + return 0; +} +#endif +#if CONFIG_IS_ENABLED(HUSH_MODERN_PARSER) +extern int u_boot_hush_start_modern(void); +extern int parse_string_outer_modern(const char *str, int flag); +extern void parse_and_run_file(void); +int set_local_var_modern(char *s, int flg_export); +#else +static inline int u_boot_hush_start_modern(void) +{ + return 0; +} + +static inline int parse_string_outer_modern(const char *str, int flag) +{ + return 1; +} + +static inline void parse_and_run_file(void) +{ +} + +static inline int set_local_var_modern(char *s, int flg_export) +{ + return 0; +} +#endif + void unset_local_var(const char *name); char *get_local_var(const char *s); diff --git a/include/clk-uclass.h b/include/clk-uclass.h index a22f1a5..cd62848 100644 --- a/include/clk-uclass.h +++ b/include/clk-uclass.h @@ -25,6 +25,7 @@ struct ofnode_phandle_args; * @set_parent: Set current clock parent * @enable: Enable a clock. * @disable: Disable a clock. + * @dump: Print clock information. * * The individual methods are described more fully below. */ @@ -39,6 +40,9 @@ struct clk_ops { int (*set_parent)(struct clk *clk, struct clk *parent); int (*enable)(struct clk *clk); int (*disable)(struct clk *clk); +#if IS_ENABLED(CONFIG_CMD_CLK) + void (*dump)(struct udevice *dev); +#endif }; #if 0 /* For documentation only */ @@ -135,6 +139,15 @@ int enable(struct clk *clk); * Return: zero on success, or -ve error code. */ int disable(struct clk *clk); + +/** + * dump() - Print clock information. + * @dev: The clock device to dump. + * + * If present, this function is called by "clk dump" command for each + * bound device. + */ +void dump(struct udevice *dev); #endif #endif diff --git a/include/clk.h b/include/clk.h index 249c0e0..3d63944 100644 --- a/include/clk.h +++ b/include/clk.h @@ -676,8 +676,6 @@ static inline bool clk_valid(struct clk *clk) return clk && !!clk->dev; } -int soc_clk_dump(void); - #endif #define clk_prepare_enable(clk) clk_enable(clk) diff --git a/include/command.h b/include/command.h index 6262365..4158ca1 100644 --- a/include/command.h +++ b/include/command.h @@ -60,6 +60,39 @@ struct cmd_tbl { #endif }; +/** + * cmd_arg_get() - Get a particular argument + * + * @argc: Number of arguments + * @argv: Argument vector of length @argc + * @argnum: Argument to get (0=first) + * Return: Pointer to argument @argnum if it exists, else NULL + */ +static inline const char *cmd_arg_get(int argc, char *const argv[], int argnum) +{ + return argc > argnum ? argv[argnum] : NULL; +} + +static inline const char *cmd_arg0(int argc, char *const argv[]) +{ + return cmd_arg_get(argc, argv, 0); +} + +static inline const char *cmd_arg1(int argc, char *const argv[]) +{ + return cmd_arg_get(argc, argv, 1); +} + +static inline const char *cmd_arg2(int argc, char *const argv[]) +{ + return cmd_arg_get(argc, argv, 2); +} + +static inline const char *cmd_arg3(int argc, char *const argv[]) +{ + return cmd_arg_get(argc, argv, 3); +} + #if defined(CONFIG_CMD_RUN) int do_run(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); @@ -153,7 +186,7 @@ int cmd_process_error(struct cmd_tbl *cmdtp, int err); * Return: data size in bytes (1, 2, 4, 8) or CMD_DATA_SIZE_ERR for an invalid * character, or CMD_DATA_SIZE_STR for a string */ -int cmd_get_data_size(char *arg, int default_size); +int cmd_get_data_size(const char *arg, int default_size); #endif #ifdef CONFIG_CMD_BOOTD @@ -390,7 +423,7 @@ int cmd_source_script(ulong addr, const char *fit_uname, const char *confname); #define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \ ll_entry_declare(struct cmd_tbl, _name, cmd) = \ U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \ - _usage, _help, _comp); + _usage, _help, _comp) #define U_BOOT_CMDREP_COMPLETE(_name, _maxargs, _cmd_rep, _usage, \ _help, _comp) \ diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h index 57003f1..496d1c2 100644 --- a/include/configs/am62ax_evm.h +++ b/include/configs/am62ax_evm.h @@ -12,10 +12,6 @@ #include <env/ti/mmc.h> #include <env/ti/k3_dfu.h> -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 - - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 811dc0f..64458eb 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -14,9 +14,6 @@ #include <env/ti/k3_rproc.h> #include <env/ti/k3_dfu.h> -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 4aa876a..81c76ef 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -9,8 +9,6 @@ #ifndef __AT91_SAMA5_COMMON_H #define __AT91_SAMA5_COMMON_H -#include <linux/kconfig.h> - /* ARM asynchronous clock */ #define CFG_SYS_AT91_SLOW_CLOCK 32768 #define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 47de4bc..7c6e072 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -45,11 +45,11 @@ #define PCIE_ARGS "pcie_args=pci=pcie_bus_safe pcie_ports=native vfio_pci.disable_idle_d3=1\0" #ifdef CONFIG_BCM_SF2_ETH -#define ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0" +#define BCM_ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0" #define NET_ARGS "bgmac_platform.ethaddr=${ethaddr} " \ "ip=${ipaddr}::${gatewayip}:${netmask}::${ethif}:off" #else -#define ETH_ADDR +#define BMC_ETH_ADDR #define NET_ARGS #endif @@ -749,7 +749,7 @@ OS_LOG_LEVEL \ EXTRA_ARGS \ PCIE_ARGS \ - ETH_ADDR \ + BMC_ETH_ADDR \ RESERVED_MEM \ SETBOOTARGS \ UPDATEME_FLASH_PARAMS \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 03f8ed1..7a9f4af 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -101,7 +101,6 @@ UBI_BOOTCMD #elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define MODULE_EXTRA_ENV_SETTINGS \ - "variant=-emmc\0" \ EMMC_ANDROID_BOOTCMD #endif diff --git a/include/configs/etamin.h b/include/configs/draco-etamin.h index 97585a4..97585a4 100644 --- a/include/configs/etamin.h +++ b/include/configs/draco-etamin.h diff --git a/include/configs/rastaban.h b/include/configs/draco-rastaban.h index 0991ebf..0991ebf 100644 --- a/include/configs/rastaban.h +++ b/include/configs/draco-rastaban.h diff --git a/include/configs/thuban.h b/include/configs/draco-thuban.h index f4c04c5..f4c04c5 100644 --- a/include/configs/thuban.h +++ b/include/configs/draco-thuban.h diff --git a/include/configs/draco.h b/include/configs/draco.h deleted file mode 100644 index 8f993ce..0000000 --- a/include/configs/draco.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef __CONFIG_DRACO_H -#define __CONFIG_DRACO_H - -#include "siemens-am33x-common.h" - -#define DDR_PLL_FREQ 303 - -#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ -#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ - -#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - "button_dfu0=27\0" \ - "led0=103,1,0\0" \ - "led1=64,0,1\0" - - /* Physical Memory Map */ -#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -/* Default env settings */ -#define CFG_EXTRA_ENV_SETTINGS \ - "hostname=draco\0" \ - "ubi_off=2048\0"\ - "nand_img_size=0x400000\0" \ - "optargs=\0" \ - "preboot=draco_led 0\0" \ - CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CFG_ENV_SETTINGS_V2 \ - CFG_ENV_SETTINGS_NAND_V2 - -#endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index 73aec34..00102cd 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -9,7 +9,6 @@ #define __CONFIGS_DRAGONBOARD410C_H #include <linux/sizes.h> -#include <asm/arch/sysmap-apq8016.h> /* Build new ELF image from u-boot.bin (U-Boot + appended DTB) */ diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 4997083..c6d9182 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -9,7 +9,6 @@ #define __CONFIGS_DRAGONBOARD820C_H #include <linux/sizes.h> -#include <asm/arch/sysmap-apq8096.h> /* Physical Memory Map */ diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h index c1e590f..14a8a2c 100644 --- a/include/configs/dragonboard845c.h +++ b/include/configs/dragonboard845c.h @@ -9,7 +9,6 @@ #define __CONFIGS_SDM845_H #include <linux/sizes.h> -#include <asm/arch/sysmap-sdm845.h> #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index f7d2b66..b777fe6 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -34,13 +34,11 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CFG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ - /* Give slow devices beyond USB HUB chance to come up. */ \ - "usb_pgood_delay=2000\0" \ "dfu_alt_info=" \ /* RAM block at DRAM offset 256..768 MiB */ \ "ram ram0=ram ram 0x50000000 0x20000000&" \ @@ -76,6 +74,11 @@ "setenv stderr ${stderr},nc && " \ "setenv stdout ${stdout},nc && " \ "setenv stdin ${stdin},nc ; " \ - "fi" + "fi\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + /* Give slow devices beyond USB HUB chance to come up. */ \ + "usb_pgood_delay=2000\0" #endif diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h index 11ac3c0..8d79540 100644 --- a/include/configs/imx8mp_data_modul_edm_sbc.h +++ b/include/configs/imx8mp_data_modul_edm_sbc.h @@ -29,8 +29,6 @@ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ - /* Give slow devices beyond USB HUB chance to come up. */ \ - "usb_pgood_delay=2000\0" \ "dmo_update_env=" \ "setenv dmo_update_env true ; saveenv ; saveenv\0" \ "dmo_update_sf_write_data=" \ @@ -40,6 +38,11 @@ "run dmo_update_sf_write_data\0" \ "dmo_update_sd_to_sf=" \ "load mmc 1:1 ${loadaddr} boot/flash.bin && " \ - "run dmo_update_sf_write_data\0" + "run dmo_update_sf_write_data\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + /* Give slow devices beyond USB HUB chance to come up. */ \ + "usb_pgood_delay=2000\0" #endif diff --git a/include/configs/imx8mp_debix_model_a.h b/include/configs/imx8mp_debix_model_a.h new file mode 100644 index 0000000..e82e8b1 --- /dev/null +++ b/include/configs/imx8mp_debix_model_a.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * Copyright 2023 Gilles Talis <gilles.talis@gmail.com> + */ + +#ifndef __IMX8MP_DEBIX_MODEL_A_H +#define __IMX8MP_DEBIX_MODEL_A_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#if defined(CONFIG_CMD_NET) +#define CFG_FEC_MXC_PHYADDR 1 + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include <config_distro_bootcmd.h> + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 + +/* 2GB DDR */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ + +#endif diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index d022faa..ea32fe1 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -28,15 +28,9 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CFG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "altbootcmd=run bootcmd ; reset\0" \ "bootlimit=3\0" \ - "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramdisk_addr_r=0x58000000\0" \ - "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - /* Give slow devices beyond USB HUB chance to come up. */ \ - "usb_pgood_delay=2000\0" \ "dfu_alt_info=" \ /* RAM block at DRAM offset 256..768 MiB */ \ "ram ram0=ram ram 0x50000000 0x20000000&" \ @@ -68,6 +62,15 @@ "dh_update_emmc_to_sf=" \ "load mmc 1:1 ${loadaddr} boot/flash.bin && " \ "run dh_update_sf_gen_fcfb dh_update_sf_write_data\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramdisk_addr_r=0x58000000\0" \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + /* Give slow devices beyond USB HUB chance to come up. */ \ + "usb_pgood_delay=2000\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/imx93_var_som.h b/include/configs/imx93_var_som.h new file mode 100644 index 0000000..18a8ee5 --- /dev/null +++ b/include/configs/imx93_var_som.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + * Copyright 2023 Variscite Ltd. + */ + +#ifndef __IMX93_VAR_SOM_H +#define __IMX93_VAR_SOM_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS BOOTENV + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define DEFAULT_SDRAM_SIZE (512 * SZ_1M) /* 512MB Minimum DDR4, see get_dram_size */ +#define VAR_EEPROM_DRAM_START (PHYS_SDRAM + (DEFAULT_SDRAM_SIZE >> 1)) +#define VAR_SOM_EEPROM_I2C_NAME "i2c@42530000" +#define VAR_CARRIER_EEPROM_I2C_NAME "i2c@44340000" + +#define CFG_SYS_FSL_USDHC_NUM 2 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#if defined(CONFIG_CMD_NET) +#define PHY_ANEG_TIMEOUT 20000 +#endif + +#endif diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index ea39d1b..c26438c 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -11,8 +11,6 @@ #include <linux/sizes.h> -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ #define CFG_SYS_FLASH_BASE 0x000000000 diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 692c6bb..846cfa7 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -12,9 +12,6 @@ #include <linux/sizes.h> #include <config_distro_bootcmd.h> -/* DDR Configuration */ -#define CFG_SYS_SDRAM_BASE1 0x880000000 - /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) #define CFG_SYS_UBOOT_BASE 0x50280000 diff --git a/include/configs/librem5.h b/include/configs/librem5.h index ce0a340..876b02f 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -56,6 +56,8 @@ "scriptaddr=0x80000000\0" \ "pxefile_addr_r=0x80100000\0" \ "kernel_addr_r=0x80800000\0" \ + "kernel_comp_addr_r=0x90000000\0" \ + "kernel_comp_size=0x08000000\0" \ "fdt_addr_r=0x84800000\0" \ "ramdisk_addr_r=0x85000000\0" \ "console=" CONSOLE ",115200\0" \ diff --git a/include/configs/mt8365.h b/include/configs/mt8365.h new file mode 100644 index 0000000..e8aacf8 --- /dev/null +++ b/include/configs/mt8365.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for MT8365 based boards + * + * Copyright (C) 2023 BayLibre, SAS + * Author: Julien Masson <jmasson@baylibre.com> + */ + +#ifndef __MT8365_H +#define __MT8365_H + +#endif diff --git a/include/configs/pe2201.h b/include/configs/pe2201.h new file mode 100644 index 0000000..80f8f17 --- /dev/null +++ b/include/configs/pe2201.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Phytium Technology Co., Ltd. + * lixinde <lixinde@phytium.com.cn> + * weichangzheng <weichangzheng@phytium.com.cn> + */ + +#ifndef __PE2201_CONFIG_H +#define __PE2201_CONFIG_H + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x74000000 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#endif diff --git a/include/configs/phycore_am62x.h b/include/configs/phycore_am62x.h new file mode 100644 index 0000000..10b78b6 --- /dev/null +++ b/include/configs/phycore_am62x.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for PHYTEC phyCORE-AM62x + * + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#ifndef __PHYCORE_AM62X_H +#define __PHYCORE_AM62X_H + +/* DDR Configuration */ +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __PHYCORE_AM62X_H */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 096e5bb..e7a8cb2 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -13,7 +13,7 @@ #define CFG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ -#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ @@ -79,9 +79,11 @@ "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ "fastboot_partition_alias_system=rootfs\0" \ "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ + "mmcautodetect=yes\0" \ PICO_BOOT_ENV #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h index 8ea59aa..9501d43 100644 --- a/include/configs/qcs404-evb.h +++ b/include/configs/qcs404-evb.h @@ -9,7 +9,6 @@ #define __CONFIGS_QCS404EVB_H #include <linux/sizes.h> -#include <asm/arch/sysmap-qcs404.h> #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 1b7d343..48f9308 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -20,12 +20,12 @@ "script_offset_f=0xffe000\0" \ "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00e00000\0" \ - "fdt_addr_r=0x0a100000\0" \ - "fdtoverlay_addr_r=0x02000000\0" \ - "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x0a200000\0" \ - "kernel_comp_addr_r=0x08000000\0" \ - "kernel_comp_size=0x2000000\0" + "kernel_addr_r=0x02000000\0" \ + "kernel_comp_addr_r=0x0a000000\0" \ + "fdt_addr_r=0x12000000\0" \ + "fdtoverlay_addr_r=0x12100000\0" \ + "ramdisk_addr_r=0x12180000\0" \ + "kernel_comp_size=0x8000000\0" #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h index 46389d0..7043061 100644 --- a/include/configs/rk3588_common.h +++ b/include/configs/rk3588_common.h @@ -19,12 +19,12 @@ "script_offset_f=0xffe000\0" \ "script_size_f=0x2000\0" \ "pxefile_addr_r=0x00e00000\0" \ - "fdt_addr_r=0x0a100000\0" \ - "fdtoverlay_addr_r=0x02000000\0" \ - "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x0a200000\0" \ - "kernel_comp_addr_r=0x08000000\0" \ - "kernel_comp_size=0x2000000\0" + "kernel_addr_r=0x02000000\0" \ + "kernel_comp_addr_r=0x0a000000\0" \ + "fdt_addr_r=0x12000000\0" \ + "fdtoverlay_addr_r=0x12100000\0" \ + "ramdisk_addr_r=0x12180000\0" \ + "kernel_comp_size=0x8000000\0" #define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index 673268d..5ad8569 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -9,7 +9,6 @@ #define __CONFIGS_SDM845_H #include <linux/sizes.h> -#include <asm/arch/sysmap-sdm845.h> #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index de8bfc1..27e0912 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -13,41 +13,4 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -/* Environment options */ - -#define BOOT_TARGET_DEVICES(func) \ - func(NVME, nvme, 0) \ - func(NVME, nvme, 1) \ - func(USB, usb, 0) \ - func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include <config_distro_bootcmd.h> - -#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47" -#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985" -#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4" - -#define PARTS_DEFAULT \ - "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \ - "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ - "name=system,size=-,bootable,type=${type_guid_gpt_system};" - -#define CFG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x80200000\0" \ - "kernel_comp_addr_r=0x88000000\0" \ - "kernel_comp_size=0x4000000\0" \ - "fdt_addr_r=0x8c000000\0" \ - "scriptaddr=0x8c100000\0" \ - "pxefile_addr_r=0x8c200000\0" \ - "ramdisk_addr_r=0x8c300000\0" \ - "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \ - "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \ - "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \ - "partitions=" PARTS_DEFAULT "\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTENV - #endif /* __SIFIVE_UNMATCHED_H */ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index ff43113..29c7447 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -40,6 +40,7 @@ "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ "fdt_addr_r=0x46000000\0" \ + "fdtoverlay_addr_r=0x45800000\0" \ "scriptaddr=0x43900000\0" \ "pxefile_addr_r=0x45900000\0" \ "ramdisk_addr_r=0x46100000\0" \ diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 62a7e9a..75bb9cd 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -31,6 +31,8 @@ "scriptaddr=0x00418000\0" \ "pxefile_addr_r=0x00428000\0" \ "ramdisk_addr_r=0x00438000\0" \ + "splashimage=0x00448000\0" \ + "splashpos=m,m\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index 8ff8822..de39b19 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -12,14 +12,13 @@ #define PHY_ANEG_TIMEOUT 20000 #ifdef CONFIG_SPL_BUILD -#define CFG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "dfu_alt_info_ram=u-boot.itb ram " \ __stringify(CONFIG_SPL_LOAD_FIT_ADDRESS) \ " 0x800000\0" #endif -#define STM32MP_BOARD_EXTRA_ENV \ - "usb_pgood_delay=1000\0" \ +#define STM32MP_BOARD_EXTRA_ENV \ "dh_update_sd_to_emmc=" /* Install U-Boot from SD to eMMC */ \ "setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \ "load mmc 0:4 ${loadaddr1} boot/u-boot-spl.stm32 && " \ @@ -49,7 +48,11 @@ "sf update ${loadaddr1} 0x40000 ${filesize1} && " \ "sf update ${loadaddr} 0x80000 ${filesize} && " \ "env set filesize1 && env set loadaddr1\0" \ - "update_sf=run dh_update_sd_to_sf\0" + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "update_sf=run dh_update_sd_to_sf\0" \ + "usb_pgood_delay=1000\0" #include <configs/stm32mp15_common.h> diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b8ca77d..b29a25d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -14,8 +14,9 @@ #include <linux/stringify.h> -/* Serial & console */ -/* ns16550 reg in the low bits of cpu reg */ +/**************************************************************************** + * base addresses for the SPL UART driver * + ****************************************************************************/ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ #define CFG_SYS_NS16550_CLK 100000000 @@ -31,8 +32,9 @@ # define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif -/* CPU */ - +/**************************************************************************** + * DRAM base address * + ****************************************************************************/ /* * The DRAM Base differs between some models. We cannot use macros for the * CONFIG_FOO defines which contain the DRAM base address since they end @@ -52,16 +54,6 @@ /* V3s do not have enough memory to place code at 0x4a000000 */ #endif -/* - * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is - * slightly bigger. Note that it is possible to map the first 32 KiB of the - * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the - * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and - * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. - * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register - * is known yet. - * H6 has SRAM A1 at 0x00020000. - */ #define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS /* FIXME: this may be larger on some SoCs */ #define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ @@ -69,36 +61,13 @@ #define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -/* - * Miscellaneous configurable options - */ - -/* FLASH and environment organization */ - +/**************************************************************************** + * environment variables holding default load addresses * + ****************************************************************************/ /* * We cannot use expressions here, because expressions won't be evaluated in * autoconf.mk. */ -#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 -#ifdef CONFIG_ARM64 -/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ -#define LOW_LEVEL_SRAM_STACK 0x00054000 -#else -#define LOW_LEVEL_SRAM_STACK 0x00018000 -#endif /* !CONFIG_ARM64 */ -#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 -#ifdef CONFIG_MACH_SUN50I_H616 -#define LOW_LEVEL_SRAM_STACK 0x52a00 /* below FEL buffers */ -#else -/* end of SRAM A2 on H6 for now */ -#define LOW_LEVEL_SRAM_STACK 0x00118000 -#endif -#else -#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ -#endif - -/* Ethernet support */ - #ifdef CONFIG_ARM64 /* * Boards seem to come with at least 512MB of DRAM. @@ -174,15 +143,11 @@ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" #ifdef CONFIG_ARM64 - #define MEM_LAYOUT_ENV_EXTRA_SETTINGS \ "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ "kernel_comp_size=" KERNEL_COMP_SIZE "\0" - #else - #define MEM_LAYOUT_ENV_EXTRA_SETTINGS "" - #endif #define DFU_ALT_INFO_RAM \ @@ -191,6 +156,9 @@ "fdt ram " FDT_ADDR_R " 0x100000;" \ "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" +/**************************************************************************** + * definitions for the distro boot system * + ****************************************************************************/ #ifdef CONFIG_MMC #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 1318f5e..08b6f32 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -21,25 +21,4 @@ */ #define CFG_SYS_NS16550_CLK 166666666 -/* - * Even though the board houses Realtek RTL8211E PHY - * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly. - * In particular "parse_status" reports link is down. - * - * Until Realtek PHY driver is fixed fall back to generic PHY driver - * which implements all required functionality and behaves much more stable. - * - * - */ - -/* - * Ethernet configuration - */ -#define ETH0_BASE_ADDRESS 0xFE100000 -#define ETH1_BASE_ADDRESS 0xFE110000 - -/* - * Console configuration - */ - #endif /* _CONFIG_TB100_H_ */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 72c04d8..b36207c 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -9,23 +9,10 @@ #ifndef __CONFIG_KS2_EVM_H #define __CONFIG_KS2_EVM_H -/* U-Boot Build Configuration */ - -/* SoC Configuration */ - /* Memory Configuration */ #define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#ifdef CONFIG_SYS_MALLOC_F_LEN -#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN -#else -#define SPL_MALLOC_F_SIZE 0 -#endif - -/* SPL SPI Loader Configuration */ -#define KEYSTONE_SPL_STACK_SIZE (8 * 1024) - /* SRAM scratch space entries */ #define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc @@ -53,8 +40,6 @@ #define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES -/* EEPROM definitions */ - /* NAND Configuration */ #define CFG_SYS_NAND_MASK_CLE 0x4000 #define CFG_SYS_NAND_MASK_ALE 0x2000 @@ -63,18 +48,10 @@ #define CFG_SYS_NAND_LARGEPAGE #define CFG_SYS_NAND_BASE_LIST { 0x30000000, } - - -/* U-Boot general configuration */ - -/* EDMA3 */ - - /* Now for the remaining common defines */ #include <configs/ti_armv7_common.h> /* we may include files below only after all above definitions */ -#include <asm/arch/hardware.h> #include <asm/arch/clock.h> #ifndef CONFIG_SOC_K2G #define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 8c75a75..2da76f1 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -8,7 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <linux/kconfig.h> #include <linux/stringify.h> /* place code in last 4 MiB of RAM */ diff --git a/include/configs/turing-rk1-rk3588.h b/include/configs/turing-rk1-rk3588.h new file mode 100644 index 0000000..760f3c6 --- /dev/null +++ b/include/configs/turing-rk1-rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#ifndef __TURINGRK1_RK3588_H +#define __TURINGRK1_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __TURINGRK1_RK3588_H */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 8072d5d..a7ea028 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -40,7 +40,6 @@ "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "fdt_addr=0x43000000\0" \ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 24d8ca0..8020689 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -187,6 +187,7 @@ func(USB, usb, 0) \ func(SATA, sata, 0) \ func(SATA, sata, 1) \ + FUNC_VIRTIO(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) \ func(AFS, afs, na) diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index d29ea70..1453254 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -14,19 +14,8 @@ #include "tegra30-common.h" -#define CFG_TEGRA_BOARD_STRING "LG X3 Board" - -#ifdef CONFIG_DEVICE_P880 /* High-level configuration options */ -#undef CFG_TEGRA_BOARD_STRING -#define CFG_TEGRA_BOARD_STRING "LG Optimus 4X HD" -#endif - -#ifdef CONFIG_DEVICE_P895 -/* High-level configuration options */ -#undef CFG_TEGRA_BOARD_STRING -#define CFG_TEGRA_BOARD_STRING "LG Optimus Vu" -#endif +#define CFG_TEGRA_BOARD_STRING "LG X3 Board" #define X3_FLASH_UBOOT \ "flash_uboot=echo Preparing RAM;" \ diff --git a/include/configs/xea.h b/include/configs/xea.h index 04ca5aa..00d6274 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -25,146 +25,6 @@ #define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -/* Extra Environment */ - -#define CFG_EXTRA_ENV_SETTINGS \ - "bootmode=update\0" \ - "bootpri=mmc_mmc\0" \ - "bootsec=sf_swu\0" \ - "consdev=ttyAMA0\0" \ - "baudrate=115200\0" \ - "dtbaddr=0x44000000\0" \ - "dtbfile=imx28-xea.dtb\0" \ - "rootdev=/dev/mmcblk0p2\0" \ - "netdev=eth0\0" \ - "rdaddr=0x43000000\0" \ - "swufile=swupdate.img\0" \ - "sf_kernel_offset=0x100000\0" \ - "sf_kernel_size=0x400000\0" \ - "sf_swu_offset=0x500000\0" \ - "sf_swu_size=0x800000\0" \ - "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \ - "do_update_mmc=" \ - "if mmc rescan ; then " \ - "mmc dev 0 ${update_mmc_part} ; " \ - "if dhcp ${hostname}/${update_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "do_update_sf=" \ - "if sf probe ; then " \ - "if dhcp ${hostname}/${update_filename} ; then " \ - "sf erase ${update_offset} +${filesize} ; " \ - "sf write ${loadaddr} ${update_offset} ${filesize} ; " \ - "fi ; " \ - "fi\0" \ - "update_spl_filename=u-boot.sb\0" \ - "update_spl=" \ - "setenv update_filename ${update_spl_filename} ; " \ - "setenv update_offset 0 ; " \ - "run do_update_sf\0" \ - "update_uboot_filename=u-boot.img\0" \ - "update_uboot=" \ - "setenv update_filename ${update_uboot_filename} ; " \ - "setenv update_offset 0x10000 ; " \ - "run do_update_sf ; " \ - "setenv update_mmc_part 1 ; " \ - "setenv update_offset 0 ; " \ - "run do_update_mmc\0" \ - "update_kernel_filename=uImage\0" \ - "update_kernel=" \ - "setenv update_mmc_part 1 ; " \ - "setenv update_filename ${update_kernel_filename} ; " \ - "setenv update_offset 0x800 ; " \ - "run do_update_mmc ; " \ - "setenv update_filename ${dtbfile} ; " \ - "setenv update_offset 0x400 ; " \ - "run do_update_mmc\0" \ - "update_sfkernel=" \ - "setenv update_filename fitImage ; " \ - "setenv update_offset ${sf_kernel_offset} ; " \ - "run do_update_sf\0" \ - "update_swu=" \ - "setenv update_filename ${swufile} ; " \ - "setenv update_offset ${sf_swu_offset} ; " \ - "run do_update_sf\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "mmc dev 0 1 ; " \ - "mmc read ${loadaddr} 0x800 0x2000 ; " \ - "mmc read ${dtbaddr} 0x400 0x80\0" \ - "netload=" \ - "dhcp ${loadaddr} ${hostname}/${bootfile} ; " \ - "tftp ${dtbaddr} ${hostname}/${dtbfile}\0" \ - "sfload=" \ - "sf probe ; " \ - "sf read ${loadaddr} ${sf_kernel_offset} ${sf_kernel_size}\0" \ - "usbload=" \ - "usb start ; " \ - "load usb 0:1 ${loadaddr} ${bootfile}\0" \ - "miscargs=panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "if run mmcload mmcargs addargs ; then " \ - "bootm ${loadaddr} - ${dtbaddr} ; " \ - "fi\0" \ - "mmc_nfs=" \ - "if run mmcload nfsargs addip addargs ; then " \ - "bootm ${loadaddr} - ${dtbaddr} ; " \ - "fi\0" \ - "sf_mmc=" \ - "if run sfload mmcargs addargs ; then " \ - "bootm ${loadaddr} - ${dtbaddr} ; " \ - "fi\0" \ - "sf_swu=" \ - "if run sfload ; then " \ - "sf read ${rdaddr} ${sf_swu_offset} ${sf_swu_size} ; " \ - "setenv bootargs root=/dev/ram0 rw ; " \ - "run addargs ; " \ - "bootm ${loadaddr} ${rdaddr} ; " \ - "fi\0" \ - "net_mmc=" \ - "if run netload mmcargs addargs ; then " \ - "bootm ${loadaddr} - ${dtbaddr} ; " \ - "fi\0" \ - "net_nfs=" \ - "if run netload nfsargs addip addargs ; then " \ - "bootm ${loadaddr} - ${dtbaddr} ; " \ - "fi\0" \ - "prebootcmd=" \ - "if test \"${envsaved}\" != y ; then ; " \ - "setenv envsaved y ; " \ - "saveenv ; " \ - "fi ; " \ - "if test \"${bootmode}\" = normal ; then " \ - "setenv bootdelay 0 ; " \ - "setenv bootpri mmc_mmc ; " \ - "elif test \"${bootmode}\" = devel ; then " \ - "setenv bootdelay 3 ; " \ - "setenv bootpri net_mmc ; " \ - "else " \ - "if test \"${bootmode}\" != update ; then " \ - "echo Warning: unknown bootmode \"${bootmode}\" ; " \ - "fi ; " \ - "setenv bootdelay 1 ; " \ - "setenv bootpri sf_swu ; " \ - "fi\0" - /* The rest of the configuration is shared */ #include <configs/mxs.h> diff --git a/include/configs/xilinx_mbv.h b/include/configs/xilinx_mbv.h new file mode 100644 index 0000000..dba398a --- /dev/null +++ b/include/configs/xilinx_mbv.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ diff --git a/include/console.h b/include/console.h index ceb733b..2617e16 100644 --- a/include/console.h +++ b/include/console.h @@ -85,6 +85,13 @@ int console_record_readline(char *str, int maxlen); int console_record_avail(void); /** + * console_record_isempty() - Returns if console output is empty + * + * Return: true if empty + */ +bool console_record_isempty(void); + +/** * console_in_puts() - Write a string to the console input buffer * * This writes the given string to the console_in buffer which will then be @@ -131,6 +138,12 @@ static inline int console_in_puts(const char *str) return 0; } +static inline bool console_record_isempty(void) +{ + /* Always empty */ + return true; +} + #endif /* !CONFIG_CONSOLE_RECORD */ /** @@ -156,6 +169,16 @@ int console_announce_r(void); */ void console_puts_select_stderr(bool serial_only, const char *s); +/** + * console_clear() - Clear the console + * + * Uses an ANSI sequence to clear the display, failing back to clearing the + * video display directly if !CONFIG_VIDEO_ANSI + * + * Return: 0 if OK, -ve on error + */ +int console_clear(void); + /* * CONSOLE multiplexing. */ diff --git a/include/dfu.h b/include/dfu.h index 68b5ca4..fa1918c 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -10,6 +10,7 @@ #ifndef __DFU_ENTITY_H_ #define __DFU_ENTITY_H_ +#include <linux/errno.h> #include <linux/list.h> #include <mmc.h> #include <spi_flash.h> @@ -98,7 +99,12 @@ struct virt_internal_data { int dev_num; }; + +#if defined(CONFIG_DFU_NAME_MAX_SIZE) +#define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE +#else #define DFU_NAME_SIZE 32 +#endif #ifndef DFU_DEFAULT_POLL_TIMEOUT #define DFU_DEFAULT_POLL_TIMEOUT 0 #endif diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index 70d8cc5..e41baea 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -6,6 +6,8 @@ #ifndef __PINCTRL_H #define __PINCTRL_H +#include <linux/errno.h> + #define PINNAME_SIZE 10 #define PINMUX_SIZE 90 diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 3f28ce6..7da4243 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -130,7 +130,7 @@ #define IMX8MP_CLK_SAI1 123 #define IMX8MP_CLK_SAI2 124 #define IMX8MP_CLK_SAI3 125 -#define IMX8MP_CLK_SAI4 126 +/* #define IMX8MP_CLK_SAI4 126 */ #define IMX8MP_CLK_SAI5 127 #define IMX8MP_CLK_SAI6 128 #define IMX8MP_CLK_ENET_QOS 129 @@ -376,7 +376,6 @@ #define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 #define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 #define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 #define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 diff --git a/include/dt-bindings/clock/mediatek,mt8365-clk.h b/include/dt-bindings/clock/mediatek,mt8365-clk.h new file mode 100644 index 0000000..e5cb8a1 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8365-clk.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + * + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT8365_H +#define _DT_BINDINGS_CLK_MT8365_H + +/* TOPCKGEN */ +#define CLK_TOP_CLK_NULL 0 +#define CLK_TOP_I2S0_BCK 1 +#define CLK_TOP_DSI0_LNTC_DSICK 2 +#define CLK_TOP_VPLL_DPIX 3 +#define CLK_TOP_LVDSTX_CLKDIG_CTS 4 +#define CLK_TOP_MFGPLL 5 +#define CLK_TOP_SYSPLL_D2 6 +#define CLK_TOP_SYSPLL1_D2 7 +#define CLK_TOP_SYSPLL1_D4 8 +#define CLK_TOP_SYSPLL1_D8 9 +#define CLK_TOP_SYSPLL1_D16 10 +#define CLK_TOP_SYSPLL_D3 11 +#define CLK_TOP_SYSPLL2_D2 12 +#define CLK_TOP_SYSPLL2_D4 13 +#define CLK_TOP_SYSPLL2_D8 14 +#define CLK_TOP_SYSPLL_D5 15 +#define CLK_TOP_SYSPLL3_D2 16 +#define CLK_TOP_SYSPLL3_D4 17 +#define CLK_TOP_SYSPLL_D7 18 +#define CLK_TOP_SYSPLL4_D2 19 +#define CLK_TOP_SYSPLL4_D4 20 +#define CLK_TOP_UNIVPLL 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL1_D2 23 +#define CLK_TOP_UNIVPLL1_D4 24 +#define CLK_TOP_UNIVPLL_D3 25 +#define CLK_TOP_UNIVPLL2_D2 26 +#define CLK_TOP_UNIVPLL2_D4 27 +#define CLK_TOP_UNIVPLL2_D8 28 +#define CLK_TOP_UNIVPLL2_D32 29 +#define CLK_TOP_UNIVPLL_D5 30 +#define CLK_TOP_UNIVPLL3_D2 31 +#define CLK_TOP_UNIVPLL3_D4 32 +#define CLK_TOP_MMPLL 33 +#define CLK_TOP_MMPLL_D2 34 +#define CLK_TOP_LVDSPLL_D2 35 +#define CLK_TOP_LVDSPLL_D4 36 +#define CLK_TOP_LVDSPLL_D8 37 +#define CLK_TOP_LVDSPLL_D16 38 +#define CLK_TOP_USB20_192M 39 +#define CLK_TOP_USB20_192M_D4 40 +#define CLK_TOP_USB20_192M_D8 41 +#define CLK_TOP_USB20_192M_D16 42 +#define CLK_TOP_USB20_192M_D32 43 +#define CLK_TOP_APLL1 44 +#define CLK_TOP_APLL1_D2 45 +#define CLK_TOP_APLL1_D4 46 +#define CLK_TOP_APLL1_D8 47 +#define CLK_TOP_APLL2 48 +#define CLK_TOP_APLL2_D2 49 +#define CLK_TOP_APLL2_D4 50 +#define CLK_TOP_APLL2_D8 51 +#define CLK_TOP_SYS_26M_D2 52 +#define CLK_TOP_MSDCPLL 53 +#define CLK_TOP_MSDCPLL_D2 54 +#define CLK_TOP_DSPPLL 55 +#define CLK_TOP_DSPPLL_D2 56 +#define CLK_TOP_DSPPLL_D4 57 +#define CLK_TOP_DSPPLL_D8 58 +#define CLK_TOP_APUPLL 59 +#define CLK_TOP_CLK26M_D52 60 +#define CLK_TOP_AXI_SEL 61 +#define CLK_TOP_MEM_SEL 62 +#define CLK_TOP_MM_SEL 63 +#define CLK_TOP_SCP_SEL 64 +#define CLK_TOP_MFG_SEL 65 +#define CLK_TOP_ATB_SEL 66 +#define CLK_TOP_CAMTG_SEL 67 +#define CLK_TOP_CAMTG1_SEL 68 +#define CLK_TOP_UART_SEL 69 +#define CLK_TOP_SPI_SEL 70 +#define CLK_TOP_MSDC50_0_HC_SEL 71 +#define CLK_TOP_MSDC2_2_HC_SEL 72 +#define CLK_TOP_MSDC50_0_SEL 73 +#define CLK_TOP_MSDC50_2_SEL 74 +#define CLK_TOP_MSDC30_1_SEL 75 +#define CLK_TOP_AUDIO_SEL 76 +#define CLK_TOP_AUD_INTBUS_SEL 77 +#define CLK_TOP_AUD_1_SEL 78 +#define CLK_TOP_AUD_2_SEL 79 +#define CLK_TOP_AUD_ENGEN1_SEL 80 +#define CLK_TOP_AUD_ENGEN2_SEL 81 +#define CLK_TOP_AUD_SPDIF_SEL 82 +#define CLK_TOP_DISP_PWM_SEL 83 +#define CLK_TOP_DXCC_SEL 84 +#define CLK_TOP_SSUSB_SYS_SEL 85 +#define CLK_TOP_SSUSB_XHCI_SEL 86 +#define CLK_TOP_SPM_SEL 87 +#define CLK_TOP_I2C_SEL 88 +#define CLK_TOP_PWM_SEL 89 +#define CLK_TOP_SENIF_SEL 90 +#define CLK_TOP_AES_FDE_SEL 91 +#define CLK_TOP_CAMTM_SEL 92 +#define CLK_TOP_DPI0_SEL 93 +#define CLK_TOP_DPI1_SEL 94 +#define CLK_TOP_DSP_SEL 95 +#define CLK_TOP_NFI2X_SEL 96 +#define CLK_TOP_NFIECC_SEL 97 +#define CLK_TOP_ECC_SEL 98 +#define CLK_TOP_ETH_SEL 99 +#define CLK_TOP_GCPU_SEL 100 +#define CLK_TOP_GCPU_CPM_SEL 101 +#define CLK_TOP_APU_SEL 102 +#define CLK_TOP_APU_IF_SEL 103 +#define CLK_TOP_MBIST_DIAG_SEL 104 +#define CLK_TOP_APLL_I2S0_SEL 105 +#define CLK_TOP_APLL_I2S1_SEL 106 +#define CLK_TOP_APLL_I2S2_SEL 107 +#define CLK_TOP_APLL_I2S3_SEL 108 +#define CLK_TOP_APLL_TDMOUT_SEL 109 +#define CLK_TOP_APLL_TDMIN_SEL 110 +#define CLK_TOP_APLL_SPDIF_SEL 111 +#define CLK_TOP_APLL12_CK_DIV0 112 +#define CLK_TOP_APLL12_CK_DIV1 113 +#define CLK_TOP_APLL12_CK_DIV2 114 +#define CLK_TOP_APLL12_CK_DIV3 115 +#define CLK_TOP_APLL12_CK_DIV4 116 +#define CLK_TOP_APLL12_CK_DIV4B 117 +#define CLK_TOP_APLL12_CK_DIV5 118 +#define CLK_TOP_APLL12_CK_DIV5B 119 +#define CLK_TOP_APLL12_CK_DIV6 120 +#define CLK_TOP_AUD_I2S0_M 121 +#define CLK_TOP_AUD_I2S1_M 122 +#define CLK_TOP_AUD_I2S2_M 123 +#define CLK_TOP_AUD_I2S3_M 124 +#define CLK_TOP_AUD_TDMOUT_M 125 +#define CLK_TOP_AUD_TDMOUT_B 126 +#define CLK_TOP_AUD_TDMIN_M 127 +#define CLK_TOP_AUD_TDMIN_B 128 +#define CLK_TOP_AUD_SPDIF_M 129 +#define CLK_TOP_USB20_48M_EN 130 +#define CLK_TOP_UNIVPLL_48M_EN 131 +#define CLK_TOP_LVDSTX_CLKDIG_EN 132 +#define CLK_TOP_VPLL_DPIX_EN 133 +#define CLK_TOP_SSUSB_TOP_CK_EN 134 +#define CLK_TOP_SSUSB_PHY_CK_EN 135 +#define CLK_TOP_CONN_32K 136 +#define CLK_TOP_CONN_26M 137 +#define CLK_TOP_DSP_32K 138 +#define CLK_TOP_DSP_26M 139 +#define CLK_TOP_NR_CLK 140 +#define CLK_TOP_CLK26M 141 +#define CLK_TOP_CLK32K 142 + +/* INFRACFG */ +#define CLK_IFR_PMIC_TMR 0 +#define CLK_IFR_PMIC_AP 1 +#define CLK_IFR_PMIC_MD 2 +#define CLK_IFR_PMIC_CONN 3 +#define CLK_IFR_ICUSB 4 +#define CLK_IFR_GCE 5 +#define CLK_IFR_THERM 6 +#define CLK_IFR_PWM_HCLK 7 +#define CLK_IFR_PWM1 8 +#define CLK_IFR_PWM2 9 +#define CLK_IFR_PWM3 10 +#define CLK_IFR_PWM4 11 +#define CLK_IFR_PWM5 12 +#define CLK_IFR_PWM 13 +#define CLK_IFR_UART0 14 +#define CLK_IFR_UART1 15 +#define CLK_IFR_UART2 16 +#define CLK_IFR_DSP_UART 17 +#define CLK_IFR_GCE_26M 18 +#define CLK_IFR_CQ_DMA_FPC 19 +#define CLK_IFR_BTIF 20 +#define CLK_IFR_SPI0 21 +#define CLK_IFR_MSDC0_HCLK 22 +#define CLK_IFR_MSDC2_HCLK 23 +#define CLK_IFR_MSDC1_HCLK 24 +#define CLK_IFR_DVFSRC 25 +#define CLK_IFR_GCPU 26 +#define CLK_IFR_TRNG 27 +#define CLK_IFR_AUXADC 28 +#define CLK_IFR_CPUM 29 +#define CLK_IFR_AUXADC_MD 30 +#define CLK_IFR_AP_DMA 31 +#define CLK_IFR_DEBUGSYS 32 +#define CLK_IFR_AUDIO 33 +#define CLK_IFR_PWM_FBCLK6 34 +#define CLK_IFR_DISP_PWM 35 +#define CLK_IFR_AUD_26M_BK 36 +#define CLK_IFR_CQ_DMA 37 +#define CLK_IFR_MSDC0_SF 38 +#define CLK_IFR_MSDC1_SF 39 +#define CLK_IFR_MSDC2_SF 40 +#define CLK_IFR_AP_MSDC0 41 +#define CLK_IFR_MD_MSDC0 42 +#define CLK_IFR_MSDC0_SRC 43 +#define CLK_IFR_MSDC1_SRC 44 +#define CLK_IFR_MSDC2_SRC 45 +#define CLK_IFR_PWRAP_TMR 46 +#define CLK_IFR_PWRAP_SPI 47 +#define CLK_IFR_PWRAP_SYS 48 +#define CLK_IFR_MCU_PM_BK 49 +#define CLK_IFR_IRRX_26M 50 +#define CLK_IFR_IRRX_32K 51 +#define CLK_IFR_I2C0_AXI 52 +#define CLK_IFR_I2C1_AXI 53 +#define CLK_IFR_I2C2_AXI 54 +#define CLK_IFR_I2C3_AXI 55 +#define CLK_IFR_NIC_AXI 56 +#define CLK_IFR_NIC_SLV_AXI 57 +#define CLK_IFR_APU_AXI 58 +#define CLK_IFR_NFIECC 59 +#define CLK_IFR_NFIECC_BK 60 +#define CLK_IFR_NFI1X_BK 61 +#define CLK_IFR_NFI_BK 62 +#define CLK_IFR_MSDC2_AP_BK 63 +#define CLK_IFR_MSDC2_MD_BK 64 +#define CLK_IFR_MSDC2_BK 65 +#define CLK_IFR_SUSB_133_BK 66 +#define CLK_IFR_SUSB_66_BK 67 +#define CLK_IFR_SSUSB_SYS 68 +#define CLK_IFR_SSUSB_REF 69 +#define CLK_IFR_SSUSB_XHCI 70 +#define CLK_IFR_NR_CLK 71 + +/* PERICFG */ +#define CLK_PERIAXI 0 +#define CLK_PERI_NR_CLK 1 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIVPLL 2 +#define CLK_APMIXED_MFGPLL 3 +#define CLK_APMIXED_MSDCPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_APLL1 6 +#define CLK_APMIXED_APLL2 7 +#define CLK_APMIXED_LVDSPLL 8 +#define CLK_APMIXED_DSPPLL 9 +#define CLK_APMIXED_APUPLL 10 +#define CLK_APMIXED_UNIV_EN 11 +#define CLK_APMIXED_USB20_EN 12 +#define CLK_APMIXED_NR_CLK 13 + +/* GCE */ +#define CLK_GCE_FAXI 0 +#define CLK_GCE_NR_CLK 1 + +/* AUDIOTOP */ +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_SPDF 7 +#define CLK_AUD_HDMI 8 +#define CLK_AUD_HDMI_IN 9 +#define CLK_AUD_ADC 10 +#define CLK_AUD_DAC 11 +#define CLK_AUD_DAC_PREDIS 12 +#define CLK_AUD_TML 13 +#define CLK_AUD_I2S1_BK 14 +#define CLK_AUD_I2S2_BK 15 +#define CLK_AUD_I2S3_BK 16 +#define CLK_AUD_I2S4_BK 17 +#define CLK_AUD_NR_CLK 18 + +/* MIPI_CSI0A */ +#define CLK_MIPI0A_CSR_CSI_EN_0A 0 +#define CLK_MIPI_RX_ANA_CSI0A_NR_CLK 1 + +/* MIPI_CSI0B */ +#define CLK_MIPI0B_CSR_CSI_EN_0B 0 +#define CLK_MIPI_RX_ANA_CSI0B_NR_CLK 1 + +/* MIPI_CSI1A */ +#define CLK_MIPI1A_CSR_CSI_EN_1A 0 +#define CLK_MIPI_RX_ANA_CSI1A_NR_CLK 1 + +/* MIPI_CSI1B */ +#define CLK_MIPI1B_CSR_CSI_EN_1B 0 +#define CLK_MIPI_RX_ANA_CSI1B_NR_CLK 1 + +/* MIPI_CSI2A */ +#define CLK_MIPI2A_CSR_CSI_EN_2A 0 +#define CLK_MIPI_RX_ANA_CSI2A_NR_CLK 1 + +/* MIPI_CSI2B */ +#define CLK_MIPI2B_CSR_CSI_EN_2B 0 +#define CLK_MIPI_RX_ANA_CSI2B_NR_CLK 1 + +/* MCUCFG */ +#define CLK_MCU_BUS_SEL 0 +#define CLK_MCU_NR_CLK 1 + +/* MFGCFG */ +#define CLK_MFG_BG3D 0 +#define CLK_MFG_MBIST_DIAG 1 +#define CLK_MFG_NR_CLK 2 + +/* MMSYS */ +#define CLK_MM_MM_MDP_RDMA0 0 +#define CLK_MM_MM_MDP_CCORR0 1 +#define CLK_MM_MM_MDP_RSZ0 2 +#define CLK_MM_MM_MDP_RSZ1 3 +#define CLK_MM_MM_MDP_TDSHP0 4 +#define CLK_MM_MM_MDP_WROT0 5 +#define CLK_MM_MM_MDP_WDMA0 6 +#define CLK_MM_MM_DISP_OVL0 7 +#define CLK_MM_MM_DISP_OVL0_2L 8 +#define CLK_MM_MM_DISP_RSZ0 9 +#define CLK_MM_MM_DISP_RDMA0 10 +#define CLK_MM_MM_DISP_WDMA0 11 +#define CLK_MM_MM_DISP_COLOR0 12 +#define CLK_MM_MM_DISP_CCORR0 13 +#define CLK_MM_MM_DISP_AAL0 14 +#define CLK_MM_MM_DISP_GAMMA0 15 +#define CLK_MM_MM_DISP_DITHER0 16 +#define CLK_MM_MM_DSI0 17 +#define CLK_MM_MM_DISP_RDMA1 18 +#define CLK_MM_MM_MDP_RDMA1 19 +#define CLK_MM_DPI0_DPI0 20 +#define CLK_MM_MM_FAKE 21 +#define CLK_MM_MM_SMI_COMMON 22 +#define CLK_MM_MM_SMI_LARB0 23 +#define CLK_MM_MM_SMI_COMM0 24 +#define CLK_MM_MM_SMI_COMM1 25 +#define CLK_MM_MM_CAM_MDP 26 +#define CLK_MM_MM_SMI_IMG 27 +#define CLK_MM_MM_SMI_CAM 28 +#define CLK_MM_IMG_IMG_DL_RELAY 29 +#define CLK_MM_IMG_IMG_DL_ASYNC_TOP 30 +#define CLK_MM_DSI0_DIG_DSI 31 +#define CLK_MM_26M_HRTWT 32 +#define CLK_MM_MM_DPI0 33 +#define CLK_MM_LVDSTX_PXL 34 +#define CLK_MM_LVDSTX_CTS 35 +#define CLK_MM_NR_CLK 36 + +/* IMGSYS */ +#define CLK_CAM_LARB2 0 +#define CLK_CAM 1 +#define CLK_CAMTG 2 +#define CLK_CAM_SENIF 3 +#define CLK_CAMSV0 4 +#define CLK_CAMSV1 5 +#define CLK_CAM_FDVT 6 +#define CLK_CAM_WPE 7 +#define CLK_CAM_NR_CLK 8 + +/* VDECSYS */ +#define CLK_VDEC_VDEC 0 +#define CLK_VDEC_LARB1 1 +#define CLK_VDEC_NR_CLK 2 + +/* VENCSYS */ +#define CLK_VENC 0 +#define CLK_VENC_JPGENC 1 +#define CLK_VENC_NR_CLK 2 + +/* APUSYS */ +#define CLK_APU_IPU_CK 0 +#define CLK_APU_AXI 1 +#define CLK_APU_JTAG 2 +#define CLK_APU_IF_CK 3 +#define CLK_APU_EDMA 4 +#define CLK_APU_AHB 5 +#define CLK_APU_NR_CLK 6 + +#endif /* _DT_BINDINGS_CLK_MT8365_H */ diff --git a/include/dt-bindings/clock/qcom,ipq4019-gcc.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h index 7130e22..7e8a7be 100644 --- a/include/dt-bindings/clock/qcom,ipq4019-gcc.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h @@ -93,4 +93,77 @@ #define GCC_APSS_CPU_PLLDIV_CLK 74 #define GCC_PCNOC_AHB_CLK_SRC 75 +#define WIFI0_CPU_INIT_RESET 0 +#define WIFI0_RADIO_SRIF_RESET 1 +#define WIFI0_RADIO_WARM_RESET 2 +#define WIFI0_RADIO_COLD_RESET 3 +#define WIFI0_CORE_WARM_RESET 4 +#define WIFI0_CORE_COLD_RESET 5 +#define WIFI1_CPU_INIT_RESET 6 +#define WIFI1_RADIO_SRIF_RESET 7 +#define WIFI1_RADIO_WARM_RESET 8 +#define WIFI1_RADIO_COLD_RESET 9 +#define WIFI1_CORE_WARM_RESET 10 +#define WIFI1_CORE_COLD_RESET 11 +#define USB3_UNIPHY_PHY_ARES 12 +#define USB3_HSPHY_POR_ARES 13 +#define USB3_HSPHY_S_ARES 14 +#define USB2_HSPHY_POR_ARES 15 +#define USB2_HSPHY_S_ARES 16 +#define PCIE_PHY_AHB_ARES 17 +#define PCIE_AHB_ARES 18 +#define PCIE_PWR_ARES 19 +#define PCIE_PIPE_STICKY_ARES 20 +#define PCIE_AXI_M_STICKY_ARES 21 +#define PCIE_PHY_ARES 22 +#define PCIE_PARF_XPU_ARES 23 +#define PCIE_AXI_S_XPU_ARES 24 +#define PCIE_AXI_M_VMIDMT_ARES 25 +#define PCIE_PIPE_ARES 26 +#define PCIE_AXI_S_ARES 27 +#define PCIE_AXI_M_ARES 28 +#define ESS_RESET 29 +#define GCC_BLSP1_BCR 30 +#define GCC_BLSP1_QUP1_BCR 31 +#define GCC_BLSP1_UART1_BCR 32 +#define GCC_BLSP1_QUP2_BCR 33 +#define GCC_BLSP1_UART2_BCR 34 +#define GCC_BIMC_BCR 35 +#define GCC_TLMM_BCR 36 +#define GCC_IMEM_BCR 37 +#define GCC_ESS_BCR 38 +#define GCC_PRNG_BCR 39 +#define GCC_BOOT_ROM_BCR 40 +#define GCC_CRYPTO_BCR 41 +#define GCC_SDCC1_BCR 42 +#define GCC_SEC_CTRL_BCR 43 +#define GCC_AUDIO_BCR 44 +#define GCC_QPIC_BCR 45 +#define GCC_PCIE_BCR 46 +#define GCC_USB2_BCR 47 +#define GCC_USB2_PHY_BCR 48 +#define GCC_USB3_BCR 49 +#define GCC_USB3_PHY_BCR 50 +#define GCC_SYSTEM_NOC_BCR 51 +#define GCC_PCNOC_BCR 52 +#define GCC_DCD_BCR 53 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +#define GCC_TCSR_BCR 68 +#define GCC_QDSS_BCR 69 +#define GCC_MPM_BCR 70 +#define GCC_SPDM_BCR 71 + #endif diff --git a/include/dt-bindings/phy/nuvoton,npcm-usbphy.h b/include/dt-bindings/phy/nuvoton,npcm-usbphy.h new file mode 100644 index 0000000..46946d3 --- /dev/null +++ b/include/dt-bindings/phy/nuvoton,npcm-usbphy.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2023 Nuvoton Technology corporation. + +#ifndef _DT_BINDINGS_NPCM_USBPHY_H +#define _DT_BINDINGS_NPCM_USBPHY_H + +#define NPCM_UDC0_7 0 +#define NPCM_UDC8 1 +#define NPCM_UDC9 2 +#define NPCM_USBH1 3 +#define NPCM_USBH2 4 +#define NPCM_MAX_USB_CTRL_ID 4 + +#endif diff --git a/include/dt-bindings/pinctrl/mt8365-pinfunc.h b/include/dt-bindings/pinctrl/mt8365-pinfunc.h new file mode 100644 index 0000000..e2ec8af --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8365-pinfunc.h @@ -0,0 +1,858 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 MediaTek Inc. + */ +#ifndef __MT8365_PINFUNC_H +#define __MT8365_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1) +#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2) +#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5) +#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1) +#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2) +#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3) +#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5) +#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) + +#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1) +#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2) +#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3) +#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5) +#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) + +#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1) +#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2) +#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) +#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5) +#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6) +#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7) + +#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1) +#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2) +#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3) +#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5) +#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6) +#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7) + +#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1) +#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2) +#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3) +#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5) +#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7) + +#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1) +#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2) +#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) +#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5) +#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6) +#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7) + +#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1) +#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3) +#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5) +#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7) + +#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1) +#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2) +#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3) +#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5) +#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7) + +#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1) +#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2) +#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3) +#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5) +#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7) + +#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1) +#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2) +#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3) +#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5) +#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7) + +#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1) +#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2) +#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3) +#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4) +#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5) +#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7) + +#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1) +#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2) +#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3) +#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4) +#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5) +#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7) + +#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1) +#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2) +#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3) +#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4) +#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5) +#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7) + +#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1) +#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2) +#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3) +#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4) +#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5) +#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6) +#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7) + +#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1) +#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2) +#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3) +#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4) +#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5) +#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6) +#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7) + +#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1) +#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2) +#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3) +#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4) +#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5) +#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6) +#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7) + +#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1) +#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2) +#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3) +#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4) +#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5) +#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6) +#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7) + +#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1) +#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2) +#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3) +#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4) +#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5) +#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6) +#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7) + +#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1) +#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2) +#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7) + +#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1) +#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2) +#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7) + +#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1) +#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2) +#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3) +#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4) +#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7) + +#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1) +#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7) + +#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1) +#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2) +#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3) +#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4) +#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5) +#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6) +#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7) + +#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1) +#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7) + +#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1) +#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2) +#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3) +#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4) +#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5) +#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6) +#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7) + +#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1) +#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3) +#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4) +#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5) +#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6) +#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7) + +#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1) +#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3) +#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4) +#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5) +#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6) +#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7) + +#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1) +#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2) +#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3) +#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4) +#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5) +#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6) +#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7) + +#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1) +#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2) +#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3) +#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4) +#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5) +#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6) +#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7) + +#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1) +#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2) +#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3) +#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4) +#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5) +#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6) + +#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1) +#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2) +#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3) +#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4) +#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5) +#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6) + +#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1) +#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2) +#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3) +#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4) +#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5) + +#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1) +#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2) +#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3) +#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4) +#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5) + +#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1) +#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2) +#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3) +#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4) +#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) + +#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1) +#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2) +#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7) + +#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1) +#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2) +#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7) + +#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1) +#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2) +#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3) +#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4) +#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5) +#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6) +#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7) + +#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1) +#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2) +#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3) +#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4) +#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5) +#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6) +#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7) + +#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1) +#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2) +#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3) +#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4) +#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5) +#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6) +#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7) + +#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1) +#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2) +#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3) +#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4) +#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5) +#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6) +#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7) + +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1) +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2) + +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) + +#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1) + +#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1) + +#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1) + +#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1) + +#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1) +#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2) + +#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1) + +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3) + +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3) + +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3) + +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3) + +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3) + +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3) + +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3) + +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3) + +#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1) + +#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1) + +#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1) +#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6) +#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7) + +#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1) +#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6) +#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7) + +#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1) + +#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1) + +#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1) + +#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1) + +#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1) +#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2) +#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7) + +#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1) +#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2) +#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7) + +#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1) +#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2) +#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4) +#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5) +#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7) + +#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1) +#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2) +#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4) +#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5) +#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7) + +#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1) +#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2) +#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3) +#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4) +#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5) +#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7) + +#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1) +#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2) +#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4) +#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5) +#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7) + +#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1) +#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2) +#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7) + +#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1) +#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2) +#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5) +#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7) + +#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1) +#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2) +#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5) +#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7) + +#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1) +#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2) +#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5) +#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7) + +#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1) +#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5) +#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7) + +#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1) +#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5) +#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7) + +#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1) +#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5) +#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7) + +#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1) +#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5) +#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7) + +#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1) +#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5) +#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7) + +#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6) + +#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6) + +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6) + +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6) + +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6) + +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5) + +#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3) + +#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7) + +#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7) + +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7) + +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7) + +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7) + +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3) + +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1) +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2) + +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1) +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2) + +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1) +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2) + +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1) +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2) + +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1) +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2) + +#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1) +#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2) + +#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1) +#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2) + +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1) +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2) + +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1) +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2) + +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1) +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2) + +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1) +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2) + +#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1) + +#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1) +#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2) +#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7) + +#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1) +#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2) +#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7) + +#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1) +#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2) +#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7) + +#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1) +#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2) +#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7) + +#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1) +#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2) +#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7) + +#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1) +#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2) +#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3) +#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4) +#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5) + +#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1) +#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2) +#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3) +#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4) +#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5) + +#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1) +#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) +#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3) +#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4) +#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5) + +#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1) +#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2) +#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3) +#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4) +#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5) + +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7) + +#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4) +#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5) +#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6) +#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7) + +#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4) +#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5) +#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6) +#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7) + +#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7) + +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7) + +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7) + +#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7) + +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7) + +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7) + +#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7) + +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7) + +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7) + +#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1) +#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2) + +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1) +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2) + +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3) + +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3) + +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3) + +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3) + +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7) + +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1) +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7) + +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1) +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7) + +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1) +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7) + +#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1) + +#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1) + +#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1) + +#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1) + +#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1) + +#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1) + +#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1) + +#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1) + +#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1) + +#endif /* __MT8365_PINFUNC_H */ diff --git a/include/dt-bindings/pmic/max77663.h b/include/dt-bindings/pmic/max77663.h new file mode 100644 index 0000000..ee169a8 --- /dev/null +++ b/include/dt-bindings/pmic/max77663.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef _DT_BINDINGS_MAX77663_H_ +#define _DT_BINDINGS_MAX77663_H_ + +/* + * MAX77663 has 8 GPIO (0 to 7) and 3 KEYS + * KEYS are appended after GPIOs + */ + +#define EN0 10 +#define ACOK 9 +#define LID 8 + +#endif diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h new file mode 100644 index 0000000..e6cfd0e --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ diff --git a/include/dt-bindings/reset/qcom,ipq4019-reset.h b/include/dt-bindings/reset/qcom,ipq4019-reset.h deleted file mode 100644 index ed047d7..0000000 --- a/include/dt-bindings/reset/qcom,ipq4019-reset.h +++ /dev/null @@ -1,92 +0,0 @@ -/* Copyright (c) 2015 The Linux Foundation. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ -#ifndef __QCOM_RESET_IPQ4019_H__ -#define __QCOM_RESET_IPQ4019_H__ - -#define WIFI0_CPU_INIT_RESET 0 -#define WIFI0_RADIO_SRIF_RESET 1 -#define WIFI0_RADIO_WARM_RESET 2 -#define WIFI0_RADIO_COLD_RESET 3 -#define WIFI0_CORE_WARM_RESET 4 -#define WIFI0_CORE_COLD_RESET 5 -#define WIFI1_CPU_INIT_RESET 6 -#define WIFI1_RADIO_SRIF_RESET 7 -#define WIFI1_RADIO_WARM_RESET 8 -#define WIFI1_RADIO_COLD_RESET 9 -#define WIFI1_CORE_WARM_RESET 10 -#define WIFI1_CORE_COLD_RESET 11 -#define USB3_UNIPHY_PHY_ARES 12 -#define USB3_HSPHY_POR_ARES 13 -#define USB3_HSPHY_S_ARES 14 -#define USB2_HSPHY_POR_ARES 15 -#define USB2_HSPHY_S_ARES 16 -#define PCIE_PHY_AHB_ARES 17 -#define PCIE_AHB_ARES 18 -#define PCIE_PWR_ARES 19 -#define PCIE_PIPE_STICKY_ARES 20 -#define PCIE_AXI_M_STICKY_ARES 21 -#define PCIE_PHY_ARES 22 -#define PCIE_PARF_XPU_ARES 23 -#define PCIE_AXI_S_XPU_ARES 24 -#define PCIE_AXI_M_VMIDMT_ARES 25 -#define PCIE_PIPE_ARES 26 -#define PCIE_AXI_S_ARES 27 -#define PCIE_AXI_M_ARES 28 -#define ESS_RESET 29 -#define GCC_BLSP1_BCR 30 -#define GCC_BLSP1_QUP1_BCR 31 -#define GCC_BLSP1_UART1_BCR 32 -#define GCC_BLSP1_QUP2_BCR 33 -#define GCC_BLSP1_UART2_BCR 34 -#define GCC_BIMC_BCR 35 -#define GCC_TLMM_BCR 36 -#define GCC_IMEM_BCR 37 -#define GCC_ESS_BCR 38 -#define GCC_PRNG_BCR 39 -#define GCC_BOOT_ROM_BCR 40 -#define GCC_CRYPTO_BCR 41 -#define GCC_SDCC1_BCR 42 -#define GCC_SEC_CTRL_BCR 43 -#define GCC_AUDIO_BCR 44 -#define GCC_QPIC_BCR 45 -#define GCC_PCIE_BCR 46 -#define GCC_USB2_BCR 47 -#define GCC_USB2_PHY_BCR 48 -#define GCC_USB3_BCR 49 -#define GCC_USB3_PHY_BCR 50 -#define GCC_SYSTEM_NOC_BCR 51 -#define GCC_PCNOC_BCR 52 -#define GCC_DCD_BCR 53 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 -#define GCC_TCSR_BCR 68 -#define GCC_QDSS_BCR 69 -#define GCC_MPM_BCR 70 -#define GCC_SPDM_BCR 71 - -#endif diff --git a/include/efi_api.h b/include/efi_api.h index 0e92cb8..ab40b1b 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -433,6 +433,10 @@ struct efi_runtime_services { EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3, \ 0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d) +#define SMBIOS3_TABLE_GUID \ + EFI_GUID(0xf2fd1544, 0x9794, 0x4a2c, \ + 0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94) + #define EFI_LOAD_FILE_PROTOCOL_GUID \ EFI_GUID(0x56ec3091, 0x954c, 0x11d2, \ 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) diff --git a/include/efi_loader.h b/include/efi_loader.h index 664dae2..5c5af4f 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -90,9 +90,7 @@ efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len); * back to u-boot world */ void efi_restore_gd(void); -/* Call this to set the current device name */ -void efi_set_bootdev(const char *dev, const char *devnr, const char *path, - void *buffer, size_t buffer_size); + /* Called by networking code to memorize the dhcp ack package */ void efi_net_set_dhcp_ack(void *pkt, int len); /* Print information about all loaded images */ @@ -114,9 +112,6 @@ static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len) /* No loader configured, stub out EFI_ENTRY */ static inline void efi_restore_gd(void) { } -static inline void efi_set_bootdev(const char *dev, const char *devnr, - const char *path, void *buffer, - size_t buffer_size) { } static inline void efi_net_set_dhcp_ack(void *pkt, int len) { } static inline void efi_print_image_infos(void *pc) { } static inline efi_status_t efi_launch_capsules(void) @@ -126,6 +121,20 @@ static inline efi_status_t efi_launch_capsules(void) #endif /* CONFIG_IS_ENABLED(EFI_LOADER) */ +#if CONFIG_IS_ENABLED(EFI_BINARY_EXEC) +/* Call this to unset the current device name */ +void efi_clear_bootdev(void); +/* Call this to set the current device name */ +void efi_set_bootdev(const char *dev, const char *devnr, const char *path, + void *buffer, size_t buffer_size); +#else +static inline void efi_clear_bootdev(void) { } + +static inline void efi_set_bootdev(const char *dev, const char *devnr, + const char *path, void *buffer, + size_t buffer_size) { } +#endif + /* Maximum number of configuration tables */ #define EFI_MAX_CONFIGURATION_TABLES 16 @@ -331,6 +340,7 @@ extern const efi_guid_t efi_guid_firmware_management_protocol; extern const efi_guid_t efi_esrt_guid; /* GUID of the SMBIOS table */ extern const efi_guid_t smbios_guid; +extern const efi_guid_t smbios3_guid; /*GUID of console */ extern const efi_guid_t efi_guid_text_input_protocol; extern const efi_guid_t efi_guid_text_output_protocol; @@ -527,14 +537,21 @@ efi_status_t efi_bootmgr_get_unused_bootoption(u16 *buf, efi_status_t efi_bootmgr_update_media_device_boot_option(void); /* Delete selected boot option */ efi_status_t efi_bootmgr_delete_boot_option(u16 boot_index); +/* Invoke EFI boot manager */ +efi_status_t efi_bootmgr_run(void *fdt); /* search the boot option index in BootOrder */ bool efi_search_bootorder(u16 *bootorder, efi_uintn_t num, u32 target, u32 *index); /* Set up console modes */ void efi_setup_console_size(void); +/* Set up load options from environment variable */ +efi_status_t efi_env_set_load_options(efi_handle_t handle, const char *env_var, + u16 **load_options); /* Install device tree */ efi_status_t efi_install_fdt(void *fdt); -/* Run loaded UEFI image */ -efi_status_t efi_run_image(void *source_buffer, efi_uintn_t source_size); +/* Execute loaded UEFI image */ +efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options); +/* Run loaded UEFI image with given fdt */ +efi_status_t efi_binary_run(void *image, size_t size, void *fdt); /* Initialize variable services */ efi_status_t efi_init_variables(void); /* Notify ExitBootServices() is called */ @@ -809,8 +826,6 @@ efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp); /* size of multi-instance device path excluding end node */ efi_uintn_t efi_dp_size(const struct efi_device_path *dp); struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp); -struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1, - const struct efi_device_path *dp2); struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp, const struct efi_device_path *node); /* Create a device path node of given type, sub-type, length */ @@ -879,14 +894,12 @@ efi_status_t __efi_runtime EFIAPI efi_get_time( efi_status_t __efi_runtime EFIAPI efi_set_time(struct efi_time *time); -#ifdef CONFIG_CMD_BOOTEFI_SELFTEST /* * Entry point for the tests of the EFI API. * It is called by 'bootefi selftest' */ efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle, struct efi_system_table *systab); -#endif efi_status_t EFIAPI efi_get_variable(u16 *variable_name, const efi_guid_t *vendor, u32 *attributes, @@ -929,7 +942,8 @@ struct efi_load_option { struct efi_device_path *efi_dp_from_lo(struct efi_load_option *lo, const efi_guid_t *guid); struct efi_device_path *efi_dp_concat(const struct efi_device_path *dp1, - const struct efi_device_path *dp2); + const struct efi_device_path *dp2, + bool split_end_node); struct efi_device_path *search_gpt_dp_node(struct efi_device_path *device_path); efi_status_t efi_deserialize_load_option(struct efi_load_option *lo, u8 *data, efi_uintn_t *size); diff --git a/include/env.h b/include/env.h index 9778e3e..d2a5954 100644 --- a/include/env.h +++ b/include/env.h @@ -356,6 +356,16 @@ int env_import_redund(const char *buf1, int buf1_read_fail, */ char *env_get_default(const char *name); +/** + * env_get_default_into() - Look up a variable from the default environment and + * copy its value in buf. + * + * @name: Variable to look up + * Return: actual length of the variable value excluding the terminating + * NULL-byte, or -1 if the variable is not found + */ +int env_get_default_into(const char *name, char *buf, unsigned int len); + /* [re]set to the default environment */ void env_set_default(const char *s, int flags); diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index f5d8421..02b410c 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -22,10 +22,14 @@ get_fit_overlaystring= done; get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile} run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} +do_main_cpsw0_qsgmii_phyinit=0 bootcmd_ti_mmc= run findfdt; run init_${boot}; #if CONFIG_CMD_REMOTEPROC - run main_cpsw0_qsgmii_phyinit; run boot_rprocs; + if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1; + then run main_cpsw0_qsgmii_phyinit; + fi; + run boot_rprocs; #endif if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_fit_overlaystring; run run_fit; diff --git a/include/env_internal.h b/include/env_internal.h index 5c289d6..cbd1ef3 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -15,7 +15,6 @@ #ifndef _ENV_INTERNAL_H_ #define _ENV_INTERNAL_H_ -#include <linux/kconfig.h> /************************************************************************** * diff --git a/include/fastboot-internal.h b/include/fastboot-internal.h index bf2f2b3..610d4f9 100644 --- a/include/fastboot-internal.h +++ b/include/fastboot-internal.h @@ -19,6 +19,13 @@ extern u32 fastboot_buf_size; extern void (*fastboot_progress_callback)(const char *msg); /** + * fastboot_getvar_all() - Writes current variable being listed from "all" to response. + * + * @response: Pointer to fastboot response buffer + */ +void fastboot_getvar_all(char *response); + +/** * fastboot_getvar() - Writes variable indicated by cmd_parameter to response. * * @cmd_parameter: Pointer to command parameter diff --git a/include/fastboot.h b/include/fastboot.h index 296451f..1e7920e 100644 --- a/include/fastboot.h +++ b/include/fastboot.h @@ -14,6 +14,16 @@ #define FASTBOOT_VERSION "0.4" +/* + * Signals u-boot fastboot code to send multiple responses by + * calling response generating function repeatedly until a OKAY/FAIL + * is generated as final response. + * + * This status code is only used internally to signal, must NOT + * be sent to host. + */ +#define FASTBOOT_MULTIRESPONSE_START ("MORE") + /* The 64 defined bytes plus \0 */ #define FASTBOOT_COMMAND_LEN (64 + 1) #define FASTBOOT_RESPONSE_LEN (64 + 1) @@ -37,6 +47,7 @@ enum { FASTBOOT_COMMAND_OEM_PARTCONF, FASTBOOT_COMMAND_OEM_BOOTBUS, FASTBOOT_COMMAND_OEM_RUN, + FASTBOOT_COMMAND_OEM_CONSOLE, FASTBOOT_COMMAND_ACMD, FASTBOOT_COMMAND_UCMD, FASTBOOT_COMMAND_COUNT @@ -172,5 +183,13 @@ void fastboot_data_download(const void *fastboot_data, */ void fastboot_data_complete(char *response); +/** + * fastboot_handle_multiresponse() - Called for each response to send + * + * @cmd: Command id that requested multiresponse + * @response: Pointer to fastboot response buffer + */ +void fastboot_multiresponse(int cmd, char *response); + void fastboot_acmd_complete(void); #endif /* _FASTBOOT_H_ */ diff --git a/include/fat.h b/include/fat.h index a9756fb..3dce99a 100644 --- a/include/fat.h +++ b/include/fat.h @@ -34,12 +34,6 @@ struct disk_partition; /* Maximum number of entry for long file name according to spec */ #define MAX_LFN_SLOT 20 -/* Filesystem identifiers */ -#define FAT12_SIGN "FAT12 " -#define FAT16_SIGN "FAT16 " -#define FAT32_SIGN "FAT32 " -#define SIGNLEN 8 - /* File attributes */ #define ATTR_RO 1 #define ATTR_HIDDEN 2 diff --git a/include/fdt_support.h b/include/fdt_support.h index 2cd8366..25600d6 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -7,8 +7,7 @@ #ifndef __FDT_SUPPORT_H #define __FDT_SUPPORT_H -#if (defined(CONFIG_OF_LIBFDT) || defined(CONFIG_OF_CONTROL)) && \ - !defined(USE_HOSTCC) +#if !defined(USE_HOSTCC) #include <asm/u-boot.h> #include <linux/libfdt.h> @@ -56,7 +55,17 @@ int fdt_chosen(void *fdt); /** * Add initrd information to the FDT before booting the OS. * - * @param fdt FDT address in memory + * Adds linux,initrd-start and linux,initrd-end properties to the /chosen node, + * creating it if necessary. + * + * A memory reservation for the ramdisk is added to the FDT, or an existing one + * (with matching @initrd_start) updated. + * + * If @initrd_start == @initrd_end this function does nothing and returns 0. + * + * @fdt: Pointer to FDT in memory + * @initrd_start: Start of ramdisk + * @initrd_end: End of ramdisk * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end); @@ -233,13 +242,23 @@ int ft_system_setup(void *blob, struct bd_info *bd); void set_working_fdt_addr(ulong addr); /** - * shrink down the given blob to minimum size + some extrasize if required + * fdt_shrink_to_minimum() - shrink FDT while allowing for some margin + * + * Shrink down the given blob to 'minimum' size + some extrasize. + * + * The new size is enough to hold the existing contents plus @extrasize bytes, + * plus 5 memory reservations. Also, the end of the FDT is aligned to a 4KB + * boundary, so it might end up up to 4KB larger than needed. + * + * If there is an existing memory reservation for @blob in the FDT, it is + * updated for the new size. * * @param blob FDT blob to update * @param extrasize additional bytes needed * Return: 0 if ok, or -FDT_ERR_... on error */ int fdt_shrink_to_minimum(void *blob, uint extrasize); + int fdt_increase_size(void *fdt, int add_len); int fdt_delete_disabled_nodes(void *blob); @@ -418,7 +437,7 @@ int fdt_valid(struct fdt_header **blobp); */ int fdt_get_cells_len(const void *blob, char *nr_cells_name); -#endif /* ifdef CONFIG_OF_LIBFDT */ +#endif /* !USE_HOSTCC */ #ifdef USE_HOSTCC int fdtdec_get_int(const void *blob, int node, const char *prop_name, diff --git a/include/fdtdec.h b/include/fdtdec.h index bd1149f..e80de24 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -72,7 +72,7 @@ struct bd_info; * U-Boot is packaged as an ELF file, e.g. for debugging purposes * @FDTSRC_ENV: Provided by the fdtcontroladdr environment variable. This should * be used for debugging/development only - * @FDTSRC_NONE: No devicetree at all + * @FDTSRC_BLOBLIST: Provided by a bloblist from an earlier phase */ enum fdt_source_t { FDTSRC_SEPARATE, @@ -80,6 +80,7 @@ enum fdt_source_t { FDTSRC_BOARD, FDTSRC_EMBED, FDTSRC_ENV, + FDTSRC_BLOBLIST, }; /* @@ -1190,7 +1191,8 @@ int fdtdec_resetup(int *rescan); * * The existing devicetree is available at gd->fdt_blob * - * @err internal error code if we fail to setup a DTB + * @err: 0 on success, -EEXIST if the devicetree is already correct, or other + * internal error code if we fail to setup a DTB * @returns new devicetree blob pointer */ void *board_fdt_blob_setup(int *err); diff --git a/include/fwu.h b/include/fwu.h index ac5c5de..eb5638f 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -122,21 +122,18 @@ int fwu_get_active_index(uint *active_idxp); int fwu_set_active_index(uint active_idx); /** - * fwu_get_image_index() - Get the Image Index to be used for capsule update - * @image_index: The Image Index for the image - * - * The FWU multi bank update feature computes the value of image_index at - * runtime, based on the bank to which the image needs to be written to. - * Derive the image_index value for the image. + * fwu_get_dfu_alt_num() - Get the dfu_alt_num to be used for capsule update + * @image_index: The Image Index for the image + * @alt_num: pointer to store dfu_alt_num * * Currently, the capsule update driver uses the DFU framework for * the updates. This function gets the DFU alt number which is to - * be used as the Image Index + * be used for capsule update. * * Return: 0 if OK, -ve on error * */ -int fwu_get_image_index(u8 *image_index); +int fwu_get_dfu_alt_num(u8 image_index, u8 *alt_num); /** * fwu_revert_boot_index() - Revert the active index in the FWU metadata diff --git a/include/getopt.h b/include/getopt.h index 6f5811e..8645082 100644 --- a/include/getopt.h +++ b/include/getopt.h @@ -9,6 +9,8 @@ #ifndef __GETOPT_H #define __GETOPT_H +#include <stdbool.h> + /** * struct getopt_state - Saved state across getopt() calls */ diff --git a/include/hwspinlock.h b/include/hwspinlock.h index d8556c0..dd51354 100644 --- a/include/hwspinlock.h +++ b/include/hwspinlock.h @@ -6,6 +6,8 @@ #ifndef _HWSPINLOCK_H_ #define _HWSPINLOCK_H_ +#include <linux/errno.h> + /** * Implement a hwspinlock uclass. * Hardware spinlocks are used to perform hardware protection of diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h index 32dcb03..cba991e 100644 --- a/include/i2c_eeprom.h +++ b/include/i2c_eeprom.h @@ -6,6 +6,8 @@ #ifndef __I2C_EEPROM #define __I2C_EEPROM +#include <linux/errno.h> + struct udevice; struct i2c_eeprom_ops { diff --git a/include/image.h b/include/image.h index 2e3cf83..21de70f 100644 --- a/include/image.h +++ b/include/image.h @@ -612,41 +612,86 @@ int boot_get_setup(struct bootm_headers *images, uint8_t arch, ulong *setup_star #define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */ #define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */ -ulong genimg_get_kernel_addr_fit(char * const img_addr, - const char **fit_uname_config, - const char **fit_uname_kernel); +/** + * genimg_get_kernel_addr_fit() - Parse FIT specifier + * + * Get the real kernel start address from a string which is normally the first + * argv of bootm/bootz + * + * These cases are dealt with, based on the value of @img_addr: + * NULL: Returns image_load_addr, does not set last two args + * "<addr>": Returns address + * + * For FIT: + * "[<addr>]#<conf>": Returns address (or image_load_addr), + * sets fit_uname_config to config name + * "[<addr>]:<subimage>": Returns address (or image_load_addr) and sets + * fit_uname_kernel to the subimage name + * + * @img_addr: a string might contain real image address (or NULL) + * @fit_uname_config: Returns configuration unit name + * @fit_uname_kernel: Returns subimage name + * + * Returns: kernel start address + */ +ulong genimg_get_kernel_addr_fit(const char *const img_addr, + const char **fit_uname_config, + const char **fit_uname_kernel); + ulong genimg_get_kernel_addr(char * const img_addr); int genimg_get_format(const void *img_addr); int genimg_has_config(struct bootm_headers *images); -int boot_get_fpga(int argc, char *const argv[], struct bootm_headers *images, - uint8_t arch, const ulong *ld_start, ulong * const ld_len); -int boot_get_ramdisk(int argc, char *const argv[], struct bootm_headers *images, - uint8_t arch, ulong *rd_start, ulong *rd_end); +/** + * boot_get_fpga() - Locate the FPGA image + * + * @images: Information about images being loaded + * Return 0 if OK, non-zero on failure + */ +int boot_get_fpga(struct bootm_headers *images); + +/** + * boot_get_ramdisk() - Locate the ramdisk + * + * @select: address or name of ramdisk to use, or NULL for default + * @images: pointer to the bootm images structure + * @arch: expected ramdisk architecture + * @rd_start: pointer to a ulong variable, will hold ramdisk start address + * @rd_end: pointer to a ulong variable, will hold ramdisk end + * + * boot_get_ramdisk() is responsible for finding a valid ramdisk image. + * Currently supported are the following ramdisk sources: + * - multicomponent kernel/ramdisk image, + * - commandline provided address of decicated ramdisk image. + * + * returns: + * 0, if ramdisk image was found and valid, or skiped + * rd_start and rd_end are set to ramdisk start/end addresses if + * ramdisk image is found and valid + * + * 1, if ramdisk image is found but corrupted, or invalid + * rd_start and rd_end are set to 0 if no ramdisk exists + */ +int boot_get_ramdisk(char const *select, struct bootm_headers *images, + uint arch, ulong *rd_start, ulong *rd_end); /** - * boot_get_loadable - routine to load a list of binaries to memory - * @argc: Ignored Argument - * @argv: Ignored Argument + * boot_get_loadable() - load a list of binaries to memory + * * @images: pointer to the bootm images structure - * @arch: expected architecture for the image - * @ld_start: Ignored Argument - * @ld_len: Ignored Argument * - * boot_get_loadable() will take the given FIT configuration, and look - * for a field named "loadables". Loadables, is a list of elements in - * the FIT given as strings. exe: + * Takes the given FIT configuration, then looks for a field named + * "loadables", a list of elements in the FIT given as strings, e.g.: * loadables = "linux_kernel", "fdt-2"; - * this function will attempt to parse each string, and load the - * corresponding element from the FIT into memory. Once placed, - * no aditional actions are taken. * - * @return: + * Each string is parsed, loading the corresponding element from the FIT into + * memory. Once placed, no additional actions are taken. + * + * Return: * 0, if only valid images or no images are found * error code, if an error occurs during fit_image_load */ -int boot_get_loadable(int argc, char *const argv[], struct bootm_headers *images, - uint8_t arch, const ulong *ld_start, ulong *const ld_len); +int boot_get_loadable(struct bootm_headers *images); int boot_get_setup_fit(struct bootm_headers *images, uint8_t arch, ulong *setup_start, ulong *setup_len); @@ -705,7 +750,13 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr, * @param load_op Decribes what to do with the load address * @param datap Returns address of loaded image * @param lenp Returns length of loaded image - * Return: node offset of image, or -ve error code on error + * Return: node offset of image, or -ve error code on error: + * -ENOEXEC - unsupported architecture + * -ENOENT - could not find image / subimage + * -EACCES - hash, signature or decryptions failure + * -EBADF - invalid OS or image type, or cannot get image load-address + * -EXDEV - memory overwritten / overlap + * -NOEXEC - image decompression error, or invalid FDT */ int fit_image_load(struct bootm_headers *images, ulong addr, const char **fit_unamep, const char **fit_uname_configp, @@ -756,9 +807,33 @@ int image_locate_script(void *buf, int size, const char *fit_uname, int fit_get_node_from_config(struct bootm_headers *images, const char *prop_name, ulong addr); -int boot_get_fdt(int flag, int argc, char *const argv[], uint8_t arch, - struct bootm_headers *images, - char **of_flat_tree, ulong *of_size); +/** + * boot_get_fdt() - locate FDT devicetree to use for booting + * + * @buf: Pointer to image + * @select: FDT to select (this is normally argv[2] of the bootm command) + * @arch: architecture (IH_ARCH_...) + * @images: pointer to the bootm images structure + * @of_flat_tree: pointer to a char* variable, will hold fdt start address + * @of_size: pointer to a ulong variable, will hold fdt length + * + * boot_get_fdt() is responsible for finding a valid flat device tree image. + * Currently supported are the following FDT sources: + * - multicomponent kernel/ramdisk/FDT image, + * - commandline provided address of decicated FDT image. + * + * Return: + * 0, if fdt image was found and valid, or skipped + * of_flat_tree and of_size are set to fdt start address and length if + * fdt image is found and valid + * + * 1, if fdt image is found but corrupted + * of_flat_tree and of_size are set to 0 if no fdt exists + */ +int boot_get_fdt(void *buf, const char *select, uint arch, + struct bootm_headers *images, char **of_flat_tree, + ulong *of_size); + void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob); int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size); @@ -936,7 +1011,7 @@ int image_decomp_type(const unsigned char *buf, ulong len); * @load: Destination load address in U-Boot memory * @image_start Image start address (where we are decompressing from) * @type: OS type (IH_OS_...) - * @load_bug: Place to decompress to + * @load_buf: Place to decompress to * @image_buf: Address to decompress from * @image_len: Number of bytes in @image_buf to decompress * @unc_len: Available space for decompression @@ -953,12 +1028,11 @@ int image_decomp(int comp, ulong load, ulong image_start, int type, * * @images: Images information * @blob: FDT to update - * @of_size: Size of the FDT * @lmb: Points to logical memory block structure * Return: 0 if ok, <0 on failure */ int image_setup_libfdt(struct bootm_headers *images, void *blob, - int of_size, struct lmb *lmb); + struct lmb *lmb); /** * Set up the FDT to use for booting a kernel @@ -1391,7 +1465,7 @@ int calculate_hash(const void *data, int data_len, const char *algo, * device */ #if defined(USE_HOSTCC) -# if defined(CONFIG_FIT_SIGNATURE) +# if CONFIG_IS_ENABLED(FIT_SIGNATURE) # define IMAGE_ENABLE_SIGN 1 # define FIT_IMAGE_ENABLE_VERIFY 1 # include <openssl/evp.h> diff --git a/include/init.h b/include/init.h index d57a24f..9a1951d 100644 --- a/include/init.h +++ b/include/init.h @@ -292,6 +292,17 @@ int misc_init_r(void); /* common/board_info.c */ int checkboard(void); + +/** + * show_board_info() - Show board information + * + * Check sysinfo for board information. Failing that if the root node of the DTB + * has a "model" property, show it. + * + * Then call checkboard(). + * + * Return 0 if OK, -ve on error + */ int show_board_info(void); /** diff --git a/include/iommu.h b/include/iommu.h index cf9719c..b8ba0b8 100644 --- a/include/iommu.h +++ b/include/iommu.h @@ -5,6 +5,15 @@ struct udevice; struct iommu_ops { /** + * init() - Connect a device to it's IOMMU, called before probe() + * The iommu device can be fetched through dev->iommu + * + * @iommu_dev: IOMMU device + * @dev: Device to connect + * @return 0 if OK, -errno on error + */ + int (*connect)(struct udevice *dev); + /** * map() - map DMA memory * * @dev: device for which to map DMA memory diff --git a/include/led.h b/include/led.h index 3290410..a635316 100644 --- a/include/led.h +++ b/include/led.h @@ -110,4 +110,12 @@ enum led_state_t led_get_state(struct udevice *dev); */ int led_set_period(struct udevice *dev, int period_ms); +/** + * led_bind_generic() - bind children of parent to given driver + * + * @parent: Top-level LED device + * @driver_name: Driver for handling individual child nodes + */ +int led_bind_generic(struct udevice *parent, const char *driver_name); + #endif diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 45307f5..a692f5d 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -11,6 +11,8 @@ #ifndef __IMMAP_QE_H__ #define __IMMAP_QE_H__ +#include <config.h> + #ifdef CONFIG_MPC83xx #if defined(CONFIG_ARCH_MPC8360) #define QE_MURAM_SIZE 0xc000UL diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 2861b73..d1dbf3e 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -136,14 +136,6 @@ #define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */ -#define SPINOR_OP_RDAR 0x65 /* Read any register */ -#define SPINOR_OP_WRAR 0x71 /* Write any register */ -#define SPINOR_REG_ADDR_STR1V 0x00800000 -#define SPINOR_REG_ADDR_CFR1V 0x00800002 -#define SPINOR_REG_ADDR_CFR3V 0x00800004 -#define SPINOR_REG_ADDR_ARCFN 0x00000006 -#define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */ -#define CFR3V_PGMBUF BIT(4) /* Program buffer size */ /* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */ @@ -188,8 +180,12 @@ /* For Cypress flash. */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ -#define SPINOR_OP_S28_SE_4K 0x21 +#define SPINOR_OP_CYPRESS_CLPEF 0x82 /* Clear P/E err flag */ +#define SPINOR_REG_CYPRESS_ARCFN 0x00000006 +#define SPINOR_REG_CYPRESS_STR1V 0x00800000 +#define SPINOR_REG_CYPRESS_CFR1V 0x00800002 #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0) #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6d68514..6f479fa 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -250,6 +250,7 @@ extern const struct spinand_manufacturer micron_spinand_manufacturer; extern const struct spinand_manufacturer paragon_spinand_manufacturer; extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; +extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants diff --git a/include/mapmem.h b/include/mapmem.h index 2134c80..f496c96 100644 --- a/include/mapmem.h +++ b/include/mapmem.h @@ -13,6 +13,8 @@ # ifdef CONFIG_ARCH_MAP_SYSMEM #include <asm/io.h> # else +#include <linux/types.h> + static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) { return (void *)(uintptr_t)paddr; @@ -26,6 +28,24 @@ static inline phys_addr_t map_to_sysmem(const void *ptr) { return (phys_addr_t)(uintptr_t)ptr; } + +/** + * nomap_sysmem() - pass through an address unchanged + * + * This is used to indicate an address which should NOT be mapped, e.g. in + * SMBIOS tables. Using this function instead of a case shows that the sandbox + * conversion has been done + */ +static inline void *nomap_sysmem(phys_addr_t paddr, unsigned long len) +{ + return (void *)(uintptr_t)paddr; +} + +static inline phys_addr_t nomap_to_sysmem(const void *ptr) +{ + return (phys_addr_t)(uintptr_t)ptr; +} + # endif #endif /* __MAPMEM_H */ diff --git a/include/memalign.h b/include/memalign.h index f67f0a7..eaa9f6b 100644 --- a/include/memalign.h +++ b/include/memalign.h @@ -11,6 +11,7 @@ * is used to align DMA buffers. */ #ifndef __ASSEMBLY__ +#include <linux/kernel.h> #include <asm/cache.h> #include <malloc.h> diff --git a/include/membuff.h b/include/membuff.h index 21051b0..4eba626 100644 --- a/include/membuff.h +++ b/include/membuff.h @@ -192,10 +192,11 @@ int membuff_free(struct membuff *mb); * @mb: membuff to adjust * @str: Place to put the line * @maxlen: Maximum line length (excluding terminator) + * @must_fit: If true then str is empty if line doesn't fit * Return: number of bytes read (including terminator) if a line has been - * read, 0 if nothing was there + * read, 0 if nothing was there or line didn't fit when must_fit is set */ -int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch); +int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool must_fit); /** * membuff_extend_by() - expand a membuff diff --git a/include/net/wget.h b/include/net/wget.h index da0920d..6714f7e 100644 --- a/include/net/wget.h +++ b/include/net/wget.h @@ -17,6 +17,5 @@ enum wget_state { }; #define DEBUG_WGET 0 /* Set to 1 for debug messages */ -#define SERVER_PORT 80 #define WGET_RETRY_COUNT 30 #define WGET_TIMEOUT 2000UL diff --git a/include/net6.h b/include/net6.h index 1e766aa..1ed989e 100644 --- a/include/net6.h +++ b/include/net6.h @@ -12,6 +12,7 @@ #include <net.h> #include <linux/ctype.h> +#include <linux/errno.h> /* struct in6_addr - 128 bits long IPv6 address */ struct in6_addr { diff --git a/include/nvmem.h b/include/nvmem.h index 822e698..e6a8a98 100644 --- a/include/nvmem.h +++ b/include/nvmem.h @@ -6,6 +6,8 @@ #ifndef NVMEM_H #define NVMEM_H +#include <linux/errno.h> + /** * DOC: Design * diff --git a/include/part.h b/include/part.h index db34bc6..32ee404 100644 --- a/include/part.h +++ b/include/part.h @@ -685,8 +685,8 @@ int part_get_type_by_name(const char *name); /** * part_get_bootable() - Find the first bootable partition * - * @desc: Block-device descriptor - * @return first bootable partition, or 0 if there is none + * @desc: Block-device descriptor + * Return: first bootable partition, or 0 if there is none */ int part_get_bootable(struct blk_desc *desc); diff --git a/include/pci.h b/include/pci.h index 2f5eb30..aad2337 100644 --- a/include/pci.h +++ b/include/pci.h @@ -1354,6 +1354,7 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, size_t len, * type 1 functions. * Can also be used on type 0 functions that support Enhanced Allocation for * 32b/64b BARs. Note that duplicate BEI entries are not supported. + * Can also be used on 64b bars on type 0 functions. * * @dev: Device to check * @bar: Bar register offset (PCI_BASE_ADDRESS_...) diff --git a/include/pci_ids.h b/include/pci_ids.h index 88b0a64..b63bf45 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1363,6 +1363,13 @@ #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6 +/* Per https://www.qemu.org/docs/master/specs/pci-ids.html */ +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007 +#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d +#define PCI_DEVICE_ID_REDHAT_NVME 0x0010 +#define PCI_DEVICE_ID_REDHAT_UFS 0x0013 + #define PCI_VENDOR_ID_INIT 0x1101 #define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */ diff --git a/include/power-domain.h b/include/power-domain.h index 2ff6c77..1852507 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -6,6 +6,8 @@ #ifndef _POWER_DOMAIN_H #define _POWER_DOMAIN_H +#include <linux/errno.h> + /** * A power domain is a portion of an SoC or chip that is powered by a * switchable source of power. In many cases, software has control over the diff --git a/include/power/max77663.h b/include/power/max77663.h index b3ae3da..fcb5916 100644 --- a/include/power/max77663.h +++ b/include/power/max77663.h @@ -13,6 +13,7 @@ #define MAX77663_LDO_DRIVER "max77663_ldo" #define MAX77663_SD_DRIVER "max77663_sd" #define MAX77663_RST_DRIVER "max77663_rst" +#define MAX77663_GPIO_DRIVER "max77663_gpio" /* Step-Down (SD) Regulator calculations */ #define SD_STATUS_MASK 0x30 diff --git a/include/power/palmas.h b/include/power/palmas.h index 0a61205..94c99dd 100644 --- a/include/power/palmas.h +++ b/include/power/palmas.h @@ -15,6 +15,7 @@ struct palmas_priv { #define PALMAS_LDO_DRIVER "palmas_ldo" #define PALMAS_SMPS_DRIVER "palmas_smps" #define PALMAS_RST_DRIVER "palmas_rst" +#define PALMAS_GPIO_DRIVER "palmas_gpio" #define PALMAS_SMPS_VOLT_MASK 0x7F #define PALMAS_SMPS_RANGE_MASK 0x80 @@ -35,3 +36,14 @@ struct palmas_priv { #define DEV_OFF 0x00 #define PALMAS_INT3_MASK 0x1B #define MASK_VBUS BIT(7) + +/* second chip */ +#define PALMAS_GPIO_DATA_IN 0x80 +#define PALMAS_GPIO_DATA_DIR 0x81 +#define PALMAS_GPIO_DATA_OUT 0x82 +#define PALMAS_GPIO_DEBOUNCE_EN 0x83 +#define PALMAS_GPIO_CLEAR_DATA_OUT 0x84 +#define PALMAS_GPIO_SET_DATA_OUT 0x85 +#define PALMAS_PU_PD_GPIO_CTRL1 0x86 +#define PALMAS_PU_PD_GPIO_CTRL2 0x87 +#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x88 diff --git a/include/power/regulator.h b/include/power/regulator.h index 200652c..bb07a81 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -7,6 +7,8 @@ #ifndef _INCLUDE_REGULATOR_H_ #define _INCLUDE_REGULATOR_H_ +#include <linux/errno.h> + struct udevice; /** diff --git a/include/remoteproc.h b/include/remoteproc.h index a11dc8a..91a8879 100644 --- a/include/remoteproc.h +++ b/include/remoteproc.h @@ -14,6 +14,7 @@ * platforms have moved to dm/fdt. */ #include <dm/platdata.h> /* For platform data support - non dt world */ +#include <linux/errno.h> /** * struct fw_rsc_hdr - firmware resource entry header diff --git a/include/rtc.h b/include/rtc.h index b6fdbb6..22f6d37 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -16,6 +16,7 @@ #include <bcd.h> #include <rtc_def.h> #include <linux/errno.h> +#include <linux/types.h> typedef int64_t time64_t; struct udevice; diff --git a/include/smbios.h b/include/smbios.h index c9df270..e2b7f69 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -8,11 +8,11 @@ #ifndef _SMBIOS_H_ #define _SMBIOS_H_ -#include <dm/ofnode.h> +#include <linux/types.h> /* SMBIOS spec version implemented */ #define SMBIOS_MAJOR_VER 3 -#define SMBIOS_MINOR_VER 0 +#define SMBIOS_MINOR_VER 7 enum { SMBIOS_STR_MAX = 64, /* Maximum length allowed for a string */ @@ -54,6 +54,32 @@ struct __packed smbios_entry { u8 bcd_rev; }; +/** + * struct smbios3_entry - SMBIOS 3.0 (64-bit) Entry Point structure + */ +struct __packed smbios3_entry { + /** @anchor: anchor string */ + u8 anchor[5]; + /** @checksum: checksum of the entry point structure */ + u8 checksum; + /** @length: length of the entry point structure */ + u8 length; + /** @major_ver: major version of the SMBIOS specification */ + u8 major_ver; + /** @minor_ver: minor version of the SMBIOS specification */ + u8 minor_ver; + /** @docrev: revision of the SMBIOS specification */ + u8 doc_rev; + /** @entry_point_rev: revision of the entry point structure */ + u8 entry_point_rev; + /** @reserved: reserved */ + u8 reserved; + /** maximum size of SMBIOS table */ + u32 max_struct_size; + /** @struct_table_address: 64-bit physical starting address */ + u64 struct_table_address; +}; + /* BIOS characteristics */ #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) @@ -113,6 +139,7 @@ struct __packed smbios_type2 { u8 chassis_location; u16 chassis_handle; u8 board_type; + u8 number_contained_objects; char eos[SMBIOS_STRUCT_EOS_BYTES]; }; @@ -228,12 +255,13 @@ static inline void fill_smbios_header(void *table, int type, * * This writes SMBIOS table at a given address. * - * @addr: start address to write SMBIOS table. If this is not - * 16-byte-aligned then it will be aligned before the table is - * written. + * @addr: start address to write SMBIOS table, 16-byte-alignment + * recommended. Note that while the SMBIOS tables themself have no alignment + * requirement, some systems may requires alignment. For example x86 systems + * which put tables at f0000 require 16-byte alignment + * * Return: end address of SMBIOS table (and start address for next entry) * or NULL in case of an error - * */ ulong write_smbios_table(ulong addr); @@ -299,10 +327,10 @@ int smbios_update_version_full(void *smbios_tab, const char *version); * This function clear the device dependent parameters such as * serial number for the measurement. * - * @entry: pointer to a struct smbios_entry + * @entry: pointer to a struct smbios3_entry * @header: pointer to a struct smbios_header */ -void smbios_prepare_measurement(const struct smbios_entry *entry, +void smbios_prepare_measurement(const struct smbios3_entry *entry, struct smbios_header *header); #endif /* _SMBIOS_H_ */ diff --git a/include/soc.h b/include/soc.h index 850db28..b8cfc50 100644 --- a/include/soc.h +++ b/include/soc.h @@ -7,6 +7,8 @@ #ifndef __SOC_H #define __SOC_H +#include <linux/errno.h> + #define SOC_MAX_STR_SIZE 128 struct udevice; diff --git a/include/spi-mem.h b/include/spi-mem.h index b07cf2e..3c8e95b 100644 --- a/include/spi-mem.h +++ b/include/spi-mem.h @@ -11,6 +11,8 @@ #ifndef __UBOOT_SPI_MEM_H #define __UBOOT_SPI_MEM_H +#include <linux/errno.h> + struct udevice; #define SPI_MEM_OP_CMD(__opcode, __buswidth) \ diff --git a/include/sysinfo.h b/include/sysinfo.h index b140d74..524c7d6 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -7,6 +7,8 @@ #ifndef __SYSINFO_H__ #define __SYSINFO_H__ +#include <linux/errno.h> + struct udevice; /* @@ -46,6 +48,9 @@ enum sysinfo_id { /* For show_board_info() */ SYSINFO_ID_BOARD_MODEL, + SYSINFO_ID_BOARD_MANUFACTURER, + SYSINFO_ID_PRIOR_STAGE_VERSION, + SYSINFO_ID_PRIOR_STAGE_DATE, /* First value available for downstream/board used */ SYSINFO_ID_USER = 0x1000, diff --git a/include/system-constants.h b/include/system-constants.h index d688629..e09fc41 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -3,6 +3,8 @@ #ifndef __SYSTEM_CONSTANTS_H__ #define __SYSTEM_CONSTANTS_H__ +#include <config.h> + /* * The most common case for our initial stack pointer address is to * say that we have defined a static intiial ram address location and diff --git a/include/tables_csum.h b/include/tables_csum.h index 4812333..9207e85 100644 --- a/include/tables_csum.h +++ b/include/tables_csum.h @@ -17,6 +17,6 @@ * @len: configuration table size * @return: the 8-bit checksum */ -u8 table_compute_checksum(void *v, int len); +u8 table_compute_checksum(const void *v, const int len); #endif diff --git a/include/test/cmd.h b/include/test/cmd.h new file mode 100644 index 0000000..c200570 --- /dev/null +++ b/include/test/cmd.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __TEST_CMD_H__ +#define __TEST_CMD_H__ + +#include <test/test.h> + +/* Declare a new command test */ +#define CMD_TEST(_name, _flags) UNIT_TEST(_name, _flags, cmd_test) + +#endif /* __TEST_CMD_H__ */ diff --git a/include/test/hush.h b/include/test/hush.h new file mode 100644 index 0000000..cca6654 --- /dev/null +++ b/include/test/hush.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2021 + * Francis Laniel, Amarula Solutions, francis.laniel@amarulasolutions.com + */ + +#ifndef __TEST_HUSH_H__ +#define __TEST_HUSH_H__ + +#include <test/test.h> + +/* Declare a new environment test */ +#define HUSH_TEST(_name, _flags) UNIT_TEST(_name, _flags, hush_test) + +#endif /* __TEST_HUSH_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h index ad4fc92..365d5f2 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -34,6 +34,7 @@ int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_bloblist(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_common(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_compression(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); @@ -42,6 +43,7 @@ int do_ut_env(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_exit(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_font(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_hush(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_lib(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_log(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); diff --git a/include/test/ut.h b/include/test/ut.h index ea6ee95..d3172af 100644 --- a/include/test/ut.h +++ b/include/test/ut.h @@ -98,6 +98,23 @@ int ut_check_skipline(struct unit_test_state *uts); int ut_check_skip_to_line(struct unit_test_state *uts, const char *fmt, ...); /** + * ut_check_skip_to_linen() - skip output until a partial line is found + * + * This creates a string and then checks it against the following lines of + * console output obtained with console_record_readline() until it is found. + * Only the characters up to the length of the string are checked, so the line + * may extend further + * + * After the function returns, uts->expect_str holds the expected string and + * uts->actual_str holds the actual string read from the console. + * + * @uts: Test state + * @fmt: printf() format string to look for, followed by args + * Return: 0 if OK, -ENOENT if not found, other value on error + */ +int ut_check_skip_to_linen(struct unit_test_state *uts, const char *fmt, ...); + +/** * ut_check_console_end() - Check there is no more console output * * After the function returns, uts->actual_str holds the actual string read @@ -359,6 +376,19 @@ int ut_check_console_dump(struct unit_test_state *uts, int total_bytes); __ret; \ }) +/* Assert that a following console output line matches */ +#define ut_assert_skip_to_linen(fmt, args...) ({ \ + int __ret = 0; \ + \ + if (ut_check_skip_to_linen(uts, fmt, ##args)) { \ + ut_failf(uts, __FILE__, __LINE__, __func__, \ + "console", "\nExpected '%s',\n got to '%s'", \ + uts->expect_str, uts->actual_str); \ + return CMD_RET_FAILURE; \ + } \ + __ret; \ +}) + /* Assert that there is no more console output */ #define ut_assert_console_end() ({ \ int __ret = 0; \ diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h index fd45e5f..2b1e19b 100644 --- a/include/tlv_eeprom.h +++ b/include/tlv_eeprom.h @@ -7,6 +7,8 @@ #ifndef __TLV_EEPROM_H_ #define __TLV_EEPROM_H_ +#include <linux/errno.h> + /* * The Definition of the TlvInfo EEPROM format can be found at onie.org or * github.com/onie diff --git a/include/u-boot/ecdsa.h b/include/u-boot/ecdsa.h index 6e0269e..53490c6 100644 --- a/include/u-boot/ecdsa.h +++ b/include/u-boot/ecdsa.h @@ -8,7 +8,6 @@ #include <errno.h> #include <image.h> -#include <linux/kconfig.h> /** * crypto_algo API impementation for ECDSA; diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 4a4ac10..04d16a2 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -901,6 +901,8 @@ union xhci_trb { /* TRB type IDs */ typedef enum { + /* reserved, used as a software sentinel */ + TRB_NONE = 0, /* bulk, interrupt, isoc scatter/gather, and control data stage */ TRB_NORMAL = 1, /* setup stage for control transfers */ |