diff options
Diffstat (limited to 'include/configs')
49 files changed, 2548 insertions, 266 deletions
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index a5bc773..90d3a8d 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -31,7 +31,8 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_EBONY 1 /* Board is ebony */ +#define CONFIG_CPCI440 1 /* Board is ebony */ +#define CONFIG_440GP 1 /* Specifc GP support */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 244e45a..bc23fc0 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -74,7 +74,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_AUTO_COMPLETE 1 +#define CONFIG_AUTO_COMPLETE 1 /* Define which ETH port will be used for connecting the network */ #define CFG_ETH_PORT ETH_0 diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index 7a1dada..ce969ec 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -527,7 +527,7 @@ PSDMR_LDOTOPRE_1C |\ PSDMR_WRC_1C |\ PSDMR_CL_2) - + /* * Init Memory Controller: * diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 7bbceb0..2ad6f06 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -200,7 +200,6 @@ /* Include auto complete with tabs */ #define CONFIG_AUTO_COMPLETE 1 -#define CFG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index b965571..465a4ec 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -268,7 +268,7 @@ /* Include auto complete with tabs */ #define CONFIG_AUTO_COMPLETE 1 -#define CFG_AUTO_COMPLETE 1 +#define CONFIG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 131c832..74a84f4 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -68,6 +68,10 @@ * The board, however, can run at 66MHz. In any event, this value * must match the settings of some switches. Details can be found * in the README.mpc85xxads. + * + * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to + * 33MHz to accommodate, based on a PCI pin. + * Note that PCI-X won't work at 33MHz. */ #ifndef CONFIG_SYS_CLK_FREQ @@ -293,12 +297,31 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8540@0" +#define OF_SOC "soc8540@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ @@ -312,9 +335,10 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) @@ -497,8 +521,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -506,13 +532,15 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 1af9231..418a3a3 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -179,12 +179,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* General PCI */ #define CFG_PCI_MEM_BASE 0x80000000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index c96b98b..db389cf 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -308,13 +308,29 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8541@0" +#define OF_SOC "soc8541@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI @@ -323,32 +339,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI) +#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -482,8 +493,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -491,7 +504,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4ca8bc3..7c4849f 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -314,13 +314,29 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8548@0" +#define OF_SOC "soc8548@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI @@ -329,32 +345,27 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -374,7 +385,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 +#undef CONFIG_MPC85XX_TSEC4 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC @@ -382,13 +393,11 @@ extern unsigned long get_clock_freq(void); #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 #define TSEC4_PHY_ADDR 3 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 -#define FEC_PHYIDX 0 /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" @@ -476,6 +485,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 @@ -498,8 +509,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" + #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -507,7 +521,9 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a44e3ec..4c8b4e7 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -308,13 +308,29 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8555@0" +#define OF_SOC "soc8555@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * General PCI @@ -323,33 +339,28 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_MPC85XX_PCI2 #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ @@ -482,8 +493,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=your.fdt.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -491,7 +504,8 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 2d5031b..835bf5c 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -290,12 +290,28 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8560@0" +#define OF_SOC "soc8560@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500" + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h new file mode 100644 index 0000000..246ac7f --- /dev/null +++ b/include/configs/MPC8641HPCN.h @@ -0,0 +1,634 @@ +/* + * Copyright 2006 Freescale Semiconductor. + * + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * MPC8641HPCN board configuration file + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#undef DEBUG + +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif + +#define CFG_RESET_ADDRESS 0xfff00100 + +/*#undef CONFIG_PCI*/ +#define CONFIG_PCI + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +/* #define CONFIG_DDR_INTERLEAVE 1 */ +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + + +#define CONFIG_ALTIVEC 1 + +/* + * L2CR setup -- make sure this is right for your board! + */ +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ + +#else + /* + * Manually set up DDR1 parameters + */ + + #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_1 0x39357322 + #define CFG_DDR_TIMING_2 0x14904cc8 + #define CFG_DDR_MODE_1 0x00480432 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_INTERVAL 0x06090100 + #define CFG_DDR_DATA_INIT 0xdeadbeef + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ + #define CFG_DDR_CONTROL2 0x04400000 + + /* Not used in fixed_sdram function */ + + #define CFG_DDR_MODE 0x00000022 + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ + #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ +#endif + +#define CFG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 + +/* + * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. + * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff + * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. + * However, when u-boot comes up, the flash_init needs hard start addresses + * to build its info table. For user convenience, the flash addresses is + * fe800000 and ff800000. That way, u-boot knows where the flash is + * and the user can download u-boot code from promjet to fef00000, a + * more intuitive location than fe700000. + * + * Note that, on switching the boot location, fef00000 becomes fff00000. + */ +#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ +#define CFG_FLASH_BASE2 0xff800000 + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} + +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ + +#define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ + +#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ + +#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ +#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ + + +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ + +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#if defined(CFG_RAMBOOT) +#undef CFG_FLASH_CFI_DRIVER +#undef CONFIG_SPD_EEPROM +#define CFG_SDRAM_SIZE 256 +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc8641@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 + +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +/* For RTL8139 */ +#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) +#define _IO_BASE 0x00000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#undef CFG_SCSI_SCAN_BUS_REVERSE + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_RTL8139 + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ + +#define CONFIG_MPC86XX_TSEC1 1 +#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" +#define CONFIG_MPC86XX_TSEC2 1 +#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" +#define CONFIG_MPC86XX_TSEC3 1 +#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" +#define CONFIG_MPC86XX_TSEC4 1 +#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 +#define TSEC4_PHY_ADDR 3 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CFG_IBAT0U CFG_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + * Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* + * BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + * Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* + * BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CGF_CMD_EXT2) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_IMLS \ + | CFG_CMD_FLASH \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_SCSI \ + | CFG_CMD_EXT2) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif +#endif + +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 192.168.1.100 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "dtbaddr=400000\0" \ + "dtbfile=mpc8641_hpcn.dtb\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=2" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h index da01186..4fb5440 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -193,12 +193,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 4d83487..87ab934 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -190,12 +190,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 0451b20..f8e3397 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -214,12 +214,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index be83b67..08674ca 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -37,7 +37,8 @@ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */ +/* On a Cameron or on a FO300 board or ... */ +#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300) #define CONFIG_STK52XX 1 /* ... on a STK52XX board */ #endif @@ -58,6 +59,20 @@ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#ifdef CONFIG_FO300 +#define CFG_DEVICE_NULLDEV 1 /* enable null device */ +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */ +#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ +#if 0 +#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ + /* switch is closed */ +#endif + +#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ + /* switch is open */ +#endif /* CONFIG_FO300 */ + #ifdef CONFIG_STK52XX #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ @@ -105,12 +120,18 @@ #define CONFIG_VIDEO_SM501_32BPP #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE + +#ifndef CONFIG_FO300 #define CONFIG_CONSOLE_EXTRA_INFO +#else +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN #define CFG_CONSOLE_IS_IN_ENV -#endif +#endif /* #ifndef CONFIG_TQM5200S */ #ifdef CONFIG_VIDEO #define ADD_BMP_CMD CFG_CMD_BMP @@ -124,7 +145,7 @@ #define CONFIG_ISO_PARTITION /* USB */ -#ifdef CONFIG_STK52XX +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) #define CONFIG_USB_OHCI #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE @@ -148,7 +169,7 @@ #endif /* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) +#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300) #define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) #else #define ADD_IDE_CMD 0 @@ -196,37 +217,19 @@ #undef CONFIG_BOOTARGS -#ifdef CONFIG_STK52XX -# if defined(CONFIG_TQM5200_B) -# if defined(CFG_LOWBOOT) -# define ENV_UPDT \ - "update=protect off FC000000 FC07FFFF;" \ - "erase FC000000 FC07FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC07FFFF\0" -# else /* highboot */ -# define ENV_UPDT \ - "update=protect off FFF00000 FFF7FFFF;" \ - "erase FFF00000 FFF7FFFF;" \ +#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT) +# define ENV_UPDT \ + "update=protect off FFF00000 +${filesize};" \ + "erase FFF00000 +${filesize};" \ "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 FFF7FFFF\0" -# endif /* CFG_LOWBOOT */ -# else /* !CONFIG_TQM5200_B */ -# define ENV_UPDT \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" -# endif /* CONFIG_TQM5200_B */ -#elif defined (CONFIG_CAM5200) + "protect on FFF00000 +${filesize}\0" +#else /* default lowboot configuration */ # define ENV_UPDT \ - "update=protect off FC000000 FC03FFFF;" \ - "erase FC000000 FC03FFFF;" \ + "update=protect off FC000000 +${filesize};" \ + "erase FC000000 +${filesize};" \ "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC03FFFF\0" -#else -# error "Unknown Carrier Board" -#endif /* CONFIG_STK52XX */ + "protect on FC000000 +${filesize}\0" +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -258,7 +261,7 @@ */ #define CFG_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200) /* * PCI Bus clocking configuration * @@ -322,13 +325,29 @@ */ #define CFG_FLASH_BASE 0xFC000000 +#ifndef CONFIG_CAM5200 /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#else /* CONFIG_CAM5200 */ +#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_WORD_SIZE unsigned int /* main flash device with */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2AA +#define CFG_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ +#define CFG_MAX_FLASH_SECT 128 +#endif /* ifndef CONFIG_CAM5200 */ + #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ #define CFG_FLASH_USE_BUFFER_WRITE 1 #if defined (CONFIG_CAM5200) @@ -339,9 +358,6 @@ # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) #endif -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ - /* Dynamic MTD partition support */ #define CONFIG_JFFS2_CMDLINE #define MTDIDS_DEFAULT "nor0=TQM5200-0" @@ -374,8 +390,13 @@ #elif defined (CONFIG_CAM5200) # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ "1792k(kernel)," \ - "3584k(small-fs)," \ + "5632k(rootfs)," \ + "24m(home)" +#elif defined (CONFIG_FO300) +# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ + "1408k(kernel)," \ "2m(initrd)," \ + "4m(small-fs)," \ "8m(misc)," \ "16m(big-fs)" #else @@ -387,7 +408,7 @@ */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ -#if defined(CONFIG_TQM5200_B) +#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) #define CFG_ENV_SECT_SIZE 0x40000 #else #define CFG_ENV_SECT_SIZE 0x20000 @@ -445,28 +466,43 @@ /* * GPIO configuration * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 + * use CS1: Bit 0 (mask: 0x80000000): + * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * SPI on PSC3 according to PSC3 setting. Use for CAM5200. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards and FO300 boards. Do not use + * with REV100 modules (because, there I2C1 is used as I2C bus). + * use ATA: Bits 6-7 (mask 0x03000000): + * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. + * Use for CAM5200 board. + * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. + * use PSC6: Bits 9-11 (mask 0x00700000): + * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as + * UART, CODEC or IrDA. + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to + * enable extended POST tests. + * Use for MINI-FAP and TQM5200_IB boards. + * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. + * Extended POST test is not available. + * Use for STK52xx, FO300 and CAM5200 boards. + * use PCI_DIS: Bit 16 (mask 0x00008000): + * 1 -> disable PCI controller (on CAM5200 board). + * use USB: Bits 18-19 (mask 0x00003000): + * 10 -> two UARTs (on FO300 and CAM5200). + * use PSC3: Bits 20-23 (mask: 0x00000f00): + * 0000 -> All PSC3 pins are GPIOs. + * 1100 -> UART/SPI (on FO300 board). + * 0100 -> UART (on CAM5200 board). + * use PSC2: Bits 25:27 (mask: 0x00000030): + * 000 -> All PSC2 pins are GPIOs. + * 100 -> UART (on CAM5200 board). + * 001 -> CAN1/2 on PSC2 pins. + * Use for REV100 STK52xx boards + * 01x -> Use AC97 (on FO300 board). + * use PSC1: Bits 29-31 (mask: 0x00000007): + * 100 -> UART (on all boards). */ #if defined (CONFIG_MINIFAP) # define CFG_GPS_PORT_CONFIG 0x91000004 @@ -480,6 +516,10 @@ # define CFG_GPS_PORT_CONFIG 0x91500004 # endif # endif +#elif defined (CONFIG_FO300) +# define CFG_GPS_PORT_CONFIG 0x91502c24 +#elif defined (CONFIG_CAM5200) +# define CFG_GPS_PORT_CONFIG 0x8050A444 #else /* TMQ5200 Inbetriebnahme-Board */ # define CFG_GPS_PORT_CONFIG 0x81000004 #endif @@ -502,6 +542,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " @@ -574,6 +615,16 @@ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ +#if defined(CONFIG_CAM5200) +#define CFG_CS4_START 0xB0000000 +#define CFG_CS4_SIZE 0x00010000 +#define CFG_CS4_CFG 0x01019C10 + +#define CFG_CS5_START 0xD0000000 +#define CFG_CS5_SIZE 0x01208000 +#define CFG_CS5_CFG 0x1414BF10 +#endif + #define CFG_RESET_ADDRESS 0xff000000 /*----------------------------------------------------------------------- diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index b1c70f8..247f705 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -123,9 +123,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 9f958f5..1461b5f 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -112,9 +112,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index 49c3872..ffd5c0b 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -237,6 +237,13 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index cec7e3e..4bbee97 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -353,6 +353,12 @@ extern int tqm834x_num_flash_banks; #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else @@ -422,9 +428,9 @@ extern int tqm834x_num_flash_banks; #define CFG_SICRL SICRL_LDP_A /* i-cache and d-cache disabled */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT -#define CFG_HID2 0x000000000 +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID2 HID2_HBE /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -437,12 +443,21 @@ extern int tqm834x_num_flash_banks; #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* PCI */ -#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#ifdef CONFIG_PCI +#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_IBAT5L (0) +#define CFG_IBAT5U (0) +#endif /* IMMRBAR */ #define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 16b2ce3..90ecbad 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -104,9 +104,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index bbc6960..b3f8f8d 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -102,9 +102,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 198db19..49aaeea 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -107,9 +107,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index e25a7a2..50df49e 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -141,9 +141,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 780f274..f45f3a2 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -186,18 +186,23 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 /* I2C RTC */ #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ @@ -424,7 +429,7 @@ #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -449,7 +454,7 @@ "run nfsargs addip addcons;bootm\0" \ "rootpath=/opt/eldk/ppc_85xx\0" \ "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE100000\0" \ + "ramdisk_addr=FE180000\0" \ "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 4a1a432..9be5db1 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 4b754ba..37f6c98 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -108,9 +108,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 1dc9f74..f03690a 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 3df060c..4959340 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -110,9 +110,8 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 8f9c2c9..148490b 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -151,11 +151,10 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index ede4e3b..d470ade 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -160,11 +160,10 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if 0 -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h new file mode 100644 index 0000000..458ebab --- /dev/null +++ b/include/configs/atstk1002.h @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * Configuration settings for the ATSTK1002 CPU daughterboard + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_ATSTK1002 1 +#define CONFIG_ATSTK1000 1 + +#define CONFIG_ATSTK1000_EXT_FLASH 1 + +/* + * Timer clock frequency. We're using the CPU-internal COUNT register + * for this, so this is equivalent to the CPU core clock frequency + */ +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL + * frequency and the peripherals to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 20000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 7 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CFG_USART1 1 + +#define CFG_CONSOLE_UART_DEV DEVICE_USART1 + +/* User serviceable stuff */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k" + +#define CONFIG_COMMANDS (CFG_CMD_BDI \ + | CFG_CMD_LOADS \ + | CFG_CMD_LOADB \ + /* | CFG_CMD_IMI */ \ + /* | CFG_CMD_CACHE */ \ + | CFG_CMD_FLASH \ + | CFG_CMD_MEMORY \ + /* | CFG_CMD_NET */ \ + | CFG_CMD_ENV \ + /* | CFG_CMD_IRQ */ \ + | CFG_CMD_BOOTD \ + | CFG_CMD_CONSOLE \ + /* | CFG_CMD_EEPROM */ \ + | CFG_CMD_ASKENV \ + | CFG_CMD_RUN \ + | CFG_CMD_ECHO \ + /* | CFG_CMD_I2C */ \ + | CFG_CMD_REGINFO \ + /* | CFG_CMD_DATE */ \ + /* | CFG_CMD_DHCP */ \ + /* | CFG_CMD_AUTOSCRIPT */ \ + /* | CFG_CMD_MII */ \ + | CFG_CMD_MISC \ + /* | CFG_CMD_SDRAM */ \ + /* | CFG_CMD_DIAG */ \ + /* | CFG_CMD_HWFLOW */ \ + /* | CFG_CMD_SAVES */ \ + /* | CFG_CMD_SPI */ \ + /* | CFG_CMD_PING */ \ + /* | CFG_CMD_MMC */ \ + /* | CFG_CMD_FAT */ \ + /* | CFG_CMD_IMLS */ \ + /* | CFG_CMD_ITEST */ \ + /* | CFG_CMD_EXT2 */ \ + ) + +#include <cmd_confdefs.h> + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +/* External flash on STK1000 */ +#if 0 +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#endif + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE 0x24000000 +#define CFG_INTRAM_SIZE 0x8000 + +#define CFG_SDRAM_BASE 0x10000000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (256*1024) +#define CFG_MALLOC_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + CFG_SDRAM_BASE + gd->sdram_size; \ + }) +#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) + +#define CFG_DMA_ALLOC_LEN (16384) +#define CFG_DMA_ALLOC_END (CFG_MALLOC_START) +#define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) +/* Allow 2MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "Uboot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 8 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START \ + ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) +#define CFG_MEMTEST_END \ + ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ + }) +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 2c1c319..4961011 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -73,6 +73,7 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ @@ -310,11 +311,11 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ - CFG_CMD_EEPROM | \ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -358,13 +359,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_CMDLINE_EDITING - -#ifdef CONFIG_CMDLINE_EDITING -#undef CONFIG_AUTO_COMPLETE -#else -#define CONFIG_AUTO_COMPLETE -#endif +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 4a79835..a66cdc3 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -200,8 +200,9 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index a26af69..d8882ea 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -143,7 +143,13 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -205,6 +211,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -243,8 +250,9 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h new file mode 100644 index 0000000..a77ccef --- /dev/null +++ b/include/configs/ep82xxm.h @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2006 Embedded Planet, LLC. + * + * U-Boot configuration for Embedded Planet EP82xxM boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MPC8260 +#define CPU_ID_STR "MPC8270" + +#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ + /* 256MB SDRAM / 64MB FLASH */ + +#undef DEBUG + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ + +#define CFG_BCSR 0xFA000000 + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#define CONFIG_NET_MULTI + +#define CONFIG_ETHER_ON_FCC2 +#define CONFIG_ETHER_ON_FCC3 + +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + +#define CFG_CPMFCR_RAMTYPE 0 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ + +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 0 /* Not used - implemented in BCSR */ +#define MDIO_ACTIVE (*(vu_char *)(CFG_BCSR + 8) &= 0xFB) +#define MDIO_TRISTATE (*(vu_char *)(CFG_BCSR + 8) |= 0x04) +#define MDIO_READ (*(vu_char *)(CFG_BCSR + 8) & 1) + +#define MDIO(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \ + else *(vu_char *)(CFG_BCSR + 8) &= 0xFE + +#define MDC(bit) if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \ + else *(vu_char *)(CFG_BCSR + 8) &= 0xFD + +#define MIIDELAY udelay(1) + + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_I2C \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_DATE \ + | CFG_CMD_DTT \ + | CFG_CMD_EEPROM \ + | CFG_CMD_PCI \ + | CFG_CMD_DIAG \ + ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_ETHADDR 00:10:EC:00:88:65 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:10:EC:80:88:65 +#define CONFIG_IPADDR 10.0.0.245 +#define CONFIG_HOSTNAME EP82xxM +#define CONFIG_SERVERIP 10.0.0.26 +#define CONFIG_GATEWAYIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_ENV_IN_OWN_SECT 1 +#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ +#endif + +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +/* EEPROM Configuration */ +#define CFG_EEPROM_SIZE 0x1000 +#define CFG_I2C_EEPROM_ADDR 0x54 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ +#define CFG_ENV_OFFSET 0x0 +#endif /* CFG_ENV_IS_IN_EEPROM */ + +/* RTC Configuration */ +#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ +#define CFG_I2C_RTC_ADDR 0x68 +#define CONFIG_M41T11_BASE_YEAR 1900 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 +#define CONFIG_DTT_SENSORS {0} +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/*----------------------------------------------------------------------- + * NVRAM Configuration + *----------------------------------------------------------------------- + */ +#define CFG_NVRAM_BASE_ADDR 0xFA080000 +#define CFG_NVRAM_SIZE (128*1024)-16 + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_BOOTDELAY 0 + +/* PCI Memory map (if different from default map */ +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) + + +/* PCIBR0 - for PCI IO*/ +#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ +#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ +/* PCIBR1 - prefetch and non-prefetch regions joined together */ +#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) + + +#define CFG_DIRECT_FLASH_TFTP + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS +#define CFG_JFFS2_FIRST_SECTOR 0 +#define CFG_JFFS2_LAST_SECTOR 62 +#define CFG_JFFS2_SORT_FRAGMENTS +#define CFG_JFFS_CUSTOM_PART +#endif /* CFG_CMD_JFFS2 */ + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ +#endif /* CFG_CMD_I2C */ + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */ + +#define CFG_DEFAULT_IMMR 0x00010000 +#define CFG_IMMR 0xF0000000 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + +/* Hard reset configuration word */ +#define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 + +#define CFG_HID2 0 + +#define CFG_SIUMCR 0x02610000 +#define CFG_SYPCR 0xFFFF0689 +#define CFG_BCR 0x8080E000 +#define CFG_SCCR 0x00000001 + +#define CFG_RMR 0 +#define CFG_TMCNTSC 0x000000C3 +#define CFG_PISCR 0x00000083 +#define CFG_RCCR 0 + +#define CFG_MPTPR 0x0A00 +#define CFG_PSDMR 0xC432246E +#define CFG_PSRT 0x32 + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) +#define CFG_SDRAM_OR 0xF0002900 + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) +#define CFG_OR0_PRELIM 0xFC000882 +#define CFG_BR4_PRELIM (CFG_BCSR | 0x00001001) +#define CFG_OR4_PRELIM 0xFFF00050 + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#endif /* __CONFIG_H */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 0335a00..0350e91 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -145,6 +145,13 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -215,6 +222,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -253,6 +261,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index ce33b85..0c935bf 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -37,12 +37,12 @@ #define CONFIG_MISC_INIT_R -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif /* @@ -51,16 +51,36 @@ * To select console on the one of 8 external UARTs, * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, * or as 5, 6, 7, or 8 for the second Quad UART. + * COM11, COM12, COM13, COM14 are located on the second Quad UART. * * CONFIG_PSC_CONSOLE must be undefined in this case. */ -/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */ +#if !defined(CONFIG_PRS200) +/* MCC200 configuration: */ +#ifdef CONFIG_CONSOLE_COM12 +#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ +#else +#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ +#endif +#else +/* PRS200 configuration: */ +#undef CONFIG_QUART_CONSOLE +#endif /* CONFIG_PRS200 */ /* * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 * and undefine CONFIG_QUART_CONSOLE. */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) +#if !defined(CONFIG_PRS200) +/* MCC200 configuration: */ +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ +#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ +#else +/* PRS200 configuration: */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#endif +#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \ + !defined(CONFIG_SERIAL_MULTI) #error "Select only one console device!" #endif #define CONFIG_BAUDRATE 115200 @@ -72,7 +92,7 @@ /* USB */ #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE /* @@ -98,33 +118,46 @@ #undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#ifdef CONFIG_PRS200 +# define CFG__BOARDNAME "prs200" +# define CFG__LINUX_CONSOLE "ttyS0" +#else +# define CFG__BOARDNAME "mcc200" +# define CFG__LINUX_CONSOLE "ttyEU7" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "hostname=mcc200\0" \ + "hostname=" CFG__BOARDNAME "\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ + "flash_self=run ramargs addip addcons;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addcons;bootm\0" \ + "console=" CFG__LINUX_CONSOLE "\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/mcc200/uImage\0" \ - "baudrate=115200\0" \ - "load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0" \ - "update=protect off FFF00000 +${filesize};" \ - "era FFF00000 +${filesize};" \ - "cp.b 200000 FFF00000 ${filesize}\0" \ - "serverip=192.168.1.1\0" \ - "ipaddr=192.168.133.144\0" \ - "netmask=255.255.0.0\0" \ + "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ + "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ + "text_base=" MK_STR(TEXT_BASE) "\0" \ + "update=protect off ${text_base} +${filesize};" \ + "era ${text_base} +${filesize};" \ + "cp.b 200000 ${text_base} ${filesize}\0" \ "unlock=yes\0" \ - "ethaddr=00:02:44:7D:73:3B\0" \ "" +#undef MK_STR +#undef XMK_STR #define CONFIG_BOOTCOMMAND "run flash_self" @@ -134,7 +167,7 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ /* * I2C configuration @@ -150,9 +183,9 @@ * TEXT base always at 0xFFF00000 * ENV_ADDR always at 0xFFF40000 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB + * 0xFE000000 for 32 MB + * 0xFF000000 for 16 MB + * 0xFF800000 for 8 MB */ #define CFG_FLASH_BASE 0xfc000000 #define CFG_FLASH_SIZE 0x04000000 @@ -174,9 +207,9 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -206,7 +239,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) # define CFG_RAMBOOT 1 #endif @@ -226,27 +259,45 @@ #define CONFIG_PHY_ADDR 1 /* + * LCD Splash Screen + */ +#if !defined(CONFIG_PRS200) +#define CONFIG_LCD 1 +#endif + +#if defined(CONFIG_LCD) +#define CONFIG_SPLASH_SCREEN 1 +#define CFG_CONSOLE_IS_IN_ENV 1 +#define LCD_BPP LCD_MONOCHROME +#endif + +/* * GPIO configuration */ /* 0x10000004 = 32MB SDRAM */ /* 0x90000004 = 64MB SDRAM */ +#if defined(CONFIG_LCD) +/* set PSC2 in UART mode */ +#define CFG_GPS_PORT_CONFIG 0x00000044 +#else #define CFG_GPS_PORT_CONFIG 0x00000004 +#endif /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ #define CFG_LOAD_ADDR 0x100000 /* default load address */ @@ -309,7 +360,7 @@ * One of four SC16C554 UARTs is selected with * A3-A4 (DA5-DA6) lines. */ -#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) +#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) #define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) #define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index a13d6a8..89e9164 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -158,7 +158,13 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -219,6 +225,9 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ @@ -226,6 +235,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -264,15 +274,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 50c1c4f..23bdfc8 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -63,6 +63,7 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (8 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 5a434dc..6e4fdb2 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -197,12 +197,16 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h new file mode 100644 index 0000000..1a460cd --- /dev/null +++ b/include/configs/sequoia.h @@ -0,0 +1,430 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * sequoia.h - configuration for Sequoia board (PowerPC440EPx) + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ +#ifndef CONFIG_RAINIER +#define CONFIG_SEQUOIA 1 /* Board is Sequoia */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#else +#define CONFIG_440GRX 1 /* Specific PPC440GRx */ +#endif +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 +#define CFG_BCSR_BASE 0xc0000000 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */ +#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ + +#ifdef CFG_ENV_IS_IN_NAND +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/sequoia/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=sequoia\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ + "bootfile=/tftpboot/sequoia/uImage\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 100000 FFFA0000 60000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* USB */ +#ifdef CONFIG_440EPX +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +#define CMD_USB CFG_CMD_USB +#else +#define CMD_USB 0 /* no USB on 440GRx */ +#endif /* CONFIG_440EPX */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DTT | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CMD_USB) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_NAND 0xD0000000 +#define CFG_CPLD 0xC0000000 + +/* + * On Sequoia CS0 and CS3 are switched when configuring for NAND booting + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03017300 +#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) +#else +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +/* Memory Bank 3 (NOR-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x03017300 +#define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND | 0x1c000) +#endif + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x24814580 +#define CFG_EBC_PB2CR (CFG_CPLD | 0x38000) + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index 3d907f8..4937638 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -261,6 +261,7 @@ #define CONFIG_MPC8220_FEC 1 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ #define CONFIG_PHY_ADDR 0x1F +#define CONFIG_MII 1 /* * Miscellaneous configurable options diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index e218597..625cf20 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -172,8 +172,11 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -183,6 +186,7 @@ /* I did the 'if 0' so we could keep the syntax above if ever needed. */ #undef CFG_I2C_NOPROBES #endif +#define CFG_I2C_OFFSET 0x3000 /* RapdIO Map configuration, mapped 1:1. */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h new file mode 100644 index 0000000..554a7a4 --- /dev/null +++ b/include/configs/v38b.h @@ -0,0 +1,343 @@ +/* + * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, + * wd@denx.de. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., 59 + * Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ +#define CONFIG_V38B 1 /* ...on V38B board */ +#define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ + +#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ +#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ + +#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ + +#define CONFIG_NETCONSOLE 1 + +#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ + +#define CFG_XLB_PIPELINING 1 /* gives better performance */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * DDR + */ +#define SDRAM_DDR 1 /* is DDR */ +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* + * PCI - no suport + */ +#undef CONFIG_PCI + +/* + * Partitions + */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 + +/* + * USB + */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_SDRAMi | \ + CFG_CMD_DATE | \ + CFG_CMD_USB | \ + CFG_CMD_FAT) + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Boot low with 16 MB Flash + */ +#define CFG_LOWBOOT 1 +#define CFG_LOWBOOT16 1 + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=run net_nfs\0" \ + "bootdelay=3\0" \ + "baudrate=115200\0" \ + "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ + "filesystem over NFS; echo\0" \ + "netdev=eth0\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "hostname=v38b\0" \ + "ethact=FEC ETHERNET\0" \ + "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ + "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ + "cp.b 200000 ff000000 $(filesize);" \ + "prot on ff000000 ff03ffff\0" \ + "load=tftp 200000 $(u-boot)\0" \ + "netmask=255.255.0.0\0" \ + "ipaddr=192.168.160.18\0" \ + "serverip=192.168.1.1\0" \ + "ethaddr=00:e0:ee:00:05:2e\0" \ + "bootfile=/tftpboot/v38b/uImage\0" \ + "u-boot=/tftpboot/v38b/u-boot.bin\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 + +/* + * RTC configuration + */ +#define CFG_I2C_RTC_ADDR 0x51 + +/* + * Flash configuration - use CFI driver + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x90001404 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/* + * IDE/ATA (supports IDE harddisk) + */ +#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +#define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ + +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */ + +#define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ + +#define CFG_ATA_STRIDE 4 /* Interval between registers */ + +/* + * Status LED + */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ + +#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ +#ifndef __ASSEMBLY__ +typedef unsigned int led_id_t; + +#define __led_toggle(_msk) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \ + } while(0) + +#define __led_set(_msk, _st) \ + do { \ + if ((_st)) \ + *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \ + else \ + *((volatile long *) (CFG_LED_BASE)) |= (_msk); \ + } while(0) + +#define __led_init(_msk, st) \ + do { \ + *((volatile long *) (CFG_LED_BASE)) |= 0x34; \ + } while(0) +#endif /* __ASSEMBLY__ */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 1171ee5..28abd6e 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -90,6 +90,11 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ @@ -97,6 +102,7 @@ CFG_CMD_DATE | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ @@ -156,16 +162,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* needed for NetConsole */ - /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- @@ -175,6 +177,13 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h index 7d55566..ba27f37 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/yellowstone.h @@ -65,6 +65,7 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (8 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ @@ -109,6 +110,8 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH @@ -229,6 +232,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -265,6 +269,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index a81cf34..3d7b4a2 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -65,6 +65,7 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (8 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ @@ -231,6 +232,7 @@ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ @@ -272,6 +274,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 0e58e7e..a6532b5 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -31,9 +31,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define DEBUG -#undef DEBUG - /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ @@ -63,17 +60,20 @@ #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ -#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */ - +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/ +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE + +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ -/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */ -/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */ -/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */ +#define CFG_PCIE0_CFGBASE 0xc0000000 +#define CFG_PCIE0_XCFGBASE 0xc0000400 +#define CFG_PCIE1_CFGBASE 0xc0001000 +#define CFG_PCIE1_XCFGBASE 0xc0001400 +#define CFG_PCIE2_CFGBASE 0xc0002000 +#define CFG_PCIE2_XCFGBASE 0xc0002400 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE @@ -220,6 +220,9 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -245,6 +248,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ @@ -292,6 +301,7 @@ */ /* Support for Intel 82557/82559/82559ER chips. */ #define CONFIG_EEPRO100 + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -506,8 +516,8 @@ #define FPGA_REG1C_PE1_WAKE 0x0040 #define FPGA_REG1C_PE2_WAKE 0x0020 #define FPGA_REG1C_PE0_PERST 0x0010 -#define FPGA_REG1C_PE1_PERST 0x0080 -#define FPGA_REG1C_PE2_PERST 0x0040 +#define FPGA_REG1C_PE1_PERST 0x0008 +#define FPGA_REG1C_PE2_PERST 0x0004 /*----------------------------------------------------------------------------+ | Defines |