diff options
Diffstat (limited to 'include/configs')
30 files changed, 0 insertions, 277 deletions
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 185f649..cd78836 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -175,9 +175,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ @@ -191,9 +188,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* 0xFFFF8396 */ #ifdef CONFIG_VSC7385_ENET @@ -201,9 +195,6 @@ /* VSC7385 Base address on CS2 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385_BASE */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) /* 0xFFFE09FF */ /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 40b0264..93b553c 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -219,14 +219,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -/* NAND */ -#define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - -/* FLASH */ -#define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM @@ -235,9 +227,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ @@ -247,9 +236,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 390ee4e..18e056e 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -188,14 +188,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -/* FLASH*/ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) - /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM @@ -204,9 +196,6 @@ #define CONFIG_SYS_BCSR_ADDR 0xFA000000 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ /* map at 0xFA000000 on LCS3 */ -/* BCSR */ -#define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ #ifdef CONFIG_VSC7385_ENET @@ -215,9 +204,6 @@ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 97b6641..708829d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -177,13 +177,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index fd884a1..c66e33a 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 41b0223..ed47bcd 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -133,9 +133,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Windows to access PIB via local bus @@ -163,17 +157,11 @@ * CS2 on Local Bus, to PIB */ -/* PIB1 */ -#define CONFIG_SYS_BR2_PRELIM (0xF8008000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * CS3 on Local Bus, to PIB */ -/* PIB2 */ -#define CONFIG_SYS_BR3_PRELIM (0xF8010000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 4cda158..3e0907d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -123,9 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -148,9 +145,6 @@ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 7f906c3..e401c29 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -123,10 +123,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -147,10 +143,6 @@ */ #define CONFIG_SYS_BCSR 0xE2400000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xE2400000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_15 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) - #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ @@ -192,10 +184,6 @@ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 */ -/* SDRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_SDRAM_XAM | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) | OR_SDRAM_EAD) - /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index e90d497..cc62fc3 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -211,9 +211,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * BRx, ORx, LBLAWBARx, and LBLAWARx */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_16MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Vitesse 7385 */ @@ -221,18 +218,12 @@ boards, we say we have two, but don't display a message if we find only one. */ #ifdef CONFIG_VSC7385_ENET -/* VSC7385 */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif #define CONFIG_SYS_LED_BASE 0xF9000000 -/* LED */ -#define CONFIG_SYS_BR2_PRELIM (0xF9000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Compact Flash */ @@ -240,9 +231,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_CF_BASE 0xF0000000 -/* CF */ -#define CONFIG_SYS_BR3_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_UPM_BI) #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e569e63..a244ae8 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -162,9 +162,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -178,9 +175,6 @@ */ #define CONFIG_SYS_BCSR 0xF8000000 /* Access window base at BCSR base */ -/* BCSR */ -#define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * NAND Flash on the Local Bus @@ -190,9 +184,6 @@ #define CONFIG_SYS_NAND_BASE 0xE0600000 -/* NAND */ -#define CONFIG_SYS_BR3_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR) /* * Serial Port diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c1898a5..006279a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -188,9 +188,6 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -204,9 +201,6 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR) /* Vitesse 7385 */ @@ -214,9 +208,6 @@ #ifdef CONFIG_VSC7385_ENET -/* VSC7385 */ -#define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c76df28..af03c03 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -76,9 +76,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0x80000000 | BR_MS_GPCM | BR_PS_32 | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_1GB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET) /* disable remaining mappings */ #define CONFIG_SYS_BR1_PRELIM 0x00000000 diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a7eb5f5..e9cfeae 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFFC00000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_4MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 3fe72db..9318e62 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -169,9 +169,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -185,9 +182,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 61f64eb..d86dda1 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,9 +142,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 @@ -163,9 +160,6 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST) /* * MRAM setup @@ -175,9 +169,6 @@ #define CONFIG_SYS_OR_TIMING_MRAM -/* MRAM */ -#define CONFIG_SYS_BR2_PRELIM (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET) /* * CPLD setup @@ -187,9 +178,6 @@ #define CONFIG_SYS_OR_TIMING_MRAM -/* CPLD */ -#define CONFIG_SYS_BR3_PRELIM (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET) /* * HW-Watchdog diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 5027073..ede8ae6 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,9 +108,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -120,9 +117,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -336,9 +330,6 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * BFTIC3 on the local bus CS4 @@ -346,9 +337,6 @@ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256 -/* BFTIC3 */ -#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 84516bb..728c9b1 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -93,9 +93,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -105,9 +102,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -316,8 +310,5 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -/* PAXE */ -#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 678cb6a..f39dbe0 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -351,16 +345,10 @@ * Configuration for C2 on the local bus */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) /* * Configuration for C3 on the local bus */ -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 3e2e425..19e4156 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index ed221e2..fe4763c 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -120,9 +120,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -132,9 +129,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -400,9 +394,6 @@ * */ -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) /* ethernet port connected to piggy (UEC2) */ #define CONFIG_HAS_ETH1 diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index c1ed71e..9302d35 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,12 +341,6 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_SCY_4 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #endif /* __CONFIG_H */ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 406b6e7..06c5923 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -112,9 +112,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -124,9 +121,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -389,13 +383,7 @@ * */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 31bf997..cb7dabd 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -179,9 +179,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFC000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_4 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -196,18 +193,12 @@ */ #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 -/* SJA1000 */ -#define CONFIG_SYS_BR1_PRELIM (0xFBFF0000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_SCY_5 | OR_GPCM_EHTR_SET) /* * CPLD on Local Bus */ #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 -/* CPLD */ -#define CONFIG_SYS_BR2_PRELIM (0xFBFF8000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | OR_GPCM_SCY_4 | OR_GPCM_EHTR_SET) /* * Serial Port diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 42a1e16..98770ca 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -98,9 +98,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ diff --git a/include/configs/strider.h b/include/configs/strider.h index 1519dad..dd89ee8 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -167,9 +167,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -183,9 +180,6 @@ #define CONFIG_SYS_FPGA0_BASE 0xE0600000 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ -/* FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE0600000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_1MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_SCY_5 | OR_GPCM_TRLX_CLEAR | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010 diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 6aacbc2..a65b61b 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,9 +110,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -122,9 +119,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -342,13 +336,7 @@ * */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_16 | BR_MS_UPMA | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index b11d496..6084e8a 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -345,8 +339,5 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) #endif /* __CONFIG_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 1bff837..86aec93 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -113,9 +113,6 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,9 +122,6 @@ * PRIO1/PIGGY on the local bus CS1 */ -/* KMBEC_FPGA */ -#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,13 +341,7 @@ * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) */ -/* APP1 */ -#define CONFIG_SYS_BR2_PRELIM (0xA0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR | OR_GPCM_EAD) -/* APP2 */ -#define CONFIG_SYS_BR3_PRELIM (0xB0000000 | BR_PS_8 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 3a5bcf9..4c5dad9 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -153,25 +153,13 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) -/* NAND */ -#define CONFIG_SYS_BR1_PRELIM (0x61000000 | BR_PS_8 | BR_DECC_CHK_GEN | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CHT | OR_FCM_SCY_2 | OR_FCM_RST | OR_FCM_TRLX) /* Still needed for spl_minimal.c */ #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM -/* NVRAM */ -#define CONFIG_SYS_BR2_PRELIM (0x60000000 | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_3 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) -/* SRAM */ -#define CONFIG_SYS_BR3_PRELIM (0x62000000 | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* * Serial Port diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index dd8aae5..9b9c1ff 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -70,15 +70,9 @@ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -/* FLASH */ -#define CONFIG_SYS_BR0_PRELIM (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 -/* WINDOW1 */ -#define CONFIG_SYS_BR1_PRELIM (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB | OR_GPCM_SETA) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ |