17 files changed, 1098 insertions, 251 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c8c6c60..14a14be 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -99,12 +99,16 @@ config LPC32XX_GPIO
 	help
 	  Support for the LPC32XX GPIO driver.
 
-config MSCC_BITBANG_SPI_GPIO
-	bool "Microsemi bitbang spi GPIO driver"
+config MSCC_SGPIO
+	bool "Microsemi Serial GPIO driver"
 	depends on DM_GPIO && SOC_VCOREIII
 	help
-	  Support controlling the GPIO used for SPI bitbang by software. Can
-	  be used by the VCoreIII SoCs, but it was mainly useful for Luton.
+	  Support for the VCoreIII SoC serial GPIO device. By using a
+          serial interface, the SIO controller significantly extends
+          the number of available GPIOs with a minimum number of
+          additional pins on the device. The primary purpose of the
+          SIO controller is to connect control signals from SFP
+          modules and to act as an LED controller.
 
 config MSM_GPIO
 	bool "Qualcomm GPIO driver"
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 61feda1..7c479ef 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,4 +59,4 @@ obj-$(CONFIG_MSM_GPIO)		+= msm_gpio.o
 obj-$(CONFIG_$(SPL_)PCF8575_GPIO)	+= pcf8575_gpio.o
 obj-$(CONFIG_PM8916_GPIO)	+= pm8916_gpio.o
 obj-$(CONFIG_MT7621_GPIO)	+= mt7621_gpio.o
-obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)	+= gpio-mscc-bitbang-spi.o
+obj-$(CONFIG_MSCC_SGPIO)	+= mscc_sgpio.o
diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c b/drivers/gpio/gpio-mscc-bitbang-spi.c
deleted file mode 100644
index b675f90..0000000
--- a/drivers/gpio/gpio-mscc-bitbang-spi.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Microsemi SoCs pinctrl driver
- *
- * Author: <gregory.clement@bootlin.com>
- * License: Dual MIT/GPL
- * Copyright (c) 2018 Microsemi Corporation
- */
-
-#include <common.h>
-#include <asm-generic/gpio.h>
-#include <asm/io.h>
-#include <dm.h>
-#include <errno.h>
-
-enum {
-	SDI,
-	CS0,
-	CS1,
-	CS2,
-	CS3,
-	SDO,
-	SCK
-};
-
-static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
-
-#define SW_SPI_CSn_OE	 0x1E	/* bits 1 to 4 */
-#define SW_SPI_CS0_OE	 BIT(1)
-#define SW_SPI_SDO_OE	 BIT(9)
-#define SW_SPI_SCK_OE	 BIT(11)
-#define SW_PIN_CTRL_MODE BIT(13)
-
-struct mscc_bb_spi_gpio {
-	void __iomem *regs;
-	u32 cache_val;
-};
-
-static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
-{
-	struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
-
-	if (val)
-		gpio->cache_val |= BIT(pinmap[oft]);
-	else
-		gpio->cache_val &= ~BIT(pinmap[oft]);
-
-	writel(gpio->cache_val, gpio->regs);
-
-	return 0;
-}
-
-static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
-					     int val)
-{
-	if (oft == 0) {
-		pr_err("SW_SPI_DSI can't be used as output\n");
-		return -ENOTSUPP;
-	}
-
-	mscc_bb_spi_gpio_set(dev, oft, val);
-
-	return 0;
-}
-
-static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
-{
-	return 0;
-}
-
-static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
-{
-	struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
-	u32 val = readl(gpio->regs);
-
-	return !!(val & BIT(pinmap[oft]));
-}
-
-static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
-	.direction_output	= mscc_bb_spi_gpio_direction_output,
-	.direction_input	= mscc_bb_spi_gpio_direction_input,
-	.set_value		= mscc_bb_spi_gpio_set,
-	.get_value		= mscc_bb_spi_gpio_get,
-};
-
-static int mscc_bb_spi_gpio_probe(struct udevice *dev)
-{
-	struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
-	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
-	gpio->regs = dev_remap_addr(dev);
-	if (!gpio->regs)
-		return -EINVAL;
-
-	uc_priv->bank_name = dev->name;
-	uc_priv->gpio_count = ARRAY_SIZE(pinmap);
-	/*
-	 * Enable software mode to control the SPI pin, enables the
-	 * output mode for most of the pin and initialize the cache
-	 * value in the same time
-	 */
-
-	gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
-	    SW_SPI_CS0_OE;
-	writel(gpio->cache_val, gpio->regs);
-
-	return 0;
-}
-
-static const struct udevice_id mscc_bb_spi_gpio_ids[] = {
-	{.compatible = "mscc,spi-bitbang-gpio"},
-	{}
-};
-
-U_BOOT_DRIVER(gpio_mscc_bb_spi) = {
-	.name	= "gpio-mscc-spi-bitbang",
-	.id	= UCLASS_GPIO,
-	.ops	= &mscc_bb_spi_gpio_ops,
-	.probe	= mscc_bb_spi_gpio_probe,
-	.of_match = of_match_ptr(mscc_bb_spi_gpio_ids),
-	.priv_auto_alloc_size = sizeof(struct mscc_bb_spi_gpio),
-};
diff --git a/drivers/gpio/mscc_sgpio.c b/drivers/gpio/mscc_sgpio.c
new file mode 100644
index 0000000..c899454
--- /dev/null
+++ b/drivers/gpio/mscc_sgpio.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs serial gpio driver
+ *
+ * Author: <lars.povlsen@microchip.com>
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <clk.h>
+
+#define MSCC_SGPIOS_PER_BANK	32
+#define MSCC_SGPIO_BANK_DEPTH	4
+
+enum {
+	REG_INPUT_DATA,
+	REG_PORT_CONFIG,
+	REG_PORT_ENABLE,
+	REG_SIO_CONFIG,
+	REG_SIO_CLOCK,
+	MAXREG
+};
+
+struct mscc_sgpio_bf {
+	u8 beg;
+	u8 end;
+};
+
+struct mscc_sgpio_props {
+	u8 regoff[MAXREG];
+	struct mscc_sgpio_bf auto_repeat;
+	struct mscc_sgpio_bf port_width;
+	struct mscc_sgpio_bf clk_freq;
+	struct mscc_sgpio_bf bit_source;
+};
+
+#define __M(bf)		GENMASK((bf).end, (bf).beg)
+#define __F(bf, x)	(__M(bf) & ((x) << (bf).beg))
+#define __X(bf, x)	(((x) >> (bf).beg) & GENMASK(((bf).end - (bf).beg), 0))
+
+#define MSCC_M_CFG_SIO_AUTO_REPEAT(p)		BIT(p->props->auto_repeat.beg)
+#define MSCC_F_CFG_SIO_PORT_WIDTH(p, x)		__F(p->props->port_width, x)
+#define MSCC_M_CFG_SIO_PORT_WIDTH(p)		__M(p->props->port_width)
+#define MSCC_F_CLOCK_SIO_CLK_FREQ(p, x)		__F(p->props->clk_freq, x)
+#define MSCC_M_CLOCK_SIO_CLK_FREQ(p)		__M(p->props->clk_freq)
+#define MSCC_F_PORT_CFG_BIT_SOURCE(p, x)	__F(p->props->bit_source, x)
+#define MSCC_X_PORT_CFG_BIT_SOURCE(p, x)	__X(p->props->bit_source, x)
+
+const struct mscc_sgpio_props props_luton = {
+	.regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
+	.auto_repeat = { 5, 5 },
+	.port_width  = { 2, 3 },
+	.clk_freq    = { 0, 11 },
+	.bit_source  = { 0, 11 },
+};
+
+const struct mscc_sgpio_props props_ocelot = {
+	.regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
+	.auto_repeat = { 10, 10 },
+	.port_width  = {  7, 8  },
+	.clk_freq    = {  8, 19 },
+	.bit_source  = { 12, 23 },
+};
+
+struct mscc_sgpio_priv {
+	u32 bitcount;
+	u32 ports;
+	u32 clock;
+	u32 mode[MSCC_SGPIOS_PER_BANK];
+	u32 __iomem *regs;
+	const struct mscc_sgpio_props *props;
+};
+
+static inline u32 sgpio_readl(struct mscc_sgpio_priv *priv, u32 rno, u32 off)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	return readl(reg);
+}
+
+static inline void sgpio_writel(struct mscc_sgpio_priv *priv,
+				u32 val, u32 rno, u32 off)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	writel(val, reg);
+}
+
+static void sgpio_clrsetbits(struct mscc_sgpio_priv *priv,
+			     u32 rno, u32 off, u32 clear, u32 set)
+{
+	u32 __iomem *reg = &priv->regs[priv->props->regoff[rno] + off];
+
+	clrsetbits_le32(reg, clear, set);
+}
+
+static int mscc_sgpio_direction_input(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+
+	priv->mode[port] |= BIT(bit);
+
+	return 0;
+}
+
+static int mscc_sgpio_direction_output(struct udevice *dev,
+				       unsigned int gpio, int value)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	u32 mask = 3 << (3 * bit);
+
+	debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
+	      port, bit, mask, value);
+
+	value = (value & 3) << (3 * bit);
+	sgpio_clrsetbits(priv, REG_PORT_CONFIG, port,
+			 MSCC_F_PORT_CFG_BIT_SOURCE(priv, mask),
+			 MSCC_F_PORT_CFG_BIT_SOURCE(priv, value));
+	clrbits_le32(&priv->mode[port], BIT(bit));
+
+	return 0;
+}
+
+static int mscc_sgpio_get_function(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	u32 val = priv->mode[port] & BIT(bit);
+
+	if (val)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static int mscc_sgpio_set_value(struct udevice *dev,
+				unsigned int gpio, int value)
+{
+	return mscc_sgpio_direction_output(dev, gpio, value);
+}
+
+static int mscc_sgpio_get_value(struct udevice *dev, unsigned int gpio)
+{
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	u32 port = gpio % MSCC_SGPIOS_PER_BANK;
+	u32 bit = gpio / MSCC_SGPIOS_PER_BANK;
+	int ret;
+
+	if (mscc_sgpio_get_function(dev, gpio) == GPIOF_INPUT) {
+		ret = !!(sgpio_readl(priv, REG_INPUT_DATA, bit) & BIT(port));
+	} else {
+		u32 portval = sgpio_readl(priv, REG_PORT_CONFIG, port);
+
+		ret = MSCC_X_PORT_CFG_BIT_SOURCE(priv, portval);
+		ret = !!(ret & (3 << (3 * bit)));
+	}
+
+	debug("get: gpio %d, port %d, bit %d, value %d\n",
+	      gpio, port, bit, ret);
+	return ret;
+}
+
+static int mscc_sgpio_get_count(struct udevice *dev)
+{
+	struct ofnode_phandle_args args;
+	int count = 0, i = 0, ret;
+
+	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3, i, &args);
+	while (ret != -ENOENT) {
+		count += args.args[2];
+		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
+						 ++i, &args);
+	}
+	return count;
+}
+
+static int mscc_sgpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mscc_sgpio_priv *priv = dev_get_priv(dev);
+	int err, div_clock = 0, port;
+	u32 val;
+	struct clk clk;
+
+	err = clk_get_by_index(dev, 0, &clk);
+	if (!err) {
+		err = clk_get_rate(&clk);
+		if (IS_ERR_VALUE(err)) {
+			dev_err(dev, "Invalid clk rate\n");
+			return -EINVAL;
+		}
+		div_clock = err;
+	} else {
+		dev_err(dev, "Failed to get clock\n");
+		return err;
+	}
+
+	priv->props = (const struct mscc_sgpio_props *)dev_get_driver_data(dev);
+	priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF);
+	priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency",
+					   12500000);
+	if (priv->clock <= 0 || priv->clock > div_clock) {
+		dev_err(dev, "Invalid frequency %d\n", priv->clock);
+		return -EINVAL;
+	}
+
+	uc_priv->gpio_count = mscc_sgpio_get_count(dev);
+	uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
+						   uc_priv->gpio_count);
+	if (uc_priv->gpio_count < 1 || uc_priv->gpio_count >
+	    (4 * MSCC_SGPIOS_PER_BANK)) {
+		dev_err(dev, "Invalid gpio count %d\n", uc_priv->gpio_count);
+		return -EINVAL;
+	}
+	priv->bitcount = DIV_ROUND_UP(uc_priv->gpio_count,
+				      MSCC_SGPIOS_PER_BANK);
+	debug("probe: gpios = %d, bit-count = %d\n",
+	      uc_priv->gpio_count, priv->bitcount);
+
+	priv->regs = (u32 __iomem *)dev_read_addr(dev);
+	uc_priv->bank_name = "sgpio";
+
+	sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0,
+			 MSCC_M_CFG_SIO_PORT_WIDTH(priv),
+			 MSCC_F_CFG_SIO_PORT_WIDTH(priv, priv->bitcount - 1) |
+			 MSCC_M_CFG_SIO_AUTO_REPEAT(priv));
+	val = div_clock / priv->clock;
+	debug("probe: div-clock = %d KHz, freq = %d KHz, div = %d\n",
+	      div_clock / 1000, priv->clock / 1000, val);
+	sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0,
+			 MSCC_M_CLOCK_SIO_CLK_FREQ(priv),
+			 MSCC_F_CLOCK_SIO_CLK_FREQ(priv, val));
+
+	for (port = 0; port < 32; port++)
+		sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
+	sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
+
+	debug("probe: sgpio regs = %p\n", priv->regs);
+
+	return 0;
+}
+
+static const struct dm_gpio_ops mscc_sgpio_ops = {
+	.direction_input	= mscc_sgpio_direction_input,
+	.direction_output	= mscc_sgpio_direction_output,
+	.get_function		= mscc_sgpio_get_function,
+	.get_value		= mscc_sgpio_get_value,
+	.set_value		= mscc_sgpio_set_value,
+};
+
+static const struct udevice_id mscc_sgpio_ids[] = {
+	{ .compatible = "mscc,luton-sgpio", .data = (ulong)&props_luton },
+	{ .compatible = "mscc,ocelot-sgpio", .data = (ulong)&props_ocelot },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_mscc_sgpio) = {
+	.name			= "mscc-sgpio",
+	.id			= UCLASS_GPIO,
+	.of_match		= mscc_sgpio_ids,
+	.ops			= &mscc_sgpio_ops,
+	.probe			= mscc_sgpio_probe,
+	.priv_auto_alloc_size	= sizeof(struct mscc_sgpio_priv),
+};
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
index 3132c3e..cb2a7c3 100644
--- a/drivers/mmc/jz_mmc.c
+++ b/drivers/mmc/jz_mmc.c
@@ -134,6 +134,60 @@ static int jz_mmc_clock_rate(void)
 	return 24000000;
 }
 
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
+{
+	int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
+	const void *buf = data->src;
+
+	while (sz--) {
+		u32 val = get_unaligned_le32(buf);
+
+		wait_for_bit_le32(priv->regs + MSC_IREG,
+				  MSC_IREG_TXFIFO_WR_REQ,
+				  true, 10000, false);
+		writel(val, priv->regs + MSC_TXFIFO);
+		buf += 4;
+	}
+}
+#else
+static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
+{}
+#endif
+
+static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
+{
+	int sz = data->blocks * data->blocksize;
+	void *buf = data->dest;
+	u32 stat, val;
+
+	do {
+		stat = readl(priv->regs + MSC_STAT);
+
+		if (stat & MSC_STAT_TIME_OUT_READ)
+			return -ETIMEDOUT;
+		if (stat & MSC_STAT_CRC_READ_ERROR)
+			return -EINVAL;
+		if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
+			udelay(10);
+			continue;
+		}
+		do {
+			val = readl(priv->regs + MSC_RXFIFO);
+			if (sz == 1)
+				*(u8 *)buf = (u8)val;
+			else if (sz == 2)
+				put_unaligned_le16(val, buf);
+			else if (sz >= 4)
+				put_unaligned_le32(val, buf);
+			buf += 4;
+			sz -= 4;
+			stat = readl(priv->regs + MSC_STAT);
+		} while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
+	} while (!(stat & MSC_STAT_DATA_TRAN_DONE));
+	return 0;
+}
+
 static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
 			   struct mmc_cmd *cmd, struct mmc_data *data)
 {
@@ -249,51 +303,14 @@ static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
 			cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
 		}
 	}
-
-	if (data && (data->flags & MMC_DATA_WRITE)) {
-		/* write the data */
-		int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
-		const void *buf = data->src;
-
-		while (sz--) {
-			u32 val = get_unaligned_le32(buf);
-
-			wait_for_bit_le32(priv->regs + MSC_IREG,
-					  MSC_IREG_TXFIFO_WR_REQ,
-					  true, 10000, false);
-			writel(val, priv->regs + MSC_TXFIFO);
-			buf += 4;
+	if (data) {
+		if (data->flags & MMC_DATA_WRITE)
+			jz_mmc_write_data(priv, data);
+		else if (data->flags & MMC_DATA_READ) {
+			ret = jz_mmc_read_data(priv, data);
+			if (ret)
+				return ret;
 		}
-	} else if (data && (data->flags & MMC_DATA_READ)) {
-		/* read the data */
-		int sz = data->blocks * data->blocksize;
-		void *buf = data->dest;
-
-		do {
-			stat = readl(priv->regs + MSC_STAT);
-
-			if (stat & MSC_STAT_TIME_OUT_READ)
-				return -ETIMEDOUT;
-			if (stat & MSC_STAT_CRC_READ_ERROR)
-				return -EINVAL;
-			if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
-				udelay(10);
-				continue;
-			}
-			do {
-				u32 val = readl(priv->regs + MSC_RXFIFO);
-
-				if (sz == 1)
-					*(u8 *)buf = (u8)val;
-				else if (sz == 2)
-					put_unaligned_le16(val, buf);
-				else if (sz >= 4)
-					put_unaligned_le32(val, buf);
-				buf += 4;
-				sz -= 4;
-				stat = readl(priv->regs + MSC_STAT);
-			} while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
-		} while (!(stat & MSC_STAT_DATA_TRAN_DONE));
 	}
 
 	return 0;
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index b8acc33..c8c83c9 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -65,13 +65,13 @@ err_out:
 	return err;
 }
 
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
 ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt)
 #else
 ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt)
 #endif
 {
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
 	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 #endif
 	int dev_num = block_dev->devnum;
@@ -183,7 +183,7 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
 	return blkcnt;
 }
 
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
 ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
 		 const void *src)
 #else
@@ -191,7 +191,7 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 		 const void *src)
 #endif
 {
-#ifdef CONFIG_BLK
+#if CONFIG_IS_ENABLED(BLK)
 	struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
 #endif
 	int dev_num = block_dev->devnum;
diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c
index a31efba..110985e 100644
--- a/drivers/net/bcm6368-eth.c
+++ b/drivers/net/bcm6368-eth.c
@@ -309,6 +309,43 @@ static int bcm6368_eth_start(struct udevice *dev)
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
 	uint8_t i;
 
+	/* disable all ports */
+	for (i = 0; i < priv->num_ports; i++) {
+		setbits_8(priv->base + ETH_PORTOV_REG(i),
+			  ETH_PORTOV_ENABLE_MASK);
+		setbits_8(priv->base + ETH_PTCTRL_REG(i),
+			  ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
+		priv->sw_port_link[i] = 0;
+	}
+
+	/* enable external ports */
+	for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
+		u8 rgmii_ctrl = ETH_RGMII_CTRL_GMII_CLK_EN;
+
+		if (!priv->used_ports[i].used)
+			continue;
+
+		if (priv->rgmii_override)
+			rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
+		if (priv->rgmii_timing)
+			rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
+
+		setbits_8(priv->base + ETH_RGMII_CTRL_REG(i), rgmii_ctrl);
+	}
+
+	/* reset mib */
+	setbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
+	mdelay(1);
+	clrbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
+	mdelay(1);
+
+	/* force CPU port state */
+	setbits_8(priv->base + ETH_IMPOV_REG,
+		  ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
+
+	/* enable switch forward engine */
+	setbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
+
 	/* prepare rx dma buffers */
 	for (i = 0; i < ETH_RX_DESC; i++) {
 		int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
@@ -368,6 +405,31 @@ static int bcm6368_eth_start(struct udevice *dev)
 static void bcm6368_eth_stop(struct udevice *dev)
 {
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
+	uint8_t i;
+
+	/* disable all ports */
+	for (i = 0; i < priv->num_ports; i++) {
+		setbits_8(priv->base + ETH_PORTOV_REG(i),
+			  ETH_PORTOV_ENABLE_MASK);
+		setbits_8(priv->base + ETH_PTCTRL_REG(i),
+			  ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
+	}
+
+	/* disable external ports */
+	for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
+		if (!priv->used_ports[i].used)
+			continue;
+
+		clrbits_8(priv->base + ETH_RGMII_CTRL_REG(i),
+			  ETH_RGMII_CTRL_GMII_CLK_EN);
+	}
+
+	/* disable CPU port */
+	clrbits_8(priv->base + ETH_IMPOV_REG,
+		  ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
+
+	/* disable switch forward engine */
+	clrbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
 
 	/* disable dma rx channel */
 	dma_disable(&priv->rx_dma);
@@ -444,7 +506,6 @@ static int bcm6368_eth_probe(struct udevice *dev)
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct bcm6368_eth_priv *priv = dev_get_priv(dev);
 	int num_ports, ret, i;
-	uint32_t val;
 	ofnode node;
 
 	/* get base address */
@@ -561,52 +622,6 @@ static int bcm6368_eth_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
-	/* disable all ports */
-	for (i = 0; i < priv->num_ports; i++) {
-		writeb_be(ETH_PORTOV_ENABLE_MASK,
-			      priv->base + ETH_PORTOV_REG(i));
-		writeb_be(ETH_PTCTRL_RXDIS_MASK |
-			      ETH_PTCTRL_TXDIS_MASK,
-			      priv->base + ETH_PTCTRL_REG(i));
-
-		priv->sw_port_link[i] = 0;
-	}
-
-	/* enable external ports */
-	for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
-		u8 rgmii_ctrl;
-
-		if (!priv->used_ports[i].used)
-			continue;
-
-		rgmii_ctrl = readb_be(priv->base + ETH_RGMII_CTRL_REG(i));
-		rgmii_ctrl |= ETH_RGMII_CTRL_GMII_CLK_EN;
-		if (priv->rgmii_override)
-			rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
-		if (priv->rgmii_timing)
-			rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
-		writeb_be(rgmii_ctrl, priv->base + ETH_RGMII_CTRL_REG(i));
-	}
-
-	/* reset mib */
-	val = readb_be(priv->base + ETH_GMCR_REG);
-	val |= ETH_GMCR_RST_MIB_MASK;
-	writeb_be(val, priv->base + ETH_GMCR_REG);
-	mdelay(1);
-	val &= ~ETH_GMCR_RST_MIB_MASK;
-	writeb_be(val, priv->base + ETH_GMCR_REG);
-	mdelay(1);
-
-	/* force CPU port state */
-	val = readb_be(priv->base + ETH_IMPOV_REG);
-	val |= ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK;
-	writeb_be(val, priv->base + ETH_IMPOV_REG);
-
-	/* enable switch forward engine */
-	val = readb_be(priv->base + ETH_SWMODE_REG);
-	val |= ETH_SWMODE_FWD_EN_MASK;
-	writeb_be(val, priv->base + ETH_SWMODE_REG);
-
 	/* enable jumbo on all ports */
 	writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG);
 	writew_be(9728, priv->base + ETH_JMBCTL_MAXSIZE_REG);
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
index cfc6c06..d07ea1b 100644
--- a/drivers/pinctrl/mscc/Kconfig
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -20,3 +20,12 @@ config PINCTRL_MSCC_LUTON
 	help
 	   Support pin multiplexing and pin configuration control on
 	   Microsemi luton SoCs.
+
+config PINCTRL_MSCC_JR2
+	depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL
+	select PINCTRL_MSCC
+	default y
+	bool "Microsemi jr2 family pin control driver"
+	help
+	    Support pin multiplexing and pin configuration control on
+	    Microsemi jr2 SoCs.
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
index 6910671..8038d54 100644
--- a/drivers/pinctrl/mscc/Makefile
+++ b/drivers/pinctrl/mscc/Makefile
@@ -3,3 +3,4 @@
 obj-y += mscc-common.o
 obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
 obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
+obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
diff --git a/drivers/pinctrl/mscc/mscc-common.c b/drivers/pinctrl/mscc/mscc-common.c
index d74b8a6..bd3e6ea 100644
--- a/drivers/pinctrl/mscc/mscc-common.c
+++ b/drivers/pinctrl/mscc/mscc-common.c
@@ -22,16 +22,37 @@
 #include <linux/io.h>
 #include "mscc-common.h"
 
-#define MSCC_GPIO_OUT_SET	0x0
-#define MSCC_GPIO_OUT_CLR	0x4
-#define MSCC_GPIO_OUT		0x8
-#define MSCC_GPIO_IN		0xc
-#define MSCC_GPIO_OE		0x10
-#define MSCC_GPIO_INTR		0x14
-#define MSCC_GPIO_INTR_ENA	0x18
-#define MSCC_GPIO_INTR_IDENT	0x1c
-#define MSCC_GPIO_ALT0		0x20
-#define MSCC_GPIO_ALT1		0x24
+static void mscc_writel(unsigned int offset, void *addr)
+{
+	if (offset < 32)
+		writel(BIT(offset), addr);
+	else
+		writel(BIT(offset % 32), addr + 4);
+}
+
+static unsigned int mscc_readl(unsigned int offset, void *addr)
+{
+	if (offset < 32)
+		return readl(addr);
+	else
+		return readl(addr + 4);
+}
+
+static void mscc_setbits(unsigned int offset, void *addr)
+{
+	if (offset < 32)
+		writel(readl(addr) | BIT(offset), addr);
+	else
+		writel(readl(addr + 4) | BIT(offset % 32), addr + 4);
+}
+
+static void mscc_clrbits(unsigned int offset, void *addr)
+{
+	if (offset < 32)
+		writel(readl(addr) & ~BIT(offset), addr);
+	else
+		writel(readl(addr + 4) & ~BIT(offset % 32), addr + 4);
+}
 
 static int mscc_get_functions_count(struct udevice *dev)
 {
@@ -67,7 +88,7 @@ static int mscc_pinmux_set_mux(struct udevice *dev,
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev);
 	struct mscc_pin_caps *pin = info->mscc_pins[pin_selector].drv_data;
-	int f;
+	int f, offset, regoff;
 
 	f = mscc_pin_function_idx(pin_selector, selector, info->mscc_pins);
 	if (f < 0)
@@ -79,15 +100,22 @@ static int mscc_pinmux_set_mux(struct udevice *dev,
 	 * This is racy because both registers can't be updated at the same time
 	 * but it doesn't matter much for now.
 	 */
+	offset = pin->pin;
+	regoff = info->mscc_gpios[MSCC_GPIO_ALT0];
+	if (offset >= 32) {
+		offset = offset % 32;
+		regoff = info->mscc_gpios[MSCC_GPIO_ALT1];
+	}
+
 	if (f & BIT(0))
-		setbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
+		mscc_setbits(offset, info->regs + regoff);
 	else
-		clrbits_le32(info->regs + MSCC_GPIO_ALT0, BIT(pin->pin));
+		mscc_clrbits(offset, info->regs + regoff);
 
 	if (f & BIT(1))
-		setbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
+		mscc_setbits(offset, info->regs + regoff + 4);
 	else
-		clrbits_le32(info->regs + MSCC_GPIO_ALT1, BIT(pin->pin - 1));
+		mscc_clrbits(offset, info->regs + regoff + 4);
 
 	return 0;
 }
@@ -120,8 +148,8 @@ static int mscc_create_group_func_map(struct udevice *dev,
 		}
 
 		info->func[f].ngroups = npins;
-		info->func[f].groups = devm_kzalloc(dev, npins *
-						    sizeof(char *), GFP_KERNEL);
+		info->func[f].groups = devm_kzalloc(dev, npins * sizeof(char *),
+						    GFP_KERNEL);
 		if (!info->func[f].groups)
 			return -ENOMEM;
 
@@ -150,9 +178,15 @@ static int mscc_gpio_get(struct udevice *dev, unsigned int offset)
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
 	unsigned int val;
 
-	val = readl(info->regs + MSCC_GPIO_IN);
+	if (mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]) &
+	    BIT(offset % 32))
+		val = mscc_readl(offset,
+				 info->regs + info->mscc_gpios[MSCC_GPIO_OUT]);
+	else
+		val = mscc_readl(offset,
+				 info->regs + info->mscc_gpios[MSCC_GPIO_IN]);
 
-	return !!(val & BIT(offset));
+	return !!(val & BIT(offset % 32));
 }
 
 static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
@@ -160,9 +194,11 @@ static int mscc_gpio_set(struct udevice *dev, unsigned int offset, int value)
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
 
 	if (value)
-		writel(BIT(offset), info->regs + MSCC_GPIO_OUT_SET);
+		mscc_writel(offset,
+			    info->regs + info->mscc_gpios[MSCC_GPIO_OUT_SET]);
 	else
-		writel(BIT(offset), info->regs + MSCC_GPIO_OUT_CLR);
+		mscc_writel(offset,
+			    info->regs + info->mscc_gpios[MSCC_GPIO_OUT_CLR]);
 
 	return 0;
 }
@@ -172,16 +208,16 @@ static int mscc_gpio_get_direction(struct udevice *dev, unsigned int offset)
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
 	unsigned int val;
 
-	val = readl(info->regs + MSCC_GPIO_OE);
+	val = mscc_readl(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
 
-	return (val & BIT(offset)) ? GPIOF_OUTPUT : GPIOF_INPUT;
+	return (val & BIT(offset % 32)) ? GPIOF_OUTPUT : GPIOF_INPUT;
 }
 
 static int mscc_gpio_direction_input(struct udevice *dev, unsigned int offset)
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
 
-	clrbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
+	mscc_clrbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
 
 	return 0;
 }
@@ -191,7 +227,7 @@ static int mscc_gpio_direction_output(struct udevice *dev,
 {
 	struct mscc_pinctrl *info = dev_get_priv(dev->parent);
 
-	setbits_le32(info->regs + MSCC_GPIO_OE, BIT(offset));
+	mscc_setbits(offset, info->regs + info->mscc_gpios[MSCC_GPIO_OE]);
 
 	return mscc_gpio_set(dev, offset, value);
 }
@@ -215,7 +251,8 @@ const struct pinctrl_ops mscc_pinctrl_ops = {
 
 int mscc_pinctrl_probe(struct udevice *dev, int num_func,
 		       const struct mscc_pin_data *mscc_pins, int num_pins,
-		       char *const *function_names)
+		       char * const *function_names,
+		       const unsigned long *mscc_gpios)
 {
 	struct mscc_pinctrl *priv = dev_get_priv(dev);
 	int ret;
@@ -230,6 +267,7 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func,
 	priv->mscc_pins = mscc_pins;
 	priv->num_pins = num_pins;
 	priv->function_names = function_names;
+	priv->mscc_gpios = mscc_gpios;
 	ret = mscc_pinctrl_register(dev, priv);
 
 	return ret;
diff --git a/drivers/pinctrl/mscc/mscc-common.h b/drivers/pinctrl/mscc/mscc-common.h
index b0001db..3c5c1fa 100644
--- a/drivers/pinctrl/mscc/mscc-common.h
+++ b/drivers/pinctrl/mscc/mscc-common.h
@@ -9,6 +9,19 @@
 
 #define MSCC_FUNC_PER_PIN	4
 
+enum mscc_regs_gpio {
+	MSCC_GPIO_OUT_SET,
+	MSCC_GPIO_OUT_CLR,
+	MSCC_GPIO_OUT,
+	MSCC_GPIO_IN,
+	MSCC_GPIO_OE,
+	MSCC_GPIO_INTR,
+	MSCC_GPIO_INTR_ENA,
+	MSCC_GPIO_INTR_IDENT,
+	MSCC_GPIO_ALT0,
+	MSCC_GPIO_ALT1,
+};
+
 struct mscc_pin_caps {
 	unsigned int pin;
 	unsigned char functions[MSCC_FUNC_PER_PIN];
@@ -41,11 +54,13 @@ struct mscc_pinctrl {
 	const struct mscc_pin_data *mscc_pins;
 	int num_pins;
 	char * const *function_names;
+	const unsigned long *mscc_gpios;
 };
 
 int mscc_pinctrl_probe(struct udevice *dev, int num_func,
 		       const struct mscc_pin_data *mscc_pins, int num_pins,
-		       char * const *function_names);
+		       char * const *function_names,
+		       const unsigned long *mscc_gpios);
 const struct pinctrl_ops mscc_pinctrl_ops;
 
 const struct dm_gpio_ops mscc_gpio_ops;
diff --git a/drivers/pinctrl/mscc/pinctrl-jr2.c b/drivers/pinctrl/mscc/pinctrl-jr2.c
new file mode 100644
index 0000000..72a9470
--- /dev/null
+++ b/drivers/pinctrl/mscc/pinctrl-jr2.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: <horatiu.vultur@microchip.com>
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/system.h>
+#include "mscc-common.h"
+
+enum {
+	FUNC_NONE,
+	FUNC_GPIO,
+	FUNC_IRQ0_IN,
+	FUNC_IRQ0_OUT,
+	FUNC_IRQ1_IN,
+	FUNC_IRQ1_OUT,
+	FUNC_MIIM1,
+	FUNC_MIIM2,
+	FUNC_PCI_WAKE,
+	FUNC_PTP0,
+	FUNC_PTP1,
+	FUNC_PTP2,
+	FUNC_PTP3,
+	FUNC_PWM,
+	FUNC_RECO_CLK0,
+	FUNC_RECO_CLK1,
+	FUNC_SFP0,
+	FUNC_SFP1,
+	FUNC_SFP2,
+	FUNC_SFP3,
+	FUNC_SFP4,
+	FUNC_SFP5,
+	FUNC_SFP6,
+	FUNC_SFP7,
+	FUNC_SFP8,
+	FUNC_SFP9,
+	FUNC_SFP10,
+	FUNC_SFP11,
+	FUNC_SFP12,
+	FUNC_SFP13,
+	FUNC_SFP14,
+	FUNC_SFP15,
+	FUNC_SG0,
+	FUNC_SG1,
+	FUNC_SG2,
+	FUNC_SI,
+	FUNC_TACHO,
+	FUNC_TWI,
+	FUNC_TWI2,
+	FUNC_TWI_SCL_M,
+	FUNC_UART,
+	FUNC_UART2,
+	FUNC_MAX
+};
+
+static char * const jr2_function_names[] = {
+	[FUNC_NONE]		= "none",
+	[FUNC_GPIO]		= "gpio",
+	[FUNC_IRQ0_IN]		= "irq0_in",
+	[FUNC_IRQ0_OUT]		= "irq0_out",
+	[FUNC_IRQ1_IN]		= "irq1_in",
+	[FUNC_IRQ1_OUT]		= "irq1_out",
+	[FUNC_MIIM1]		= "miim1",
+	[FUNC_MIIM2]		= "miim2",
+	[FUNC_PCI_WAKE]		= "pci_wake",
+	[FUNC_PTP0]		= "ptp0",
+	[FUNC_PTP1]		= "ptp1",
+	[FUNC_PTP2]		= "ptp2",
+	[FUNC_PTP3]		= "ptp3",
+	[FUNC_PWM]		= "pwm",
+	[FUNC_RECO_CLK0]	= "reco_clk0",
+	[FUNC_RECO_CLK1]	= "reco_clk1",
+	[FUNC_SFP0]		= "sfp0",
+	[FUNC_SFP1]		= "sfp1",
+	[FUNC_SFP2]		= "sfp2",
+	[FUNC_SFP3]		= "sfp3",
+	[FUNC_SFP4]		= "sfp4",
+	[FUNC_SFP5]		= "sfp5",
+	[FUNC_SFP6]		= "sfp6",
+	[FUNC_SFP7]		= "sfp7",
+	[FUNC_SFP8]		= "sfp8",
+	[FUNC_SFP9]		= "sfp9",
+	[FUNC_SFP10]		= "sfp10",
+	[FUNC_SFP11]		= "sfp11",
+	[FUNC_SFP12]		= "sfp12",
+	[FUNC_SFP13]		= "sfp13",
+	[FUNC_SFP14]		= "sfp14",
+	[FUNC_SFP15]		= "sfp15",
+	[FUNC_SG0]		= "sg0",
+	[FUNC_SG1]		= "sg1",
+	[FUNC_SG2]		= "sg2",
+	[FUNC_SI]		= "si",
+	[FUNC_TACHO]		= "tacho",
+	[FUNC_TWI]		= "twi",
+	[FUNC_TWI2]		= "twi2",
+	[FUNC_TWI_SCL_M]	= "twi_scl_m",
+	[FUNC_UART]		= "uart",
+	[FUNC_UART2]		= "uart2",
+};
+
+#define JR2_P(p, f0, f1)						\
+static struct mscc_pin_caps jr2_pin_##p = {				\
+	.pin = p,							\
+	.functions = {							\
+			FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE	\
+	},								\
+}
+
+JR2_P(0,  SG0,       NONE);
+JR2_P(1,  SG0,       NONE);
+JR2_P(2,  SG0,       NONE);
+JR2_P(3,  SG0,       NONE);
+JR2_P(4,  SG1,       NONE);
+JR2_P(5,  SG1,       NONE);
+JR2_P(6,  IRQ0_IN,   IRQ0_OUT);
+JR2_P(7,  IRQ1_IN,   IRQ1_OUT);
+JR2_P(8,  PTP0,      NONE);
+JR2_P(9,  PTP1,      NONE);
+JR2_P(10, UART,      NONE);
+JR2_P(11, UART,      NONE);
+JR2_P(12, SG1,       NONE);
+JR2_P(13, SG1,       NONE);
+JR2_P(14, TWI,       TWI_SCL_M);
+JR2_P(15, TWI,       NONE);
+JR2_P(16, SI,        TWI_SCL_M);
+JR2_P(17, SI,        TWI_SCL_M);
+JR2_P(18, SI,        TWI_SCL_M);
+JR2_P(19, PCI_WAKE,  NONE);
+JR2_P(20, IRQ0_OUT,  TWI_SCL_M);
+JR2_P(21, IRQ1_OUT,  TWI_SCL_M);
+JR2_P(22, TACHO,     NONE);
+JR2_P(23, PWM,       NONE);
+JR2_P(24, UART2,     NONE);
+JR2_P(25, UART2,     SI);
+JR2_P(26, PTP2,      SI);
+JR2_P(27, PTP3,      SI);
+JR2_P(28, TWI2,      SI);
+JR2_P(29, TWI,       SI);
+JR2_P(30, SG2,       SI);
+JR2_P(31, SG2,       SI);
+JR2_P(32, SG2,       SI);
+JR2_P(33, SG2,       SI);
+JR2_P(34, NONE,      TWI_SCL_M);
+JR2_P(35, NONE,      TWI_SCL_M);
+JR2_P(36, NONE,      TWI_SCL_M);
+JR2_P(37, NONE,      TWI_SCL_M);
+JR2_P(38, NONE,      TWI_SCL_M);
+JR2_P(39, NONE,      TWI_SCL_M);
+JR2_P(40, NONE,      TWI_SCL_M);
+JR2_P(41, NONE,      TWI_SCL_M);
+JR2_P(42, NONE,      TWI_SCL_M);
+JR2_P(43, NONE,      TWI_SCL_M);
+JR2_P(44, NONE,      SFP8);
+JR2_P(45, NONE,      SFP9);
+JR2_P(46, NONE,      SFP10);
+JR2_P(47, NONE,      SFP11);
+JR2_P(48, SFP0,      NONE);
+JR2_P(49, SFP1,      SI);
+JR2_P(50, SFP2,      SI);
+JR2_P(51, SFP3,      SI);
+JR2_P(52, SFP4,      NONE);
+JR2_P(53, SFP5,      NONE);
+JR2_P(54, SFP6,      NONE);
+JR2_P(55, SFP7,      NONE);
+JR2_P(56, MIIM1,     SFP12);
+JR2_P(57, MIIM1,     SFP13);
+JR2_P(58, MIIM2,     SFP14);
+JR2_P(59, MIIM2,     SFP15);
+JR2_P(60, NONE,      NONE);
+JR2_P(61, NONE,      NONE);
+JR2_P(62, NONE,      NONE);
+JR2_P(63, NONE,      NONE);
+
+#define JR2_PIN(n) {						\
+	.name = "GPIO_"#n,					\
+	.drv_data = &jr2_pin_##n				\
+}
+
+static const struct mscc_pin_data jr2_pins[] = {
+	JR2_PIN(0),
+	JR2_PIN(1),
+	JR2_PIN(2),
+	JR2_PIN(3),
+	JR2_PIN(4),
+	JR2_PIN(5),
+	JR2_PIN(6),
+	JR2_PIN(7),
+	JR2_PIN(8),
+	JR2_PIN(9),
+	JR2_PIN(10),
+	JR2_PIN(11),
+	JR2_PIN(12),
+	JR2_PIN(13),
+	JR2_PIN(14),
+	JR2_PIN(15),
+	JR2_PIN(16),
+	JR2_PIN(17),
+	JR2_PIN(18),
+	JR2_PIN(19),
+	JR2_PIN(20),
+	JR2_PIN(21),
+	JR2_PIN(22),
+	JR2_PIN(23),
+	JR2_PIN(24),
+	JR2_PIN(25),
+	JR2_PIN(26),
+	JR2_PIN(27),
+	JR2_PIN(28),
+	JR2_PIN(29),
+	JR2_PIN(30),
+	JR2_PIN(31),
+	JR2_PIN(32),
+	JR2_PIN(33),
+	JR2_PIN(34),
+	JR2_PIN(35),
+	JR2_PIN(36),
+	JR2_PIN(37),
+	JR2_PIN(38),
+	JR2_PIN(39),
+	JR2_PIN(40),
+	JR2_PIN(41),
+	JR2_PIN(42),
+	JR2_PIN(43),
+	JR2_PIN(44),
+	JR2_PIN(45),
+	JR2_PIN(46),
+	JR2_PIN(47),
+	JR2_PIN(48),
+	JR2_PIN(49),
+	JR2_PIN(50),
+	JR2_PIN(51),
+	JR2_PIN(52),
+	JR2_PIN(53),
+	JR2_PIN(54),
+	JR2_PIN(55),
+	JR2_PIN(56),
+	JR2_PIN(57),
+	JR2_PIN(58),
+	JR2_PIN(59),
+	JR2_PIN(60),
+	JR2_PIN(61),
+	JR2_PIN(62),
+	JR2_PIN(63),
+};
+
+static const unsigned long jr2_gpios[] = {
+	[MSCC_GPIO_OUT_SET] = 0x00,
+	[MSCC_GPIO_OUT_CLR] = 0x08,
+	[MSCC_GPIO_OUT] = 0x10,
+	[MSCC_GPIO_IN] = 0x18,
+	[MSCC_GPIO_OE] = 0x20,
+	[MSCC_GPIO_INTR] = 0x28,
+	[MSCC_GPIO_INTR_ENA] = 0x30,
+	[MSCC_GPIO_INTR_IDENT] = 0x38,
+	[MSCC_GPIO_ALT0] = 0x40,
+	[MSCC_GPIO_ALT1] = 0x48,
+};
+
+static int jr2_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv;
+
+	uc_priv = dev_get_uclass_priv(dev);
+	uc_priv->bank_name = "jr2-gpio";
+	uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
+
+	return 0;
+}
+
+static struct driver jr2_gpio_driver = {
+	.name	= "jr2-gpio",
+	.id	= UCLASS_GPIO,
+	.probe	= jr2_gpio_probe,
+	.ops	= &mscc_gpio_ops,
+};
+
+static int jr2_pinctrl_probe(struct udevice *dev)
+{
+	int ret;
+
+	ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
+				 ARRAY_SIZE(jr2_pins),
+				 jr2_function_names,
+				 jr2_gpios);
+
+	if (ret)
+		return ret;
+
+	ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
+			  dev_of_offset(dev), NULL);
+
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static const struct udevice_id jr2_pinctrl_of_match[] = {
+	{ .compatible = "mscc,jaguar2-pinctrl" },
+	{},
+};
+
+U_BOOT_DRIVER(jr2_pinctrl) = {
+	.name = "jr2-pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = of_match_ptr(jr2_pinctrl_of_match),
+	.probe = jr2_pinctrl_probe,
+	.priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
+	.ops = &mscc_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c b/drivers/pinctrl/mscc/pinctrl-luton.c
index 7166588..17fbc53 100644
--- a/drivers/pinctrl/mscc/pinctrl-luton.c
+++ b/drivers/pinctrl/mscc/pinctrl-luton.c
@@ -123,6 +123,19 @@ static const struct mscc_pin_data luton_pins[] = {
 	LUTON_PIN(31),
 };
 
+static const unsigned long luton_gpios[] = {
+	[MSCC_GPIO_OUT_SET] = 0x00,
+	[MSCC_GPIO_OUT_CLR] = 0x04,
+	[MSCC_GPIO_OUT] = 0x08,
+	[MSCC_GPIO_IN] = 0x0c,
+	[MSCC_GPIO_OE] = 0x10,
+	[MSCC_GPIO_INTR] = 0x14,
+	[MSCC_GPIO_INTR_ENA] = 0x18,
+	[MSCC_GPIO_INTR_IDENT] = 0x1c,
+	[MSCC_GPIO_ALT0] = 0x20,
+	[MSCC_GPIO_ALT1] = 0x24,
+};
+
 static int luton_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv;
@@ -146,7 +159,8 @@ int luton_pinctrl_probe(struct udevice *dev)
 	int ret;
 
 	ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
-				 ARRAY_SIZE(luton_pins), luton_function_names);
+				 ARRAY_SIZE(luton_pins), luton_function_names,
+				 luton_gpios);
 
 	if (ret)
 		return ret;
diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c b/drivers/pinctrl/mscc/pinctrl-ocelot.c
index 10f9b90..49e026b 100644
--- a/drivers/pinctrl/mscc/pinctrl-ocelot.c
+++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c
@@ -138,6 +138,19 @@ static const struct mscc_pin_data ocelot_pins[] = {
 	OCELOT_PIN(21),
 };
 
+static const unsigned long ocelot_gpios[] = {
+	[MSCC_GPIO_OUT_SET] = 0x00,
+	[MSCC_GPIO_OUT_CLR] = 0x04,
+	[MSCC_GPIO_OUT] = 0x08,
+	[MSCC_GPIO_IN] = 0x0c,
+	[MSCC_GPIO_OE] = 0x10,
+	[MSCC_GPIO_INTR] = 0x14,
+	[MSCC_GPIO_INTR_ENA] = 0x18,
+	[MSCC_GPIO_INTR_IDENT] = 0x1c,
+	[MSCC_GPIO_ALT0] = 0x20,
+	[MSCC_GPIO_ALT1] = 0x24,
+};
+
 static int ocelot_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv;
@@ -162,7 +175,8 @@ int ocelot_pinctrl_probe(struct udevice *dev)
 
 	ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
 				 ARRAY_SIZE(ocelot_pins),
-				 ocelot_function_names);
+				 ocelot_function_names,
+				 ocelot_gpios);
 
 	if (ret)
 		return ret;
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a7bb5b3..de4d62d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -294,6 +294,13 @@ config SOFT_SPI
 	 Enable Soft SPI driver. This driver is to use GPIO simulate
 	 the SPI protocol.
 
+config MSCC_BB_SPI
+	bool "MSCC bitbang SPI driver"
+	depends on SOC_VCOREIII
+	help
+	  Enable MSCC bitbang SPI driver. This driver can be used on
+	  MSCC SOCs.
+
 config CF_SPI
 	bool "ColdFire SPI driver"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 392a925..4acec3e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
 obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
 obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
 obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
+obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
 obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
 obj-$(CONFIG_MXC_SPI) += mxc_spi.o
 obj-$(CONFIG_MXS_SPI) += mxs_spi.o
diff --git a/drivers/spi/mscc_bb_spi.c b/drivers/spi/mscc_bb_spi.c
new file mode 100644
index 0000000..c3c7b80
--- /dev/null
+++ b/drivers/spi/mscc_bb_spi.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs spi driver
+ *
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <spi.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+struct mscc_bb_priv {
+	void __iomem *regs;
+	u32 deactivate_delay_us;
+	bool cs_active;   /* State flag as to whether CS is asserted */
+	int cs_num;
+	u32 svalue;			/* Value to start transfer with */
+	u32 clk1;			/* Clock value start */
+	u32 clk2;			/* Clock value 2nd phase */
+};
+
+/* Delay 24 instructions for this particular application */
+#define hold_time_delay() mscc_vcoreiii_nop_delay(3)
+
+static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)
+{
+	if (!priv->cs_active) {
+		int cpha = mode & SPI_CPHA;
+		u32 cs_value;
+
+		priv->cs_num = cs;
+
+		if (cpha) {
+			/* Initial clock starts SCK=1 */
+			priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;
+			priv->clk2 = 0;
+		} else {
+			/* Initial clock starts SCK=0 */
+			priv->clk1 = 0;
+			priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;
+		}
+
+		/* Enable bitbang, SCK_OE, SDO_OE */
+		priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */
+				ICPU_SW_MODE_SW_SPI_SCK_OE    | /* SCK_OE */
+				ICPU_SW_MODE_SW_SPI_SDO_OE);   /* SDO OE */
+
+		/* Add CS */
+		if (cs >= 0) {
+			cs_value =
+				ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |
+				ICPU_SW_MODE_SW_SPI_CS(BIT(cs));
+		} else {
+			cs_value = 0;
+		}
+
+		priv->svalue |= cs_value;
+
+		/* Enable the CS in HW, Initial clock value */
+		writel(priv->svalue | priv->clk2, priv->regs);
+
+		priv->cs_active = true;
+		debug("Activated CS%d\n", priv->cs_num);
+	}
+
+	return 0;
+}
+
+static int mscc_bb_spi_cs_deactivate(struct mscc_bb_priv *priv, int deact_delay)
+{
+	if (priv->cs_active) {
+		/* Keep driving the CLK to its current value while
+		 * actively deselecting CS.
+		 */
+		u32 value = readl(priv->regs);
+
+		value &= ~ICPU_SW_MODE_SW_SPI_CS_M;
+		writel(value, priv->regs);
+		hold_time_delay();
+
+		/* Stop driving the clock, but keep CS with nCS == 1 */
+		value &= ~ICPU_SW_MODE_SW_SPI_SCK_OE;
+		writel(value, priv->regs);
+
+		/* Deselect hold time delay */
+		if (deact_delay)
+			udelay(deact_delay);
+
+		/* Drop everything */
+		writel(0, priv->regs);
+
+		priv->cs_active = false;
+		debug("Deactivated CS%d\n", priv->cs_num);
+	}
+
+	return 0;
+}
+
+int mscc_bb_spi_claim_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+int mscc_bb_spi_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+int mscc_bb_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		     const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+	struct mscc_bb_priv *priv = dev_get_priv(bus);
+	u32             i, count;
+	const u8	*txd = dout;
+	u8		*rxd = din;
+
+	debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",
+	      dev->parent->name, dev->name, plat->cs,  plat->mode, dout,
+	      din, bitlen);
+
+	if (flags & SPI_XFER_BEGIN)
+		mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);
+
+	count = bitlen / 8;
+	for (i = 0; i < count; i++) {
+		u32 rx = 0, mask = 0x80, value;
+
+		while (mask) {
+			/* Initial condition: CLK is low. */
+			value = priv->svalue;
+			if (txd && txd[i] & mask)
+				value |= ICPU_SW_MODE_SW_SPI_SDO;
+
+			/* Drive data while taking CLK low. The device
+			 * we're accessing will sample on the
+			 * following rising edge and will output data
+			 * on this edge for us to be sampled at the
+			 * end of this loop.
+			 */
+			writel(value | priv->clk1, priv->regs);
+
+			/* Wait for t_setup. All devices do have a
+			 * setup-time, so we always insert some delay
+			 * here. Some devices have a very long
+			 * setup-time, which can be adjusted by the
+			 * user through vcoreiii_device->delay.
+			 */
+			hold_time_delay();
+
+			/* Drive the clock high. */
+			writel(value | priv->clk2, priv->regs);
+
+			/* Wait for t_hold. See comment about t_setup
+			 * above.
+			 */
+			hold_time_delay();
+
+			/* We sample as close to the next falling edge
+			 * as possible.
+			 */
+			value = readl(priv->regs);
+			if (value & ICPU_SW_MODE_SW_SPI_SDI)
+				rx |= mask;
+			mask >>= 1;
+		}
+		if (rxd) {
+			debug("Read 0x%02x\n", rx);
+			rxd[i] = (u8)rx;
+		}
+		debug("spi_xfer: byte %d/%d\n", i + 1, count);
+	}
+
+	debug("spi_xfer: done\n");
+
+	if (flags & SPI_XFER_END)
+		mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);
+
+	return 0;
+}
+
+int mscc_bb_spi_set_speed(struct udevice *dev, unsigned int speed)
+{
+	/* Accept any speed */
+	return 0;
+}
+
+int mscc_bb_spi_set_mode(struct udevice *dev, unsigned int mode)
+{
+	return 0;
+}
+
+static const struct dm_spi_ops mscc_bb_ops = {
+	.claim_bus	= mscc_bb_spi_claim_bus,
+	.release_bus	= mscc_bb_spi_release_bus,
+	.xfer		= mscc_bb_spi_xfer,
+	.set_speed	= mscc_bb_spi_set_speed,
+	.set_mode	= mscc_bb_spi_set_mode,
+};
+
+static const struct udevice_id mscc_bb_ids[] = {
+	{ .compatible = "mscc,luton-bb-spi" },
+	{ }
+};
+
+static int mscc_bb_spi_probe(struct udevice *bus)
+{
+	struct mscc_bb_priv *priv = dev_get_priv(bus);
+
+	debug("%s: loaded, priv %p\n", __func__, priv);
+
+	priv->regs = (void __iomem *)dev_read_addr(bus);
+
+	priv->deactivate_delay_us =
+		dev_read_u32_default(bus, "spi-deactivate-delay", 0);
+
+	priv->cs_active = false;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(mscc_bb) = {
+	.name	= "mscc_bb",
+	.id	= UCLASS_SPI,
+	.of_match = mscc_bb_ids,
+	.ops	= &mscc_bb_ops,
+	.priv_auto_alloc_size = sizeof(struct mscc_bb_priv),
+	.probe	= mscc_bb_spi_probe,
+};