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-rw-r--r--drivers/clk/renesas/Kconfig15
-rw-r--r--drivers/clk/renesas/Makefile3
-rw-r--r--drivers/clk/renesas/r9a06g032-clocks.c1103
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/renesas/Kconfig7
-rw-r--r--drivers/pinctrl/renesas/Makefile1
-rw-r--r--drivers/pinctrl/renesas/pinctrl-rzn1.c379
-rw-r--r--drivers/ram/Kconfig1
-rw-r--r--drivers/ram/Makefile3
-rw-r--r--drivers/ram/cadence/Kconfig12
-rw-r--r--drivers/ram/cadence/Makefile1
-rw-r--r--drivers/ram/cadence/ddr_ctrl.c414
-rw-r--r--drivers/ram/renesas/Makefile3
-rw-r--r--drivers/ram/renesas/rzn1/Makefile3
-rw-r--r--drivers/ram/renesas/rzn1/ddr_async.c376
15 files changed, 2320 insertions, 2 deletions
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 45671c6..437a82c 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -2,7 +2,12 @@ config CLK_RENESAS
bool "Renesas clock drivers"
depends on CLK && ARCH_RMOBILE
help
- Enable support for clock present on Renesas RCar SoCs.
+ Enable support for clock present on Renesas SoCs.
+
+config CLK_RCAR
+ bool "Renesas RCar clock driver support"
+ help
+ Enable common code for clocks on Renesas RCar SoCs.
config CLK_RCAR_CPG_LIB
bool "CPG/MSSR library functions"
@@ -11,6 +16,7 @@ config CLK_RCAR_GEN2
bool "Renesas RCar Gen2 clock driver"
def_bool y if RCAR_32
depends on CLK_RENESAS
+ select CLK_RCAR
help
Enable this to support the clocks on Renesas RCar Gen2 SoC.
@@ -48,6 +54,7 @@ config CLK_RCAR_GEN3
bool "Renesas RCar Gen3 and Gen4 clock driver"
def_bool y if RCAR_64
depends on CLK_RENESAS
+ select CLK_RCAR
select CLK_RCAR_CPG_LIB
select DM_RESET
help
@@ -143,3 +150,9 @@ config CLK_R8A779G0
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A779G0 SoC.
+
+config CLK_R9A06G032
+ bool "Renesas R9A06G032 clock driver"
+ depends on CLK_RENESAS
+ help
+ Enable this to support the clocks on Renesas R9A06G032 SoC.
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index fe0391e..48373e6 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -1,4 +1,4 @@
-obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
+obj-$(CONFIG_CLK_RCAR) += renesas-cpg-mssr.o
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
@@ -22,3 +22,4 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
+obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
new file mode 100644
index 0000000..d2f6123
--- /dev/null
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -0,0 +1,1103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R9A06G032 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#include <dt-bindings/clock/r9a06g032-sysctrl.h>
+
+/**
+ * struct regbit - describe one bit in a register
+ * @reg: offset of register relative to base address,
+ * expressed in units of 32-bit words (not bytes),
+ * @bit: which bit (0 to 31) in the register
+ *
+ * This structure is used to compactly encode the location
+ * of a single bit in a register. Five bits are needed to
+ * encode the bit number. With uint16_t data type, this
+ * leaves 11 bits to encode a register offset up to 2047.
+ *
+ * Since registers are aligned on 32-bit boundaries, the
+ * offset will be specified in 32-bit words rather than bytes.
+ * This allows encoding an offset up to 0x1FFC (8188) bytes.
+ *
+ * Helper macro RB() takes care of converting the register
+ * offset from bytes to 32-bit words.
+ */
+struct regbit {
+ u16 reg:11;
+ u16 bit:5;
+};
+
+#define RB(_reg, _bit) ((struct regbit) { \
+ .reg = (_reg) / 4, \
+ .bit = (_bit) \
+})
+
+/**
+ * struct r9a06g032_gate - clock-related control bits
+ * @gate: clock enable/disable
+ * @reset: clock module reset (active low)
+ * @ready: enables NoC forwarding of read/write requests to device,
+ * (eg. device is ready to handle read/write requests)
+ * @midle: request to idle the NoC interconnect
+ *
+ * Each of these fields describes a single bit in a register,
+ * which controls some aspect of clock gating. The @gate field
+ * is mandatory, this one enables/disables the clock. The
+ * other fields are optional, with zero indicating "not used".
+ *
+ * In most cases there is a @reset bit which needs to be
+ * de-asserted to bring the module out of reset.
+ *
+ * Modules may also need to signal when the are @ready to
+ * handle requests (read/writes) from the NoC interconnect.
+ *
+ * Similarly, the @midle bit is used to idle the master.
+ */
+struct r9a06g032_gate {
+ struct regbit gate, reset, ready, midle;
+ /* Unused fields omitted to save space */
+ /* struct regbit scon, mirack, mistat */;
+};
+
+enum gate_type {
+ K_GATE = 0, /* gate which enable/disable */
+ K_FFC, /* fixed factor clock */
+ K_DIV, /* divisor */
+ K_BITSEL, /* special for UARTs */
+ K_DUALGATE /* special for UARTs */
+};
+
+/**
+ * struct r9a06g032_clkdesc - describe a single clock
+ * @name: string describing this clock
+ * @managed: boolean indicating if this clock should be
+ * started/stopped as part of power management
+ * (not used in u-boot)
+ * @type: see enum @gate_type
+ * @index: the ID of this clock element
+ * @source: the ID+1 of the parent clock element.
+ * Root clock uses ID of ~0 (PARENT_ID);
+ * @gate: clock enable/disable
+ * @div_min: smallest permitted clock divider
+ * @div_max: largest permitted clock divider
+ * @reg: clock divider register offset, in 32-bit words
+ * @div_table: optional list of fixed clock divider values;
+ * must be in ascending order, zero for unused
+ * @div: divisor for fixed-factor clock
+ * @mul: multiplier for fixed-factor clock
+ * @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7
+ * @sel: select either g1/r1 or g2/r2 as clock source
+ * @g1: 1st source gate (clock enable/disable)
+ * @r1: 1st source reset (module reset)
+ * @g2: 2nd source gate (clock enable/disable)
+ * @r2: 2nd source reset (module reset)
+ *
+ * Describes a single element in the clock tree hierarchy.
+ * As there are quite a large number of clock elements, this
+ * structure is packed tightly to conserve space.
+ */
+struct r9a06g032_clkdesc {
+ const char *name;
+ uint32_t managed:1;
+ enum gate_type type:3;
+ uint32_t index:8;
+ uint32_t source:8; /* source index + 1 (0 == none) */
+ union {
+ /* type = K_GATE */
+ struct r9a06g032_gate gate;
+ /* type = K_DIV */
+ struct {
+ unsigned int div_min:10, div_max:10, reg:10;
+ u16 div_table[4];
+ };
+ /* type = K_FFC */
+ struct {
+ u16 div, mul;
+ };
+ /* type = K_DUALGATE */
+ struct {
+ uint16_t group:1;
+ struct regbit sel, g1, r1, g2, r2;
+ } dual;
+ };
+};
+
+/*
+ * The last three arguments are not currently used,
+ * but are kept in the r9a06g032_clocks table below.
+ */
+#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \
+ .gate = _clk, \
+ .reset = _rst, \
+ .ready = _rdy, \
+ .midle = _midle, \
+ /* .scon = _scon, */ \
+ /* .mirack = _mirack, */ \
+ /* .mistat = _mistat */ \
+}
+#define D_GATE(_idx, _n, _src, ...) { \
+ .type = K_GATE, \
+ .index = R9A06G032_##_idx, \
+ .source = 1 + R9A06G032_##_src, \
+ .name = _n, \
+ .gate = I_GATE(__VA_ARGS__) \
+}
+#define D_MODULE(_idx, _n, _src, ...) { \
+ .type = K_GATE, \
+ .index = R9A06G032_##_idx, \
+ .source = 1 + R9A06G032_##_src, \
+ .name = _n, \
+ .managed = 1, \
+ .gate = I_GATE(__VA_ARGS__) \
+}
+#define D_ROOT(_idx, _n, _mul, _div) { \
+ .type = K_FFC, \
+ .index = R9A06G032_##_idx, \
+ .name = _n, \
+ .div = _div, \
+ .mul = _mul \
+}
+#define D_FFC(_idx, _n, _src, _div) { \
+ .type = K_FFC, \
+ .index = R9A06G032_##_idx, \
+ .source = 1 + R9A06G032_##_src, \
+ .name = _n, \
+ .div = _div, \
+ .mul = 1 \
+}
+#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \
+ .type = K_DIV, \
+ .index = R9A06G032_##_idx, \
+ .source = 1 + R9A06G032_##_src, \
+ .name = _n, \
+ .reg = _reg, \
+ .div_min = _min, \
+ .div_max = _max, \
+ .div_table = { __VA_ARGS__ } \
+}
+#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \
+ .type = K_DUALGATE, \
+ .index = R9A06G032_##_idx, \
+ .source = 1 + R9A06G032_##_src, \
+ .name = _n, \
+ .dual = { \
+ .group = _g, \
+ .g1 = _g1, \
+ .r1 = _r1, \
+ .g2 = _g2, \
+ .r2 = _r2 \
+ }, \
+}
+
+/* Internal clock IDs */
+#define R9A06G032_CLKOUT 0
+#define R9A06G032_CLKOUT_D10 2
+#define R9A06G032_CLKOUT_D16 3
+#define R9A06G032_CLKOUT_D160 4
+#define R9A06G032_CLKOUT_D1OR2 5
+#define R9A06G032_CLKOUT_D20 6
+#define R9A06G032_CLKOUT_D40 7
+#define R9A06G032_CLKOUT_D5 8
+#define R9A06G032_CLKOUT_D8 9
+#define R9A06G032_DIV_ADC 10
+#define R9A06G032_DIV_I2C 11
+#define R9A06G032_DIV_NAND 12
+#define R9A06G032_DIV_P1_PG 13
+#define R9A06G032_DIV_P2_PG 14
+#define R9A06G032_DIV_P3_PG 15
+#define R9A06G032_DIV_P4_PG 16
+#define R9A06G032_DIV_P5_PG 17
+#define R9A06G032_DIV_P6_PG 18
+#define R9A06G032_DIV_QSPI0 19
+#define R9A06G032_DIV_QSPI1 20
+#define R9A06G032_DIV_REF_SYNC 21
+#define R9A06G032_DIV_SDIO0 22
+#define R9A06G032_DIV_SDIO1 23
+#define R9A06G032_DIV_SWITCH 24
+#define R9A06G032_DIV_UART 25
+#define R9A06G032_DIV_MOTOR 64
+#define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78
+#define R9A06G032_CLK_ECAT100_D4 79
+#define R9A06G032_CLK_HSR100_D2 80
+#define R9A06G032_CLK_REF_SYNC_D4 81
+#define R9A06G032_CLK_REF_SYNC_D8 82
+#define R9A06G032_CLK_SERCOS100_D2 83
+#define R9A06G032_DIV_CA7 84
+
+#define R9A06G032_UART_GROUP_012 154
+#define R9A06G032_UART_GROUP_34567 155
+
+#define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1)
+
+static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
+ D_ROOT(CLKOUT, "clkout", 25, 1),
+ D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10),
+ D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
+ D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
+ D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
+ D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
+ D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
+ D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
+ D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
+ D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
+ D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
+ D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
+ D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
+ D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
+ D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
+ D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
+ D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
+ D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
+ D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
+ D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
+ D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
+ D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
+ D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
+ D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
+ D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
+ D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
+ D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9),
+ RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0),
+ RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12),
+ RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0),
+ RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15),
+ RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0),
+ RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18),
+ RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0),
+ RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21),
+ RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0),
+ RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10),
+ RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6),
+ RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8),
+ RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4),
+ RB(0x50, 5), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20),
+ RB(0xec, 21), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2),
+ RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4),
+ RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6),
+ RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4),
+ RB(0x104, 5), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6),
+ RB(0x104, 7), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0),
+ RB(0x114, 1), RB(0x114, 2), RB(0x00, 0),
+ RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3),
+ RB(0x114, 4), RB(0x114, 5), RB(0x00, 0),
+ RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6),
+ RB(0x114, 7), RB(0x114, 8), RB(0x00, 0),
+ RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9),
+ RB(0x114, 10), RB(0x114, 11), RB(0x00, 0),
+ RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4),
+ RB(0x54, 5), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4),
+ RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0),
+ RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0),
+ RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2),
+ RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4),
+ RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6),
+ RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0),
+ RB(0x104, 1), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2),
+ RB(0x104, 3), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2),
+ RB(0x130, 3), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
+ D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0),
+ RB(0x80, 1), RB(0x00, 0), RB(0x80, 2),
+ RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)),
+ D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0),
+ RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0),
+ RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0),
+ RB(0x84, 2), RB(0x00, 0), RB(0x84, 1),
+ RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)),
+ D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3),
+ RB(0x118, 4), RB(0x118, 5), RB(0x00, 0),
+ RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6),
+ RB(0x118, 7), RB(0x118, 8), RB(0x00, 0),
+ RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9),
+ RB(0x118, 10), RB(0x118, 11), RB(0x00, 0),
+ RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3),
+ RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0),
+ RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6),
+ RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0),
+ RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3),
+ RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4),
+ RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)),
+ D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0),
+ RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2),
+ RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)),
+ D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12),
+ RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14),
+ RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)),
+ D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9),
+ RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0),
+ RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)),
+ D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
+ D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
+ D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
+ D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
+ D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
+ D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
+ D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
+ D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3),
+ RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0),
+ RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6),
+ RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0),
+ RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15),
+ RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12),
+ RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0),
+ RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0),
+ RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0),
+ RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3),
+ RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
+ D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0),
+ RB(0x174, 1), RB(0x00, 0), RB(0x174, 2),
+ RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)),
+ D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3),
+ RB(0x64, 4), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3),
+ RB(0x80, 4), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4),
+ RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0),
+ RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4),
+ RB(0x84, 3), RB(0x00, 0), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15),
+ RB(0x34, 16), RB(0x34, 17), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0),
+ RB(0x184, 1), RB(0x184, 2), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3),
+ RB(0x24, 4), RB(0x24, 5), RB(0x00, 0),
+ RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0),
+ RB(0x24, 1), RB(0x00, 0), RB(0x24, 2),
+ RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)),
+ D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0),
+ RB(0x64, 2), RB(0x00, 0), RB(0x64, 1),
+ RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)),
+ D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0),
+ RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3),
+ RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)),
+ D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4),
+ RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7),
+ RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)),
+ D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0),
+ RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3),
+ RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)),
+ D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0),
+ RB(0x70, 1), RB(0x70, 2), RB(0x70, 3),
+ RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)),
+ D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18),
+ RB(0x40, 19), RB(0x40, 20), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21),
+ RB(0x40, 22), RB(0x40, 23), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9),
+ RB(0x44, 10), RB(0x44, 11), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0),
+ RB(0x90, 2), RB(0x00, 0), RB(0x90, 1),
+ RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)),
+ D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9),
+ RB(0x34, 10), RB(0x34, 11), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12),
+ RB(0x34, 13), RB(0x34, 14), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0),
+ RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0),
+ RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4),
+ RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0),
+ RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0),
+ RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3),
+ RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)),
+ D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0),
+ RB(0x50, 1), RB(0x50, 2), RB(0x50, 3),
+ RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)),
+ D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12),
+ RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14),
+ RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)),
+ D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12),
+ RB(0x44, 13), RB(0x44, 14), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15),
+ RB(0x44, 16), RB(0x44, 17), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6),
+ RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0),
+ RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9),
+ RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0),
+ RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0),
+ RB(0x54, 1), RB(0x54, 2), RB(0x54, 3),
+ RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)),
+ D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0),
+ RB(0x90, 1), RB(0x90, 2), RB(0x90, 3),
+ RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)),
+ D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0),
+ RB(0x154, 1), RB(0x154, 2), RB(0x00, 0),
+ RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0),
+ RB(0x140, 3), RB(0x00, 0), RB(0x140, 2),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0),
+ RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3),
+ RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)),
+ D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0),
+ RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3),
+ RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)),
+ D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3),
+ RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0),
+ RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0),
+ RB(0x40, 1), RB(0x40, 2), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3),
+ RB(0x40, 4), RB(0x40, 5), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6),
+ RB(0x40, 7), RB(0x40, 8), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9),
+ RB(0x40, 10), RB(0x40, 11), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12),
+ RB(0x40, 13), RB(0x40, 14), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15),
+ RB(0x40, 16), RB(0x40, 17), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0),
+ RB(0x00, 0), RB(0x130, 1), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0),
+ RB(0x188, 1), RB(0x188, 2), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0),
+ RB(0x34, 1), RB(0x34, 2), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3),
+ RB(0x34, 4), RB(0x34, 5), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6),
+ RB(0x34, 7), RB(0x34, 8), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24),
+ RB(0x40, 25), RB(0x40, 26), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27),
+ RB(0x40, 28), RB(0x40, 29), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0),
+ RB(0x44, 1), RB(0x44, 2), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3),
+ RB(0x44, 4), RB(0x44, 5), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6),
+ RB(0x44, 7), RB(0x44, 8), RB(0x00, 0),
+ RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
+ /*
+ * These are not hardware clocks, but are needed to handle the special
+ * case where we have a 'selector bit' that doesn't just change the
+ * parent for a clock, but also the gate it's supposed to use.
+ */
+ {
+ .index = R9A06G032_UART_GROUP_012,
+ .name = "uart_group_012",
+ .type = K_BITSEL,
+ .source = 1 + R9A06G032_DIV_UART,
+ /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
+ .dual.sel = RB(0x34, 30),
+ .dual.group = 0,
+ },
+ {
+ .index = R9A06G032_UART_GROUP_34567,
+ .name = "uart_group_34567",
+ .type = K_BITSEL,
+ .source = 1 + R9A06G032_DIV_P2_PG,
+ /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
+ .dual.sel = RB(0xec, 24),
+ .dual.group = 1,
+ },
+ D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0,
+ RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)),
+ D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0,
+ RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)),
+ D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0,
+ RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)),
+ D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1,
+ RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)),
+ D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1,
+ RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)),
+ D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1,
+ RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)),
+ D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1,
+ RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)),
+ D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1,
+ RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)),
+};
+
+struct r9a06g032_priv {
+ struct regmap *regmap;
+ struct clk mclk;
+};
+
+static const struct r9a06g032_clkdesc *r9a06g032_clk_get(struct clk *clk)
+{
+ const unsigned long clkid = clk->id & 0xffff;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); i++) {
+ if (r9a06g032_clocks[i].index == clkid)
+ return &r9a06g032_clocks[i];
+ }
+
+ return NULL;
+}
+
+#define PARENT_ID (~0)
+
+static int r9a06g032_clk_get_parent(struct clk *clk, struct clk *parent)
+{
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+
+ if (!desc)
+ return -ENOENT;
+
+ if (desc->source)
+ parent->id = desc->source - 1;
+ else
+ parent->id = PARENT_ID; /* Top-level clock */
+
+ parent->dev = clk->dev;
+
+ return 0;
+}
+
+static ulong r9a06g032_clk_get_parent_rate(struct clk *clk)
+{
+ struct clk parent;
+ unsigned long parent_rate;
+ struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
+
+ if (r9a06g032_clk_get_parent(clk, &parent)) {
+ dev_dbg(clk->dev, "Failed to get parent clock for id=%lu\b", clk->id);
+ return 0;
+ }
+
+ if (parent.id == PARENT_ID)
+ parent_rate = clk_get_rate(&clocks->mclk);
+ else
+ parent_rate = clk_get_rate(&parent);
+
+ if (!parent_rate)
+ dev_dbg(clk->dev, "%s: parent_rate is zero\n", __func__);
+
+ return parent_rate;
+}
+
+/* register/bit pairs are encoded as an uint16_t */
+static void clk_rdesc_set(struct r9a06g032_priv *clocks,
+ struct regbit rb, unsigned int on)
+{
+ uint reg = rb.reg * 4;
+ uint bit = rb.bit;
+
+ if (!reg && !bit)
+ return;
+
+ uint mask = BIT(bit);
+ uint val = (!!on) << bit;
+
+ regmap_update_bits(clocks->regmap, reg, mask, val);
+}
+
+static int clk_rdesc_get(struct r9a06g032_priv *clocks,
+ struct regbit rb)
+{
+ uint reg = rb.reg * 4;
+ uint bit = rb.bit;
+ u32 val = 0;
+
+ regmap_read(clocks->regmap, reg, &val);
+
+ return !!(val & BIT(bit));
+}
+
+/*
+ * Cheating a little bit here: leverage the existing code to control the
+ * per-clock reset. It should really be handled by a reset controller instead.
+ */
+void clk_rzn1_reset_state(struct clk *clk, int on)
+{
+ struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+ const struct r9a06g032_gate *g;
+
+ assert(desc);
+ assert(desc->type == K_GATE);
+ g = &desc->gate;
+
+ clk_rdesc_set(clocks, g->reset, on);
+}
+
+/*
+ * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
+ * clock gate framework as the gates on the R9A06G032 have a special enabling
+ * sequence, therefore we use this little proxy.
+ */
+static int r9a06g032_clk_gate_set(struct clk *clk, int on)
+{
+ struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+ const struct r9a06g032_gate *g;
+
+ assert(desc);
+ assert(desc->type == K_GATE);
+ g = &desc->gate;
+
+ /* Enable or disable the clock */
+ clk_rdesc_set(clocks, g->gate, on);
+
+ /* De-assert reset */
+ clk_rdesc_set(clocks, g->reset, 1);
+
+ /* Hardware manual recommends 5us delay after enabling clock & reset */
+ udelay(5);
+
+ /* If the peripheral is memory mapped (i.e. an AXI slave), there is an
+ * associated SLVRDY bit in the System Controller that needs to be set
+ * so that the FlexWAY bus fabric passes on the read/write requests.
+ */
+ clk_rdesc_set(clocks, g->ready, on);
+
+ /* Clear 'Master Idle Request' bit */
+ clk_rdesc_set(clocks, g->midle, !on);
+
+ /* Note: We don't wait for FlexWAY Socket Connection signal */
+
+ return 0;
+}
+
+static int r9a06g032_clk_gate_enable(struct clk *clk)
+{
+ return r9a06g032_clk_gate_set(clk, 1);
+}
+
+static int r9a06g032_clk_gate_disable(struct clk *clk)
+{
+ return r9a06g032_clk_gate_set(clk, 0);
+}
+
+/*
+ * Fixed factor clock
+ */
+static ulong r9a06g032_ffc_get_rate(struct clk *clk)
+{
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+ unsigned long parent_rate = r9a06g032_clk_get_parent_rate(clk);
+ unsigned long long rate;
+
+ rate = (unsigned long long)parent_rate * desc->mul;
+ rate = DIV_ROUND_UP(rate, desc->div);
+
+ return (ulong)rate;
+}
+
+/*
+ * This implements R9A06G032 clock divider 'driver'. This differs from the
+ * standard clk_divider because the set_rate method must also set b[31] to
+ * trigger the hardware rate change. In theory it should also wait for this
+ * bit to clear.
+ */
+static ulong r9a06g032_div_get_rate(struct clk *clk)
+{
+ struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+ unsigned long parent_rate = r9a06g032_clk_get_parent_rate(clk);
+ u32 div = 0;
+
+ regmap_read(clocks->regmap, 4 * desc->reg, &div);
+
+ if (div < desc->div_min)
+ div = desc->div_min;
+ else if (div > desc->div_max)
+ div = desc->div_max;
+ return DIV_ROUND_UP(parent_rate, div);
+}
+
+static ulong r9a06g032_div_set_rate(struct clk *clk, ulong rate)
+{
+ struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+ unsigned long parent_rate = r9a06g032_clk_get_parent_rate(clk);
+ size_t i;
+
+ /* + 1 to cope with rates that have the remainder dropped */
+ u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
+
+ /* Clamp to allowable range */
+ if (div < desc->div_min)
+ div = desc->div_min;
+ else if (div > desc->div_max)
+ div = desc->div_max;
+
+ /* Limit to allowable divisors */
+ for (i = 0; i < ARRAY_SIZE(desc->div_table) - 2; i++) {
+ u16 div_m = desc->div_table[i];
+ u16 div_p = desc->div_table[i + 1];
+
+ if (!div_m || !div_p)
+ continue;
+
+ if (div >= div_m && div <= div_p) {
+ /*
+ * select the divider that generates
+ * the value closest to ideal frequency
+ */
+ u32 m = rate - DIV_ROUND_UP(parent_rate, div_m);
+ u32 p = DIV_ROUND_UP(parent_rate, div_p) - rate;
+
+ div = p >= m ? div_m : div_p;
+ }
+ }
+
+ dev_dbg(clk->dev, "%s clkid %lu rate %ld parent %ld div %d\n",
+ __func__, clk->id, rate, parent_rate, div);
+
+ /*
+ * Need to write the bit 31 with the divider value to
+ * latch it. Technically we should wait until it has been
+ * cleared too.
+ * TODO: Find whether this callback is sleepable, in case
+ * the hardware /does/ require some sort of spinloop here.
+ */
+ regmap_write(clocks->regmap, 4 * desc->reg, div | BIT(31));
+
+ return 0;
+}
+
+/*
+ * Dual gate. This handles toggling the approprate clock/reset bits,
+ * which depends on the mux setting above.
+ */
+static int r9a06g032_clk_dualgate_setenable(struct r9a06g032_priv *clocks,
+ const struct r9a06g032_clkdesc *desc,
+ int enable)
+{
+ u8 sel_bit = clk_rdesc_get(clocks, desc->dual.sel);
+ struct regbit gate[2] = { desc->dual.g1, desc->dual.g2 };
+ struct regbit reset[2] = { desc->dual.r1, desc->dual.r2 };
+
+ /* we always turn off the 'other' gate, regardless */
+ clk_rdesc_set(clocks, gate[!sel_bit], 0);
+ clk_rdesc_set(clocks, reset[!sel_bit], 1);
+
+ /* set the gate as requested */
+ clk_rdesc_set(clocks, gate[sel_bit], enable);
+ clk_rdesc_set(clocks, reset[sel_bit], 1);
+
+ return 0;
+}
+
+static int r9a06g032_clk_dualgate_enable(struct clk *clk)
+{
+ struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+
+ return r9a06g032_clk_dualgate_setenable(clocks, desc, 1);
+}
+
+static int r9a06g032_clk_dualgate_disable(struct clk *clk)
+{
+ struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+
+ return r9a06g032_clk_dualgate_setenable(clocks, desc, 0);
+}
+
+static int r9a06g032_clk_dualgate_is_enabled(struct clk *clk)
+{
+ struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+ u8 sel_bit = clk_rdesc_get(clocks, desc->dual.sel);
+ struct regbit gate[2] = { desc->dual.g1, desc->dual.g2 };
+
+ return clk_rdesc_get(clocks, gate[sel_bit]);
+}
+
+/*
+ * Main clock driver
+ */
+static int r9a06g032_clk_enable(struct clk *clk)
+{
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+
+ switch (desc->type) {
+ case K_GATE:
+ return r9a06g032_clk_gate_enable(clk);
+ case K_DUALGATE:
+ return r9a06g032_clk_dualgate_enable(clk);
+ default:
+ dev_dbg(clk->dev, "ERROR: unhandled type=%d\n", desc->type);
+ break;
+ }
+
+ return 0;
+}
+
+static int r9a06g032_clk_disable(struct clk *clk)
+{
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+
+ switch (desc->type) {
+ case K_GATE:
+ return r9a06g032_clk_gate_disable(clk);
+ case K_DUALGATE:
+ return r9a06g032_clk_dualgate_disable(clk);
+ default:
+ dev_dbg(clk->dev, "ERROR: unhandled type=%d\n", desc->type);
+ break;
+ }
+
+ return 0;
+}
+
+static ulong r9a06g032_clk_get_rate(struct clk *clk)
+{
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+ ulong ret = 0;
+
+ assert(desc);
+
+ switch (desc->type) {
+ case K_FFC:
+ ret = r9a06g032_ffc_get_rate(clk);
+ break;
+ case K_GATE:
+ ret = r9a06g032_clk_get_parent_rate(clk);
+ break;
+ case K_DIV:
+ ret = r9a06g032_div_get_rate(clk);
+ break;
+ case K_BITSEL:
+ /*
+ * Look at the mux to determine parent.
+ * 0 means it is coming from UART DIV (group 012 or 34567)
+ * 1 means it is coming from USB_PLL (fixed at 48MHz)
+ */
+ if (r9a06g032_clk_dualgate_is_enabled(clk)) {
+ struct clk usb_clk = { .id = R9A06G032_CLK_PLL_USB };
+
+ ret = r9a06g032_clk_get_parent_rate(&usb_clk);
+ } else {
+ ret = r9a06g032_clk_get_parent_rate(clk);
+ }
+ break;
+ case K_DUALGATE:
+ ret = r9a06g032_clk_get_parent_rate(clk);
+ break;
+ }
+
+ return ret;
+}
+
+static ulong r9a06g032_clk_set_rate(struct clk *clk, ulong rate)
+{
+ const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);
+ ulong ret = 0;
+
+ assert(desc);
+
+ switch (desc->type) {
+ case K_DIV:
+ ret = r9a06g032_div_set_rate(clk, rate);
+ break;
+ default:
+ dev_dbg(clk->dev, "ERROR: not implemented for %d\n", desc->type);
+ };
+
+ return ret;
+}
+
+static int r9a06g032_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 1) {
+ dev_dbg(clk->dev, "Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ clk->id = args->args[0];
+
+ return 0;
+}
+
+static const struct clk_ops r9a06g032_clk_ops = {
+ .enable = r9a06g032_clk_enable,
+ .disable = r9a06g032_clk_disable,
+ .get_rate = r9a06g032_clk_get_rate,
+ .set_rate = r9a06g032_clk_set_rate,
+ .of_xlate = r9a06g032_clk_of_xlate,
+};
+
+/* Reset Enable Register */
+#define RZN1_SYSCTRL_REG_RSTEN 288 /* 0x120*/
+#define RZN1_SYSCTRL_REG_RSTEN_MRESET_EN BIT(0)
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_CA7_0_EN BIT(1)
+#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_CA7_1_EN BIT(2)
+#define RZN1_SYSCTRL_REG_RSTEN_WDM3RST_EN BIT(3)
+#define RZN1_SYSCTRL_REG_RSTEN_CM3LOCKUPRST_EN BIT(4)
+#define RZN1_SYSCTRL_REG_RSTEN_CM3SYSRESET_EN BIT(5)
+#define RZN1_SYSCTRL_REG_RSTEN_SWRST_EN BIT(6)
+
+static int r9a06g032_clk_probe(struct udevice *dev)
+{
+ struct r9a06g032_priv *priv = dev_get_priv(dev);
+
+ priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap");
+ if (IS_ERR(priv->regmap)) {
+ dev_dbg(dev, "unable to find regmap\n");
+ return PTR_ERR(priv->regmap);
+ }
+
+ /* Enable S/W reset */
+ regmap_write(priv->regmap, RZN1_SYSCTRL_REG_RSTEN,
+ RZN1_SYSCTRL_REG_RSTEN_MRESET_EN |
+ RZN1_SYSCTRL_REG_RSTEN_SWRST_EN);
+
+ /* Get master clock */
+ return clk_get_by_name(dev, "mclk", &priv->mclk);
+}
+
+static const struct udevice_id r9a06g032_clk_ids[] = {
+ { .compatible = "renesas,r9a06g032-sysctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_r9a06g032) = {
+ .name = "clk_r9a06g032",
+ .id = UCLASS_CLK,
+ .of_match = r9a06g032_clk_ids,
+ .priv_auto = sizeof(struct r9a06g032_priv),
+ .ops = &r9a06g032_clk_ops,
+ .probe = &r9a06g032_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 852adee..fc1f01a 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
obj-$(CONFIG_ARCH_NPCM) += nuvoton/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
+obj-$(CONFIG_ARCH_RZN1) += renesas/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 509cdd3..0ea39b4 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -139,3 +139,10 @@ config PINCTRL_PFC_R7S72100
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
endif
+
+config PINCTRL_RZN1
+ bool "Renesas RZ/N1 R906G032 pin control driver"
+ depends on RZN1
+ default y if RZN1
+ help
+ Support pin multiplexing control on Renesas RZ/N1 R906G032 SoCs.
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 5cea142..1a61c39 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c
new file mode 100644
index 0000000..fdc43c8
--- /dev/null
+++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
+ *
+ * Phil Edworthy <phil.edworthy@renesas.com>
+ * Based on a driver originally written by Michel Pollet at Renesas.
+ */
+
+#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
+
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <dm/read.h>
+#include <regmap.h>
+
+/* Field positions and masks in the pinmux registers */
+#define RZN1_L1_PIN_DRIVE_STRENGTH 10
+#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
+#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
+#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
+#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
+#define RZN1_L1_PIN_PULL 8
+#define RZN1_L1_PIN_PULL_NONE 0
+#define RZN1_L1_PIN_PULL_UP 1
+#define RZN1_L1_PIN_PULL_DOWN 3
+#define RZN1_L1_FUNCTION 0
+#define RZN1_L1_FUNC_MASK 0xf
+#define RZN1_L1_FUNCTION_L2 0xf
+
+/*
+ * The hardware manual describes two levels of multiplexing, but it's more
+ * logical to think of the hardware as three levels, with level 3 consisting of
+ * the multiplexing for Ethernet MDIO signals.
+ *
+ * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
+ * that level 2 functions are used instead. Level 2 has a lot more options,
+ * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
+ * floating, or one of seven internal peripherals. Unfortunately, there are two
+ * level 2 functions that can select MDIO, and two MDIO channels so we have four
+ * sets of level 3 functions.
+ *
+ * For this driver, we've compounded the numbers together, so:
+ * 0 to 9 is level 1
+ * 10 to 71 is 10 + level 2 number
+ * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
+ * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
+ * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
+ * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
+ * Examples:
+ * Function 28 corresponds UART0
+ * Function 73 corresponds to MDIO0 to GMAC0
+ *
+ * There are 170 configurable pins (called PL_GPIO in the datasheet).
+ */
+
+/*
+ * Structure detailing the HW registers on the RZ/N1 devices.
+ * Both the Level 1 mux registers and Level 2 mux registers have the same
+ * structure. The only difference is that Level 2 has additional MDIO registers
+ * at the end.
+ */
+struct rzn1_pinctrl_regs {
+ u32 conf[170];
+ u32 pad0[86];
+ u32 status_protect; /* 0x400 */
+ /* MDIO mux registers, level2 only */
+ u32 l2_mdio[2];
+};
+
+#define NUM_CONF ARRAY_SIZE(((struct rzn1_pinctrl_regs *)0)->conf)
+
+#define level1_write(map, member, val) \
+ regmap_range_set(map, 0, struct rzn1_pinctrl_regs, member, val)
+
+#define level1_read(map, member, valp) \
+ regmap_range_get(map, 0, struct rzn1_pinctrl_regs, member, valp)
+
+#define level2_write(map, member, val) \
+ regmap_range_set(map, 1, struct rzn1_pinctrl_regs, member, val)
+
+#define level2_read(map, member, valp) \
+ regmap_range_get(map, 1, struct rzn1_pinctrl_regs, member, valp)
+
+/**
+ * struct rzn1_pmx_func - describes rzn1 pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct rzn1_pmx_func {
+ const char *name;
+ const char **groups;
+ unsigned int num_groups;
+};
+
+/**
+ * struct rzn1_pin_group - describes an rzn1 pin group
+ * @name: the name of this specific pin group
+ * @func: the name of the function selected by this group
+ * @npins: the number of pins in this group array, i.e. the number of
+ * elements in .pins so we can iterate over that array
+ * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
+ * @pin_ids: array of pin_ids, i.e. the value used to select the mux
+ */
+struct rzn1_pin_group {
+ const char *name;
+ const char *func;
+ unsigned int npins;
+ unsigned int *pins;
+ u8 *pin_ids;
+};
+
+struct rzn1_pinctrl {
+ struct device *dev;
+ struct clk *clk;
+ struct pinctrl_dev *pctl;
+ u32 lev1_protect_phys;
+ u32 lev2_protect_phys;
+ int mdio_func[2];
+
+ struct rzn1_pin_group *groups;
+ unsigned int ngroups;
+
+ struct rzn1_pmx_func *functions;
+ unsigned int nfunctions;
+};
+
+struct rzn1_pinctrl_priv {
+ struct regmap *regmap;
+ u32 lev1_protect_phys;
+ u32 lev2_protect_phys;
+
+ struct clk *clk;
+};
+
+enum {
+ LOCK_LEVEL1 = 0x1,
+ LOCK_LEVEL2 = 0x2,
+ LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
+};
+
+static void rzn1_hw_set_lock(struct rzn1_pinctrl_priv *priv, u8 lock, u8 value)
+{
+ /*
+ * The pinmux configuration is locked by writing the physical address of
+ * the status_protect register to itself. It is unlocked by writing the
+ * address | 1.
+ */
+ if (lock & LOCK_LEVEL1) {
+ u32 val = priv->lev1_protect_phys | !(value & LOCK_LEVEL1);
+
+ level1_write(priv->regmap, status_protect, val);
+ }
+
+ if (lock & LOCK_LEVEL2) {
+ u32 val = priv->lev2_protect_phys | !(value & LOCK_LEVEL2);
+
+ level2_write(priv->regmap, status_protect, val);
+ }
+}
+
+static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl_priv *priv, int mdio,
+ u32 func)
+{
+ debug("setting mdio%d to %u\n", mdio, func);
+
+ level2_write(priv->regmap, l2_mdio[mdio], func);
+}
+
+/*
+ * Using a composite pin description, set the hardware pinmux registers
+ * with the corresponding values.
+ * Make sure to unlock write protection and reset it afterward.
+ *
+ * NOTE: There is no protection for potential concurrency, it is assumed these
+ * calls are serialized already.
+ */
+static int rzn1_set_hw_pin_func(struct rzn1_pinctrl_priv *priv,
+ unsigned int pin, unsigned int func)
+{
+ u32 l1_cache;
+ u32 l2_cache;
+ u32 l1;
+ u32 l2;
+
+ /* Level 3 MDIO multiplexing */
+ if (func >= RZN1_FUNC_MDIO0_HIGHZ &&
+ func <= RZN1_FUNC_MDIO1_E1_SWITCH) {
+ int mdio_channel;
+ u32 mdio_func;
+
+ if (func <= RZN1_FUNC_MDIO1_HIGHZ)
+ mdio_channel = 0;
+ else
+ mdio_channel = 1;
+
+ /* Get MDIO func, and convert the func to the level 2 number */
+ if (func <= RZN1_FUNC_MDIO0_SWITCH) {
+ mdio_func = func - RZN1_FUNC_MDIO0_HIGHZ;
+ func = RZN1_FUNC_ETH_MDIO;
+ } else if (func <= RZN1_FUNC_MDIO0_E1_SWITCH) {
+ mdio_func = func - RZN1_FUNC_MDIO0_E1_HIGHZ;
+ func = RZN1_FUNC_ETH_MDIO_E1;
+ } else if (func <= RZN1_FUNC_MDIO1_SWITCH) {
+ mdio_func = func - RZN1_FUNC_MDIO1_HIGHZ;
+ func = RZN1_FUNC_ETH_MDIO;
+ } else {
+ mdio_func = func - RZN1_FUNC_MDIO1_E1_HIGHZ;
+ func = RZN1_FUNC_ETH_MDIO_E1;
+ }
+ rzn1_pinctrl_mdio_select(priv, mdio_channel, mdio_func);
+ }
+
+ /* Note here, we do not allow anything past the MDIO Mux values */
+ if (pin >= NUM_CONF || func >= RZN1_FUNC_MDIO0_HIGHZ)
+ return -EINVAL;
+
+ level1_read(priv->regmap, conf[pin], &l1);
+ l1_cache = l1;
+ level2_read(priv->regmap, conf[pin], &l2);
+ l2_cache = l2;
+
+ debug("setting func for pin %u to %u\n", pin, func);
+
+ l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
+
+ if (func < RZN1_FUNC_L2_OFFSET) {
+ l1 |= (func << RZN1_L1_FUNCTION);
+ } else {
+ l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
+
+ l2 = func - RZN1_FUNC_L2_OFFSET;
+ }
+
+ /* If either configuration changes, we update both anyway */
+ if (l1 != l1_cache || l2 != l2_cache) {
+ level1_write(priv->regmap, conf[pin], l1);
+ level2_write(priv->regmap, conf[pin], l2);
+ }
+
+ return 0;
+}
+
+static int rzn1_pinconf_set(struct rzn1_pinctrl_priv *priv, unsigned int pin,
+ unsigned int bias, unsigned int strength)
+{
+ u32 l1, l1_cache;
+ u32 drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
+
+ level1_read(priv->regmap, conf[pin], &l1);
+ l1_cache = l1;
+
+ switch (bias) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ debug("set pin %d pull up\n", pin);
+ l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
+ l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ debug("set pin %d pull down\n", pin);
+ l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
+ l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ debug("set pin %d bias off\n", pin);
+ l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
+ l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
+ break;
+ }
+
+ switch (strength) {
+ case 4:
+ drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
+ break;
+ case 6:
+ drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
+ break;
+ case 8:
+ drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
+ break;
+ case 12:
+ drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
+ break;
+ }
+
+ debug("set pin %d drv %umA\n", pin, drv);
+
+ l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
+ l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
+
+ if (l1 != l1_cache)
+ level1_write(priv->regmap, conf[pin], l1);
+
+ return 0;
+}
+
+static int rzn1_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ struct rzn1_pinctrl_priv *priv = dev_get_priv(dev);
+ int size;
+ int ret;
+ u32 val;
+ u32 bias;
+
+ /* Pullup/down bias, common to all pins in group */
+ bias = PIN_CONFIG_BIAS_PULL_UP;
+ if (dev_read_bool(config, "bias-disable"))
+ bias = PIN_CONFIG_BIAS_DISABLE;
+ else if (dev_read_bool(config, "bias-pull-up"))
+ bias = PIN_CONFIG_BIAS_PULL_UP;
+ else if (dev_read_bool(config, "bias-pull-down"))
+ bias = PIN_CONFIG_BIAS_PULL_DOWN;
+
+ /* Drive strength, common to all pins in group */
+ u32 strength = dev_read_u32_default(config, "drive-strength", 8);
+
+ /* Number of pins */
+ ret = dev_read_size(config, "pinmux");
+ if (ret < 0)
+ return ret;
+
+ size = ret / sizeof(val);
+
+ for (int i = 0; i < size; i++) {
+ ret = dev_read_u32_index(config, "pinmux", i, &val);
+ if (ret)
+ return ret;
+ unsigned int pin = val & 0xff;
+ unsigned int func = val >> 8;
+
+ debug("%s pin %d func %d bias %d strength %d\n",
+ config->name, pin, func, bias, strength);
+
+ rzn1_hw_set_lock(priv, LOCK_ALL, LOCK_ALL);
+ rzn1_set_hw_pin_func(priv, pin, func);
+ rzn1_pinconf_set(priv, pin, bias, strength);
+ rzn1_hw_set_lock(priv, LOCK_ALL, 0);
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops rzn1_pinctrl_ops = {
+ .set_state = rzn1_pinctrl_set_state,
+};
+
+static int rzn1_pinctrl_probe(struct udevice *dev)
+{
+ struct rzn1_pinctrl_priv *priv = dev_get_priv(dev);
+ ofnode node = dev_ofnode(dev);
+ int ret;
+
+ ret = regmap_init_mem(node, &priv->regmap);
+ if (ret)
+ return ret;
+
+ priv->lev1_protect_phys = (u32)regmap_get_range(priv->regmap, 0) +
+ offsetof(struct rzn1_pinctrl_regs, status_protect);
+ priv->lev2_protect_phys = (u32)regmap_get_range(priv->regmap, 1) +
+ offsetof(struct rzn1_pinctrl_regs, status_protect);
+
+ return 0;
+}
+
+static const struct udevice_id rzn1_pinctrl_ids[] = {
+ { .compatible = "renesas,rzn1-pinctrl", },
+ { },
+};
+
+U_BOOT_DRIVER(pinctrl_rzn1) = {
+ .name = "rzn1-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rzn1_pinctrl_ids,
+ .priv_auto = sizeof(struct rzn1_pinctrl_priv),
+ .ops = &rzn1_pinctrl_ops,
+ .probe = rzn1_pinctrl_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 1acf212..bf99964 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -108,6 +108,7 @@ config IMXRT_SDRAM
This driver is for the sdram memory interface with the SEMC.
source "drivers/ram/aspeed/Kconfig"
+source "drivers/ram/cadence/Kconfig"
source "drivers/ram/rockchip/Kconfig"
source "drivers/ram/sifive/Kconfig"
source "drivers/ram/stm32mp1/Kconfig"
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 2b9429c..6eb1a24 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -24,3 +24,6 @@ ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
endif
obj-$(CONFIG_ARCH_OCTEON) += octeon/
+
+obj-$(CONFIG_ARCH_RMOBILE) += renesas/
+obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
diff --git a/drivers/ram/cadence/Kconfig b/drivers/ram/cadence/Kconfig
new file mode 100644
index 0000000..2d5469c
--- /dev/null
+++ b/drivers/ram/cadence/Kconfig
@@ -0,0 +1,12 @@
+if RAM || SPL_RAM
+
+config CADENCE_DDR_CTRL
+ bool "Enable Cadence DDR controller"
+ depends on DM
+ help
+ Enable support for Cadence DDR controller, as found on
+ the Renesas RZ/N1 SoC. This controller has a large number
+ of registers which need to be programmed, mostly using values
+ obtained from Denali SOMA files via a TCL script.
+
+endif
diff --git a/drivers/ram/cadence/Makefile b/drivers/ram/cadence/Makefile
new file mode 100644
index 0000000..b4226cf
--- /dev/null
+++ b/drivers/ram/cadence/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CADENCE_DDR_CTRL) += ddr_ctrl.o
diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c
new file mode 100644
index 0000000..3e5959a
--- /dev/null
+++ b/drivers/ram/cadence/ddr_ctrl.c
@@ -0,0 +1,414 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Cadence DDR Controller
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe Ltd
+ */
+
+/*
+ * The Cadence DDR Controller has a huge number of registers that principally
+ * cover two aspects, DDR specific timing information and AXI bus interfacing.
+ * Cadence's TCL script generates all of the register values for specific
+ * DDR devices operating at a specific frequency. The TCL script uses Denali
+ * SOMA files as inputs. The tool also generates the AXI bus register values as
+ * well, however this driver assumes that users will want to modifiy these to
+ * meet a specific application's needs.
+ * Therefore, this driver is passed two arrays containing register values for
+ * the DDR device specific information, and explicity sets the AXI registers.
+ *
+ * AXI bus interfacing:
+ * The controller has four AXI slaves connections, and each of these can be
+ * programmed to accept requests from specific AXI masters (using their IDs).
+ * The regions of DDR that can be accessed by each AXI slave can be set such
+ * as to isolate DDR used by one AXI master from another. Further, the maximum
+ * bandwidth allocated to each AXI slave can be set.
+ */
+
+#include <common.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <wait_bit.h>
+#include <renesas/ddr_ctrl.h>
+
+/* avoid warning for real pr_debug in <linux/printk.h> */
+#ifdef pr_debug
+#undef pr_debug
+#endif
+
+#ifdef DEBUG
+ #define pr_debug(fmt, args...) printf(fmt, ##args)
+ #define pr_debug2(fmt, args...) printf(fmt, ##args)
+#else
+ #define pr_debug(fmt, args...)
+ #define pr_debug2(fmt, args...)
+#endif
+
+#define DDR_NR_AXI_PORTS 4
+#define DDR_NR_ENTRIES 16
+
+#define DDR_START_REG (0) /* DENALI_CTL_00 */
+#define DDR_CS0_MR1_REG (32 * 4) /* DENALI_CTL_32 */
+#define DDR_CS0_MR2_REG (32 * 4 + 2) /* DENALI_CTL_32 */
+#define DDR_CS1_MR1_REG (34 * 4 + 2) /* DENALI_CTL_34 */
+#define DDR_CS1_MR2_REG (35 * 4) /* DENALI_CTL_35 */
+#define DDR_ECC_ENABLE_REG (36 * 4 + 2) /* DENALI_CTL_36 */
+#define DDR_ECC_DISABLE_W_UC_ERR_REG (37 * 4 + 2) /* DENALI_CTL_37 */
+#define DDR_HALF_DATAPATH_REG (54 * 4) /* DENALI_CTL_54 */
+#define DDR_INTERRUPT_STATUS (56 * 4) /* DENALI_CTL_56 */
+#define DDR_INTERRUPT_ACK (57 * 4) /* DENALI_CTL_57 */
+#define DDR_INTERRUPT_MASK (58 * 4) /* DENALI_CTL_58 */
+#define DDR_CS0_ODT_MAP_REG (62 * 4 + 2) /* DENALI_CTL_62 */
+#define DDR_CS1_ODT_MAP_REG (63 * 4) /* DENALI_CTL_63 */
+#define DDR_ODT_TODTL_2CMD (63 * 4 + 2) /* DENALI_CTL_63 */
+#define DDR_ODT_TODTH_WR (63 * 4 + 3) /* DENALI_CTL_63 */
+#define DDR_ODT_TODTH_RD (64 * 4 + 0) /* DENALI_CTL_64 */
+#define DDR_ODT_EN (64 * 4 + 1) /* DENALI_CTL_64 */
+#define DDR_ODT_WR_TO_ODTH (64 * 4 + 2) /* DENALI_CTL_64 */
+#define DDR_ODT_RD_TO_ODTH (64 * 4 + 3) /* DENALI_CTL_64 */
+#define DDR_DIFF_CS_DELAY_REG (66 * 4) /* DENALI_CTL_66 */
+#define DDR_SAME_CS_DELAY_REG (67 * 4) /* DENALI_CTL_67 */
+#define DDR_RW_PRIORITY_REGS (87 * 4 + 2) /* DENALI_CTL_87 */
+#define DDR_RW_FIFO_TYPE_REGS (88 * 4) /* DENALI_CTL_88 */
+#define DDR_AXI_PORT_PROT_ENABLE_REG (90 * 4 + 3) /* DENALI_CTL_90 */
+#define DDR_ADDR_RANGE_REGS (91 * 4) /* DENALI_CTL_91 */
+#define DDR_RANGE_PROT_REGS (218 * 4 + 2) /* DENALI_CTL_218 */
+#define DDR_ARB_CMD_Q_THRESHOLD_REG (346 * 4 + 2) /* DENALI_CTL_346 */
+#define DDR_AXI_PORT_BANDWIDTH_REG (346 * 4 + 3) /* DENALI_CTL_346 */
+#define DDR_OPT_RMODW_REG (372 * 4 + 3) /* DENALI_CTL_372 */
+
+static void ddrc_writeb(u8 val, void *p)
+{
+ pr_debug2("DDR: %p = 0x%02x\n", p, val);
+ writeb(val, p);
+}
+
+static void ddrc_writew(u16 val, void *p)
+{
+ pr_debug2("DDR: %p = 0x%04x\n", p, val);
+ writew(val, p);
+}
+
+static void ddrc_writel(u32 val, void *p)
+{
+ pr_debug2("DDR: %p = 0x%08x\n", p, val);
+ writel(val, p);
+}
+
+void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength)
+{
+ void *reg;
+ u16 tmp;
+
+ if (cs == 0)
+ reg = (u8 *)base + DDR_CS0_MR1_REG;
+ else
+ reg = (u8 *)base + DDR_CS1_MR1_REG;
+
+ tmp = readw(reg);
+
+ tmp &= ~MODE_REGISTER_MASK;
+ tmp |= MODE_REGISTER_MR1;
+
+ tmp &= ~MR1_ODT_IMPEDANCE_MASK;
+ tmp |= odt_impedance;
+
+ tmp &= ~MR1_DRIVE_STRENGTH_MASK;
+ tmp |= drive_strength;
+
+ writew(tmp, reg);
+}
+
+void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp)
+{
+ void *reg;
+ u16 tmp;
+
+ if (cs == 0)
+ reg = (u8 *)base + DDR_CS0_MR2_REG;
+ else
+ reg = (u8 *)base + DDR_CS1_MR2_REG;
+
+ tmp = readw(reg);
+
+ tmp &= ~MODE_REGISTER_MASK;
+ tmp |= MODE_REGISTER_MR2;
+
+ tmp &= ~MR2_DYNAMIC_ODT_MASK;
+ tmp |= dynamic_odt;
+
+ tmp &= ~MR2_SELF_REFRESH_TEMP_MASK;
+ tmp |= self_refresh_temp;
+
+ writew(tmp, reg);
+}
+
+void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map)
+{
+ void *reg;
+
+ if (cs == 0)
+ reg = (u8 *)base + DDR_CS0_ODT_MAP_REG;
+ else
+ reg = (u8 *)base + DDR_CS1_ODT_MAP_REG;
+
+ writew(odt_map, reg);
+}
+
+void cdns_ddr_set_odt_times(void *base, u8 TODTL_2CMD, u8 TODTH_WR, u8 TODTH_RD,
+ u8 WR_TO_ODTH, u8 RD_TO_ODTH)
+{
+ writeb(TODTL_2CMD, (u8 *)base + DDR_ODT_TODTL_2CMD);
+ writeb(TODTH_WR, (u8 *)base + DDR_ODT_TODTH_WR);
+ writeb(TODTH_RD, (u8 *)base + DDR_ODT_TODTH_RD);
+ writeb(1, (u8 *)base + DDR_ODT_EN);
+ writeb(WR_TO_ODTH, (u8 *)base + DDR_ODT_WR_TO_ODTH);
+ writeb(RD_TO_ODTH, (u8 *)base + DDR_ODT_RD_TO_ODTH);
+}
+
+void cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w)
+{
+ u32 val = (w2w << 24) | (w2r << 16) | (r2w << 8) | r2r;
+
+ writel(val, (u8 *)base + DDR_SAME_CS_DELAY_REG);
+}
+
+void cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w)
+{
+ u32 val = (w2w << 24) | (w2r << 16) | (r2w << 8) | r2r;
+
+ writel(val, (u8 *)base + DDR_DIFF_CS_DELAY_REG);
+}
+
+void cdns_ddr_set_port_rw_priority(void *base, int port,
+ u8 read_pri, u8 write_pri)
+{
+ u8 *reg8 = (u8 *)base + DDR_RW_PRIORITY_REGS;
+
+ reg8 += (port * 3);
+ pr_debug("%s port %d (reg8=%p, DENALI_CTL_%d)\n",
+ __func__, port, reg8, (reg8 - (u8 *)base) / 4);
+
+ ddrc_writeb(read_pri, reg8++);
+ ddrc_writeb(write_pri, reg8++);
+}
+
+/* The DDR Controller has 16 entries. Each entry can specify an allowed address
+ * range (with 16KB resolution) for one of the 4 AXI slave ports.
+ */
+void cdns_ddr_enable_port_addr_range(void *base, int port, int entry,
+ u32 addr_start, u32 size)
+{
+ u32 addr_end;
+ u32 *reg32 = (u32 *)((u8 *)base + DDR_ADDR_RANGE_REGS);
+ u32 tmp;
+
+ reg32 += (port * DDR_NR_ENTRIES * 2);
+ reg32 += (entry * 2);
+ pr_debug("%s port %d, entry %d (reg32=%p, DENALI_CTL_%d)\n",
+ __func__, port, entry, reg32, ((u8 *)reg32 - (u8 *)base) / 4);
+
+ /* These registers represent 16KB address blocks */
+ addr_start /= SZ_16K;
+ size /= SZ_16K;
+ if (size)
+ addr_end = addr_start + size - 1;
+ else
+ addr_end = addr_start;
+
+ ddrc_writel(addr_start, reg32++);
+
+ /*
+ * end_addr: Ensure we only set the bottom 18-bits as DENALI_CTL_218
+ * also contains the AXI0 range protection bits.
+ */
+ tmp = readl(reg32);
+ tmp &= ~(BIT(18) - 1);
+ tmp |= addr_end;
+ ddrc_writel(tmp, reg32);
+}
+
+void cdns_ddr_enable_addr_range(void *base, int entry,
+ u32 addr_start, u32 size)
+{
+ int axi;
+
+ for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++)
+ cdns_ddr_enable_port_addr_range(base, axi, entry,
+ addr_start, size);
+}
+
+void cdns_ddr_enable_port_prot(void *base, int port, int entry,
+ enum cdns_ddr_range_prot range_protection_bits,
+ u16 range_RID_check_bits,
+ u16 range_WID_check_bits,
+ u8 range_RID_check_bits_ID_lookup,
+ u8 range_WID_check_bits_ID_lookup)
+{
+ /*
+ * Technically, the offset here points to the byte before the start of
+ * the range protection registers. However, all entries consist of 8
+ * bytes, except the first one (which is missing a padding byte) so we
+ * work around that subtlely.
+ */
+ u8 *reg8 = (u8 *)base + DDR_RANGE_PROT_REGS;
+
+ reg8 += (port * DDR_NR_ENTRIES * 8);
+ reg8 += (entry * 8);
+ pr_debug("%s port %d, entry %d (reg8=%p, DENALI_CTL_%d)\n",
+ __func__, port, entry, reg8, (reg8 - (u8 *)base) / 4);
+
+ if (port == 0 && entry == 0)
+ ddrc_writeb(range_protection_bits, reg8 + 1);
+ else
+ ddrc_writeb(range_protection_bits, reg8);
+
+ ddrc_writew(range_RID_check_bits, reg8 + 2);
+ ddrc_writew(range_WID_check_bits, reg8 + 4);
+ ddrc_writeb(range_RID_check_bits_ID_lookup, reg8 + 6);
+ ddrc_writeb(range_WID_check_bits_ID_lookup, reg8 + 7);
+}
+
+void cdns_ddr_enable_prot(void *base, int entry,
+ enum cdns_ddr_range_prot range_protection_bits,
+ u16 range_RID_check_bits,
+ u16 range_WID_check_bits,
+ u8 range_RID_check_bits_ID_lookup,
+ u8 range_WID_check_bits_ID_lookup)
+{
+ int axi;
+
+ for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++)
+ cdns_ddr_enable_port_prot(base, axi, entry,
+ range_protection_bits,
+ range_RID_check_bits,
+ range_WID_check_bits,
+ range_RID_check_bits_ID_lookup,
+ range_WID_check_bits_ID_lookup);
+}
+
+void cdns_ddr_set_port_bandwidth(void *base, int port,
+ u8 max_percent, u8 overflow_ok)
+{
+ u8 *reg8 = (u8 *)base + DDR_AXI_PORT_BANDWIDTH_REG;
+
+ reg8 += (port * 3);
+ pr_debug("%s port %d, (reg8=%p, DENALI_CTL_%d)\n",
+ __func__, port, reg8, (reg8 - (u8 *)base) / 4);
+
+ ddrc_writeb(max_percent, reg8++); /* Maximum bandwidth percentage */
+ ddrc_writeb(overflow_ok, reg8++); /* Bandwidth overflow allowed */
+}
+
+void cdns_ddr_ctrl_init(void *ddr_ctrl_basex, int async,
+ const u32 *reg0, const u32 *reg350,
+ u32 ddr_start_addr, u32 ddr_size,
+ int enable_ecc, int enable_8bit)
+{
+ int i, axi, entry;
+ u32 *ddr_ctrl_base = (u32 *)ddr_ctrl_basex;
+ u8 *base8 = (u8 *)ddr_ctrl_basex;
+
+ ddrc_writel(*reg0, ddr_ctrl_base + 0);
+ /* 1 to 6 are read only */
+ for (i = 7; i <= 26; i++)
+ ddrc_writel(*(reg0 + i), ddr_ctrl_base + i);
+ /* 27 to 29 are not changed */
+ for (i = 30; i <= 87; i++)
+ ddrc_writel(*(reg0 + i), ddr_ctrl_base + i);
+
+ /* Enable/disable ECC */
+ if (enable_ecc) {
+ pr_debug("%s enabling ECC\n", __func__);
+ ddrc_writeb(1, base8 + DDR_ECC_ENABLE_REG);
+ } else {
+ ddrc_writeb(0, base8 + DDR_ECC_ENABLE_REG);
+ }
+
+ /* ECC: Disable corruption for read/modify/write operations */
+ ddrc_writeb(1, base8 + DDR_ECC_DISABLE_W_UC_ERR_REG);
+
+ /* Set 8/16-bit data width using reduce bit (enable half datapath)*/
+ if (enable_8bit) {
+ pr_debug("%s using 8-bit data\n", __func__);
+ ddrc_writeb(1, base8 + DDR_HALF_DATAPATH_REG);
+ } else {
+ ddrc_writeb(0, base8 + DDR_HALF_DATAPATH_REG);
+ }
+
+ /* Threshold for command queue */
+ ddrc_writeb(4, base8 + DDR_ARB_CMD_Q_THRESHOLD_REG);
+
+ /* AXI port protection => enable */
+ ddrc_writeb(0x01, base8 + DDR_AXI_PORT_PROT_ENABLE_REG);
+
+ /* Set port interface type, default port priority and bandwidths */
+ for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++) {
+ /* port interface type: synchronous or asynchronous AXI clock */
+ u8 *fifo_reg = base8 + DDR_RW_FIFO_TYPE_REGS + (axi * 3);
+
+ if (async)
+ ddrc_writeb(0, fifo_reg);
+ else
+ ddrc_writeb(3, fifo_reg);
+
+ /* R/W priorities */
+ cdns_ddr_set_port_rw_priority(ddr_ctrl_base, axi, 2, 2);
+
+ /* AXI bandwidth */
+ cdns_ddr_set_port_bandwidth(ddr_ctrl_base, axi, 50, 1);
+ }
+
+ /*
+ * The hardware requires that the valid address ranges must not overlap.
+ * So, we initialise all address ranges to be above the DDR, length 0.
+ */
+ for (entry = 0; entry < DDR_NR_ENTRIES; entry++)
+ cdns_ddr_enable_addr_range(ddr_ctrl_base, entry,
+ ddr_start_addr + ddr_size, 0);
+
+ for (i = 350; i <= 374; i++)
+ ddrc_writel(*(reg350 - 350 + i), ddr_ctrl_base + i);
+
+ /* Disable optimised read-modify-write logic */
+ ddrc_writeb(0, base8 + DDR_OPT_RMODW_REG);
+
+ /*
+ * Disable all interrupts, we are not handling them.
+ * For detail of the interrupt mask, ack and status bits, see the
+ * manual's description of the 'int_status' parameter.
+ */
+ ddrc_writel(0, base8 + DDR_INTERRUPT_MASK);
+
+ /*
+ * Default settings to enable full access to the entire DDR.
+ * Users can set different ranges and access rights by calling these
+ * functions before calling cdns_ddr_ctrl_start().
+ */
+ cdns_ddr_enable_addr_range(ddr_ctrl_base, 0,
+ ddr_start_addr, ddr_size);
+ cdns_ddr_enable_prot(ddr_ctrl_base, 0, CDNS_DDR_RANGE_PROT_BITS_FULL,
+ 0xffff, 0xffff, 0x0f, 0x0f);
+}
+
+void cdns_ddr_ctrl_start(void *ddr_ctrl_basex)
+{
+ u32 *ddr_ctrl_base = (u32 *)ddr_ctrl_basex;
+ u8 *base8 = (u8 *)ddr_ctrl_basex;
+
+ /* Start */
+ ddrc_writeb(1, base8 + DDR_START_REG);
+
+ /* Wait for controller to be ready (interrupt status) */
+ wait_for_bit_le32(base8 + DDR_INTERRUPT_STATUS, 0x100, true, 1000, false);
+
+ /* clear all interrupts */
+ ddrc_writel(~0, base8 + DDR_INTERRUPT_ACK);
+
+ /* Step 19 Wait 500us from MRESETB=1 */
+ udelay(500);
+
+ /* Step 20 tCKSRX wait (From supply stable clock for MCK) */
+ /* DENALI_CTL_19 TREF_ENABLE=0x1(=1), AREFRESH=0x1(=1) */
+ ddrc_writel(0x01000100, ddr_ctrl_base + 19);
+}
diff --git a/drivers/ram/renesas/Makefile b/drivers/ram/renesas/Makefile
new file mode 100644
index 0000000..705cc4b
--- /dev/null
+++ b/drivers/ram/renesas/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_RZN1) += rzn1/
diff --git a/drivers/ram/renesas/rzn1/Makefile b/drivers/ram/renesas/rzn1/Makefile
new file mode 100644
index 0000000..357c2a5
--- /dev/null
+++ b/drivers/ram/renesas/rzn1/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += ddr_async.o
diff --git a/drivers/ram/renesas/rzn1/ddr_async.c b/drivers/ram/renesas/rzn1/ddr_async.c
new file mode 100644
index 0000000..7a81497
--- /dev/null
+++ b/drivers/ram/renesas/rzn1/ddr_async.c
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * RZ/N1 DDR Controller initialisation
+ *
+ * The DDR Controller register values for a specific DDR device, mode and
+ * frequency are generated using a Cadence tool.
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe Ltd
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <wait_bit.h>
+#include <renesas/ddr_ctrl.h>
+
+void clk_rzn1_reset_state(struct clk *clk, int on);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct cadence_ddr_info {
+ struct udevice *dev;
+ void __iomem *ddrc;
+ void __iomem *phy;
+ struct clk clk_ddrc;
+ struct clk hclk_ddrc;
+ struct regmap *syscon;
+ bool enable_ecc;
+ bool enable_8bit;
+ u32 ddr_size;
+
+ /* These two used only during .probe */
+ u32 *reg0;
+ u32 *reg350;
+};
+
+static inline u32 cadence_readl(void __iomem *addr, unsigned int offset)
+{
+ return readl(addr + offset);
+}
+
+static inline void cadence_writel(void __iomem *addr, unsigned int offset,
+ u32 data)
+{
+ debug("%s: addr = 0x%p, value = 0x%08x\n", __func__, addr + offset, data);
+ writel(data, addr + offset);
+}
+
+#define ddrc_readl(off) cadence_readl(priv->ddrc, off)
+#define ddrc_writel(val, off) cadence_writel(priv->ddrc, off, val)
+
+#define phy_readl(off) cadence_readl(priv->phy, off)
+#define phy_writel(val, off) cadence_writel(priv->phy, off, val)
+
+#define RZN1_DDR3_SINGLE_BANK 3
+#define RZN1_DDR3_DUAL_BANK 32
+
+#define FUNCCTRL 0x00
+#define FUNCCTRL_MASKSDLOFS (0x18 << 16)
+#define FUNCCTRL_DVDDQ_1_5V BIT(8)
+#define FUNCCTRL_RESET_N BIT(0)
+#define DLLCTRL 0x04
+#define DLLCTRL_ASDLLOCK BIT(26)
+#define DLLCTRL_MFSL_500MHz (2 << 1)
+#define DLLCTRL_MDLLSTBY BIT(0)
+#define ZQCALCTRL 0x08
+#define ZQCALCTRL_ZQCALEND BIT(30)
+#define ZQCALCTRL_ZQCALRSTB BIT(0)
+#define ZQODTCTRL 0x0c
+#define RDCTRL 0x10
+#define RDTMG 0x14
+#define FIFOINIT 0x18
+#define FIFOINIT_RDPTINITEXE BIT(8)
+#define FIFOINIT_WRPTINITEXE BIT(0)
+#define OUTCTRL 0x1c
+#define OUTCTRL_ADCMDOE BIT(0)
+#define WLCTRL1 0x40
+#define WLCTRL1_WLSTR BIT(24)
+#define DQCALOFS1 0xe8
+
+/* DDR PHY setup */
+static void ddr_phy_init(struct cadence_ddr_info *priv, int ddr_type)
+{
+ u32 val;
+
+ /* Disable DDR Controller clock and FlexWAY connection */
+ clk_disable(&priv->hclk_ddrc);
+ clk_disable(&priv->clk_ddrc);
+
+ clk_rzn1_reset_state(&priv->hclk_ddrc, 0);
+ clk_rzn1_reset_state(&priv->clk_ddrc, 0);
+
+ /* Enable DDR Controller clock and FlexWAY connection */
+ clk_enable(&priv->clk_ddrc);
+ clk_enable(&priv->hclk_ddrc);
+
+ /* DDR PHY Soft reset assert */
+ ddrc_writel(FUNCCTRL_MASKSDLOFS | FUNCCTRL_DVDDQ_1_5V, FUNCCTRL);
+
+ clk_rzn1_reset_state(&priv->hclk_ddrc, 1);
+ clk_rzn1_reset_state(&priv->clk_ddrc, 1);
+
+ /* DDR PHY setup */
+ phy_writel(DLLCTRL_MFSL_500MHz | DLLCTRL_MDLLSTBY, DLLCTRL);
+ phy_writel(0x00000182, ZQCALCTRL);
+ if (ddr_type == RZN1_DDR3_DUAL_BANK)
+ phy_writel(0xAB330031, ZQODTCTRL);
+ else if (ddr_type == RZN1_DDR3_SINGLE_BANK)
+ phy_writel(0xAB320051, ZQODTCTRL);
+ else /* DDR2 */
+ phy_writel(0xAB330071, ZQODTCTRL);
+ phy_writel(0xB545B544, RDCTRL);
+ phy_writel(0x000000B0, RDTMG);
+ phy_writel(0x020A0806, OUTCTRL);
+ if (ddr_type == RZN1_DDR3_DUAL_BANK)
+ phy_writel(0x80005556, WLCTRL1);
+ else
+ phy_writel(0x80005C5D, WLCTRL1);
+ phy_writel(0x00000101, FIFOINIT);
+ phy_writel(0x00004545, DQCALOFS1);
+
+ /* Step 9 MDLL reset release */
+ val = phy_readl(DLLCTRL);
+ val &= ~DLLCTRL_MDLLSTBY;
+ phy_writel(val, DLLCTRL);
+
+ /* Step 12 Soft reset release */
+ val = phy_readl(FUNCCTRL);
+ val |= FUNCCTRL_RESET_N;
+ phy_writel(val, FUNCCTRL);
+
+ /* Step 13 FIFO pointer initialize */
+ phy_writel(FIFOINIT_RDPTINITEXE | FIFOINIT_WRPTINITEXE, FIFOINIT);
+
+ /* Step 14 Execute ZQ Calibration */
+ val = phy_readl(ZQCALCTRL);
+ val |= ZQCALCTRL_ZQCALRSTB;
+ phy_writel(val, ZQCALCTRL);
+
+ /* Step 15 Wait for 200us or more, or wait for DFIINITCOMPLETE to be "1" */
+ wait_for_bit_le32(priv->phy + DLLCTRL, DLLCTRL_ASDLLOCK, true, 1, false);
+ wait_for_bit_le32(priv->phy + ZQCALCTRL, ZQCALCTRL_ZQCALEND, true, 1, false);
+
+ /* Step 16 Enable Address and Command output */
+ val = phy_readl(OUTCTRL);
+ val |= OUTCTRL_ADCMDOE;
+ phy_writel(val, OUTCTRL);
+
+ /* Step 17 Wait for 200us or more(from MRESETB=0) */
+ udelay(200);
+}
+
+static void ddr_phy_enable_wl(struct cadence_ddr_info *priv)
+{
+ u32 val;
+
+ /* Step 26 (Set Write Leveling) */
+ val = phy_readl(WLCTRL1);
+ val |= WLCTRL1_WLSTR;
+ phy_writel(val, WLCTRL1);
+}
+
+#define RZN1_V_DDR_BASE 0x80000000 /* RZ/N1D only */
+
+static void rzn1_ddr3_single_bank(void *ddr_ctrl_base)
+{
+ /* CS0 */
+ cdns_ddr_set_mr1(ddr_ctrl_base, 0,
+ MR1_ODT_IMPEDANCE_60_OHMS,
+ MR1_DRIVE_STRENGTH_40_OHMS);
+ cdns_ddr_set_mr2(ddr_ctrl_base, 0,
+ MR2_DYNAMIC_ODT_OFF,
+ MR2_SELF_REFRESH_TEMP_EXT);
+
+ /* ODT_WR_MAP_CS0 = 1, ODT_RD_MAP_CS0 = 0 */
+ cdns_ddr_set_odt_map(ddr_ctrl_base, 0, 0x0100);
+}
+
+static int rzn1_dram_init(struct cadence_ddr_info *priv)
+{
+ u32 version;
+ u32 ddr_start_addr = 0;
+
+ ddr_phy_init(priv, RZN1_DDR3_SINGLE_BANK);
+
+ /*
+ * Override DDR PHY Interface (DFI) related settings
+ * DFI is the internal interface between the DDR controller and the DDR PHY.
+ * These settings are specific to the board and can't be known by the settings
+ * provided for each DDR model within the generated include.
+ */
+ priv->reg350[351 - 350] = 0x001e0000;
+ priv->reg350[352 - 350] = 0x1e680000;
+ priv->reg350[353 - 350] = 0x02000020;
+ priv->reg350[354 - 350] = 0x02000200;
+ priv->reg350[355 - 350] = 0x00000c30;
+ priv->reg350[356 - 350] = 0x00009808;
+ priv->reg350[357 - 350] = 0x020a0706;
+ priv->reg350[372 - 350] = 0x01000000;
+
+ /*
+ * On ES1.0 devices, the DDR start address that the DDR Controller sees
+ * is the physical address of the DDR. However, later devices changed it
+ * to be 0 in order to fix an issue with DDR out-of-range detection.
+ */
+#define RZN1_SYSCTRL_REG_VERSION 412
+ regmap_read(priv->syscon, RZN1_SYSCTRL_REG_VERSION, &version);
+ if (version == 0x10)
+ ddr_start_addr = RZN1_V_DDR_BASE;
+
+ if (priv->enable_ecc)
+ priv->ddr_size = priv->ddr_size / 2;
+
+ /* DDR Controller is always in ASYNC mode */
+ cdns_ddr_ctrl_init(priv->ddrc, 1,
+ priv->reg0, priv->reg350,
+ ddr_start_addr, priv->ddr_size,
+ priv->enable_ecc, priv->enable_8bit);
+
+ rzn1_ddr3_single_bank(priv->ddrc);
+ cdns_ddr_set_diff_cs_delays(priv->ddrc, 2, 7, 2, 2);
+ cdns_ddr_set_same_cs_delays(priv->ddrc, 0, 7, 0, 0);
+ cdns_ddr_set_odt_times(priv->ddrc, 5, 6, 6, 0, 4);
+ cdns_ddr_ctrl_start(priv->ddrc);
+
+ ddr_phy_enable_wl(priv);
+
+ if (priv->enable_ecc) {
+ /*
+ * Any read before a write will trigger an ECC un-correctable error,
+ * causing a data abort. However, this is also true for any read with a
+ * size less than the AXI bus width. So, the only sensible solution is
+ * to write to all of DDR now and take the hit...
+ */
+ memset((void *)RZN1_V_DDR_BASE, 0xff, priv->ddr_size);
+ }
+
+ return 0;
+}
+
+static int cadence_ddr_get_info(struct udevice *udev, struct ram_info *info)
+{
+ info->base = 0;
+ info->size = gd->ram_size;
+
+ return 0;
+}
+
+static struct ram_ops cadence_ddr_ops = {
+ .get_info = cadence_ddr_get_info,
+};
+
+static int cadence_ddr_test(long *base, long maxsize)
+{
+ volatile long *addr = base;
+ long cnt;
+
+ maxsize /= sizeof(long);
+
+ for (cnt = 1; cnt <= maxsize; cnt <<= 1) {
+ addr[cnt - 1] = ~cnt;
+ }
+
+ for (cnt = 1; cnt <= maxsize; cnt <<= 1) {
+ if (addr[cnt - 1] != ~cnt) {
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+static int cadence_ddr_probe(struct udevice *dev)
+{
+ struct cadence_ddr_info *priv = dev_get_priv(dev);
+ ofnode subnode;
+ int ret;
+
+ priv->dev = dev;
+
+ priv->ddrc = dev_remap_addr_name(dev, "ddrc");
+ if (!priv->ddrc) {
+ dev_err(dev, "No reg property for Cadence DDR CTRL\n");
+ return -EINVAL;
+ }
+
+ priv->phy = dev_remap_addr_name(dev, "phy");
+ if (!priv->phy) {
+ dev_err(dev, "No reg property for Cadence DDR PHY\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_by_name(dev, "clk_ddrc", &priv->clk_ddrc);
+ if (ret) {
+ dev_err(dev, "No clock for Cadence DDR\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "hclk_ddrc", &priv->hclk_ddrc);
+ if (ret) {
+ dev_err(dev, "No HCLK for Cadence DDR\n");
+ return ret;
+ }
+
+ priv->syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
+ if (IS_ERR(priv->syscon)) {
+ dev_err(dev, "No syscon node found\n");
+ return PTR_ERR(priv->syscon);
+ }
+
+ priv->enable_ecc = dev_read_bool(dev, "enable-ecc");
+ priv->enable_8bit = dev_read_bool(dev, "enable-8bit");
+
+ priv->reg0 = malloc(88 * sizeof(u32));
+ priv->reg350 = malloc(25 * sizeof(u32));
+ if (!priv->reg0 || !priv->reg350)
+ panic("malloc failure\n");
+
+ /* There may be multiple DDR configurations to try */
+ dev_for_each_subnode(subnode, dev) {
+ ret = ofnode_read_u32(subnode, "size", &priv->ddr_size);
+ if (ret) {
+ dev_err(dev, "No size for Cadence DDR\n");
+ continue;
+ }
+
+ ret = ofnode_read_u32_array(subnode, "cadence,ctl-000", priv->reg0, 88);
+ if (ret) {
+ dev_err(dev, "No cadence,ctl-000\n");
+ continue;
+ }
+
+ ret = ofnode_read_u32_array(subnode, "cadence,ctl-350", priv->reg350, 25);
+ if (ret) {
+ dev_err(dev, "No cadence,ctl-350\n");
+ continue;
+ }
+
+ if (rzn1_dram_init(priv))
+ continue;
+
+ if (cadence_ddr_test((long *)RZN1_V_DDR_BASE, priv->ddr_size)) {
+ gd->ram_base = RZN1_V_DDR_BASE;
+ gd->ram_size = priv->ddr_size;
+ break;
+ }
+ }
+
+ if (!priv->ddr_size)
+ panic("No valid DDR to start");
+
+ free(priv->reg350);
+ free(priv->reg0);
+
+ return 0;
+}
+
+static const struct udevice_id cadence_ddr_ids[] = {
+ { .compatible = "cadence,ddr-ctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(cadence_ddr) = {
+ .name = "cadence_ddr",
+ .id = UCLASS_RAM,
+ .of_match = cadence_ddr_ids,
+ .ops = &cadence_ddr_ops,
+ .probe = cadence_ddr_probe,
+ .priv_auto = sizeof(struct cadence_ddr_info),
+ .flags = DM_FLAG_PRE_RELOC,
+};