diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/renesas/r8a7792-cpg-mssr.c | 10 | ||||
| -rw-r--r-- | drivers/clk/renesas/r8a7794-cpg-mssr.c | 10 | ||||
| -rw-r--r-- | drivers/clk/uniphier/Kconfig | 1 | ||||
| -rw-r--r-- | drivers/clk/uniphier/clk-uniphier-sys.c | 6 | ||||
| -rw-r--r-- | drivers/mmc/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/mmc/meson_gx_mmc.c | 3 | ||||
| -rw-r--r-- | drivers/mmc/mmc.c | 2 | ||||
| -rw-r--r-- | drivers/mmc/renesas-sdhi.c | 23 | ||||
| -rw-r--r-- | drivers/mmc/sh_mmcif.c | 165 | ||||
| -rw-r--r-- | drivers/mmc/tmio-common.c | 22 | ||||
| -rw-r--r-- | drivers/mmc/uniphier-sd.c | 29 | ||||
| -rw-r--r-- | drivers/mtd/nand/zynq_nand.c | 8 | ||||
| -rw-r--r-- | drivers/reset/reset-uniphier.c | 5 | ||||
| -rw-r--r-- | drivers/usb/host/Kconfig | 3 | ||||
| -rw-r--r-- | drivers/usb/host/dwc3-of-simple.c | 3 | ||||
| -rw-r--r--[-rwxr-xr-x] | drivers/video/anx9804.c | 0 | ||||
| -rw-r--r-- | drivers/video/video-uclass.c | 2 | ||||
| -rw-r--r-- | drivers/watchdog/cdns_wdt.c | 5 |
18 files changed, 239 insertions, 64 deletions
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c index 260bb89..4ba18b1 100644 --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c @@ -39,7 +39,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7792_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -78,7 +78,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = { DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1), }; -static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7792_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7792_CLK_MP), DEF_MOD("jpu", 106, R8A7792_CLK_M2), DEF_MOD("tmu1", 111, R8A7792_CLK_P), @@ -152,10 +152,6 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = { DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), }; -static const unsigned int r8a7792_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -179,7 +175,7 @@ static const unsigned int r8a7792_crit_mod_clks[] __initconst = { #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = { { 1, 208, 106, 200 }, { 1, 208, 88, 200 }, { 1, 156, 80, 150 }, diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c index 90bac3d..e8f57c3 100644 --- a/drivers/clk/renesas/r8a7794-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c @@ -40,7 +40,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7794_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7794_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), @@ -85,7 +85,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = { DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240), }; -static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7794_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7794_CLK_MP), DEF_MOD("vcp0", 101, R8A7794_CLK_ZS), DEF_MOD("vpc0", 103, R8A7794_CLK_ZS), @@ -188,10 +188,6 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = { DEF_MOD("scifa5", 1108, R8A7794_CLK_MP), }; -static const unsigned int r8a7794_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -210,7 +206,7 @@ static const unsigned int r8a7794_crit_mod_clks[] __initconst = { */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = { { 1, 208, 88, 200 }, { 1, 156, 66, 150 }, { 2, 240, 102, 230 }, diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig index 3666d84..a26ca8c 100644 --- a/drivers/clk/uniphier/Kconfig +++ b/drivers/clk/uniphier/Kconfig @@ -2,7 +2,6 @@ config CLK_UNIPHIER def_bool y depends on ARCH_UNIPHIER select CLK - select SPL_CLK if SPL help Support for clock controllers on UniPhier SoCs. Say Y if you want to control clocks provided by System Control diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index c852c78..0230a18 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -21,7 +21,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) UNIPHIER_LD4_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ + UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ + UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ @@ -34,6 +37,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ @@ -45,6 +49,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ + UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */ diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6935da2..4fa8dd8 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -266,6 +266,12 @@ config SH_SDHI help Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform +config SH_MMCIF + bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support" + depends on ARCH_RMOBILE || SH + help + Support for the on-chip MMCIF host controller on SuperH/Renesas ARM SoCs platform + config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index a2cd5d3..454593e 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -35,6 +35,9 @@ static void meson_mmc_config_clock(struct mmc *mmc) uint32_t meson_mmc_clk = 0; unsigned int clk, clk_src, clk_div; + if (!mmc->clock) + return; + /* 1GHz / CLK_MAX_DIV = 15,9 MHz */ if (mmc->clock > 16000000) { clk = SD_EMMC_CLKSRC_DIV2; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c930893..f72b80c 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1334,7 +1334,7 @@ static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode) return 0; } -int sd_select_bus_width(struct mmc *mmc, int w) +static int sd_select_bus_width(struct mmc *mmc, int w) { int err; struct mmc_cmd cmd; diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 56a43ca..8e49b2f 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -330,8 +330,10 @@ static const struct udevice_id renesas_sdhi_match[] = { static int renesas_sdhi_probe(struct udevice *dev) { + struct tmio_sd_priv *priv = dev_get_priv(dev); u32 quirks = dev_get_driver_data(dev); struct fdt_resource reg_res; + struct clk clk; DECLARE_GLOBAL_DATA_PTR; int ret; @@ -348,6 +350,27 @@ static int renesas_sdhi_probe(struct udevice *dev) quirks |= TMIO_SD_CAP_16BIT; } + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get host clock\n"); + return ret; + } + + /* set to max rate */ + priv->mclk = clk_set_rate(&clk, ULONG_MAX); + if (IS_ERR_VALUE(priv->mclk)) { + dev_err(dev, "failed to set rate for host clock\n"); + clk_free(&clk); + return priv->mclk; + } + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret) { + dev_err(dev, "failed to enable host clock\n"); + return ret; + } + ret = tmio_sd_probe(dev, quirks); #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) if (!ret) diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 1ff59f0..26fe125 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -11,9 +11,13 @@ #include <watchdog.h> #include <command.h> #include <mmc.h> +#include <clk.h> +#include <dm.h> #include <malloc.h> #include <linux/errno.h> -#include <asm/io.h> +#include <linux/compat.h> +#include <linux/io.h> +#include <linux/sizes.h> #include "sh_mmcif.h" #define DRIVER_NAME "sh_mmcif" @@ -510,10 +514,9 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, return ret; } -static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) +static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host, + struct mmc_cmd *cmd, struct mmc_data *data) { - struct sh_mmcif_host *host = mmc->priv; int ret; WATCHDOG_RESET(); @@ -539,10 +542,8 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, return ret; } -static int sh_mmcif_set_ios(struct mmc *mmc) +static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc) { - struct sh_mmcif_host *host = mmc->priv; - if (mmc->clock) sh_mmcif_clock_control(host, mmc->clock); @@ -558,19 +559,45 @@ static int sh_mmcif_set_ios(struct mmc *mmc) return 0; } -static int sh_mmcif_init(struct mmc *mmc) +static int sh_mmcif_initialize_common(struct sh_mmcif_host *host) { - struct sh_mmcif_host *host = mmc->priv; - sh_mmcif_sync_reset(host); sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask); return 0; } +#ifndef CONFIG_DM_MMC +static void *mmc_priv(struct mmc *mmc) +{ + return (void *)mmc->priv; +} + +static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_send_cmd_common(host, cmd, data); +} + +static int sh_mmcif_set_ios(struct mmc *mmc) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_set_ios_common(host, mmc); +} + +static int sh_mmcif_initialize(struct mmc *mmc) +{ + struct sh_mmcif_host *host = mmc_priv(mmc); + + return sh_mmcif_initialize_common(host); +} + static const struct mmc_ops sh_mmcif_ops = { - .send_cmd = sh_mmcif_request, - .set_ios = sh_mmcif_set_ios, - .init = sh_mmcif_init, + .send_cmd = sh_mmcif_send_cmd, + .set_ios = sh_mmcif_set_ios, + .init = sh_mmcif_initialize, }; static struct mmc_config sh_mmcif_cfg = { @@ -606,3 +633,115 @@ int mmcif_mmc_init(void) return 0; } + +#else +struct sh_mmcif_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_mmcif_host *host = dev_get_priv(dev); + + return sh_mmcif_send_cmd_common(host, cmd, data); +} + +int sh_mmcif_dm_set_ios(struct udevice *dev) +{ + struct sh_mmcif_host *host = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return sh_mmcif_set_ios_common(host, mmc); +} + +static const struct dm_mmc_ops sh_mmcif_dm_ops = { + .send_cmd = sh_mmcif_dm_send_cmd, + .set_ios = sh_mmcif_dm_set_ios, +}; + +static int sh_mmcif_dm_bind(struct udevice *dev) +{ + struct sh_mmcif_plat *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} + +static int sh_mmcif_dm_probe(struct udevice *dev) +{ + struct sh_mmcif_plat *plat = dev_get_platdata(dev); + struct sh_mmcif_host *host = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct clk sh_mmcif_clk; + fdt_addr_t base; + int ret; + + base = devfdt_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K); + if (!host->regs) + return -ENOMEM; + + ret = clk_get_by_index(dev, 0, &sh_mmcif_clk); + if (ret) { + debug("failed to get clock, ret=%d\n", ret); + return ret; + } + + ret = clk_enable(&sh_mmcif_clk); + if (ret) { + debug("failed to enable clock, ret=%d\n", ret); + return ret; + } + + host->clk = clk_get_rate(&sh_mmcif_clk); + + plat->cfg.name = dev->name; + plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + + switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", + 1)) { + case 8: + plat->cfg.host_caps |= MMC_MODE_8BIT; + break; + case 4: + plat->cfg.host_caps |= MMC_MODE_4BIT; + break; + case 1: + break; + default: + dev_err(dev, "Invalid \"bus-width\" value\n"); + return -EINVAL; + } + + sh_mmcif_initialize_common(host); + + plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk); + plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk); + plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + upriv->mmc = &plat->mmc; + + return 0; +} + +static const struct udevice_id sh_mmcif_sd_match[] = { + { .compatible = "renesas,sh-mmcif" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sh_mmcif_mmc) = { + .name = "sh-mmcif", + .id = UCLASS_MMC, + .of_match = sh_mmcif_sd_match, + .bind = sh_mmcif_dm_bind, + .probe = sh_mmcif_dm_probe, + .priv_auto_alloc_size = sizeof(struct sh_mmcif_host), + .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat), + .ops = &sh_mmcif_dm_ops, +}; +#endif diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index 5f1c9c0..4ea6612 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -713,7 +713,6 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) struct tmio_sd_priv *priv = dev_get_priv(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); fdt_addr_t base; - struct clk clk; int ret; base = devfdt_get_addr(dev); @@ -728,27 +727,6 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev); #endif - ret = clk_get_by_index(dev, 0, &clk); - if (ret < 0) { - dev_err(dev, "failed to get host clock\n"); - return ret; - } - - /* set to max rate */ - priv->mclk = clk_set_rate(&clk, ULONG_MAX); - if (IS_ERR_VALUE(priv->mclk)) { - dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&clk); - return priv->mclk; - } - - ret = clk_enable(&clk); - clk_free(&clk); - if (ret) { - dev_err(dev, "failed to enable host clock\n"); - return ret; - } - ret = mmc_of_parse(dev, &plat->cfg); if (ret < 0) { dev_err(dev, "failed to parse host caps\n"); diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 47379b0..61f8da4 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -32,6 +32,35 @@ static const struct udevice_id uniphier_sd_match[] = { static int uniphier_sd_probe(struct udevice *dev) { + struct tmio_sd_priv *priv = dev_get_priv(dev); +#ifndef CONFIG_SPL_BUILD + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get host clock\n"); + return ret; + } + + /* set to max rate */ + priv->mclk = clk_set_rate(&clk, ULONG_MAX); + if (IS_ERR_VALUE(priv->mclk)) { + dev_err(dev, "failed to set rate for host clock\n"); + clk_free(&clk); + return priv->mclk; + } + + ret = clk_enable(&clk); + clk_free(&clk); + if (ret) { + dev_err(dev, "failed to enable host clock\n"); + return ret; + } +#else + priv->mclk = 100000000; +#endif + return tmio_sd_probe(dev, 0); } diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c index 6494196..2d4e8b4 100644 --- a/drivers/mtd/nand/zynq_nand.c +++ b/drivers/mtd/nand/zynq_nand.c @@ -1006,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd) return 0; } -int zynq_nand_init(struct nand_chip *nand_chip, int devnum) +static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) { struct zynq_nand_info *xnand; struct mtd_info *mtd; @@ -1025,7 +1025,7 @@ int zynq_nand_init(struct nand_chip *nand_chip, int devnum) } xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR; - mtd = get_nand_dev_by_index(0); + mtd = nand_to_mtd(nand_chip); nand_chip->priv = xnand; mtd->priv = nand_chip; @@ -1192,14 +1192,12 @@ fail: return err; } -#ifdef CONFIG_SYS_NAND_SELF_INIT static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; -void __weak board_nand_init(void) +void board_nand_init(void) { struct nand_chip *nand = &nand_chip[0]; if (zynq_nand_init(nand, 0)) puts("ZYNQ NAND init failed\n"); } -#endif diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index a40cea5..e7a7da7 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -43,6 +43,7 @@ struct uniphier_reset_data { /* System reset data */ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ + UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */ UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */ UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ @@ -52,6 +53,7 @@ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ + UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */ UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ @@ -68,6 +70,7 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ + UNIPHIER_RESETX(6, 0x200c, 6), /* ETHER */ UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */ UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */ UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ @@ -80,6 +83,8 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ + UNIPHIER_RESETX(6, 0x200c, 9), /* ETHER0 */ + UNIPHIER_RESETX(7, 0x200c, 10), /* ETHER1 */ UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ UNIPHIER_RESETX(12, 0x200c, 5), /* USB30 (GIO0) */ UNIPHIER_RESETX(13, 0x200c, 6), /* USB31 (GIO1) */ diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 6caa615..3455e81 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -23,7 +23,8 @@ config USB_XHCI_DWC3 config USB_XHCI_DWC3_OF_SIMPLE bool "DesignWare USB3 DRD Generic OF Simple Glue Layer" - select MISC + depends on DM_USB + default y if DRA7XX help Support USB2/3 functionality in simple SoC integrations with USB controller based on the DesignWare USB3 IP Core. diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index 54a5f60..440dd10 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -50,7 +50,7 @@ static int dwc3_of_simple_clk_init(struct udevice *dev, int ret; ret = clk_get_bulk(dev, &simple->clks); - if (ret == -ENOTSUPP) + if (ret == -ENOSYS) return 0; if (ret) return ret; @@ -95,6 +95,7 @@ static int dwc3_of_simple_remove(struct udevice *dev) static const struct udevice_id dwc3_of_simple_ids[] = { { .compatible = "amlogic,meson-gxl-dwc3" }, + { .compatible = "ti,dwc3" }, { } }; diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c index 3910458..3910458 100755..100644 --- a/drivers/video/anx9804.c +++ b/drivers/video/anx9804.c diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index b5bb8e0..93fdc68 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -272,7 +272,7 @@ static int video_post_bind(struct udevice *dev) ulong size; /* Before relocation there is nothing to do here */ - if ((!gd->flags & GD_FLG_RELOC)) + if (!(gd->flags & GD_FLG_RELOC)) return 0; size = alloc_fb(dev, &addr); if (addr < gd->video_bottom) { diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index 71733cf..c43f7e8 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -25,7 +25,6 @@ struct cdns_regs { struct cdns_wdt_priv { bool rst; u32 timeout; - void __iomem *reg; struct cdns_regs *regs; }; @@ -224,12 +223,8 @@ static int cdns_wdt_stop(struct udevice *dev) */ static int cdns_wdt_probe(struct udevice *dev) { - struct cdns_wdt_priv *priv = dev_get_priv(dev); - debug("%s: Probing wdt%u\n", __func__, dev->seq); - priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs)); - cdns_wdt_stop(dev); return 0; |