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-rw-r--r--drivers/Kconfig2
-rw-r--r--drivers/Makefile1
-rw-r--r--drivers/clk/clk_stm32mp1.c243
-rw-r--r--drivers/misc/Kconfig2
-rw-r--r--drivers/misc/stm32_rcc.c19
-rw-r--r--drivers/mmc/stm32_sdmmc2.c78
-rw-r--r--drivers/phy/phy-uclass.c17
-rw-r--r--drivers/power/regulator/stpmu1.c20
-rw-r--r--drivers/reset/stm32-reset.c16
-rw-r--r--drivers/rtc/Kconfig7
-rw-r--r--drivers/rtc/Makefile1
-rw-r--r--drivers/rtc/date.c43
-rw-r--r--drivers/rtc/i2c_rtc_emul.c4
-rw-r--r--drivers/rtc/mc146818.c8
-rw-r--r--drivers/rtc/rtc-lib.c73
-rw-r--r--drivers/smem/Kconfig24
-rw-r--r--drivers/smem/Makefile7
-rw-r--r--drivers/smem/msm_smem.c932
-rw-r--r--drivers/smem/sandbox_smem.c45
-rw-r--r--drivers/smem/smem-uclass.c45
-rw-r--r--drivers/sysreset/sysreset_syscon.c16
21 files changed, 1453 insertions, 150 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 9e21b28..c72abf8 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -84,6 +84,8 @@ source "drivers/scsi/Kconfig"
source "drivers/serial/Kconfig"
+source "drivers/smem/Kconfig"
+
source "drivers/sound/Kconfig"
source "drivers/spi/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 66834c3..276e5ee 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -98,6 +98,7 @@ obj-y += pwm/
obj-y += reset/
obj-y += input/
# SOC specific infrastructure drivers.
+obj-y += smem/
obj-y += soc/
obj-$(CONFIG_REMOTEPROC) += remoteproc/
obj-y += thermal/
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 1a77eba..6a8c7b7 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -98,6 +98,8 @@
#define RCC_QSPICKSELR 0x900
#define RCC_FMCCKSELR 0x904
#define RCC_USBCKSELR 0x91C
+#define RCC_DSICKSELR 0x924
+#define RCC_ADCCKSELR 0x928
#define RCC_MP_APB1ENSETR 0xA00
#define RCC_MP_APB2ENSETR 0XA08
#define RCC_MP_APB3ENSETR 0xA10
@@ -147,6 +149,7 @@
#define RCC_BDCR_LSEON BIT(0)
#define RCC_BDCR_LSEBYP BIT(1)
#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_DIGBYP BIT(3)
#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
#define RCC_BDCR_LSEDRV_SHIFT 4
#define RCC_BDCR_LSECSSON BIT(8)
@@ -175,13 +178,14 @@
#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
-/* used for ALL PLLNCFGR2 registers */
+/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
+#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
-#define RCC_PLLNCFGR2_DIVP_SHIFT 0
+#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
-#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
+#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
-#define RCC_PLLNCFGR2_DIVR_SHIFT 16
+#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
/* used for ALL PLLNFRACR registers */
@@ -200,6 +204,7 @@
/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
#define RCC_OCENR_HSION BIT(0)
#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_DIGBYP BIT(7)
#define RCC_OCENR_HSEON BIT(8)
#define RCC_OCENR_HSEBYP BIT(10)
#define RCC_OCENR_HSECSSON BIT(11)
@@ -266,6 +271,7 @@ enum stm32mp1_parent_id {
_CK_PER,
_CK_MPU,
_CK_MCU,
+ _DSI_PHY,
_PARENT_NB,
_UNKNOWN_ID = 0xff,
};
@@ -286,6 +292,8 @@ enum stm32mp1_parent_sel {
_USBPHY_SEL,
_USBO_SEL,
_STGEN_SEL,
+ _DSI_SEL,
+ _ADC12_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
@@ -511,6 +519,9 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
@@ -518,6 +529,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
@@ -535,10 +548,9 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
@@ -568,6 +580,8 @@ static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
+static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
+static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
@@ -590,6 +604,8 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
+ STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
+ STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
@@ -681,7 +697,8 @@ static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
[_CK_PER] = "CK_PER",
[_CK_MPU] = "CK_MPU",
[_CK_MCU] = "CK_MCU",
- [_USB_PHY_48] = "USB_PHY_48"
+ [_USB_PHY_48] = "USB_PHY_48",
+ [_DSI_PHY] = "DSI_PHY_PLL",
};
static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
@@ -699,7 +716,9 @@ static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
[_FMC_SEL] = "FMC",
[_USBPHY_SEL] = "USBPHY",
[_USBO_SEL] = "USBO",
- [_STGEN_SEL] = "STGEN"
+ [_STGEN_SEL] = "STGEN",
+ [_DSI_SEL] = "DSI",
+ [_ADC12_SEL] = "ADC12",
};
#endif
@@ -807,60 +826,87 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
return -EINVAL;
}
-static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
- int pll_id, int div_id)
+static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
+ int pll_id)
{
const struct stm32mp1_clk_pll *pll = priv->data->pll;
- int divm, divn, divy, src;
- ulong refclk, dfout;
- u32 selr, cfgr1, cfgr2, fracr;
- const u8 shift[_DIV_NB] = {
- [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
- [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
- [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
-
- debug("%s(%d, %d)\n", __func__, pll_id, div_id);
- if (div_id > _DIV_NB)
- return 0;
+ u32 selr;
+ int src;
+ ulong refclk;
+ /* Get current refclk */
selr = readl(priv->base + pll[pll_id].rckxselr);
+ src = selr & RCC_SELR_SRC_MASK;
+
+ refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
+ debug("PLL%d : selr=%x refclk = %d kHz\n",
+ pll_id, selr, (u32)(refclk / 1000));
+
+ return refclk;
+}
+
+/*
+ * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
+ * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
+ * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
+ * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
+ */
+static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
+ int pll_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ int divm, divn;
+ ulong refclk, fvco;
+ u32 cfgr1, fracr;
+
cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
- cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
fracr = readl(priv->base + pll[pll_id].pllxfracr);
- debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
- pll_id, selr, cfgr1, cfgr2, fracr);
-
divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
- divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
- debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
+ debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
+ pll_id, cfgr1, fracr, divn, divm);
- src = selr & RCC_SELR_SRC_MASK;
- refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
-
- debug(" refclk = %d kHz\n", (u32)(refclk / 1000));
+ refclk = pll_get_fref_ck(priv, pll_id);
- /*
- * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
- * So same final result than PLL2 et 4
- * with FRACV :
- * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
- * / (DIVM + 1) * (DIVy + 1)
+ /* with FRACV :
+ * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
* without FRACV
- * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
+ * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
*/
if (fracr & RCC_PLLNFRACR_FRACLE) {
u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
>> RCC_PLLNFRACR_FRACV_SHIFT;
- dfout = (ulong)lldiv((unsigned long long)refclk *
+ fvco = (ulong)lldiv((unsigned long long)refclk *
(((divn + 1) << 13) + fracv),
- ((unsigned long long)(divm + 1) *
- (divy + 1)) << 13);
+ ((unsigned long long)(divm + 1)) << 13);
} else {
- dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
+ fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
}
+ debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
+
+ return fvco;
+}
+
+static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
+ int pll_id, int div_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ int divy;
+ ulong dfout;
+ u32 cfgr2;
+
+ debug("%s(%d, %d)\n", __func__, pll_id, div_id);
+ if (div_id >= _DIV_NB)
+ return 0;
+
+ cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
+ divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
+
+ debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
+
+ dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
return dfout;
@@ -1032,7 +1078,22 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
case _USB_PHY_48:
clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
break;
-
+ case _DSI_PHY:
+ {
+ struct clk clk;
+ struct udevice *dev = NULL;
+
+ if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
+ &dev)) {
+ if (clk_request(dev, &clk)) {
+ pr_err("ck_dsi_phy request");
+ } else {
+ clk.id = 0;
+ clock = clk_get_rate(&clk);
+ }
+ }
+ break;
+ }
default:
break;
}
@@ -1143,11 +1204,15 @@ static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
return ret;
}
-static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
+static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
+ int lsedrv)
{
u32 value;
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
+
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
/*
@@ -1182,9 +1247,11 @@ static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
}
-static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
+static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
{
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP);
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
@@ -1547,26 +1614,27 @@ static int stm32mp1_clktree(struct udevice *dev)
stm32mp1_lsi_set(rcc, 1);
if (priv->osc[_LSE]) {
- int bypass;
- int lsedrv;
+ int bypass, digbyp, lsedrv;
struct udevice *dev = priv->osc_dev[_LSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
lse_css = dev_read_bool(dev, "st,css");
lsedrv = dev_read_u32_default(dev, "st,drive",
LSEDRV_MEDIUM_HIGH);
- stm32mp1_lse_enable(rcc, bypass, lsedrv);
+ stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
}
if (priv->osc[_HSE]) {
- int bypass, css;
+ int bypass, digbyp, css;
struct udevice *dev = priv->osc_dev[_HSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
css = dev_read_bool(dev, "st,css");
- stm32mp1_hse_enable(rcc, bypass, css);
+ stm32mp1_hse_enable(rcc, bypass, digbyp, css);
}
/* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
* => switch on CSI even if node is not present in device tree
@@ -1695,6 +1763,70 @@ static int stm32mp1_clktree(struct udevice *dev)
}
#endif /* STM32MP1_CLOCK_TREE_INIT */
+static int pll_set_output_rate(struct udevice *dev,
+ int pll_id,
+ int div_id,
+ unsigned long clk_rate)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+ int div;
+ ulong fvco;
+
+ if (div_id > _DIV_NB)
+ return -EINVAL;
+
+ fvco = pll_get_fvco(priv, pll_id);
+
+ if (fvco <= clk_rate)
+ div = 1;
+ else
+ div = DIV_ROUND_UP(fvco, clk_rate);
+
+ if (div > 128)
+ div = 128;
+
+ debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
+ /* stop the requested output */
+ clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
+ /* change divider */
+ clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
+ RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
+ (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
+ /* start the requested output */
+ setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
+
+ return 0;
+}
+
+static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ int p;
+
+ switch (clk->id) {
+ case LTDC_PX:
+ case DSI_PX:
+ break;
+ default:
+ pr_err("not supported");
+ return -EINVAL;
+ }
+
+ p = stm32mp1_clk_get_parent(priv, clk->id);
+ if (p < 0)
+ return -EINVAL;
+
+ switch (p) {
+ case _PLL4_Q:
+ /* for LTDC_PX and DSI_PX case */
+ return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
+ }
+
+ return -EINVAL;
+}
+
static void stm32mp1_osc_clk_init(const char *name,
struct stm32mp1_clk_priv *priv,
int index)
@@ -1762,17 +1894,12 @@ static const struct clk_ops stm32mp1_clk_ops = {
.enable = stm32mp1_clk_enable,
.disable = stm32mp1_clk_disable,
.get_rate = stm32mp1_clk_get_rate,
-};
-
-static const struct udevice_id stm32mp1_clk_ids[] = {
- { .compatible = "st,stm32mp1-rcc-clk" },
- { }
+ .set_rate = stm32mp1_clk_set_rate,
};
U_BOOT_DRIVER(stm32mp1_clock) = {
.name = "stm32mp1_clk",
.id = UCLASS_CLK,
- .of_match = stm32mp1_clk_ids,
.ops = &stm32mp1_clk_ops,
.priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
.probe = stm32mp1_clk_probe,
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 17b3a80..c031dfd 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -169,7 +169,7 @@ config STM32MP_FUSE
config STM32_RCC
bool "Enable RCC driver for the STM32 SoC's family"
- depends on STM32 && MISC
+ depends on (STM32 || ARCH_STM32MP) && MISC
help
Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
block) is responsible of the management of the clock and reset
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index 980b3a5..13d7069 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -30,6 +30,11 @@ struct stm32_rcc_clk stm32_rcc_clk_h7 = {
.drv_name = "stm32h7_rcc_clock",
};
+struct stm32_rcc_clk stm32_rcc_clk_mp1 = {
+ .drv_name = "stm32mp1_clk",
+ .soc = STM32MP1,
+};
+
static int stm32_rcc_bind(struct udevice *dev)
{
struct udevice *child;
@@ -39,7 +44,6 @@ static int stm32_rcc_bind(struct udevice *dev)
int ret;
debug("%s(dev=%p)\n", __func__, dev);
-
drv = lists_driver_lookup_name(rcc_clk->drv_name);
if (!drv) {
debug("Cannot find driver '%s'\n", rcc_clk->drv_name);
@@ -53,9 +57,15 @@ static int stm32_rcc_bind(struct udevice *dev)
if (ret)
return ret;
- return device_bind_driver_to_node(dev, "stm32_rcc_reset",
- "stm32_rcc_reset",
- dev_ofnode(dev), &child);
+ drv = lists_driver_lookup_name("stm32_rcc_reset");
+ if (!drv) {
+ dev_err(dev, "Cannot find driver stm32_rcc_reset'\n");
+ return -ENOENT;
+ }
+
+ return device_bind_with_driver_data(dev, drv, "stm32_rcc_reset",
+ rcc_clk->soc,
+ dev_ofnode(dev), &child);
}
static const struct misc_ops stm32_rcc_ops = {
@@ -66,6 +76,7 @@ static const struct udevice_id stm32_rcc_ids[] = {
{.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 },
{.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
{.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
+ {.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
{ }
};
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index e8292c4..a36612d 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -56,7 +56,10 @@ struct stm32_sdmmc2_ctx {
#define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
/* SDMMC_POWER register */
-#define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
+#define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0)
+#define SDMMC_POWER_PWRCTRL_OFF 0
+#define SDMMC_POWER_PWRCTRL_CYCLE 2
+#define SDMMC_POWER_PWRCTRL_ON 3
#define SDMMC_POWER_VSWITCH BIT(2)
#define SDMMC_POWER_VSWITCHEN BIT(3)
#define SDMMC_POWER_DIRPOL BIT(4)
@@ -440,23 +443,74 @@ retry_cmd:
return ret;
}
-static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
+/*
+ * Reset the SDMMC with the RCC.SDMMCxRST register bit.
+ * This will reset the SDMMC to the reset state and the CPSM and DPSM
+ * to the Idle state. SDMMC is disabled, Signals Hiz.
+ */
+static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
{
/* Reset */
reset_assert(&priv->reset_ctl);
udelay(2);
reset_deassert(&priv->reset_ctl);
- udelay(1000);
+ /* init the needed SDMMC register after reset */
+ writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
+}
+
+/*
+ * Set the SDMMC in power-cycle state.
+ * This will make that the SDMMC_D[7:0],
+ * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
+ * supplied through the signal lines.
+ */
+static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
+{
+ if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
+ SDMMC_POWER_PWRCTRL_CYCLE)
+ return;
- /* Set Power State to ON */
- writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER);
+ stm32_sdmmc2_reset(priv);
+ writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
+ priv->base + SDMMC_POWER);
+}
+
+/*
+ * set the SDMMC state Power-on: the card is clocked
+ * manage the SDMMC state control:
+ * Reset => Power-Cycle => Power-Off => Power
+ * PWRCTRL=10 PWCTRL=00 PWCTRL=11
+ */
+static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
+{
+ u32 pwrctrl =
+ readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
+
+ if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
+ return;
+
+ /* warning: same PWRCTRL value after reset and for power-off state
+ * it is the reset state here = the only managed by the driver
+ */
+ if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
+ writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
+ priv->base + SDMMC_POWER);
+ }
/*
- * 1ms: required power up waiting time before starting the
- * SD initialization sequence
+ * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
+ * switch to Power-Off state: SDMCC disable, signals drive 1
*/
- udelay(1000);
+ writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
+ priv->base + SDMMC_POWER);
+
+ /* After the 1ms delay set the SDMMC to power-on */
+ mdelay(1);
+ writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
+ priv->base + SDMMC_POWER);
+
+ /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
}
#define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
@@ -464,8 +518,6 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev)
{
struct mmc *mmc = mmc_get_mmc_dev(dev);
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
- struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
- struct mmc_config *cfg = &plat->cfg;
u32 desired = mmc->clock;
u32 sys_clock = clk_get_rate(&priv->clk);
u32 clk = 0;
@@ -473,7 +525,9 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev)
debug("%s: bus_with = %d, clock = %d\n", __func__,
mmc->bus_width, mmc->clock);
- if ((mmc->bus_width == 1) && (desired == cfg->f_min))
+ if (mmc->clk_disable)
+ stm32_sdmmc2_pwrcycle(priv);
+ else
stm32_sdmmc2_pwron(priv);
/*
@@ -577,6 +631,8 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
upriv->mmc = &plat->mmc;
+ /* SDMMC init */
+ stm32_sdmmc2_reset(priv);
return 0;
clk_disable:
diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index c4b3e40..6162395 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -36,8 +36,8 @@ int generic_phy_get_by_index(struct udevice *dev, int index,
{
struct ofnode_phandle_args args;
struct phy_ops *ops;
- int ret;
struct udevice *phydev;
+ int i, ret;
debug("%s(dev=%p, index=%d, phy=%p)\n", __func__, dev, index, phy);
@@ -55,7 +55,20 @@ int generic_phy_get_by_index(struct udevice *dev, int index,
if (ret) {
debug("%s: uclass_get_device_by_ofnode failed: err=%d\n",
__func__, ret);
- return ret;
+
+ /* Check if args.node's parent is a PHY provider */
+ ret = uclass_get_device_by_ofnode(UCLASS_PHY,
+ ofnode_get_parent(args.node),
+ &phydev);
+ if (ret)
+ return ret;
+
+ /* insert phy idx at first position into args array */
+ for (i = args.args_count; i > 1 ; i--)
+ args.args[i] = args.args[i - 1];
+
+ args.args_count++;
+ args.args[0] = ofnode_read_u32_default(args.node, "reg", -1);
}
phy->dev = phydev;
diff --git a/drivers/power/regulator/stpmu1.c b/drivers/power/regulator/stpmu1.c
index 2dedb80..6eb2420 100644
--- a/drivers/power/regulator/stpmu1.c
+++ b/drivers/power/regulator/stpmu1.c
@@ -183,6 +183,8 @@ static int stpmu1_buck_get_enable(struct udevice *dev)
static int stpmu1_buck_set_enable(struct udevice *dev, bool enable)
{
struct dm_regulator_uclass_platdata *uc_pdata;
+ int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
+ STPMU1_DEFAULT_STOP_DELAY_MS;
int ret, uv;
/* if regulator is already in the wanted state, nothing to do */
@@ -199,8 +201,7 @@ static int stpmu1_buck_set_enable(struct udevice *dev, bool enable)
ret = pmic_clrsetbits(dev->parent,
STPMU1_BUCKX_CTRL_REG(dev->driver_data - 1),
STPMU1_BUCK_EN, enable ? STPMU1_BUCK_EN : 0);
- if (enable)
- mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+ mdelay(delay);
return ret;
}
@@ -361,6 +362,8 @@ static int stpmu1_ldo_get_enable(struct udevice *dev)
static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable)
{
struct dm_regulator_uclass_platdata *uc_pdata;
+ int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
+ STPMU1_DEFAULT_STOP_DELAY_MS;
int ret, uv;
/* if regulator is already in the wanted state, nothing to do */
@@ -377,8 +380,7 @@ static int stpmu1_ldo_set_enable(struct udevice *dev, bool enable)
ret = pmic_clrsetbits(dev->parent,
STPMU1_LDOX_CTRL_REG(dev->driver_data - 1),
STPMU1_LDO_EN, enable ? STPMU1_LDO_EN : 0);
- if (enable)
- mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+ mdelay(delay);
return ret;
}
@@ -489,6 +491,8 @@ static int stpmu1_vref_ddr_get_enable(struct udevice *dev)
static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable)
{
+ int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
+ STPMU1_DEFAULT_STOP_DELAY_MS;
int ret;
/* if regulator is already in the wanted state, nothing to do */
@@ -497,8 +501,7 @@ static int stpmu1_vref_ddr_set_enable(struct udevice *dev, bool enable)
ret = pmic_clrsetbits(dev->parent, STPMU1_VREF_CTRL_REG,
STPMU1_VREF_EN, enable ? STPMU1_VREF_EN : 0);
- if (enable)
- mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+ mdelay(delay);
return ret;
}
@@ -610,6 +613,8 @@ static int stpmu1_pwr_sw_get_enable(struct udevice *dev)
static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable)
{
uint mask = 1 << dev->driver_data;
+ int delay = enable ? STPMU1_DEFAULT_START_UP_DELAY_MS :
+ STPMU1_DEFAULT_STOP_DELAY_MS;
int ret;
ret = pmic_reg_read(dev->parent, STPMU1_USB_CTRL_REG);
@@ -633,8 +638,7 @@ static int stpmu1_pwr_sw_set_enable(struct udevice *dev, bool enable)
ret = pmic_clrsetbits(dev->parent, STPMU1_USB_CTRL_REG,
mask, enable ? mask : 0);
- if (enable)
- mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
+ mdelay(delay);
return ret;
}
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index c21ede2..16d3dba 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -8,16 +8,12 @@
#include <dm.h>
#include <errno.h>
#include <reset-uclass.h>
+#include <stm32_rcc.h>
#include <asm/io.h>
/* reset clear offset for STM32MP RCC */
#define RCC_CL 0x4
-enum rcc_type {
- RCC_STM32 = 0,
- RCC_STM32MP,
-};
-
struct stm32_reset_priv {
fdt_addr_t base;
};
@@ -40,7 +36,7 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl)
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
- if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+ if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
/* reset assert is done in rcc set register */
writel(BIT(offset), priv->base + bank);
else
@@ -57,7 +53,7 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
reset_ctl->id, bank, offset);
- if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP)
+ if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
/* reset deassert is done in rcc clr register */
writel(BIT(offset), priv->base + bank + RCC_CL);
else
@@ -88,15 +84,9 @@ static int stm32_reset_probe(struct udevice *dev)
return 0;
}
-static const struct udevice_id stm32_reset_ids[] = {
- { .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP },
- { }
-};
-
U_BOOT_DRIVER(stm32_rcc_reset) = {
.name = "stm32_rcc_reset",
.id = UCLASS_RESET,
- .of_match = stm32_reset_ids,
.probe = stm32_reset_probe,
.priv_auto_alloc_size = sizeof(struct stm32_reset_priv),
.ops = &stm32_reset_ops,
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index a3f8c8a..5436509 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -48,6 +48,13 @@ config RTC_RX8010SJ
help
Support for Epson RX8010SJ Real Time Clock devices.
+config RTC_PL031
+ bool "Enable ARM AMBA PL031 RTC driver"
+ help
+ The ARM PrimeCell Real Time Clock (PL031) is an optional SoC
+ peripheral based on the Advanced Microcontroller Bus Architecture
+ (AMBA). It is emulated in QEMU virtual ARM machines.
+
config RTC_MV
bool "Enable Marvell RTC driver"
depends on DM_RTC
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 09f2b08..513e3ff 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_DM_RTC) += rtc-uclass.o
obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
obj-y += date.o
+obj-y += rtc-lib.o
obj-$(CONFIG_RTC_DAVINCI) += davinci.o
obj-$(CONFIG_RTC_DS1302) += ds1302.o
obj-$(CONFIG_RTC_DS1306) += ds1306.o
diff --git a/drivers/rtc/date.c b/drivers/rtc/date.c
index 1256ffe..f2568cf 100644
--- a/drivers/rtc/date.c
+++ b/drivers/rtc/date.c
@@ -19,10 +19,6 @@
#define days_in_year(a) (leapyear(a) ? 366 : 365)
#define days_in_month(a) (month_days[(a) - 1])
-static int month_days[12] = {
- 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
-};
-
static int month_offset[] = {
0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
};
@@ -65,45 +61,6 @@ int rtc_calc_weekday(struct rtc_time *tm)
return 0;
}
-int rtc_to_tm(int tim, struct rtc_time *tm)
-{
- register int i;
- register long hms, day;
-
- day = tim / SECDAY;
- hms = tim % SECDAY;
-
- /* Hours, minutes, seconds are easy */
- tm->tm_hour = hms / 3600;
- tm->tm_min = (hms % 3600) / 60;
- tm->tm_sec = (hms % 3600) % 60;
-
- /* Number of years in days */
- for (i = STARTOFTIME; day >= days_in_year(i); i++)
- day -= days_in_year(i);
- tm->tm_year = i;
-
- /* Number of months in days left */
- if (leapyear(tm->tm_year))
- days_in_month(FEBRUARY) = 29;
- for (i = 1; day >= days_in_month(i); i++)
- day -= days_in_month(i);
- days_in_month(FEBRUARY) = 28;
- tm->tm_mon = i;
-
- /* Days are what is left over (+1) from all that */
- tm->tm_mday = day + 1;
-
- /* Zero unused fields */
- tm->tm_yday = 0;
- tm->tm_isdst = 0;
-
- /*
- * Determine the day of week
- */
- return rtc_calc_weekday(tm);
-}
-
/*
* Converts Gregorian date to seconds since 1970-01-01 00:00:00.
* Assumes input in normal date format, i.e. 1980-12-31 23:59:59
diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c
index bad61c3..d4b33e5 100644
--- a/drivers/rtc/i2c_rtc_emul.c
+++ b/drivers/rtc/i2c_rtc_emul.c
@@ -96,7 +96,9 @@ static int sandbox_i2c_rtc_get(struct udevice *dev, struct rtc_time *time)
now = plat->base_time;
}
- return rtc_to_tm(now + plat->offset, time);
+ rtc_to_tm(now + plat->offset, time);
+
+ return 0;
}
static int sandbox_i2c_rtc_set(struct udevice *dev, const struct rtc_time *time)
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c
index 500eef2..ee29c71 100644
--- a/drivers/rtc/mc146818.c
+++ b/drivers/rtc/mc146818.c
@@ -83,7 +83,7 @@ static void mc146818_write8(int reg, uchar val)
static int mc146818_get(struct rtc_time *tmp)
{
- uchar sec, min, hour, mday, wday, mon, year;
+ uchar sec, min, hour, mday, wday __attribute__((unused)),mon, year;
/* here check if rtc can be accessed */
while ((mc146818_read8(RTC_CONFIG_A) & 0x80) == 0x80)
@@ -111,7 +111,6 @@ static int mc146818_get(struct rtc_time *tmp)
tmp->tm_mday = bcd2bin(mday & 0x3f);
tmp->tm_mon = bcd2bin(mon & 0x1f);
tmp->tm_year = bcd2bin(year);
- tmp->tm_wday = bcd2bin(wday & 0x07);
if (tmp->tm_year < 70)
tmp->tm_year += 2000;
@@ -120,6 +119,11 @@ static int mc146818_get(struct rtc_time *tmp)
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
+ /*
+ * The mc146818 only updates wday if it is non-zero, sunday is 1
+ * saturday is 7. So let's use our library routine.
+ */
+ rtc_calc_weekday(tmp);
#ifdef RTC_DEBUG
printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
diff --git a/drivers/rtc/rtc-lib.c b/drivers/rtc/rtc-lib.c
new file mode 100644
index 0000000..b8a7a8b
--- /dev/null
+++ b/drivers/rtc/rtc-lib.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rtc and date/time utility functions
+ *
+ * Copyright (C) 2005-06 Tower Technologies
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * U-Boot rtc_time differs from Linux rtc_time:
+ * - The year field takes the actual value, not year - 1900.
+ * - January is month 1.
+ */
+
+#include <common.h>
+#include <rtc.h>
+#include <linux/math64.h>
+
+static const unsigned char rtc_days_in_month[] = {
+ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
+};
+
+#define LEAPS_THRU_END_OF(y) ((y) / 4 - (y) / 100 + (y) / 400)
+
+/*
+ * The number of days in the month.
+ */
+static int rtc_month_days(unsigned int month, unsigned int year)
+{
+ return rtc_days_in_month[month] + (is_leap_year(year) && month == 1);
+}
+
+/*
+ * rtc_to_tm - Converts u64 to rtc_time.
+ * Convert seconds since 01-01-1970 00:00:00 to Gregorian date.
+ */
+void rtc_to_tm(u64 time, struct rtc_time *tm)
+{
+ unsigned int month, year, secs, days;
+
+ days = div_u64_rem(time, 86400, &secs);
+
+ /* day of the week, 1970-01-01 was a Thursday */
+ tm->tm_wday = (days + 4) % 7;
+
+ year = 1970 + days / 365;
+ days -= (year - 1970) * 365
+ + LEAPS_THRU_END_OF(year - 1)
+ - LEAPS_THRU_END_OF(1970 - 1);
+ while (days < 0) {
+ year -= 1;
+ days += 365 + is_leap_year(year);
+ }
+ tm->tm_year = year; /* Not year - 1900 */
+ tm->tm_yday = days + 1;
+
+ for (month = 0; month < 11; month++) {
+ int newdays;
+
+ newdays = days - rtc_month_days(month, year);
+ if (newdays < 0)
+ break;
+ days = newdays;
+ }
+ tm->tm_mon = month + 1; /* January = 1 */
+ tm->tm_mday = days + 1;
+
+ tm->tm_hour = secs / 3600;
+ secs -= tm->tm_hour * 3600;
+ tm->tm_min = secs / 60;
+ tm->tm_sec = secs - tm->tm_min * 60;
+
+ /* Zero unused fields */
+ tm->tm_isdst = 0;
+}
diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig
new file mode 100644
index 0000000..7169d0f
--- /dev/null
+++ b/drivers/smem/Kconfig
@@ -0,0 +1,24 @@
+menuconfig SMEM
+ bool "SMEM (Shared Memory mamanger) support"
+
+if SMEM
+
+config SANDBOX_SMEM
+ bool "Sandbox Shared Memory Manager (SMEM)"
+ depends on SANDBOX && DM
+ help
+ enable SMEM support for sandbox. This is an emulation of a real SMEM
+ manager.
+ The sandbox driver allocates a shared memory from the heap and
+ initialzies it on start.
+
+config MSM_SMEM
+ bool "Qualcomm Shared Memory Manager (SMEM)"
+ depends on DM
+ depends on ARCH_SNAPDRAGON
+ help
+ Enable support for the Qualcomm Shared Memory Manager.
+ The driver provides an interface to items in a heap shared among all
+ processors in a Qualcomm platform.
+
+endif # menu "SMEM Support"
diff --git a/drivers/smem/Makefile b/drivers/smem/Makefile
new file mode 100644
index 0000000..af3e9b5
--- /dev/null
+++ b/drivers/smem/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile for the U-Boot SMEM interface drivers
+
+obj-$(CONFIG_SANDBOX_SMEM) += sandbox_smem.o
+obj-$(CONFIG_SMEM) += smem-uclass.o
+obj-$(CONFIG_MSM_SMEM) += msm_smem.o
diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c
new file mode 100644
index 0000000..9fa653a
--- /dev/null
+++ b/drivers/smem/msm_smem.c
@@ -0,0 +1,932 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015, Sony Mobile Communications AB.
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <dm/of_addr.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <smem.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The Qualcomm shared memory system is an allocate-only heap structure that
+ * consists of one of more memory areas that can be accessed by the processors
+ * in the SoC.
+ *
+ * All systems contains a global heap, accessible by all processors in the SoC,
+ * with a table of contents data structure (@smem_header) at the beginning of
+ * the main shared memory block.
+ *
+ * The global header contains meta data for allocations as well as a fixed list
+ * of 512 entries (@smem_global_entry) that can be initialized to reference
+ * parts of the shared memory space.
+ *
+ *
+ * In addition to this global heap, a set of "private" heaps can be set up at
+ * boot time with access restrictions so that only certain processor pairs can
+ * access the data.
+ *
+ * These partitions are referenced from an optional partition table
+ * (@smem_ptable), that is found 4kB from the end of the main smem region. The
+ * partition table entries (@smem_ptable_entry) lists the involved processors
+ * (or hosts) and their location in the main shared memory region.
+ *
+ * Each partition starts with a header (@smem_partition_header) that identifies
+ * the partition and holds properties for the two internal memory regions. The
+ * two regions are cached and non-cached memory respectively. Each region
+ * contain a link list of allocation headers (@smem_private_entry) followed by
+ * their data.
+ *
+ * Items in the non-cached region are allocated from the start of the partition
+ * while items in the cached region are allocated from the end. The free area
+ * is hence the region between the cached and non-cached offsets. The header of
+ * cached items comes after the data.
+ *
+ * Version 12 (SMEM_GLOBAL_PART_VERSION) changes the item alloc/get procedure
+ * for the global heap. A new global partition is created from the global heap
+ * region with partition type (SMEM_GLOBAL_HOST) and the max smem item count is
+ * set by the bootloader.
+ *
+ */
+
+/*
+ * The version member of the smem header contains an array of versions for the
+ * various software components in the SoC. We verify that the boot loader
+ * version is a valid version as a sanity check.
+ */
+#define SMEM_MASTER_SBL_VERSION_INDEX 7
+#define SMEM_GLOBAL_HEAP_VERSION 11
+#define SMEM_GLOBAL_PART_VERSION 12
+
+/*
+ * The first 8 items are only to be allocated by the boot loader while
+ * initializing the heap.
+ */
+#define SMEM_ITEM_LAST_FIXED 8
+
+/* Highest accepted item number, for both global and private heaps */
+#define SMEM_ITEM_COUNT 512
+
+/* Processor/host identifier for the application processor */
+#define SMEM_HOST_APPS 0
+
+/* Processor/host identifier for the global partition */
+#define SMEM_GLOBAL_HOST 0xfffe
+
+/* Max number of processors/hosts in a system */
+#define SMEM_HOST_COUNT 10
+
+/**
+ * struct smem_proc_comm - proc_comm communication struct (legacy)
+ * @command: current command to be executed
+ * @status: status of the currently requested command
+ * @params: parameters to the command
+ */
+struct smem_proc_comm {
+ __le32 command;
+ __le32 status;
+ __le32 params[2];
+};
+
+/**
+ * struct smem_global_entry - entry to reference smem items on the heap
+ * @allocated: boolean to indicate if this entry is used
+ * @offset: offset to the allocated space
+ * @size: size of the allocated space, 8 byte aligned
+ * @aux_base: base address for the memory region used by this unit, or 0 for
+ * the default region. bits 0,1 are reserved
+ */
+struct smem_global_entry {
+ __le32 allocated;
+ __le32 offset;
+ __le32 size;
+ __le32 aux_base; /* bits 1:0 reserved */
+};
+#define AUX_BASE_MASK 0xfffffffc
+
+/**
+ * struct smem_header - header found in beginning of primary smem region
+ * @proc_comm: proc_comm communication interface (legacy)
+ * @version: array of versions for the various subsystems
+ * @initialized: boolean to indicate that smem is initialized
+ * @free_offset: index of the first unallocated byte in smem
+ * @available: number of bytes available for allocation
+ * @reserved: reserved field, must be 0
+ * toc: array of references to items
+ */
+struct smem_header {
+ struct smem_proc_comm proc_comm[4];
+ __le32 version[32];
+ __le32 initialized;
+ __le32 free_offset;
+ __le32 available;
+ __le32 reserved;
+ struct smem_global_entry toc[SMEM_ITEM_COUNT];
+};
+
+/**
+ * struct smem_ptable_entry - one entry in the @smem_ptable list
+ * @offset: offset, within the main shared memory region, of the partition
+ * @size: size of the partition
+ * @flags: flags for the partition (currently unused)
+ * @host0: first processor/host with access to this partition
+ * @host1: second processor/host with access to this partition
+ * @cacheline: alignment for "cached" entries
+ * @reserved: reserved entries for later use
+ */
+struct smem_ptable_entry {
+ __le32 offset;
+ __le32 size;
+ __le32 flags;
+ __le16 host0;
+ __le16 host1;
+ __le32 cacheline;
+ __le32 reserved[7];
+};
+
+/**
+ * struct smem_ptable - partition table for the private partitions
+ * @magic: magic number, must be SMEM_PTABLE_MAGIC
+ * @version: version of the partition table
+ * @num_entries: number of partitions in the table
+ * @reserved: for now reserved entries
+ * @entry: list of @smem_ptable_entry for the @num_entries partitions
+ */
+struct smem_ptable {
+ u8 magic[4];
+ __le32 version;
+ __le32 num_entries;
+ __le32 reserved[5];
+ struct smem_ptable_entry entry[];
+};
+
+static const u8 SMEM_PTABLE_MAGIC[] = { 0x24, 0x54, 0x4f, 0x43 }; /* "$TOC" */
+
+/**
+ * struct smem_partition_header - header of the partitions
+ * @magic: magic number, must be SMEM_PART_MAGIC
+ * @host0: first processor/host with access to this partition
+ * @host1: second processor/host with access to this partition
+ * @size: size of the partition
+ * @offset_free_uncached: offset to the first free byte of uncached memory in
+ * this partition
+ * @offset_free_cached: offset to the first free byte of cached memory in this
+ * partition
+ * @reserved: for now reserved entries
+ */
+struct smem_partition_header {
+ u8 magic[4];
+ __le16 host0;
+ __le16 host1;
+ __le32 size;
+ __le32 offset_free_uncached;
+ __le32 offset_free_cached;
+ __le32 reserved[3];
+};
+
+static const u8 SMEM_PART_MAGIC[] = { 0x24, 0x50, 0x52, 0x54 };
+
+/**
+ * struct smem_private_entry - header of each item in the private partition
+ * @canary: magic number, must be SMEM_PRIVATE_CANARY
+ * @item: identifying number of the smem item
+ * @size: size of the data, including padding bytes
+ * @padding_data: number of bytes of padding of data
+ * @padding_hdr: number of bytes of padding between the header and the data
+ * @reserved: for now reserved entry
+ */
+struct smem_private_entry {
+ u16 canary; /* bytes are the same so no swapping needed */
+ __le16 item;
+ __le32 size; /* includes padding bytes */
+ __le16 padding_data;
+ __le16 padding_hdr;
+ __le32 reserved;
+};
+#define SMEM_PRIVATE_CANARY 0xa5a5
+
+/**
+ * struct smem_info - smem region info located after the table of contents
+ * @magic: magic number, must be SMEM_INFO_MAGIC
+ * @size: size of the smem region
+ * @base_addr: base address of the smem region
+ * @reserved: for now reserved entry
+ * @num_items: highest accepted item number
+ */
+struct smem_info {
+ u8 magic[4];
+ __le32 size;
+ __le32 base_addr;
+ __le32 reserved;
+ __le16 num_items;
+};
+
+static const u8 SMEM_INFO_MAGIC[] = { 0x53, 0x49, 0x49, 0x49 }; /* SIII */
+
+/**
+ * struct smem_region - representation of a chunk of memory used for smem
+ * @aux_base: identifier of aux_mem base
+ * @virt_base: virtual base address of memory with this aux_mem identifier
+ * @size: size of the memory region
+ */
+struct smem_region {
+ u32 aux_base;
+ void __iomem *virt_base;
+ size_t size;
+};
+
+/**
+ * struct qcom_smem - device data for the smem device
+ * @dev: device pointer
+ * @global_partition: pointer to global partition when in use
+ * @global_cacheline: cacheline size for global partition
+ * @partitions: list of pointers to partitions affecting the current
+ * processor/host
+ * @cacheline: list of cacheline sizes for each host
+ * @item_count: max accepted item number
+ * @num_regions: number of @regions
+ * @regions: list of the memory regions defining the shared memory
+ */
+struct qcom_smem {
+ struct udevice *dev;
+
+ struct smem_partition_header *global_partition;
+ size_t global_cacheline;
+ struct smem_partition_header *partitions[SMEM_HOST_COUNT];
+ size_t cacheline[SMEM_HOST_COUNT];
+ u32 item_count;
+
+ unsigned int num_regions;
+ struct smem_region regions[0];
+};
+
+static struct smem_private_entry *
+phdr_to_last_uncached_entry(struct smem_partition_header *phdr)
+{
+ void *p = phdr;
+
+ return p + le32_to_cpu(phdr->offset_free_uncached);
+}
+
+static void *phdr_to_first_cached_entry(struct smem_partition_header *phdr,
+ size_t cacheline)
+{
+ void *p = phdr;
+
+ return p + le32_to_cpu(phdr->size) - ALIGN(sizeof(*phdr), cacheline);
+}
+
+static void *phdr_to_last_cached_entry(struct smem_partition_header *phdr)
+{
+ void *p = phdr;
+
+ return p + le32_to_cpu(phdr->offset_free_cached);
+}
+
+static struct smem_private_entry *
+phdr_to_first_uncached_entry(struct smem_partition_header *phdr)
+{
+ void *p = phdr;
+
+ return p + sizeof(*phdr);
+}
+
+static struct smem_private_entry *
+uncached_entry_next(struct smem_private_entry *e)
+{
+ void *p = e;
+
+ return p + sizeof(*e) + le16_to_cpu(e->padding_hdr) +
+ le32_to_cpu(e->size);
+}
+
+static struct smem_private_entry *
+cached_entry_next(struct smem_private_entry *e, size_t cacheline)
+{
+ void *p = e;
+
+ return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline);
+}
+
+static void *uncached_entry_to_item(struct smem_private_entry *e)
+{
+ void *p = e;
+
+ return p + sizeof(*e) + le16_to_cpu(e->padding_hdr);
+}
+
+static void *cached_entry_to_item(struct smem_private_entry *e)
+{
+ void *p = e;
+
+ return p - le32_to_cpu(e->size);
+}
+
+/* Pointer to the one and only smem handle */
+static struct qcom_smem *__smem;
+
+static int qcom_smem_alloc_private(struct qcom_smem *smem,
+ struct smem_partition_header *phdr,
+ unsigned int item,
+ size_t size)
+{
+ struct smem_private_entry *hdr, *end;
+ size_t alloc_size;
+ void *cached;
+
+ hdr = phdr_to_first_uncached_entry(phdr);
+ end = phdr_to_last_uncached_entry(phdr);
+ cached = phdr_to_last_cached_entry(phdr);
+
+ while (hdr < end) {
+ if (hdr->canary != SMEM_PRIVATE_CANARY) {
+ dev_err(smem->dev,
+ "Found invalid canary in hosts %d:%d partition\n",
+ phdr->host0, phdr->host1);
+ return -EINVAL;
+ }
+
+ if (le16_to_cpu(hdr->item) == item)
+ return -EEXIST;
+
+ hdr = uncached_entry_next(hdr);
+ }
+
+ /* Check that we don't grow into the cached region */
+ alloc_size = sizeof(*hdr) + ALIGN(size, 8);
+ if ((void *)hdr + alloc_size >= cached) {
+ dev_err(smem->dev, "Out of memory\n");
+ return -ENOSPC;
+ }
+
+ hdr->canary = SMEM_PRIVATE_CANARY;
+ hdr->item = cpu_to_le16(item);
+ hdr->size = cpu_to_le32(ALIGN(size, 8));
+ hdr->padding_data = cpu_to_le16(le32_to_cpu(hdr->size) - size);
+ hdr->padding_hdr = 0;
+
+ /*
+ * Ensure the header is written before we advance the free offset, so
+ * that remote processors that does not take the remote spinlock still
+ * gets a consistent view of the linked list.
+ */
+ dmb();
+ le32_add_cpu(&phdr->offset_free_uncached, alloc_size);
+
+ return 0;
+}
+
+static int qcom_smem_alloc_global(struct qcom_smem *smem,
+ unsigned int item,
+ size_t size)
+{
+ struct smem_global_entry *entry;
+ struct smem_header *header;
+
+ header = smem->regions[0].virt_base;
+ entry = &header->toc[item];
+ if (entry->allocated)
+ return -EEXIST;
+
+ size = ALIGN(size, 8);
+ if (WARN_ON(size > le32_to_cpu(header->available)))
+ return -ENOMEM;
+
+ entry->offset = header->free_offset;
+ entry->size = cpu_to_le32(size);
+
+ /*
+ * Ensure the header is consistent before we mark the item allocated,
+ * so that remote processors will get a consistent view of the item
+ * even though they do not take the spinlock on read.
+ */
+ dmb();
+ entry->allocated = cpu_to_le32(1);
+
+ le32_add_cpu(&header->free_offset, size);
+ le32_add_cpu(&header->available, -size);
+
+ return 0;
+}
+
+/**
+ * qcom_smem_alloc() - allocate space for a smem item
+ * @host: remote processor id, or -1
+ * @item: smem item handle
+ * @size: number of bytes to be allocated
+ *
+ * Allocate space for a given smem item of size @size, given that the item is
+ * not yet allocated.
+ */
+static int qcom_smem_alloc(unsigned int host, unsigned int item, size_t size)
+{
+ struct smem_partition_header *phdr;
+ int ret;
+
+ if (!__smem)
+ return -EPROBE_DEFER;
+
+ if (item < SMEM_ITEM_LAST_FIXED) {
+ dev_err(__smem->dev,
+ "Rejecting allocation of static entry %d\n", item);
+ return -EINVAL;
+ }
+
+ if (WARN_ON(item >= __smem->item_count))
+ return -EINVAL;
+
+ if (host < SMEM_HOST_COUNT && __smem->partitions[host]) {
+ phdr = __smem->partitions[host];
+ ret = qcom_smem_alloc_private(__smem, phdr, item, size);
+ } else if (__smem->global_partition) {
+ phdr = __smem->global_partition;
+ ret = qcom_smem_alloc_private(__smem, phdr, item, size);
+ } else {
+ ret = qcom_smem_alloc_global(__smem, item, size);
+ }
+
+ return ret;
+}
+
+static void *qcom_smem_get_global(struct qcom_smem *smem,
+ unsigned int item,
+ size_t *size)
+{
+ struct smem_header *header;
+ struct smem_region *area;
+ struct smem_global_entry *entry;
+ u32 aux_base;
+ unsigned int i;
+
+ header = smem->regions[0].virt_base;
+ entry = &header->toc[item];
+ if (!entry->allocated)
+ return ERR_PTR(-ENXIO);
+
+ aux_base = le32_to_cpu(entry->aux_base) & AUX_BASE_MASK;
+
+ for (i = 0; i < smem->num_regions; i++) {
+ area = &smem->regions[i];
+
+ if (area->aux_base == aux_base || !aux_base) {
+ if (size != NULL)
+ *size = le32_to_cpu(entry->size);
+ return area->virt_base + le32_to_cpu(entry->offset);
+ }
+ }
+
+ return ERR_PTR(-ENOENT);
+}
+
+static void *qcom_smem_get_private(struct qcom_smem *smem,
+ struct smem_partition_header *phdr,
+ size_t cacheline,
+ unsigned int item,
+ size_t *size)
+{
+ struct smem_private_entry *e, *end;
+
+ e = phdr_to_first_uncached_entry(phdr);
+ end = phdr_to_last_uncached_entry(phdr);
+
+ while (e < end) {
+ if (e->canary != SMEM_PRIVATE_CANARY)
+ goto invalid_canary;
+
+ if (le16_to_cpu(e->item) == item) {
+ if (size != NULL)
+ *size = le32_to_cpu(e->size) -
+ le16_to_cpu(e->padding_data);
+
+ return uncached_entry_to_item(e);
+ }
+
+ e = uncached_entry_next(e);
+ }
+
+ /* Item was not found in the uncached list, search the cached list */
+
+ e = phdr_to_first_cached_entry(phdr, cacheline);
+ end = phdr_to_last_cached_entry(phdr);
+
+ while (e > end) {
+ if (e->canary != SMEM_PRIVATE_CANARY)
+ goto invalid_canary;
+
+ if (le16_to_cpu(e->item) == item) {
+ if (size != NULL)
+ *size = le32_to_cpu(e->size) -
+ le16_to_cpu(e->padding_data);
+
+ return cached_entry_to_item(e);
+ }
+
+ e = cached_entry_next(e, cacheline);
+ }
+
+ return ERR_PTR(-ENOENT);
+
+invalid_canary:
+ dev_err(smem->dev, "Found invalid canary in hosts %d:%d partition\n",
+ phdr->host0, phdr->host1);
+
+ return ERR_PTR(-EINVAL);
+}
+
+/**
+ * qcom_smem_get() - resolve ptr of size of a smem item
+ * @host: the remote processor, or -1
+ * @item: smem item handle
+ * @size: pointer to be filled out with size of the item
+ *
+ * Looks up smem item and returns pointer to it. Size of smem
+ * item is returned in @size.
+ */
+static void *qcom_smem_get(unsigned int host, unsigned int item, size_t *size)
+{
+ struct smem_partition_header *phdr;
+ size_t cacheln;
+ void *ptr = ERR_PTR(-EPROBE_DEFER);
+
+ if (!__smem)
+ return ptr;
+
+ if (WARN_ON(item >= __smem->item_count))
+ return ERR_PTR(-EINVAL);
+
+ if (host < SMEM_HOST_COUNT && __smem->partitions[host]) {
+ phdr = __smem->partitions[host];
+ cacheln = __smem->cacheline[host];
+ ptr = qcom_smem_get_private(__smem, phdr, cacheln, item, size);
+ } else if (__smem->global_partition) {
+ phdr = __smem->global_partition;
+ cacheln = __smem->global_cacheline;
+ ptr = qcom_smem_get_private(__smem, phdr, cacheln, item, size);
+ } else {
+ ptr = qcom_smem_get_global(__smem, item, size);
+ }
+
+ return ptr;
+
+}
+
+/**
+ * qcom_smem_get_free_space() - retrieve amount of free space in a partition
+ * @host: the remote processor identifying a partition, or -1
+ *
+ * To be used by smem clients as a quick way to determine if any new
+ * allocations has been made.
+ */
+static int qcom_smem_get_free_space(unsigned int host)
+{
+ struct smem_partition_header *phdr;
+ struct smem_header *header;
+ unsigned int ret;
+
+ if (!__smem)
+ return -EPROBE_DEFER;
+
+ if (host < SMEM_HOST_COUNT && __smem->partitions[host]) {
+ phdr = __smem->partitions[host];
+ ret = le32_to_cpu(phdr->offset_free_cached) -
+ le32_to_cpu(phdr->offset_free_uncached);
+ } else if (__smem->global_partition) {
+ phdr = __smem->global_partition;
+ ret = le32_to_cpu(phdr->offset_free_cached) -
+ le32_to_cpu(phdr->offset_free_uncached);
+ } else {
+ header = __smem->regions[0].virt_base;
+ ret = le32_to_cpu(header->available);
+ }
+
+ return ret;
+}
+
+static int qcom_smem_get_sbl_version(struct qcom_smem *smem)
+{
+ struct smem_header *header;
+ __le32 *versions;
+
+ header = smem->regions[0].virt_base;
+ versions = header->version;
+
+ return le32_to_cpu(versions[SMEM_MASTER_SBL_VERSION_INDEX]);
+}
+
+static struct smem_ptable *qcom_smem_get_ptable(struct qcom_smem *smem)
+{
+ struct smem_ptable *ptable;
+ u32 version;
+
+ ptable = smem->regions[0].virt_base + smem->regions[0].size - SZ_4K;
+ if (memcmp(ptable->magic, SMEM_PTABLE_MAGIC, sizeof(ptable->magic)))
+ return ERR_PTR(-ENOENT);
+
+ version = le32_to_cpu(ptable->version);
+ if (version != 1) {
+ dev_err(smem->dev,
+ "Unsupported partition header version %d\n", version);
+ return ERR_PTR(-EINVAL);
+ }
+ return ptable;
+}
+
+static u32 qcom_smem_get_item_count(struct qcom_smem *smem)
+{
+ struct smem_ptable *ptable;
+ struct smem_info *info;
+
+ ptable = qcom_smem_get_ptable(smem);
+ if (IS_ERR_OR_NULL(ptable))
+ return SMEM_ITEM_COUNT;
+
+ info = (struct smem_info *)&ptable->entry[ptable->num_entries];
+ if (memcmp(info->magic, SMEM_INFO_MAGIC, sizeof(info->magic)))
+ return SMEM_ITEM_COUNT;
+
+ return le16_to_cpu(info->num_items);
+}
+
+static int qcom_smem_set_global_partition(struct qcom_smem *smem)
+{
+ struct smem_partition_header *header;
+ struct smem_ptable_entry *entry = NULL;
+ struct smem_ptable *ptable;
+ u32 host0, host1, size;
+ int i;
+
+ ptable = qcom_smem_get_ptable(smem);
+ if (IS_ERR(ptable))
+ return PTR_ERR(ptable);
+
+ for (i = 0; i < le32_to_cpu(ptable->num_entries); i++) {
+ entry = &ptable->entry[i];
+ host0 = le16_to_cpu(entry->host0);
+ host1 = le16_to_cpu(entry->host1);
+
+ if (host0 == SMEM_GLOBAL_HOST && host0 == host1)
+ break;
+ }
+
+ if (!entry) {
+ dev_err(smem->dev, "Missing entry for global partition\n");
+ return -EINVAL;
+ }
+
+ if (!le32_to_cpu(entry->offset) || !le32_to_cpu(entry->size)) {
+ dev_err(smem->dev, "Invalid entry for global partition\n");
+ return -EINVAL;
+ }
+
+ if (smem->global_partition) {
+ dev_err(smem->dev, "Already found the global partition\n");
+ return -EINVAL;
+ }
+
+ header = smem->regions[0].virt_base + le32_to_cpu(entry->offset);
+ host0 = le16_to_cpu(header->host0);
+ host1 = le16_to_cpu(header->host1);
+
+ if (memcmp(header->magic, SMEM_PART_MAGIC, sizeof(header->magic))) {
+ dev_err(smem->dev, "Global partition has invalid magic\n");
+ return -EINVAL;
+ }
+
+ if (host0 != SMEM_GLOBAL_HOST && host1 != SMEM_GLOBAL_HOST) {
+ dev_err(smem->dev, "Global partition hosts are invalid\n");
+ return -EINVAL;
+ }
+
+ if (le32_to_cpu(header->size) != le32_to_cpu(entry->size)) {
+ dev_err(smem->dev, "Global partition has invalid size\n");
+ return -EINVAL;
+ }
+
+ size = le32_to_cpu(header->offset_free_uncached);
+ if (size > le32_to_cpu(header->size)) {
+ dev_err(smem->dev,
+ "Global partition has invalid free pointer\n");
+ return -EINVAL;
+ }
+
+ smem->global_partition = header;
+ smem->global_cacheline = le32_to_cpu(entry->cacheline);
+
+ return 0;
+}
+
+static int qcom_smem_enumerate_partitions(struct qcom_smem *smem,
+ unsigned int local_host)
+{
+ struct smem_partition_header *header;
+ struct smem_ptable_entry *entry;
+ struct smem_ptable *ptable;
+ unsigned int remote_host;
+ u32 host0, host1;
+ int i;
+
+ ptable = qcom_smem_get_ptable(smem);
+ if (IS_ERR(ptable))
+ return PTR_ERR(ptable);
+
+ for (i = 0; i < le32_to_cpu(ptable->num_entries); i++) {
+ entry = &ptable->entry[i];
+ host0 = le16_to_cpu(entry->host0);
+ host1 = le16_to_cpu(entry->host1);
+
+ if (host0 != local_host && host1 != local_host)
+ continue;
+
+ if (!le32_to_cpu(entry->offset))
+ continue;
+
+ if (!le32_to_cpu(entry->size))
+ continue;
+
+ if (host0 == local_host)
+ remote_host = host1;
+ else
+ remote_host = host0;
+
+ if (remote_host >= SMEM_HOST_COUNT) {
+ dev_err(smem->dev,
+ "Invalid remote host %d\n",
+ remote_host);
+ return -EINVAL;
+ }
+
+ if (smem->partitions[remote_host]) {
+ dev_err(smem->dev,
+ "Already found a partition for host %d\n",
+ remote_host);
+ return -EINVAL;
+ }
+
+ header = smem->regions[0].virt_base + le32_to_cpu(entry->offset);
+ host0 = le16_to_cpu(header->host0);
+ host1 = le16_to_cpu(header->host1);
+
+ if (memcmp(header->magic, SMEM_PART_MAGIC,
+ sizeof(header->magic))) {
+ dev_err(smem->dev,
+ "Partition %d has invalid magic\n", i);
+ return -EINVAL;
+ }
+
+ if (host0 != local_host && host1 != local_host) {
+ dev_err(smem->dev,
+ "Partition %d hosts are invalid\n", i);
+ return -EINVAL;
+ }
+
+ if (host0 != remote_host && host1 != remote_host) {
+ dev_err(smem->dev,
+ "Partition %d hosts are invalid\n", i);
+ return -EINVAL;
+ }
+
+ if (le32_to_cpu(header->size) != le32_to_cpu(entry->size)) {
+ dev_err(smem->dev,
+ "Partition %d has invalid size\n", i);
+ return -EINVAL;
+ }
+
+ if (le32_to_cpu(header->offset_free_uncached) > le32_to_cpu(header->size)) {
+ dev_err(smem->dev,
+ "Partition %d has invalid free pointer\n", i);
+ return -EINVAL;
+ }
+
+ smem->partitions[remote_host] = header;
+ smem->cacheline[remote_host] = le32_to_cpu(entry->cacheline);
+ }
+
+ return 0;
+}
+
+static int qcom_smem_map_memory(struct qcom_smem *smem, struct udevice *dev,
+ const char *name, int i)
+{
+ struct fdt_resource r;
+ int ret;
+ int node = dev_of_offset(dev);
+
+ ret = fdtdec_lookup_phandle(gd->fdt_blob, node, name);
+ if (ret < 0) {
+ dev_err(dev, "No %s specified\n", name);
+ return -EINVAL;
+ }
+
+ ret = fdt_get_resource(gd->fdt_blob, ret, "reg", 0, &r);
+ if (ret)
+ return ret;
+
+ smem->regions[i].aux_base = (u32)r.start;
+ smem->regions[i].size = fdt_resource_size(&r);
+ smem->regions[i].virt_base = devm_ioremap(dev, r.start, fdt_resource_size(&r));
+ if (!smem->regions[i].virt_base)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static int qcom_smem_probe(struct udevice *dev)
+{
+ struct smem_header *header;
+ struct qcom_smem *smem;
+ size_t array_size;
+ int num_regions;
+ u32 version;
+ int ret;
+ int node = dev_of_offset(dev);
+
+ num_regions = 1;
+ if (fdtdec_lookup_phandle(gd->fdt_blob, node, "qcomrpm-msg-ram") >= 0)
+ num_regions++;
+
+ array_size = num_regions * sizeof(struct smem_region);
+ smem = devm_kzalloc(dev, sizeof(*smem) + array_size, GFP_KERNEL);
+ if (!smem)
+ return -ENOMEM;
+
+ smem->dev = dev;
+ smem->num_regions = num_regions;
+
+ ret = qcom_smem_map_memory(smem, dev, "memory-region", 0);
+ if (ret)
+ return ret;
+
+ if (num_regions > 1) {
+ ret = qcom_smem_map_memory(smem, dev,
+ "qcom,rpm-msg-ram", 1);
+ if (ret)
+ return ret;
+ }
+
+ header = smem->regions[0].virt_base;
+ if (le32_to_cpu(header->initialized) != 1 ||
+ le32_to_cpu(header->reserved)) {
+ dev_err(&pdev->dev, "SMEM is not initialized by SBL\n");
+ return -EINVAL;
+ }
+
+ version = qcom_smem_get_sbl_version(smem);
+ switch (version >> 16) {
+ case SMEM_GLOBAL_PART_VERSION:
+ ret = qcom_smem_set_global_partition(smem);
+ if (ret < 0)
+ return ret;
+ smem->item_count = qcom_smem_get_item_count(smem);
+ break;
+ case SMEM_GLOBAL_HEAP_VERSION:
+ smem->item_count = SMEM_ITEM_COUNT;
+ break;
+ default:
+ dev_err(dev, "Unsupported SMEM version 0x%x\n", version);
+ return -EINVAL;
+ }
+
+ ret = qcom_smem_enumerate_partitions(smem, SMEM_HOST_APPS);
+ if (ret < 0 && ret != -ENOENT)
+ return ret;
+
+ __smem = smem;
+
+ return 0;
+}
+
+static int qcom_smem_remove(struct udevice *dev)
+{
+ __smem = NULL;
+
+ return 0;
+}
+
+const struct udevice_id qcom_smem_of_match[] = {
+ { .compatible = "qcom,smem" },
+ { }
+};
+
+static const struct smem_ops msm_smem_ops = {
+ .alloc = qcom_smem_alloc,
+ .get = qcom_smem_get,
+ .get_free_space = qcom_smem_get_free_space,
+};
+
+U_BOOT_DRIVER(qcom_smem) = {
+ .name = "qcom_smem",
+ .id = UCLASS_SMEM,
+ .of_match = qcom_smem_of_match,
+ .ops = &msm_smem_ops,
+ .probe = qcom_smem_probe,
+ .remove = qcom_smem_remove,
+};
diff --git a/drivers/smem/sandbox_smem.c b/drivers/smem/sandbox_smem.c
new file mode 100644
index 0000000..7397e44
--- /dev/null
+++ b/drivers/smem/sandbox_smem.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <smem.h>
+#include <asm/test.h>
+
+static int sandbox_smem_alloc(unsigned int host,
+ unsigned int item, size_t size)
+{
+ return 0;
+}
+
+static void *sandbox_smem_get(unsigned int host,
+ unsigned int item, size_t *size)
+{
+ return NULL;
+}
+
+static int sandbox_smem_get_free_space(unsigned int host)
+{
+ return 0;
+}
+
+static const struct smem_ops sandbox_smem_ops = {
+ .alloc = sandbox_smem_alloc,
+ .get = sandbox_smem_get,
+ .get_free_space = sandbox_smem_get_free_space,
+};
+
+static const struct udevice_id sandbox_smem_ids[] = {
+ { .compatible = "sandbox,smem" },
+ { }
+};
+
+U_BOOT_DRIVER(smem_sandbox) = {
+ .name = "smem_sandbox",
+ .id = UCLASS_SMEM,
+ .of_match = sandbox_smem_ids,
+ .ops = &sandbox_smem_ops,
+};
diff --git a/drivers/smem/smem-uclass.c b/drivers/smem/smem-uclass.c
new file mode 100644
index 0000000..ce7bf40
--- /dev/null
+++ b/drivers/smem/smem-uclass.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <smem.h>
+
+int smem_alloc(struct udevice *dev, unsigned int host,
+ unsigned int item, size_t size)
+{
+ struct smem_ops *ops = smem_get_ops(dev);
+
+ if (!ops->alloc)
+ return -ENOSYS;
+
+ return ops->alloc(host, item, size);
+}
+
+void *smem_get(struct udevice *dev, unsigned int host,
+ unsigned int item, size_t *size)
+{
+ struct smem_ops *ops = smem_get_ops(dev);
+
+ if (!ops->get)
+ return NULL;
+
+ return ops->get(host, item, size);
+}
+
+int smem_get_free_space(struct udevice *dev, unsigned int host)
+{
+ struct smem_ops *ops = smem_get_ops(dev);
+
+ if (!ops->get_free_space)
+ return -ENOSYS;
+
+ return ops->get_free_space(host);
+}
+
+UCLASS_DRIVER(smem) = {
+ .id = UCLASS_SMEM,
+ .name = "smem",
+};
diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c
index f19e80e..3450640 100644
--- a/drivers/sysreset/sysreset_syscon.c
+++ b/drivers/sysreset/sysreset_syscon.c
@@ -35,18 +35,20 @@ static struct sysreset_ops syscon_reboot_ops = {
int syscon_reboot_probe(struct udevice *dev)
{
- struct udevice *syscon;
struct syscon_reboot_priv *priv = dev_get_priv(dev);
int err;
+ u32 phandle;
+ ofnode node;
- err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
- "regmap", &syscon);
- if (err) {
- pr_err("unable to find syscon device\n");
+ err = ofnode_read_u32(dev_ofnode(dev), "regmap", &phandle);
+ if (err)
return err;
- }
- priv->regmap = syscon_get_regmap(syscon);
+ node = ofnode_get_by_phandle(phandle);
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ priv->regmap = syscon_node_to_regmap(node);
if (!priv->regmap) {
pr_err("unable to find regmap\n");
return -ENODEV;
generated by cgit v1.1 at 2024-09-16 14:58:43 +0000