diff options
Diffstat (limited to 'drivers/ram')
-rw-r--r-- | drivers/ram/k3-am654-ddrss.c | 55 | ||||
-rw-r--r-- | drivers/ram/k3-am654-ddrss.h | 10 |
2 files changed, 58 insertions, 7 deletions
diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c index 100cb9f..7015d8c 100644 --- a/drivers/ram/k3-am654-ddrss.c +++ b/drivers/ram/k3-am654-ddrss.c @@ -259,6 +259,8 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0); ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1); + ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0); + ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3); ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5); ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0); @@ -294,6 +296,10 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2); ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl); + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl); + debug("%s: DDR phy register configuration completed\n", __func__); } @@ -479,18 +485,43 @@ int VREF_training(struct am654_ddrss_desc *ddrss) int enable_dqs_pd(struct am654_ddrss_desc *ddrss) { - ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x012640F7); - ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x012640F7); - ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x012640F7); + u32 val; + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL); + val &= ~0xFF; + val |= 0xF7; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val); + sdelay(16); return 0; } int disable_dqs_pd(struct am654_ddrss_desc *ddrss) { - ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, 0x01264000); - ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, 0x01264000); - ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, 0x01264000); + u32 val; + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val); + + val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL); + val &= ~0xFF; + ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val); + sdelay(16); return 0; } @@ -595,12 +626,14 @@ static int am654_ddrss_init(struct am654_ddrss_desc *ddrss) { int ret; u32 val; + struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg; debug("Starting DDR initialization...\n"); debug("%s(ddrss=%p)\n", __func__, ddrss); - ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF); + ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, + reg->ddrss_v2h_ctl_reg); am654_ddrss_ctrl_configuration(ddrss); @@ -901,6 +934,14 @@ static int am654_ddrss_ofdata_to_priv(struct udevice *dev) } ddrss->ddrss_phy_cfg = (void *)reg; + ret = dev_read_u32_array(dev, "ti,ss-reg", + (u32 *)&ddrss->params.ss_reg, + sizeof(ddrss->params.ss_reg) / sizeof(u32)); + if (ret) { + dev_err(dev, "Cannot read ti,ss-reg params\n"); + return ret; + } + ret = dev_read_u32_array(dev, "ti,ctl-reg", (u32 *)&ddrss->params.ctl_reg, sizeof(ddrss->params.ctl_reg) / sizeof(u32)); diff --git a/drivers/ram/k3-am654-ddrss.h b/drivers/ram/k3-am654-ddrss.h index 78d73cd..94a7c91 100644 --- a/drivers/ram/k3-am654-ddrss.h +++ b/drivers/ram/k3-am654-ddrss.h @@ -996,6 +996,10 @@ PGSR0_DIDONE_MASK) #define PGSR0_DATA_TR_INIT_MASK (PGSR0_DRAM_INIT_MASK) +struct ddrss_ss_reg_params { + u32 ddrss_v2h_ctl_reg; +}; + struct ddrss_ddrctl_reg_params { u32 ddrctl_dfimisc; u32 ddrctl_dfitmg0; @@ -1111,12 +1115,15 @@ struct ddrss_ddrphy_cfg_params { u32 ddrphy_dx8sl0dxctl2; u32 ddrphy_dx8sl0iocr; u32 ddrphy_dx8sl0pllcr0; + u32 ddrphy_dx8sl0dqsctl; u32 ddrphy_dx8sl1dxctl2; u32 ddrphy_dx8sl1iocr; u32 ddrphy_dx8sl1pllcr0; + u32 ddrphy_dx8sl1dqsctl; u32 ddrphy_dx8sl2dxctl2; u32 ddrphy_dx8sl2iocr; u32 ddrphy_dx8sl2pllcr0; + u32 ddrphy_dx8sl2dqsctl; u32 ddrphy_dxccr; u32 ddrphy_odtcr; u32 ddrphy_pgcr0; @@ -1147,6 +1154,8 @@ struct ddrss_ddrphy_ctrl_params { }; struct ddrss_ddrphy_ioctl_params { + u32 ddrphy_aciocr0; + u32 ddrphy_aciocr3; u32 ddrphy_aciocr5; u32 ddrphy_iovcr0; }; @@ -1173,6 +1182,7 @@ struct ddrss_ddrphy_zq_params { }; struct ddrss_params { + struct ddrss_ss_reg_params ss_reg; struct ddrss_ddrctl_reg_params ctl_reg; struct ddrss_ddrctl_crc_params ctl_crc; struct ddrss_ddrctl_ecc_params ctl_ecc; |