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path: root/drivers/pci/pci-aardvark.c
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Diffstat (limited to 'drivers/pci/pci-aardvark.c')
-rw-r--r--drivers/pci/pci-aardvark.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 38eff49..9e623b6 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -445,7 +445,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
* for returning CRS, so that if U-Boot does support CRS in the future,
* it will work for Aardvark.
*/
- allow_crs = pcie->cfgcrssve;
+ allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve;
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
@@ -581,6 +581,10 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
if (offset >= 0x10 && offset < 0x34) {
data = pcie->cfgcache[(offset - 0x10) / 4];
data = pci_conv_size_to_32(data, value, offset, size);
+ /* This PCI bridge does not have configurable bars */
+ if ((offset & ~3) == PCI_BASE_ADDRESS_0 ||
+ (offset & ~3) == PCI_BASE_ADDRESS_1)
+ data = 0x0;
pcie->cfgcache[(offset - 0x10) / 4] = data;
} else if ((offset & ~3) == PCI_ROM_ADDRESS1) {
data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG);