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-rw-r--r--drivers/net/bcm6368-eth.c3
-rw-r--r--drivers/net/dwc_eth_qos.c7
-rw-r--r--drivers/net/ftgmac100.c4
-rw-r--r--drivers/net/mvneta.c56
-rw-r--r--drivers/net/mvpp2.c87
-rw-r--r--drivers/net/phy/mscc.c129
-rw-r--r--drivers/net/smc911x.c3
-rw-r--r--drivers/net/sun8i_emac.c9
-rw-r--r--drivers/net/sunxi_emac.c5
-rw-r--r--drivers/net/ti/cpsw.c6
10 files changed, 205 insertions, 104 deletions
diff --git a/drivers/net/bcm6368-eth.c b/drivers/net/bcm6368-eth.c
index 648fafd..38a2a30 100644
--- a/drivers/net/bcm6368-eth.c
+++ b/drivers/net/bcm6368-eth.c
@@ -249,8 +249,7 @@ static int bcm6368_eth_adjust_link(struct udevice *dev)
/* link changed */
if (!up) {
- dev_info(&priv->pdev->dev, "link DOWN on %s\n",
- port->name);
+ dev_info(dev, "link DOWN on %s\n", port->name);
writeb_be(ETH_PORTOV_ENABLE_MASK,
priv->base + ETH_PORTOV_REG(i));
writeb_be(ETH_PTCTRL_RXDIS_MASK |
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 810a2b9..db11025 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -26,6 +26,7 @@
* supports a single RGMII PHY. This configuration also has SW control over
* all clock and reset signals to the HW block.
*/
+
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
@@ -1893,8 +1894,7 @@ static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
interface = phy_get_interface_by_name(phy_mode);
@@ -1931,8 +1931,7 @@ static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
- NULL);
+ phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
interface = phy_get_interface_by_name(phy_mode);
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 5676a5b..00bda24 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -551,6 +551,10 @@ static int ftgmac100_probe(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
+#ifdef CONFIG_PHY_ADDR
+ priv->phy_addr = CONFIG_PHY_ADDR;
+#endif
+
ret = clk_enable_bulk(&priv->clks);
if (ret)
goto out;
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 4c7d06c..83f99e5 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -625,9 +625,9 @@ static void mvneta_port_down(struct mvneta_port *pp)
count = 0;
do {
if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
- netdev_warn(pp->dev,
- "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
- val);
+ dev_warn(pp->phydev->dev,
+ "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
+ val);
break;
}
mdelay(1);
@@ -648,9 +648,9 @@ static void mvneta_port_down(struct mvneta_port *pp)
count = 0;
do {
if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
- netdev_warn(pp->dev,
- "TIMEOUT for TX stopped status=0x%08x\n",
- val);
+ dev_warn(pp->phydev->dev,
+ "TIMEOUT for TX stopped status=0x%08x\n",
+ val);
break;
}
mdelay(1);
@@ -664,9 +664,9 @@ static void mvneta_port_down(struct mvneta_port *pp)
count = 0;
do {
if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
- netdev_warn(pp->dev,
- "TX FIFO empty timeout status=0x08%x\n",
- val);
+ dev_warn(pp->phydev->dev,
+ "TX FIFO empty timeout status=0x08%x\n",
+ val);
break;
}
mdelay(1);
@@ -949,28 +949,32 @@ static void mvneta_rx_error(struct mvneta_port *pp,
u32 status = rx_desc->status;
if (!mvneta_rxq_desc_is_first_last(status)) {
- netdev_err(pp->dev,
- "bad rx status %08x (buffer oversize), size=%d\n",
- status, rx_desc->data_size);
+ dev_err(pp->phydev->dev,
+ "bad rx status %08x (buffer oversize), size=%d\n",
+ status, rx_desc->data_size);
return;
}
switch (status & MVNETA_RXD_ERR_CODE_MASK) {
case MVNETA_RXD_ERR_CRC:
- netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
- status, rx_desc->data_size);
+ dev_err(pp->phydev->dev,
+ "bad rx status %08x (crc error), size=%d\n", status,
+ rx_desc->data_size);
break;
case MVNETA_RXD_ERR_OVERRUN:
- netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
- status, rx_desc->data_size);
+ dev_err(pp->phydev->dev,
+ "bad rx status %08x (overrun error), size=%d\n", status,
+ rx_desc->data_size);
break;
case MVNETA_RXD_ERR_LEN:
- netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
- status, rx_desc->data_size);
+ dev_err(pp->phydev->dev,
+ "bad rx status %08x (max frame length error), size=%d\n",
+ status, rx_desc->data_size);
break;
case MVNETA_RXD_ERR_RESOURCE:
- netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
- status, rx_desc->data_size);
+ dev_err(pp->phydev->dev,
+ "bad rx status %08x (resource error), size=%d\n",
+ status, rx_desc->data_size);
break;
}
}
@@ -1127,8 +1131,8 @@ static int mvneta_setup_rxqs(struct mvneta_port *pp)
for (queue = 0; queue < rxq_number; queue++) {
int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
if (err) {
- netdev_err(pp->dev, "%s: can't create rxq=%d\n",
- __func__, queue);
+ dev_err(pp->phydev->dev, "%s: can't create rxq=%d\n",
+ __func__, queue);
mvneta_cleanup_rxqs(pp);
return err;
}
@@ -1145,8 +1149,8 @@ static int mvneta_setup_txqs(struct mvneta_port *pp)
for (queue = 0; queue < txq_number; queue++) {
int err = mvneta_txq_init(pp, &pp->txqs[queue]);
if (err) {
- netdev_err(pp->dev, "%s: can't create txq=%d\n",
- __func__, queue);
+ dev_err(pp->phydev->dev, "%s: can't create txq=%d\n",
+ __func__, queue);
mvneta_cleanup_txqs(pp);
return err;
}
@@ -1402,7 +1406,7 @@ static int mvneta_init(struct udevice *dev)
err = mvneta_init2(pp);
if (err < 0) {
- dev_err(&pdev->dev, "can't init eth hal\n");
+ dev_err(dev, "can't init eth hal\n");
return err;
}
@@ -1410,7 +1414,7 @@ static int mvneta_init(struct udevice *dev)
err = mvneta_port_power_up(pp, pp->phy_interface);
if (err < 0) {
- dev_err(&pdev->dev, "can't power up port\n");
+ dev_err(dev, "can't power up port\n");
return err;
}
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index a5747a2..8f790a8 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2568,7 +2568,7 @@ static int mvpp2_bm_pool_create(struct udevice *dev,
if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
MVPP2_BM_POOL_PTR_ALIGN)) {
- dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
+ dev_err(dev, "BM pool %d is not %d bytes aligned\n",
bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
return -ENOMEM;
}
@@ -2659,7 +2659,7 @@ static int mvpp2_bm_pools_init(struct udevice *dev,
return 0;
err_unroll_pools:
- dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
+ dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
for (i = i - 1; i >= 0; i--)
mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
return err;
@@ -2773,9 +2773,9 @@ static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
if (buf_num < 0 ||
(buf_num + bm_pool->buf_num > bm_pool->size)) {
- netdev_err(port->dev,
- "cannot allocate %d buffers for pool %d\n",
- buf_num, bm_pool->id);
+ dev_err(port->phy_dev->dev,
+ "cannot allocate %d buffers for pool %d\n", buf_num,
+ bm_pool->id);
return 0;
}
@@ -2803,7 +2803,7 @@ mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
int num;
if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
- netdev_err(port->dev, "mixing pool types is forbidden\n");
+ dev_err(port->phy_dev->dev, "mixing pool types is forbidden\n");
return NULL;
}
@@ -2834,8 +2834,9 @@ mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
/* Allocate buffers for this pool */
num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
if (num != pkts_num) {
- dev_err(dev, "pool %d: %d of %d allocated\n",
- new_pool->id, num, pkts_num);
+ dev_err(port->phy_dev->dev,
+ "pool %d: %d of %d allocated\n", new_pool->id,
+ num, pkts_num);
return NULL;
}
}
@@ -3344,8 +3345,7 @@ static int gop_port_init(struct mvpp2_port *port)
int num_of_act_lanes;
if (mac_num >= MVPP22_GOP_MAC_NUM) {
- netdev_err(NULL, "%s: illegal port number %d", __func__,
- mac_num);
+ log_err("illegal port number %d", mac_num);
return -1;
}
@@ -3399,8 +3399,8 @@ static int gop_port_init(struct mvpp2_port *port)
break;
default:
- netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
- __func__, port->phy_interface);
+ log_err("Requested port mode (%d) not supported\n",
+ port->phy_interface);
return -1;
}
@@ -3440,8 +3440,8 @@ static void gop_port_enable(struct mvpp2_port *port, int enable)
break;
default:
- netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
- port->phy_interface);
+ log_err("%s: Wrong port mode (%d)\n", __func__,
+ port->phy_interface);
return;
}
}
@@ -3811,9 +3811,9 @@ static void mvpp2_egress_disable(struct mvpp2_port *port)
delay = 0;
do {
if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
- netdev_warn(port->dev,
- "Tx stop timed out, status=0x%08x\n",
- reg_data);
+ dev_warn(port->phy_dev->dev,
+ "Tx stop timed out, status=0x%08x\n",
+ reg_data);
break;
}
mdelay(1);
@@ -4261,9 +4261,9 @@ static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
delay = 0;
do {
if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
- netdev_warn(port->dev,
- "port %d: cleaning queue %d timed out\n",
- port->id, txq->log_id);
+ dev_warn(port->phy_dev->dev,
+ "port %d: cleaning queue %d timed out\n",
+ port->id, txq->log_id);
break;
}
mdelay(1);
@@ -4430,16 +4430,19 @@ static void mvpp2_rx_error(struct mvpp2_port *port,
switch (status & MVPP2_RXD_ERR_CODE_MASK) {
case MVPP2_RXD_ERR_CRC:
- netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
- status, sz);
+ dev_err(port->phy_dev->dev,
+ "bad rx status %08x (crc error), size=%zu\n", status,
+ sz);
break;
case MVPP2_RXD_ERR_OVERRUN:
- netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
- status, sz);
+ dev_err(port->phy_dev->dev,
+ "bad rx status %08x (overrun error), size=%zu\n",
+ status, sz);
break;
case MVPP2_RXD_ERR_RESOURCE:
- netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
- status, sz);
+ dev_err(port->phy_dev->dev,
+ "bad rx status %08x (resource error), size=%zu\n",
+ status, sz);
break;
}
}
@@ -4507,8 +4510,8 @@ static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
*/
if (phy_dev &&
phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
- netdev_warn(port->dev,
- "Marking phy as invalid, link will not be checked\n");
+ dev_warn(port->phy_dev->dev,
+ "Marking phy as invalid, link will not be checked\n");
/* set phy_addr to invalid value */
port->phyaddr = PHY_MAX_ADDR;
mvpp2_egress_enable(port);
@@ -4519,7 +4522,7 @@ static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
port->phy_dev = phy_dev;
if (!phy_dev) {
- netdev_err(port->dev, "cannot connect to phy\n");
+ dev_err(port->phy_dev->dev, "cannot connect to phy\n");
return;
}
phy_dev->supported &= PHY_GBIT_FEATURES;
@@ -4550,31 +4553,31 @@ static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
if (err) {
- netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
+ dev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
return err;
}
err = mvpp2_prs_mac_da_accept(port->priv, port->id,
port->dev_addr, true);
if (err) {
- netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
+ dev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
return err;
}
err = mvpp2_prs_def_flow(port);
if (err) {
- netdev_err(dev, "mvpp2_prs_def_flow failed\n");
+ dev_err(dev, "mvpp2_prs_def_flow failed\n");
return err;
}
/* Allocate the Rx/Tx queues */
err = mvpp2_setup_rxqs(port);
if (err) {
- netdev_err(port->dev, "cannot allocate Rx queues\n");
+ dev_err(port->phy_dev->dev, "cannot allocate Rx queues\n");
return err;
}
err = mvpp2_setup_txqs(port);
if (err) {
- netdev_err(port->dev, "cannot allocate Tx queues\n");
+ dev_err(port->phy_dev->dev, "cannot allocate Tx queues\n");
return err;
}
@@ -4725,7 +4728,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
int parent;
phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
if (phyaddr < 0) {
- dev_err(&pdev->dev, "could not find phy address\n");
+ dev_err(dev, "could not find phy address\n");
return -1;
}
parent = fdt_parent_offset(gd->fdt_blob, phy_node);
@@ -4742,13 +4745,13 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
if (phy_mode_str)
phy_mode = phy_get_interface_by_name(phy_mode_str);
if (phy_mode == -1) {
- dev_err(&pdev->dev, "incorrect phy mode\n");
+ dev_err(dev, "incorrect phy mode\n");
return -EINVAL;
}
id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
if (id == -1) {
- dev_err(&pdev->dev, "missing port-id value\n");
+ dev_err(dev, "missing port-id value\n");
return -EINVAL;
}
@@ -4807,7 +4810,7 @@ static int mvpp2_port_probe(struct udevice *dev,
err = mvpp2_port_init(dev, port);
if (err < 0) {
- dev_err(&pdev->dev, "failed to init port %d\n", port->id);
+ dev_err(dev, "failed to init port %d\n", port->id);
return err;
}
mvpp2_port_power_up(port);
@@ -4978,7 +4981,7 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
/* Checks for hardware constraints (U-Boot uses only one rxq) */
if ((rxq_number > priv->max_port_rxqs) ||
(txq_number > MVPP2_MAX_TXQ)) {
- dev_err(&pdev->dev, "invalid queue size parameter\n");
+ dev_err(dev, "invalid queue size parameter\n");
return -EINVAL;
}
@@ -5099,7 +5102,7 @@ static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
if (err) {
- netdev_err(port->dev, "failed to refill BM pools\n");
+ dev_err(port->phy_dev->dev, "failed to refill BM pools\n");
return 0;
}
@@ -5345,7 +5348,7 @@ static int mvpp2_probe(struct udevice *dev)
port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gop-port-id", -1);
if (port->id == -1) {
- dev_err(&pdev->dev, "missing gop-port-id value\n");
+ dev_err(dev, "missing gop-port-id value\n");
return -EINVAL;
}
@@ -5364,7 +5367,7 @@ static int mvpp2_probe(struct udevice *dev)
/* Initialize network controller */
err = mvpp2_init(dev, priv);
if (err < 0) {
- dev_err(&pdev->dev, "failed to initialize controller\n");
+ dev_err(dev, "failed to initialize controller\n");
return err;
}
priv->num_ports = 0;
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 709979f..d1a643c 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -157,6 +157,14 @@
#define INT_MEM_DATA_M GENMASK(7, 0)
#define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))
+/* Extended page GPIO register 13G */
+#define MSCC_CLKOUT_CNTL 13
+#define CLKOUT_ENABLE BIT(15)
+#define CLKOUT_FREQ_MASK GENMASK(14, 13)
+#define CLKOUT_FREQ_25M (0x0 << 13)
+#define CLKOUT_FREQ_50M (0x1 << 13)
+#define CLKOUT_FREQ_125M (0x2 << 13)
+
/* Extended page GPIO register 18G */
#define MSCC_PHY_PROC_CMD 18
#define PROC_CMD_NCOMPLETED BIT(15)
@@ -1168,6 +1176,9 @@ static int vsc8531_vsc8541_mac_config(struct phy_device *phydev)
rx_clk_out = RX_CLK_OUT_NORMAL;
break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII:
/* Set Reg23.12:11=2 */
mac_if = MAC_IF_SELECTION_RGMII;
@@ -1210,13 +1221,84 @@ static int vsc8531_vsc8541_mac_config(struct phy_device *phydev)
return 0;
}
+static int vsc8531_vsc8541_clkout_config(struct phy_device *phydev)
+{
+ struct ofnode_phandle_args phandle_args;
+ u32 clkout_rate = 0;
+ u16 reg_val;
+ int retval;
+
+ retval = dev_read_phandle_with_args(phydev->dev, "phy-handle", NULL,
+ 0, 0, &phandle_args);
+ if (!retval)
+ clkout_rate = ofnode_read_u32_default(phandle_args.node,
+ "vsc8531,clk-out-frequency", 0);
+
+ switch (clkout_rate) {
+ case 0:
+ reg_val = 0;
+ break;
+ case 25000000:
+ reg_val = CLKOUT_FREQ_25M | CLKOUT_ENABLE;
+ break;
+ case 50000000:
+ reg_val = CLKOUT_FREQ_50M | CLKOUT_ENABLE;
+ break;
+ case 125000000:
+ reg_val = CLKOUT_FREQ_125M | CLKOUT_ENABLE;
+ break;
+ default:
+ printf("PHY 8530/31 invalid clkout rate %u\n",
+ clkout_rate);
+ return -EINVAL;
+ }
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_GPIO);
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_CLKOUT_CNTL, reg_val);
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return 0;
+}
+
+static int vsc8531_vsc8541_clk_skew_config(struct phy_device *phydev)
+{
+ enum vsc_phy_rgmii_skew rx_clk_skew = VSC_PHY_RGMII_DELAY_200_PS;
+ enum vsc_phy_rgmii_skew tx_clk_skew = VSC_PHY_RGMII_DELAY_200_PS;
+ u16 reg_val;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ rx_clk_skew = VSC_PHY_RGMII_DELAY_2000_PS;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+ phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
+ tx_clk_skew = VSC_PHY_RGMII_DELAY_2000_PS;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_EXT2);
+ reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);
+
+ /* Reg20E2 - Update RGMII RX_Clk Skews. */
+ reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,
+ RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew);
+ /* Reg20E2 - Update RGMII TX_Clk Skews. */
+ reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,
+ RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);
+ phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
+ MSCC_PHY_PAGE_STD);
+
+ return 0;
+}
+
static int vsc8531_config(struct phy_device *phydev)
{
int retval = -EINVAL;
u16 reg_val;
u16 rmii_clk_out;
- enum vsc_phy_rgmii_skew rx_clk_skew = VSC_PHY_RGMII_DELAY_1700_PS;
- enum vsc_phy_rgmii_skew tx_clk_skew = VSC_PHY_RGMII_DELAY_800_PS;
enum vsc_phy_clk_slew edge_rate = VSC_PHY_CLK_SLEW_RATE_4;
/* For VSC8530/31 and VSC8540/41 the init scripts are the same */
@@ -1226,6 +1308,9 @@ static int vsc8531_config(struct phy_device *phydev)
switch (phydev->interface) {
case PHY_INTERFACE_MODE_RMII:
case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_ID:
retval = vsc8531_vsc8541_mac_config(phydev);
if (retval != 0)
return retval;
@@ -1242,19 +1327,12 @@ static int vsc8531_config(struct phy_device *phydev)
/* Default RMII Clk Output to 0=OFF/1=ON */
rmii_clk_out = 0;
+ retval = vsc8531_vsc8541_clk_skew_config(phydev);
+ if (retval != 0)
+ return retval;
+
phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_EXT2);
- reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);
-
- /* Reg20E2 - Update RGMII RX_Clk Skews. */
- reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,
- RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew);
- /* Reg20E2 - Update RGMII TX_Clk Skews. */
- reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,
- RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew);
-
- phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);
-
reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL);
/* Reg27E2 - Update Clk Slew Rate. */
reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS,
@@ -1267,6 +1345,11 @@ static int vsc8531_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_STD);
+ /* Configure the clk output */
+ retval = vsc8531_vsc8541_clkout_config(phydev);
+ if (retval != 0)
+ return retval;
+
return genphy_config_aneg(phydev);
}
@@ -1275,8 +1358,6 @@ static int vsc8541_config(struct phy_device *phydev)
int retval = -EINVAL;
u16 reg_val;
u16 rmii_clk_out;
- enum vsc_phy_rgmii_skew rx_clk_skew = VSC_PHY_RGMII_DELAY_1700_PS;
- enum vsc_phy_rgmii_skew tx_clk_skew = VSC_PHY_RGMII_DELAY_800_PS;
enum vsc_phy_clk_slew edge_rate = VSC_PHY_CLK_SLEW_RATE_4;
/* For VSC8530/31 and VSC8540/41 the init scripts are the same */
@@ -1304,17 +1385,12 @@ static int vsc8541_config(struct phy_device *phydev)
/* Default RMII Clk Output to 0=OFF/1=ON */
rmii_clk_out = 0;
+ retval = vsc8531_vsc8541_clk_skew_config(phydev);
+ if (retval != 0)
+ return retval;
+
phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_EXT2);
- reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG);
- /* Reg20E2 - Update RGMII RX_Clk Skews. */
- reg_val = bitfield_replace(reg_val, RGMII_RX_CLK_DELAY_POS,
- RGMII_RX_CLK_DELAY_WIDTH, rx_clk_skew);
- /* Reg20E2 - Update RGMII TX_Clk Skews. */
- reg_val = bitfield_replace(reg_val, RGMII_TX_CLK_DELAY_POS,
- RGMII_TX_CLK_DELAY_WIDTH, tx_clk_skew);
- phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_RGMII_CNTL_REG, reg_val);
-
reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_WOL_MAC_CONTROL);
/* Reg27E2 - Update Clk Slew Rate. */
reg_val = bitfield_replace(reg_val, EDGE_RATE_CNTL_POS,
@@ -1327,6 +1403,11 @@ static int vsc8541_config(struct phy_device *phydev)
phy_write(phydev, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_STD);
+ /* Configure the clk output */
+ retval = vsc8531_vsc8541_clkout_config(phydev);
+ if (retval != 0)
+ return retval;
+
return genphy_config_aneg(phydev);
}
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index 09372d7..1fa3667 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <env.h>
#include <command.h>
#include <malloc.h>
#include <net.h>
@@ -185,6 +186,8 @@ static void smc911x_handle_mac_address(struct smc911x_priv *priv)
smc911x_set_mac_csr(priv, ADDRH, addrh);
printf(DRIVERNAME ": MAC %pM\n", m);
+ if (!env_get("ethaddr"))
+ env_set("ethaddr", (const char *)m);
}
static bool smc911x_read_mac_address(struct smc911x_priv *priv)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 546cc6c..1dae81c 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -663,7 +663,8 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
return _sun8i_write_hwaddr(priv, pdata->enetaddr);
}
-static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
+static int sun8i_emac_board_setup(struct udevice *dev,
+ struct emac_eth_dev *priv)
{
int ret;
@@ -833,7 +834,7 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
priv->mac_reg = (void *)pdata->iobase;
- ret = sun8i_emac_board_setup(priv);
+ ret = sun8i_emac_board_setup(dev, priv);
if (ret)
return ret;
@@ -854,7 +855,7 @@ static const struct eth_ops sun8i_emac_eth_ops = {
.stop = sun8i_emac_eth_stop,
};
-static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
+static int sun8i_get_ephy_nodes(struct udevice *dev, struct emac_eth_dev *priv)
{
int emac_node, ephy_node, ret, ephy_handle;
@@ -986,7 +987,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
}
if (priv->variant == H3_EMAC) {
- ret = sun8i_get_ephy_nodes(priv);
+ ret = sun8i_get_ephy_nodes(dev, priv);
if (ret)
return ret;
}
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index df18ecc..8e66ce2 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -505,7 +505,8 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
return 0;
}
-static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static int sunxi_emac_board_setup(struct udevice *dev,
+ struct emac_eth_dev *priv)
{
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
@@ -576,7 +577,7 @@ static int sunxi_emac_eth_probe(struct udevice *dev)
return ret;
}
- ret = sunxi_emac_board_setup(priv);
+ ret = sunxi_emac_board_setup(dev, priv);
if (ret)
return ret;
diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index d6fefe5..1c11257 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -856,8 +856,14 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
ret = phy_set_supported(phydev, slave->data->max_speed);
if (ret)
return ret;
+#if CONFIG_IS_ENABLED(DM_ETH)
dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
slave->slave_num + 1, slave->data->max_speed);
+#else
+ log_debug("%s: Port %u speed forced to %uMbit\n",
+ priv->dev->name, slave->slave_num + 1,
+ slave->data->max_speed);
+#endif
}
phydev->advertising = phydev->supported;
generated by cgit v1.1 at 2024-08-14 10:21:41 +0000