diff options
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.h | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 894e376..06318c8 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -34,8 +34,13 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN4_MAIN, CLK_TYPE_GEN4_PLL1, - CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */ + CLK_TYPE_GEN4_PLL2, + CLK_TYPE_GEN4_PLL2X_3X, /* R8A779A0 only */ + CLK_TYPE_GEN4_PLL3, CLK_TYPE_GEN4_PLL5, + CLK_TYPE_GEN4_PLL4, + CLK_TYPE_GEN4_PLL6, + CLK_TYPE_GEN4_SDSRC, CLK_TYPE_GEN4_SDH, CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ @@ -107,11 +112,27 @@ struct rcar_gen3_cpg_pll_config { u8 pll3_mult; u8 pll3_div; u8 osc_prediv; +}; + +struct rcar_gen4_cpg_pll_config { + u8 extal_div; + u8 pll1_mult; + u8 pll1_div; + u8 pll2_mult; + u8 pll2_div; + u8 pll3_mult; + u8 pll3_div; + u8 pll4_mult; + u8 pll4_div; u8 pll5_mult; u8 pll5_div; + u8 pll6_mult; + u8 pll6_div; + u8 osc_prediv; }; #define CPG_RST_MODEMR 0x060 +#define CPG_RST_MODEMR0 0x000 #define CPG_SDCKCR_STPnHCK BIT(9) #define CPG_SDCKCR_STPnCK BIT(8) @@ -133,7 +154,10 @@ struct gen3_clk_priv { struct clk clk_extal; struct clk clk_extalr; u32 cpg_mode; - const struct rcar_gen3_cpg_pll_config *cpg_pll_config; + union { + const struct rcar_gen3_cpg_pll_config *gen3_cpg_pll_config; + const struct rcar_gen4_cpg_pll_config *gen4_cpg_pll_config; + }; }; int gen3_cpg_bind(struct udevice *parent); |