diff options
Diffstat (limited to 'doc')
-rw-r--r-- | doc/device-tree-bindings/clock/snps,hsdk-cgu.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/clock/snps,hsdk-cgu.txt b/doc/device-tree-bindings/clock/snps,hsdk-cgu.txt new file mode 100644 index 0000000..82fe1dd --- /dev/null +++ b/doc/device-tree-bindings/clock/snps,hsdk-cgu.txt @@ -0,0 +1,35 @@ +* Synopsys HSDK clock generation unit + +The Synopsys HSDK clock controller generates and supplies clock to various +controllers and peripherals within the SoC. + +Required Properties: + +- compatible: should be "snps,hsdk-cgu-clock" +- reg: the pair of physical base address and length of clock generation unit + memory mapped region and creg arc core divider memory mapped region. +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be +used in device tree sources. + +Example: Clock controller node: + + cgu_clk: cgu-clk@f0000000 { + compatible = "snps,hsdk-cgu-clock"; + reg = <0xf0000000 0x1000>, <0xf00014B8 0x4>; + #clock-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock +controller: + + uart0: serial0@f0005000 { + compatible = "snps,dw-apb-uart"; + reg = <0xf0005000 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cgu_clk CLK_SYS_UART_REF>; + }; |