diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/coreboot/Kconfig | 26 | ||||
| -rw-r--r-- | board/google/Kconfig | 43 | ||||
| -rw-r--r-- | board/intel/Kconfig | 51 |
3 files changed, 120 insertions, 0 deletions
diff --git a/board/coreboot/Kconfig b/board/coreboot/Kconfig new file mode 100644 index 0000000..dc9b70f --- /dev/null +++ b/board/coreboot/Kconfig @@ -0,0 +1,26 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_COREBOOT + +choice + prompt "Mainboard model" + +config TARGET_COREBOOT + bool "coreboot" + help + This target is used for running U-Boot on top of coreboot. In + this case coreboot does the early inititalisation, and U-Boot + takes over once the RAM, video and CPU are fully running. + U-Boot is loaded as a fallback payload from coreboot, in + coreboot terminology. This method was used for the Chromebook + Pixel when launched. + +endchoice + +source "board/coreboot/coreboot/Kconfig" + +endif diff --git a/board/google/Kconfig b/board/google/Kconfig new file mode 100644 index 0000000..302f68e --- /dev/null +++ b/board/google/Kconfig @@ -0,0 +1,43 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_GOOGLE + +choice + prompt "Mainboard model" + +config TARGET_CHROMEBOOK_LINK + bool "Chromebook link" + help + This is the Chromebook Pixel released in 2013. It uses an Intel + i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of + SDRAM. It has a Panther Point platform controller hub, PCIe + WiFi and Bluetooth. It also includes a 720p webcam, USB SD + reader, microphone and speakers, display port and 32GB SATA + solid state drive. There is a Chrome OS EC connected on LPC, + and it provides a 2560x1700 high resolution touch-enabled LCD + display. + +config TARGET_CHROMEBOX_PANTHER + bool "Chromebox panther (not available)" + select n + help + Note: At present this must be used with coreboot. See README.x86 + for instructions. + + This is the Asus Chromebox CN60 released in 2014. It uses an Intel + Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a + Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also + includes a USB SD reader, four USB3 ports, display port and HDMI + video output and a 16GB SATA solid state drive. There is no Chrome + OS EC on this model. + +endchoice + +source "board/google/chromebook_link/Kconfig" +source "board/google/chromebox_panther/Kconfig" + +endif diff --git a/board/intel/Kconfig b/board/intel/Kconfig new file mode 100644 index 0000000..7fe21b9 --- /dev/null +++ b/board/intel/Kconfig @@ -0,0 +1,51 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_INTEL + +choice + prompt "Mainboard model" + +config TARGET_CROWNBAY + bool "Crown Bay" + help + This is the Intel Crown Bay Customer Reference Board. It contains + the Intel Atom Processor E6xx populated on the COM Express module + with 1GB DDR2 soldered down memory and a carrier board with the + Intel Platform Controller Hub EG20T, other system components and + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. + +config TARGET_GALILEO + bool "Galileo" + help + This is the Intel Galileo board, which is the first in a family of + Arduino-certified development and prototyping boards based on Intel + architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit + single-core, single-thread, Intel Pentium processor instrunction set + architecture (ISA) compatible, operating at speeds up to 400Mhz, + along with 256MB DDR3 memory. It supports a wide range of industry + standard I/O interfaces, including a full-sized mini-PCIe slot, + one 100Mb Ethernet port, a microSD card slot, a USB host port and + a USB client port. + +config TARGET_MINNOWMAX + bool "Minnowboard MAX" + help + This is the Intel Minnowboard MAX. It contains an Atom E3800 + processor in a small form factor with Ethernet, micro-SD, USB 2, + USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +endchoice + +source "board/intel/crownbay/Kconfig" +source "board/intel/galileo/Kconfig" +source "board/intel/minnowmax/Kconfig" + +endif |