diff options
Diffstat (limited to 'board')
24 files changed, 1047 insertions, 380 deletions
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index 04e9eab..2939389 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -161,18 +161,18 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = { }; static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = { - .p0_mpwldectrl0 = 0x0011000E, - .p0_mpwldectrl1 = 0x000E001B, - .p1_mpwldectrl0 = 0x00190015, - .p1_mpwldectrl1 = 0x00070018, - .p0_mpdgctrl0 = 0x42720306, - .p0_mpdgctrl1 = 0x026F0266, - .p1_mpdgctrl0 = 0x4273030A, - .p1_mpdgctrl1 = 0x02740240, - .p0_mprddlctl = 0x45393B3E, - .p1_mprddlctl = 0x403A3747, - .p0_mpwrdlctl = 0x40434541, - .p1_mpwrdlctl = 0x473E4A3B, + .p0_mpwldectrl0 = 0x001a001a, + .p0_mpwldectrl1 = 0x00260015, + .p0_mpdgctrl0 = 0x030c0320, + .p0_mpdgctrl1 = 0x03100304, + .p0_mprddlctl = 0x432e3538, + .p0_mpwrdlctl = 0x363f423d, + .p1_mpwldectrl0 = 0x0006001e, + .p1_mpwldectrl1 = 0x00050015, + .p1_mpdgctrl0 = 0x031c0324, + .p1_mpdgctrl1 = 0x030c0258, + .p1_mprddlctl = 0x3834313f, + .p1_mpwrdlctl = 0x47374a42, }; static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = { @@ -482,6 +482,29 @@ static void setup_iomux_usb(void) SETUP_IOMUX_PADS(usb_pads); } +/* Perform DDR DRAM calibration */ +static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) +{ + int ret = 0; + +#ifdef CONFIG_MX6_DDRCAL + udelay(100); + ret = mmdc_do_write_level_calibration(sysinfo); + if (ret) { + printf("DDR3: Write level calibration error [%d]\n", ret); + return ret; + } + + ret = mmdc_do_dqs_calibration(sysinfo); + if (ret) { + printf("DDR3: DQS calibration error [%d]\n", ret); + return ret; + } +#endif /* CONFIG_MX6_DDRCAL */ + + return ret; +} + /* DRAM */ static void dhcom_spl_dram_init(void) @@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit); } else if (is_cpu_type(MXC_CPU_MX6DL)) { mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs, @@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + spl_dram_perform_cal(&dhcom_ddr_64bit); } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs, @@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void) } /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_32bit); + spl_dram_perform_cal(&dhcom_ddr_32bit); } } diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig new file mode 100644 index 0000000..93d7d5f --- /dev/null +++ b/board/freescale/imx8qm_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8QM_MEK + +config SYS_BOARD + default "imx8qm_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qm_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8qm_mek/MAINTAINERS b/board/freescale/imx8qm_mek/MAINTAINERS new file mode 100644 index 0000000..115830d --- /dev/null +++ b/board/freescale/imx8qm_mek/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8QM MEK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/imx8qm_mek/ +F: include/configs/imx8qm_mek.h +F: configs/imx8qm_mek_defconfig diff --git a/board/freescale/imx8qm_mek/Makefile b/board/freescale/imx8qm_mek/Makefile new file mode 100644 index 0000000..bc9a126 --- /dev/null +++ b/board/freescale/imx8qm_mek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_mek.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README new file mode 100644 index 0000000..c352380 --- /dev/null +++ b/board/freescale/imx8qm_mek/README @@ -0,0 +1,57 @@ +U-Boot for the NXP i.MX8QM EVK board + +Quick Start +=========== + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +====================================== + +$ git clone https://source.codeaurora.org/external/imx/imx-atf +$ cd imx-atf/ +$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga +$ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +============================== + +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin +$ chmod +x imx-sc-firmware-1.1.bin +$ ./imx-sc-firmware-1.1.bin +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin +$ chmod +x firmware-imx-8.0.bin +$ ./firmware-imx-8.0.bin + +Copy the following binaries to U-Boot folder: + +$ cp imx-atf/build/imx8qm/release/bl31.bin . +$ cp u-boot/u-boot.bin . + +Copy the following firmwares U-Boot folder : + +$ cp firmware-imx-7.6/firmware/seco/ahab-container.img . +$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin . + +Build U-Boot +============ +$ export ATF_LOAD_ADDR=0x80000000 +$ export BL33_LOAD_ADDR=0x80020000 +$ make imx8qm_mek_defconfig +$ make flash.bin +$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984 + +Flash the binary into the SD card +================================= + +Burn the flash.bin binary to SD card offset 32KB: + +$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 + +Boot +==== +Set Boot switch SW2: 1100. diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c new file mode 100644 index 0000000..e69efc4 --- /dev/null +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + int ret; + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + + /* Power up UART0 */ + ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (ret) + return ret; + + ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); + if (ret) + return ret; + + /* Enable UART0 clock root */ + ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + if (ret) + return ret; + + setup_iomux_uart(); + + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +void build_info(void) +{ + u32 sc_build = 0, sc_commit = 0; + + /* Get SCFW build and commit id */ + sc_misc_build_info(-1, &sc_build, &sc_commit); + if (!sc_build) { + printf("SCFW does not support build info\n"); + sc_commit = 0; /* Display 0 when the build info is not supported*/ + } + printf("Build: SCFW %x\n", sc_commit); +} + +int checkboard(void) +{ + puts("Board: iMX8QM MEK\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + /* Power up base board */ + sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); + + board_gpio_init(); + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8QM"); +#endif + + return 0; +} diff --git a/board/freescale/imx8qm_mek/imximage.cfg b/board/freescale/imx8qm_mek/imximage.cfg new file mode 100644 index 0000000..7dc6b93 --- /dev/null +++ b/board/freescale/imx8qm_mek/imximage.cfg @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c new file mode 100644 index 0000000..95ce9f3 --- /dev/null +++ b/board/freescale/imx8qm_mek/spl.c @@ -0,0 +1,75 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <dm/lists.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int offset; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); + while (offset != -FDT_ERR_NOTFOUND) { + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), + NULL, true); + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + "nxp,imx8-pd"); + } + + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index 95ce9f3..cb4006e 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -18,7 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; void spl_board_init(void) { struct udevice *dev; - int offset; uclass_find_first_device(UCLASS_MISC, &dev); @@ -27,21 +26,6 @@ void spl_board_init(void) continue; } - offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); - while (offset != -FDT_ERR_NOTFOUND) { - lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), - NULL, true); - offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, - "nxp,imx8-pd"); - } - - uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); - - for (; dev; uclass_find_next_device(&dev)) { - if (device_probe(dev)) - continue; - } - arch_cpu_init(); board_early_init_f(); diff --git a/board/k+p/bootscripts/tpcboot.cmd b/board/k+p/bootscripts/tpcboot.cmd index 0576e81..b81494d 100644 --- a/board/k+p/bootscripts/tpcboot.cmd +++ b/board/k+p/bootscripts/tpcboot.cmd @@ -27,6 +27,12 @@ setenv miscadj " if test '${boardsoc}' = 'imx53'; then setenv bootargs '${bootargs} di=${dig_in} key1=${key1}'; fi;" +setenv nfsadj " +if test '${boardsoc}' = 'imx53'; then + if test '${boardtype}' = 'hsc'; then + setenv bootargs '${bootargs} dsa_core.blacklist=yes'; + fi; +fi;" setenv boot_fitImage " setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb'; setenv itbcfg "\"#\${fdt_conf}\""; @@ -72,6 +78,7 @@ setenv boot_nfs " if run download_kernel; then run nfsargs; run addip; + run nfsadj; setenv bootargs '${bootargs}' console=${console}; run boot_fitImage; diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index becb6a6..b447e13 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -13,14 +13,10 @@ #include <asm/arch/iomux-mx53.h> #include <asm/arch/clock.h> #include <asm/gpio.h> -#include <mmc.h> -#include <fsl_esdhc.h> #include <power/pmic.h> #include <fsl_pmic.h> #include "kp_id_rev.h" -#define VBUS_PWR_EN IMX_GPIO_NR(7, 8) -#define PHY_nRST IMX_GPIO_NR(7, 6) #define BOOSTER_OFF IMX_GPIO_NR(2, 23) #define LCD_BACKLIGHT IMX_GPIO_NR(1, 1) #define KEY1 IMX_GPIO_NR(2, 26) @@ -45,59 +41,6 @@ int dram_init_banksize(void) return 0; } -#ifdef CONFIG_USB_EHCI_MX5 -int board_ehci_hcd_init(int port) -{ - gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN"); - gpio_direction_output(VBUS_PWR_EN, 1); - return 0; -} -#endif - -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[] = { - {MMC_SDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; /* eMMC is always present */ -} - -#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_100K_UP) -#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_DSE_HIGH) - -int board_mmc_init(bd_t *bis) -{ - int ret; - - static const iomux_v3_cfg_t sd3_pads[] = { - NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - SD_CMD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), - NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), - }; - - esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads)); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - if (ret) - return ret; - - return 0; -} -#endif - static int power_init(void) { struct udevice *dev; @@ -168,17 +111,6 @@ int board_init(void) return 0; } -void eth_phy_reset(void) -{ - gpio_request(PHY_nRST, "PHY_nRST"); - gpio_direction_output(PHY_nRST, 1); - udelay(50); - gpio_set_value(PHY_nRST, 0); - udelay(400); - gpio_set_value(PHY_nRST, 1); - udelay(50); -} - void board_disable_display(void) { gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT"); @@ -210,8 +142,6 @@ int board_late_init(void) if (ret) printf("Error %d reading EEPROM content!\n", ret); - eth_phy_reset(); - show_eeprom(); read_board_id(); diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 767d13d..e63b19d 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -13,10 +13,8 @@ #include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> #include <common.h> -#include <fsl_esdhc.h> #include <i2c.h> #include <miiphy.h> -#include <mmc.h> #include <netdev.h> #include <usb.h> #include <power/pmic.h> @@ -28,9 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) -#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) - #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) @@ -126,20 +121,6 @@ static iomux_v3_cfg_t const uart5_pads[] = { MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { - MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - #ifdef CONFIG_FEC_MXC static iomux_v3_cfg_t const fec1_pads[] = { MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), @@ -165,7 +146,7 @@ static iomux_v3_cfg_t const fec1_pads[] = { static void setup_iomux_fec(void) { imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - + gpio_request(FEC1_RST_GPIO, "phy_rst"); gpio_direction_output(FEC1_RST_GPIO, 0); udelay(500); gpio_set_value(FEC1_RST_GPIO, 1); @@ -224,25 +205,6 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC3_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - /* Assume uSDHC3 emmc is always present */ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - imx_iomux_v3_setup_multiple_pads( - usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} - int board_early_init_f(void) { setup_iomux_uart(); @@ -291,6 +253,8 @@ static iomux_v3_cfg_t const lcd_pads[] = { void setup_lcd(void) { imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness"); + gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable"); /* Set Brightness to high */ gpio_direction_output(IMX_GPIO_NR(1, 11) , 1); /* Set LCD enable to high */ diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index 8c34438..92a4646 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -5,11 +5,15 @@ * Author: Richard Hu <richard.hu@technexion.com> */ +#include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/mx7-pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch-mx7/mx7-ddr.h> +#include <asm/mach-imx/iomux-v3.h> #include <asm/gpio.h> +#include <fsl_esdhc.h> #include <spl.h> #if defined(CONFIG_SPL_BUILD) @@ -119,4 +123,38 @@ void board_init_f(ulong dummy) void reset_cpu(ulong addr) { } + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* Assume uSDHC3 emmc is always present */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} #endif diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c index fcb49a0..21addaf 100644 --- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Toradex AG + * Copyright (C) 2018-2019 Toradex AG */ #include <common.h> + #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> @@ -14,47 +15,30 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/io.h> -#include <common.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> #include <fdt_support.h> -#include <fsl_esdhc.h> #include <imx_thermal.h> #include <jffs2/load_kernel.h> #include <linux/sizes.h> -#include <mmc.h> #include <miiphy.h> #include <mtd_node.h> #include <netdev.h> -#include <usb.h> -#include <usb/ehci-ci.h> + #include "../common/tdx-common.h" +#include "../common/tdx-cfg-block.h" DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) -#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ PAD_CTL_DSE_48ohm) +#define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040 + #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) -#define USB_CDET_GPIO IMX_GPIO_NR(7, 14) - int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -62,56 +46,13 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -#ifdef CONFIG_FSL_ESDHC -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - - MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - -static iomux_v3_cfg_t const usb_cdet_pads[] = { - MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - #ifdef CONFIG_NAND_MXS -static iomux_v3_cfg_t const gpmi_pads[] = { - MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), -}; - static void setup_gpmi_nand(void) { - imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); - setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); } -#endif +#endif /* CONFIG_NAND_MXS */ #ifdef CONFIG_VIDEO_MXS static iomux_v3_cfg_t const lcd_pads[] = { @@ -168,100 +109,24 @@ static int setup_lcd(void) #endif #ifdef CONFIG_FEC_MXC -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, - MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); -} -#endif - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -#ifdef CONFIG_FSL_ESDHC - -#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) - -static struct fsl_esdhc_cfg usdhc_cfg[] = { - {USDHC1_BASE_ADDR, 0, 4}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int i, ret; - - /* USDHC1 is mmc0 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; - default: - printf("Warning: you configured more USDHC controllers" - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} -#endif - -#ifdef CONFIG_FEC_MXC - static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; - setup_iomux_fec(); - /* provide the PHY clock from the i.MX 6 */ ret = enable_fec_anatop_clock(1, ENET_50MHZ); if (ret) return ret; - /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */ + /* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + /* give new Ethernet PHY power save mode circuitry time to settle */ + mdelay(300); + return 0; } @@ -271,14 +136,7 @@ int board_phy_config(struct phy_device *phydev) phydev->drv->config(phydev); return 0; } -#endif - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} +#endif /* CONFIG_FEC_MXC */ int board_init(void) { @@ -297,11 +155,6 @@ int board_init(void) setup_lcd(); #endif -#ifdef CONFIG_USB_EHCI_MX6 - imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); - gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); -#endif - return 0; } @@ -317,10 +170,23 @@ static const struct boot_mode board_boot_modes[] = { int board_late_init(void) { - int minc, maxc; - - if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL) +#ifdef CONFIG_TDX_CFG_BLOCK + /* + * If we have a valid config block and it says we are a module with + * Wi-Fi/Bluetooth make sure we use the -wifi device tree. + */ + if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT || + tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT) env_set("variant", "-wifi"); +#endif + + /* + * Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the + * SOC to request for a lower voltage during sleep. This is necessary + * because the voltage is changing too slow for the SOC to wake up + * properly. + */ + __raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR); #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); @@ -362,41 +228,6 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_USB_EHCI_MX6 -static iomux_v3_cfg_t const usb_otg2_pads[] = { - MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -int board_ehci_hcd_init(int port) -{ - switch (port) { - case 0: - break; - case 1: - imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, - ARRAY_SIZE(usb_otg2_pads)); - break; - default: - return -EINVAL; - } - return 0; -} - -int board_usb_phy_mode(int port) -{ - switch (port) { - case 0: - if (gpio_get_value(USB_CDET_GPIO)) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; - case 1: - default: - return USB_INIT_HOST; - } -} -#endif - static struct mxc_serial_platdata mxc_serial_plat = { .reg = (struct mxc_uart *)UART1_BASE, .use_dte = 1, diff --git a/board/toradex/colibri_vf/MAINTAINERS b/board/toradex/colibri_vf/MAINTAINERS index 3ee2b33..66b2150 100644 --- a/board/toradex/colibri_vf/MAINTAINERS +++ b/board/toradex/colibri_vf/MAINTAINERS @@ -1,7 +1,7 @@ Colibri VFxx M: Stefan Agner <stefan.agner@toradex.com> W: http://developer.toradex.com/software/linux/linux-software -W: https://www.toradex.com/community +W: https://www.toradex.com/community S: Maintained F: board/toradex/colibri_vf/ F: include/configs/colibri_vf.h diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index b90077b..f69c443 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -1,12 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (c) 2016 Toradex, Inc. + * Copyright (c) 2016-2019 Toradex, Inc. */ #include <common.h> #include "tdx-cfg-block.h" -#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6) +#if defined(CONFIG_TARGET_APALIS_IMX6) || \ + defined(CONFIG_TARGET_COLIBRI_IMX6) || \ + defined(CONFIG_TARGET_COLIBRI_IMX8QXP) #include <asm/arch/sys_proto.h> #else #define is_cpu_type(cpu) (0) @@ -92,12 +94,22 @@ const char * const toradex_modules[] = { [34] = "Apalis TK1 2GB", [35] = "Apalis iMX6 Dual 1GB IT", [36] = "Colibri iMX6ULL 256MB", - [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth", - [38] = "Colibri iMX8X", + [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT", + [38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT", [39] = "Colibri iMX7 Dual 1GB (eMMC)", - [40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT", + [40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT", [41] = "Colibri iMX7 Dual 512MB EPDC", [42] = "Apalis TK1 4GB", + [43] = "Colibri T20 512MB IT SETEK", + [44] = "Colibri iMX6ULL 512MB IT", + [45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth", + [46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT", + [47] = "Apalis iMX8 QuadMax 4GB IT", + [48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT", + [49] = "Apalis iMX8 QuadPlus 2GB", + [50] = "Colibri iMX8 QuadXPlus 2GB IT", + [51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth", + [52] = "Colibri iMX8 DualX 1GB", }; #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC @@ -277,6 +289,9 @@ static int get_cfgblock_interactive(void) char it = 'n'; int len; + /* Unknown module by default */ + tdx_hw_tag.prodid = 0; + if (cpu_is_pxa27x()) sprintf(message, "Is the module the 312 MHz version? [y/N] "); else @@ -287,34 +302,56 @@ static int get_cfgblock_interactive(void) soc = env_get("soc"); if (!strcmp("mx6", soc)) { -#ifdef CONFIG_MACH_TYPE - if (it == 'y' || it == 'Y') +#ifdef CONFIG_TARGET_APALIS_IMX6 + if (it == 'y' || it == 'Y') { if (is_cpu_type(MXC_CPU_MX6Q)) tdx_hw_tag.prodid = APALIS_IMX6Q_IT; else tdx_hw_tag.prodid = APALIS_IMX6D_IT; - else + } else { if (is_cpu_type(MXC_CPU_MX6Q)) tdx_hw_tag.prodid = APALIS_IMX6Q; else tdx_hw_tag.prodid = APALIS_IMX6D; -#else - if (it == 'y' || it == 'Y') + } +#elif CONFIG_TARGET_COLIBRI_IMX6 + if (it == 'y' || it == 'Y') { if (is_cpu_type(MXC_CPU_MX6DL)) tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT; - else + else if (is_cpu_type(MXC_CPU_MX6SOLO)) tdx_hw_tag.prodid = COLIBRI_IMX6S_IT; - else + } else { if (is_cpu_type(MXC_CPU_MX6DL)) tdx_hw_tag.prodid = COLIBRI_IMX6DL; - else + else if (is_cpu_type(MXC_CPU_MX6SOLO)) tdx_hw_tag.prodid = COLIBRI_IMX6S; -#endif /* CONFIG_MACH_TYPE */ - } else if (!strcmp("imx7d", soc)) { + } +#elif CONFIG_TARGET_COLIBRI_IMX6ULL + char wb = 'n'; + + sprintf(message, "Does the module have Wi-Fi / Bluetooth? " \ + "[y/N] "); + len = cli_readline(message); + wb = console_buffer[0]; + if (it == 'y' || it == 'Y') { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT; + else + tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT; + } else { + if (wb == 'y' || wb == 'Y') + tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT; + else + tdx_hw_tag.prodid = COLIBRI_IMX6ULL; + } +#endif + } else if (!strcmp("imx7d", soc)) tdx_hw_tag.prodid = COLIBRI_IMX7D; - } else if (!strcmp("imx7s", soc)) { + else if (!strcmp("imx7s", soc)) tdx_hw_tag.prodid = COLIBRI_IMX7S; - } else if (!strcmp("tegra20", soc)) { + else if (is_cpu_type(MXC_CPU_IMX8QXP)) + tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT; + else if (!strcmp("tegra20", soc)) { if (it == 'y' || it == 'Y') if (gd->ram_size == 0x10000000) tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT; @@ -330,8 +367,9 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ; else tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ; + } #ifdef CONFIG_MACH_TYPE - } else if (!strcmp("tegra30", soc)) { + else if (!strcmp("tegra30", soc)) { if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) { if (it == 'y' || it == 'Y') tdx_hw_tag.prodid = APALIS_T30_IT; @@ -346,8 +384,9 @@ static int get_cfgblock_interactive(void) else tdx_hw_tag.prodid = COLIBRI_T30; } + } #endif /* CONFIG_MACH_TYPE */ - } else if (!strcmp("tegra124", soc)) { + else if (!strcmp("tegra124", soc)) { tdx_hw_tag.prodid = APALIS_TK1_2GB; } else if (!strcmp("vf500", soc)) { if (it == 'y' || it == 'Y') @@ -359,7 +398,9 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_VF61_IT; else tdx_hw_tag.prodid = COLIBRI_VF61; - } else { + } + + if (!tdx_hw_tag.prodid) { printf("Module type not detectable due to unknown SoC\n"); return -1; } @@ -373,7 +414,7 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.ver_minor = console_buffer[2] - '0'; tdx_hw_tag.ver_assembly = console_buffer[3] - 'A'; - if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1)) + if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1) tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ - COLIBRI_PXA270_V1_312MHZ); @@ -441,7 +482,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, * On NAND devices, recreation is only allowed if the page is * empty (config block invalid...) */ - printf("NAND erase block %d need to be erased before creating a Toradex config block\n", + printf("NAND erase block %d need to be erased before creating" \ + " a Toradex config block\n", CONFIG_TDX_CFG_BLOCK_OFFSET / get_nand_dev_by_index(0)->erasesize); goto out; @@ -450,7 +492,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc, * On NOR devices, recreation is only allowed if the sector is * empty and write protection is off (config block invalid...) */ - printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n", + printf("NOR sector at offset 0x%02x need to be erased and " \ + "unprotected before creating a Toradex config block\n", CONFIG_TDX_CFG_BLOCK_OFFSET); goto out; #else diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index da60e78..bfdc8b7 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -25,42 +25,54 @@ enum { COLIBRI_PXA270_V1_520MHZ, COLIBRI_PXA320, COLIBRI_PXA300, - COLIBRI_PXA310, + COLIBRI_PXA310, /* 5 */ COLIBRI_PXA320_IT, COLIBRI_PXA300_XT, COLIBRI_PXA270_312MHZ, COLIBRI_PXA270_520MHZ, - COLIBRI_VF50, /* not currently on sale */ - COLIBRI_VF61, + COLIBRI_VF50, /* 10 */ + COLIBRI_VF61, /* not currently on sale */ COLIBRI_VF61_IT, COLIBRI_VF50_IT, COLIBRI_IMX6S, - COLIBRI_IMX6DL, + COLIBRI_IMX6DL, /* 15 */ COLIBRI_IMX6S_IT, COLIBRI_IMX6DL_IT, + /* 18 */ + /* 19 */ COLIBRI_T20_256MB = 20, COLIBRI_T20_512MB, COLIBRI_T20_512MB_IT, COLIBRI_T30, COLIBRI_T20_256MB_IT, - APALIS_T30_2GB, + APALIS_T30_2GB, /* 25 */ APALIS_T30_1GB, APALIS_IMX6Q, APALIS_IMX6Q_IT, APALIS_IMX6D, - COLIBRI_T30_IT, + COLIBRI_T30_IT, /* 30 */ APALIS_T30_IT, COLIBRI_IMX7S, COLIBRI_IMX7D, APALIS_TK1_2GB, - APALIS_IMX6D_IT, + APALIS_IMX6D_IT, /* 35 */ COLIBRI_IMX6ULL, - APALIS_IMX8QM, /* 37 */ - COLIBRI_IMX8X, + APALIS_IMX8QM_WIFI_BT_IT, + COLIBRI_IMX8QXP_WIFI_BT_IT, COLIBRI_IMX7D_EMMC, COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */ COLIBRI_IMX7D_EPDC, - APALIS_TK1_4GB, + APALIS_TK1_4GB, /* not currently on sale */ + COLIBRI_T20_512MB_IT_SETEK, + COLIBRI_IMX6ULL_IT, + COLIBRI_IMX6ULL_WIFI_BT, /* 45 */ + APALIS_IMX8QXP_WIFI_BT_IT, + APALIS_IMX8QM_IT, + APALIS_IMX8QP_WIFI_BT, + APALIS_IMX8QP, + COLIBRI_IMX8QXP_IT, /* 50 */ + COLIBRI_IMX8DX_WIFI_BT, + COLIBRI_IMX8DX, }; extern const char * const toradex_modules[]; diff --git a/board/variscite/dart_6ul/Kconfig b/board/variscite/dart_6ul/Kconfig new file mode 100644 index 0000000..1765af1 --- /dev/null +++ b/board/variscite/dart_6ul/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DART_6UL + +config SYS_BOARD + default "dart_6ul" + +config SYS_VENDOR + default "variscite" + +config SYS_CONFIG_NAME + default "dart_6ul" + +endif diff --git a/board/variscite/dart_6ul/MAINTAINERS b/board/variscite/dart_6ul/MAINTAINERS new file mode 100644 index 0000000..339f93f --- /dev/null +++ b/board/variscite/dart_6ul/MAINTAINERS @@ -0,0 +1,8 @@ +MX6UL_DART BOARD +M: Parthiban Nallathambi <parthitce@gmail.com> +S: Maintained +F: arch/arm/dts/imx6ull-dart-6ul.dts +F: arch/arm/dts/imx6ull-dart-6ul.dtsi +F: board/variscite/dart_6ul/ +F: configs/variscite_dart6ul_defconfig +F: include/configs/dart_6ul.h diff --git a/board/variscite/dart_6ul/Makefile b/board/variscite/dart_6ul/Makefile new file mode 100644 index 0000000..48aa361 --- /dev/null +++ b/board/variscite/dart_6ul/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := dart_6ul.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/variscite/dart_6ul/README b/board/variscite/dart_6ul/README new file mode 100644 index 0000000..d76b997 --- /dev/null +++ b/board/variscite/dart_6ul/README @@ -0,0 +1,41 @@ +How to use U-Boot on variscite DART-6UL Evaluation Kit +------------------------------------------------------ + +- Configure and build U-Boot for DART-6UL iMX6ULL: + + $ make mrproper + $ make variscite_dart6ul_defconfig + $ make + + This will generate SPL and u-boot-dtb.img images. + +Boot from MMC/SD: +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 0 + +Boot from eMMC: +- if bootpart is not enabled by default, to enable under Linux + echo 0 >/sys/block/mmcblk1boot0/force_ro + mmc bootpart enable 1 1 /dev/mmcblk1boot0 + +- Flash the SPL and u-boot-dtb.img to mmcblk1boot0 + $ sudo dd if=SPL of=/dev/mmcblk1boot0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk1boot0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Insert the micro SD card in the board and power it up. + +- U-Boot messages should come up. diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c new file mode 100644 index 0000000..4765595 --- /dev/null +++ b/board/variscite/dart_6ul/dart_6ul.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2019 Variscite Ltd. + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com> + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc.h> +#include <linux/bitops.h> +#include <miiphy.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_NAND_MXS +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + clrbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* + * config gpmi and bch clock to 100 MHz + * bch/gpmi select PLL2 PFD2 400M + * 100M = 400M / 4 + */ + clrbits_le32(&mxc_ccm->cscmr1, + MXC_CCM_CSCMR1_BCH_CLK_SEL | + MXC_CCM_CSCMR1_GPMI_CLK_SEL); + clrsetbits_le32(&mxc_ccm->cscdr1, + MXC_CCM_CSCDR1_BCH_PODF_MASK | + MXC_CCM_CSCDR1_GPMI_PODF_MASK, + (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST) +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_ODE) +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) + imx_iomux_v3_setup_multiple_pads(fec1_pads, + ARRAY_SIZE(fec1_pads)); + else + imx_iomux_v3_setup_multiple_pads(fec2_pads, + ARRAY_SIZE(fec2_pads)); +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + +#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER) + /* USB Ethernet Gadget */ + usb_eth_initialize(bis); +#endif + return ret; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + /* + * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select + * 50 MHz RMII clock mode. + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif /* CONFIG_FEC_MXC */ + +int board_early_init_f(void) +{ + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; +} + +int checkboard(void) +{ + puts("Board: Variscite DART-6UL Evaluation Kit\n"); + + return 0; +} diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c new file mode 100644 index 0000000..f7e6ab6 --- /dev/null +++ b/board/variscite/dart_6ul/spl.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2019 Variscite Ltd. + * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com> + */ + +#include <common.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <fsl_esdhc.h> + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x414C0158, + .p0_mprddlctl = 0x40403A3A, + .p0_mpwrdlctl = 0x40405A56, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); + /* Enable Audio Clock for SOM codec */ + writel(0x01130100, (long *)CCM_CCOSR); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* setup GP timer */ + timer_init(); + + setup_iomux_uart(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 2882dc9..134a6c9 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -14,7 +14,6 @@ #include <asm/io.h> #include <common.h> #include <asm/arch/crm_regs.h> -#include <usb.h> #include <netdev.h> #include <power/pmic.h> #include <power/pfuze3000_pmic.h> @@ -128,11 +127,6 @@ int checkboard(void) return 0; } -int board_usb_phy_mode(int port) -{ - return USB_INIT_DEVICE; -} - int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |