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-rw-r--r--board/CZ.NIC/turris_omnia/turris_omnia.c90
-rw-r--r--board/Marvell/sheevaplug/sheevaplug.c54
-rw-r--r--board/zyxel/nsa310s/nsa310s.c47
3 files changed, 171 insertions, 20 deletions
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 8b2f94f..a7e5f56e 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -13,6 +13,7 @@
#include <init.h>
#include <log.h>
#include <miiphy.h>
+#include <mtd.h>
#include <net.h>
#include <netdev.h>
#include <asm/global_data.h>
@@ -31,6 +32,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define OMNIA_SPI_NOR_PATH "/soc/spi@10600/spi-nor@0"
+
#define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
#define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
@@ -557,3 +560,90 @@ out:
return 0;
}
+#if defined(CONFIG_OF_BOARD_SETUP)
+/*
+ * I plan to generalize this function and move it to common/fdt_support.c.
+ * This will require some more work on multiple boards, though, so for now leave
+ * it here.
+ */
+static bool fixup_mtd_partitions(void *blob, int offset, struct mtd_info *mtd)
+{
+ struct mtd_info *slave;
+ int parts;
+
+ parts = fdt_subnode_offset(blob, offset, "partitions");
+ if (parts < 0)
+ return false;
+
+ if (fdt_del_node(blob, parts) < 0)
+ return false;
+
+ parts = fdt_add_subnode(blob, offset, "partitions");
+ if (parts < 0)
+ return false;
+
+ if (fdt_setprop_u32(blob, parts, "#address-cells", 1) < 0)
+ return false;
+
+ if (fdt_setprop_u32(blob, parts, "#size-cells", 1) < 0)
+ return false;
+
+ if (fdt_setprop_string(blob, parts, "compatible",
+ "fixed-partitions") < 0)
+ return false;
+
+ mtd_probe_devices();
+
+ list_for_each_entry(slave, &mtd->partitions, node) {
+ char name[32];
+ int part;
+
+ snprintf(name, sizeof(name), "partition@%llx", slave->offset);
+ part = fdt_add_subnode(blob, parts, name);
+ if (part < 0)
+ return false;
+
+ if (fdt_setprop_u32(blob, part, "reg", slave->offset) < 0)
+ return false;
+
+ if (fdt_appendprop_u32(blob, part, "reg", slave->size) < 0)
+ return false;
+
+ if (fdt_setprop_string(blob, part, "label", slave->name) < 0)
+ return false;
+
+ if (!(slave->flags & MTD_WRITEABLE))
+ if (fdt_setprop_empty(blob, part, "read-only") < 0)
+ return false;
+
+ if (slave->flags & MTD_POWERUP_LOCK)
+ if (fdt_setprop_empty(blob, part, "lock") < 0)
+ return false;
+ }
+
+ return true;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ struct mtd_info *mtd;
+ int node;
+
+ mtd = get_mtd_device_nm(OMNIA_SPI_NOR_PATH);
+ if (IS_ERR_OR_NULL(mtd))
+ goto fail;
+
+ node = fdt_path_offset(blob, OMNIA_SPI_NOR_PATH);
+ if (node < 0)
+ goto fail;
+
+ if (!fixup_mtd_partitions(blob, node, mtd))
+ goto fail;
+
+ return 0;
+
+fail:
+ printf("Failed fixing SPI NOR partitions!\n");
+ return 0;
+}
+#endif
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index 0cc7f2b..5952d15 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2021 Tony Dinh <mibodhi@gmail.com>
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
@@ -100,36 +101,65 @@ int board_init(void)
return 0;
}
+static int fdt_get_phy_addr(const char *path)
+{
+ const void *fdt = gd->fdt_blob;
+ const u32 *reg;
+ const u32 *val;
+ int node, phandle, addr;
+
+ /* Find the node by its full path */
+ node = fdt_path_offset(fdt, path);
+ if (node >= 0) {
+ /* Look up phy-handle */
+ val = fdt_getprop(fdt, node, "phy-handle", NULL);
+ if (val) {
+ phandle = fdt32_to_cpu(*val);
+ if (!phandle)
+ return -1;
+ /* Follow it to its node */
+ node = fdt_node_offset_by_phandle(fdt, phandle);
+ if (node) {
+ /* Look up reg */
+ reg = fdt_getprop(fdt, node, "reg", NULL);
+ if (reg) {
+ addr = fdt32_to_cpu(*reg);
+ return addr;
+ }
+ }
+ }
+ }
+ return -1;
+}
+
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
u16 reg;
- u16 devadr;
- char *name = "egiga0";
+ int phyaddr;
+ char *name = "ethernet-controller@72000";
+ char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
if (miiphy_set_current_dev(name))
return;
- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
- printf("Err..%s could not read PHY dev address\n",
- __FUNCTION__);
+ phyaddr = fdt_get_phy_addr(eth0_path);
+ if (phyaddr < 0)
return;
- }
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
- miiphy_reset(name, devadr);
+ miiphy_reset(name, phyaddr);
printf("88E1116 Initialized on %s\n", name);
}
diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c
index cd4a772..b71de4e 100644
--- a/board/zyxel/nsa310s/nsa310s.c
+++ b/board/zyxel/nsa310s/nsa310s.c
@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2015
- * Gerald Kerma <dreagle@doukki.net>
- * Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2015, 2021 Tony Dinh <mibodhi@gmail.com>
+ * Copyright (C) 2015 Gerald Kerma <dreagle@doukki.net>
*/
#include <common.h>
@@ -81,21 +80,51 @@ int board_init(void)
return 0;
}
+static int fdt_get_phy_addr(const char *path)
+{
+ const void *fdt = gd->fdt_blob;
+ const u32 *reg;
+ const u32 *val;
+ int node, phandle, addr;
+
+ /* Find the node by its full path */
+ node = fdt_path_offset(fdt, path);
+ if (node >= 0) {
+ /* Look up phy-handle */
+ val = fdt_getprop(fdt, node, "phy-handle", NULL);
+ if (val) {
+ phandle = fdt32_to_cpu(*val);
+ if (!phandle)
+ return -1;
+ /* Follow it to its node */
+ node = fdt_node_offset_by_phandle(fdt, phandle);
+ if (node) {
+ /* Look up reg */
+ reg = fdt_getprop(fdt, node, "reg", NULL);
+ if (reg) {
+ addr = fdt32_to_cpu(*reg);
+ return addr;
+ }
+ }
+ }
+ }
+ return -1;
+}
+
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
u16 reg;
u16 phyaddr;
- char *name = "egiga0";
+ char *name = "ethernet-controller@72000";
+ char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
if (miiphy_set_current_dev(name))
return;
- /* read PHY dev address */
- if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
- printf("could not read PHY dev address\n");
+ phyaddr = fdt_get_phy_addr(eth0_path);
+ if (phyaddr < 0)
return;
- }
/* set RGMII delay */
miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
@@ -131,5 +160,7 @@ void reset_phy(void)
/* downshift */
miiphy_write(name, phyaddr, 0x10, 0x3860);
miiphy_write(name, phyaddr, 0x0, 0x9140);
+
+ printf("MV88E1318 PHY initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */
generated by cgit v1.1 at 2024-11-17 15:44:15 +0000