diff options
Diffstat (limited to 'board')
254 files changed, 0 insertions, 37497 deletions
diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig deleted file mode 100644 index 033deaf..0000000 --- a/board/amcc/acadia/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ACADIA - -config SYS_BOARD - default "acadia" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "acadia" - -endif diff --git a/board/amcc/acadia/MAINTAINERS b/board/amcc/acadia/MAINTAINERS deleted file mode 100644 index c16961f..0000000 --- a/board/amcc/acadia/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ACADIA BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/acadia/ -F: include/configs/acadia.h -F: configs/acadia_defconfig diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile deleted file mode 100644 index 035f407..0000000 --- a/board/amcc/acadia/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = acadia.o cmd_acadia.o memory.o pll.o diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c deleted file mode 100644 index 2eb18df..0000000 --- a/board/amcc/acadia/acadia.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> - -extern void board_pll_init_f(void); - -static void acadia_gpio_init(void) -{ - /* - * GPIO0 setup (select GPIO or alternate function) - */ - out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); - out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ - out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); - out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ - out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); - out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ - - /* - * Ultra (405EZ) was nice enough to add another GPIO controller - */ - out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */ - out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL); - out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */ - out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L); - out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */ - out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL); - out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */ -} - -int board_early_init_f(void) -{ - unsigned int reg; - - /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR0_PINSTP, reg); - if (reg != 0xf0000000) - board_pll_init_f(); - - acadia_gpio_init(); - - /* Configure 405EZ for NAND usage */ - mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); - mfsdr(SDR0_ULTRA0, reg); - reg &= ~SDR_ULTRA0_CSN_MASK; - reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | - SDR_ULTRA0_NDGPIOBP | - SDR_ULTRA0_EBCRDYEN | - SDR_ULTRA0_NFSRSTEN; - mtsdr(SDR0_ULTRA0, reg); - - /* USB Host core needs this bit set */ - mfsdr(SDR0_ULTRA1, reg); - mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE); - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000010); - mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */ - mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -int misc_init_f(void) -{ - /* Set EPLD to take PHY out of reset */ - out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00); - udelay(100000); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 rev; - - rev = in8(CONFIG_SYS_CPLD_BASE + 0); - printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c deleted file mode 100644 index e9df61b..0000000 --- a/board/amcc/acadia/cmd_acadia.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <i2c.h> - -static u8 boot_267_nor[] = { - 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, - 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static u8 boot_267_nand[] = { - 0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00, - 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u8 chip; - u8 *buf; - int cpu_freq; - - if (argc < 3) - return cmd_usage(cmdtp); - - cpu_freq = simple_strtol(argv[1], NULL, 10); - if (cpu_freq != 267) { - printf("Unsupported cpu-frequency - only 267 supported\n"); - return 1; - } - - /* use 0x50 as I2C EEPROM address for now */ - chip = 0x50; - - if ((strcmp(argv[2], "nor") != 0) && - (strcmp(argv[2], "nand") != 0)) { - printf("Unsupported boot-device - only nor|nand support\n"); - return 1; - } - - if (strcmp(argv[2], "nand") == 0) { - switch (cpu_freq) { - case 267: - buf = boot_267_nand; - break; - default: - break; - } - } else { - switch (cpu_freq) { - case 267: - buf = boot_267_nor; - break; - default: - break; - } - } - - if (i2c_write(chip, 0, 1, buf, 16) != 0) - printf("Error writing to EEPROM at address 0x%x\n", chip); - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); - if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0) - printf("Error2 writing to EEPROM at address 0x%x\n", chip); - - printf("Done\n"); - printf("Please power-cycle the board for the changes to take effect\n"); - - return 0; -} - -U_BOOT_CMD( - bootstrap, 3, 0, do_bootstrap, - "program the I2C bootstrap EEPROM", - "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM" -); diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk deleted file mode 100644 index 5350ec0..0000000 --- a/board/amcc/acadia/config.mk +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2007-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 405EZ Reference Platform (Acadia) board -# - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c deleted file mode 100644 index 36500da..0000000 --- a/board/amcc/acadia/memory.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void board_pll_init_f(void); - -static void cram_bcr_write(u32 wr_val) -{ - wr_val <<= 2; - - /* set CRAM_CRE to 1 */ - gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); - - /* Write BCR to CRAM on CS1 */ - out32(wr_val + 0x00200000, 0); - debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000); - - /* Write BCR to CRAM on CS2 */ - out32(wr_val + 0x02200000, 0); - debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000); - - sync(); - eieio(); - - /* set CRAM_CRE back to 0 (normal operation) */ - gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); - - return; -} - -int dram_init(void) -{ - int i; - u32 val; - - /* 1. EBC need to program READY, CLK, ADV for ASync mode */ - gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); - - /* 2. EBC in Async mode */ - mtebc(PB1AP, 0x078F1EC0); - mtebc(PB2AP, 0x078F1EC0); - mtebc(PB1CR, 0x000BC000); - mtebc(PB2CR, 0x020BC000); - - /* 3. Set CRAM in Sync mode */ - cram_bcr_write(0x7012); /* CRAM burst setting */ - - /* 4. EBC in Sync mode */ - mtebc(PB1AP, 0x9C0201C0); - mtebc(PB2AP, 0x9C0201C0); - - /* Set GPIO pins back to alternate function */ - gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - - /* Config EBC to use RDY */ - mfsdr(SDR0_ULTRA0, val); - mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN); - - /* Wait a short while, since for NAND booting this is too fast */ - for (i=0; i<200000; i++) - ; - - gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20; - - return 0; -} diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c deleted file mode 100644 index d868582..0000000 --- a/board/amcc/acadia/pll.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc405.h> - -/* test-only: move into cpu directory!!! */ - -#if defined(PLLMR0_200_133_66) -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 200.0 | 4 (0x02)| - * | PLB | 133.3 | 6 (0x06)| - * | OPB | 66.6 | 12 (0x0C)| - * | EBC | 66.6 | 12 (0x0C)| - * | SPI | 66.6 | 12 (0x0C)| - * | UART0 | 10.0 | 40 (0x28)| - * | UART1 | 10.0 | 40 (0x28)| - * | DAC | 2.0 | 200 (0xC8)| - * | ADC | 2.0 | 200 (0xC8)| - * | PWM | 100.0 | 4 (0x04)| - * | EMAC | 25.0 | 16 (0x10)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x0000033c); - mtcpr(CPR0_PLLD, 0x0c010200); - mtcpr(CPR0_PRIMAD, 0x04060c0c); - mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_CLKUPD, 0x40000000); -} - -#elif defined(PLLMR0_266_160_80) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 266.64 | 3 | - * | PLB | 159.98 | 5 (0x05)| - * | OPB | 79.99 | 10 (0x0A)| - * | EBC | 79.99 | 10 (0x0A)| - * | SPI | 79.99 | 10 (0x0A)| - * | UART0 | 28.57 | 7 (0x07)| - * | UART1 | 28.57 | 7 (0x07)| - * | DAC | 28.57 | 7 (0xA7)| - * | ADC | 4 | 50 (0x32)| - * | PWM | 28.57 | 7 (0x07)| - * | EMAC | 4 | 50 (0x32)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x20000238); - mtcpr(CPR0_PLLD, 0x03010400); - mtcpr(CPR0_PRIMAD, 0x03050a0a); - mtcpr(CPR0_PERC0, 0x00000000); - mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0x07323200); - mtcpr(CPR0_CLKUP, 0x40000000); -} - -#elif defined(PLLMR0_333_166_83) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------------------- - * | CLK | FREQ (MHz) | DIV RATIO | - * ---------------------------------- - * | CPU | 333.33 | 2 | - * | PLB | 166.66 | 4 (0x04)| - * | OPB | 83.33 | 8 (0x08)| - * | EBC | 83.33 | 8 (0x08)| - * | SPI | 83.33 | 8 (0x08)| - * | UART0 | 16.66 | 5 (0x05)| - * | UART1 | 16.66 | 5 (0x05)| - * | DAC | ???? | 166 (0xA6)| - * | ADC | ???? | 166 (0xA6)| - * | PWM | 41.66 | 3 (0x03)| - * | EMAC | ???? | 3 (0x03)| - * ----------------------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x0000033C); - mtcpr(CPR0_PLLD, 0x0a010000); - mtcpr(CPR0_PRIMAD, 0x02040808); - mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0xA6A60300); - mtcpr(CPR0_CLKUP, 0x40000000); -} - -#elif defined(PLLMR0_100_100_12) - -void board_pll_init_f(void) -{ - /* - * set PLL clocks based on input sysclk is 33M - * - * ---------------------- - * | CLK | FREQ (MHz) | - * ---------------------- - * | CPU | 100.00 | - * | PLB | 100.00 | - * | OPB | 12.00 | - * | EBC | 49.00 | - * ---------------------- - */ - - /* Initialize PLL */ - mtcpr(CPR0_PLLC, 0x000003BC); - mtcpr(CPR0_PLLD, 0x06060600); - mtcpr(CPR0_PRIMAD, 0x02020004); - mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_PERD1, 0xC8C81600); - mtcpr(CPR0_CLKUP, 0x40000000); -} -#endif /* CPU_<speed>_405EZ */ diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig deleted file mode 100644 index c0bd40a..0000000 --- a/board/amcc/bamboo/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_BAMBOO - -config SYS_BOARD - default "bamboo" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "bamboo" - -endif diff --git a/board/amcc/bamboo/MAINTAINERS b/board/amcc/bamboo/MAINTAINERS deleted file mode 100644 index 4c8929e..0000000 --- a/board/amcc/bamboo/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BAMBOO BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/bamboo/ -F: include/configs/bamboo.h -F: configs/bamboo_defconfig diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile deleted file mode 100644 index 4c0a125..0000000 --- a/board/amcc/bamboo/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = bamboo.o flash.o -extra-y += init.o diff --git a/board/amcc/bamboo/README b/board/amcc/bamboo/README deleted file mode 100644 index e139c6d..0000000 --- a/board/amcc/bamboo/README +++ /dev/null @@ -1,77 +0,0 @@ -The 2 important dipswitches are configured as shown below: - -SW1 (for 33MHz SysClk) ----------------------- -S1 S2 S3 S4 S5 S6 S7 S8 -OFF OFF OFF OFF OFF OFF OFF ON - -SW7 (for Op-Code Flash and Boot Option H) ------------------------------------------ -S1 S2 S3 S4 S5 S6 S7 S8 -OFF OFF OFF ON OFF OFF OFF OFF - -The EEPROM at location 0x52 is loaded with these 16 bytes: -C47042A6 05D7A190 40082350 0d050000 - -SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors -SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB -SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output -SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz -SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor -SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A -SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B -SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B -SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor -SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor -SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 -SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 -SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 -SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer -SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit -SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC -SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled -SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled -SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 -SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled -SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 -SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled -SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC -SDR0_SDSTP0[NE]: 0 : NDFC: disabled -SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit -SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection -SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) -SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled -SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready -SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter -SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC -SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC -SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC -SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC -SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count - -PPC440EP Clocking Configuration - -SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz -OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz - -The above information is reported by Eugene O'Brien -<Eugene.O'Brien@advantechamt.com>. Thanks a lot. - -2007-08-06, Stefan Roese <sr@denx.de> ---------------------------------------------------------------------- - -The configuration for the AMCC 440EP eval board "Bamboo" was changed -to only use 384 kbytes of FLASH for the U-Boot image. This way the -redundant environment can be saved in the remaining 2 sectors of the -same flash chip. - -Caution: With an upgrade from an earlier U-Boot version the current -environment will be erased since the environment is now saved in -different sectors. By using the following command the environment can -be saved after upgrading the U-Boot image and *before* resetting the -board: - -setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \ - 'cp.b FFF60000 FFF80000 20000' - -2006-07-27, Stefan Roese <sr@denx.de> diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c deleted file mode 100644 index 9f64207..0000000 --- a/board/amcc/bamboo/bamboo.c +++ /dev/null @@ -1,1896 +0,0 @@ -/* - * (C) Copyright 2005-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc4xx-gpio.h> -#include <spd_sdram.h> -#include <asm/ppc440.h> -#include "bamboo.h" - -DECLARE_GLOBAL_DATA_PTR; - -void ext_bus_cntlr_init(void); -void configure_ppc440ep_pins(void); -int is_nand_selected(void); - -/************************************************************************* - * - * Bamboo has one bank onboard sdram (plus DIMM) - * - * Fixed memory is composed of : - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, - * 13 row add bits, 10 column add bits (but 12 row used only). - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, - * 12 row add bits, 10 column add bits. - * Prepare a subset (only the used ones) of SPD data - * - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of - * the corresponding bank is divided by 2 due to number of Row addresses - * 12 in the ECC module - * - * Assumes: 64 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -const unsigned char cfg_simulate_spd_eeprom[128] = { - 0x80, /* number of SPD bytes used: 128 */ - 0x08, /* total number bytes in SPD device = 256 */ - 0x07, /* DDR ram */ -#ifdef CONFIG_DDR_ECC - 0x0C, /* num Row Addr: 12 */ -#else - 0x0D, /* num Row Addr: 13 */ -#endif - 0x09, /* numColAddr: 9 */ - 0x01, /* numBanks: 1 */ - 0x20, /* Module data width: 32 bits */ - 0x00, /* Module data width continued: +0 */ - 0x04, /* 2.5 Volt */ - 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ - 0x00, /* SDRAM Access from clock */ -#ifdef CONFIG_DDR_ECC - 0x02, /* ECC ON : 02 OFF : 00 */ -#else - 0x00, /* ECC ON : 02 OFF : 00 */ -#endif - 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */ - 0, - 0, - 0x01, /* wcsbc = 1 */ - 0, - 0, - 0x0C, /* casBit (2,2.5) */ - 0, - 0, - 0x00, /* not registered: 0 registered : 0x02*/ - 0, - 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */ - 0, - 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */ - 0, - 0x50, /* tRpNs = 20 ns */ - 0, - 0x50, /* tRcdNs = 20 ns */ - 45, /* tRasNs */ -#ifdef CONFIG_DDR_ECC - 0x08, /* bankSizeID: 32MB */ -#else - 0x10, /* bankSizeID: 64MB */ -#endif - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 -}; - -#if 0 -{ /* GPIO Alternate1 Alternate2 Alternate3 */ - { - /* GPIO Core 0 */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */ - { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */ - { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */ - }, - { - /* GPIO Core 1 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */ - { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */ - } -}; -#endif - -/*----------------------------------------------------------------------------+ - | EBC Devices Characteristics - | Peripheral Bank Access Parameters - EBC0_BnAP - | Peripheral Bank Configuration Register - EBC0_BnCR - +----------------------------------------------------------------------------*/ -/* Small Flash */ -#define EBC0_BNAP_SMALL_FLASH \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(6) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(3) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_SMALL_FLASH_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -#define EBC0_BNCR_SMALL_FLASH_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -/* Large Flash or SRAM */ -#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(8) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(1) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_RW | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_16BIT - - -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_16BIT - -/* NVRAM - FPGA */ -#define EBC0_BNAP_NVRAM_FPGA \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(9) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ - EBC0_BNAP_PEN_DISABLED - -#define EBC0_BNCR_NVRAM_FPGA_CS5 \ - EBC0_BNCR_BAS_ENCODE(0x80000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_8BIT - -/* Nand Flash */ -#define EBC0_BNAP_NAND_FLASH \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(3) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(0) | \ - EBC0_BNAP_WBN_ENCODE(0) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_NOT_DELAYED | \ - EBC0_BNAP_BEM_RW | \ - EBC0_BNAP_PEN_DISABLED - - -#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000 - -/* NAND0 */ -#define EBC0_BNCR_NAND_FLASH_CS1 \ - EBC0_BNCR_BAS_ENCODE(0x90000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT -/* NAND1 - Bank2 */ -#define EBC0_BNCR_NAND_FLASH_CS2 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT - -/* NAND1 - Bank3 */ -#define EBC0_BNCR_NAND_FLASH_CS3 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ - EBC0_BNCR_BW_32BIT - -int board_early_init_f(void) -{ - ext_bus_cntlr_init(); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- - * Setup the GPIO pins - *-------------------------------------------------------------------*/ - out32(GPIO0_OSRL, 0x00000400); - out32(GPIO0_OSRH, 0x00000000); - out32(GPIO0_TSRL, 0x00000400); - out32(GPIO0_TSRH, 0x00000000); - out32(GPIO0_ISR1L, 0x00000000); - out32(GPIO0_ISR1H, 0x00000000); - out32(GPIO0_ISR2L, 0x00000000); - out32(GPIO0_ISR2H, 0x00000000); - out32(GPIO0_ISR3L, 0x00000000); - out32(GPIO0_ISR3H, 0x00000000); - - out32(GPIO1_OSRL, 0x0C380000); - out32(GPIO1_OSRH, 0x00000000); - out32(GPIO1_TSRL, 0x0C380000); - out32(GPIO1_TSRH, 0x00000000); - out32(GPIO1_ISR1L, 0x0FC30000); - out32(GPIO1_ISR1H, 0x00000000); - out32(GPIO1_ISR2L, 0x0C010000); - out32(GPIO1_ISR2H, 0x00000000); - out32(GPIO1_ISR3L, 0x01400000); - out32(GPIO1_ISR3H, 0x00000000); - - configure_ppc440ep_pins(); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Bamboo - AMCC PPC440EP Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - - -int dram_init(void) -{ - gd->ram_size = spd_sdram(); - - return 0; -} - -/*----------------------------------------------------------------------------+ - | is_powerpc440ep_pass1. - +----------------------------------------------------------------------------*/ -int is_powerpc440ep_pass1(void) -{ - unsigned long pvr; - - pvr = get_pvr(); - - if (pvr == PVR_POWERPC_440EP_PASS1) - return true; - else if (pvr == PVR_POWERPC_440EP_PASS2) - return false; - else { - printf("brdutil error 3\n"); - for (;;) - ; - } - - return false; -} - -/*----------------------------------------------------------------------------+ - | is_nand_selected. - +----------------------------------------------------------------------------*/ -int is_nand_selected(void) -{ -#ifdef CONFIG_BAMBOO_NAND - return true; -#else - return false; -#endif -} - -/*----------------------------------------------------------------------------+ - | config_on_ebc_cs4_is_small_flash => from EPLD - +----------------------------------------------------------------------------*/ -unsigned char config_on_ebc_cs4_is_small_flash(void) -{ - /* Not implemented yet => returns constant value */ - return true; -} - -/*----------------------------------------------------------------------------+ - | Ext_bus_cntlr_init. - | Initialize the external bus controller - +----------------------------------------------------------------------------*/ -void ext_bus_cntlr_init(void) -{ - unsigned long sdr0_pstrp0, sdr0_sdstp1; - unsigned long bootstrap_settings, boot_selection, ebc_boot_size; - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0; - unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0; - unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0; - unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0; - unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0; - - - /*-------------------------------------------------------------------------+ - | - | PART 1 : Initialize EBC Bank 5 - | ============================== - | Bank5 is always associated to the NVRAM/EPLD. - | It has to be initialized prior to other banks settings computation since - | some board registers values may be needed - | - +-------------------------------------------------------------------------*/ - /* NVRAM - FPGA */ - mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA); - mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5); - - /*-------------------------------------------------------------------------+ - | - | PART 2 : Determine which boot device was selected - | ========================================= - | - | Read Pin Strap Register in PPC440EP - | In case of boot from IIC, read Serial Device Strap Register1 - | - | Result can either be : - | - Boot from EBC 8bits => SMALL FLASH - | - Boot from EBC 16bits => Large Flash or SRAM - | - Boot from NAND Flash - | - Boot from PCI - | - +-------------------------------------------------------------------------*/ - /* Read Pin Strap Register in PPC440EP */ - mfsdr(SDR0_PINSTP, sdr0_pstrp0); - bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK; - - /*-------------------------------------------------------------------------+ - | PPC440EP Pass1 - +-------------------------------------------------------------------------*/ - if (is_powerpc440ep_pass1() == true) { - switch(bootstrap_settings) { - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: - /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: - /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: - /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */ - /* Boot from Nand Flash */ - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: - /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - - case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: - case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: - /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ - /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(SDR0_SDSTP1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - } - break; - } - } - - /*-------------------------------------------------------------------------+ - | PPC440EP Pass2 - +-------------------------------------------------------------------------*/ - else { - switch(bootstrap_settings) { - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: - /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ - /* Boot from Small Flash */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: - /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: - /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */ - /* Boot from Nand Flash */ - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: - /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */ - /* Boot from Large Flash or SRAM */ - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: - /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */ - /* Boot from Large Flash or SRAM */ - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6: - /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */ - /* Boot from PCI */ - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: - case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: - /* Default Strap Settings 5-7 */ - /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ - /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(SDR0_SDSTP1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - computed_boot_device = BOOT_FROM_PCI; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - computed_boot_device = BOOT_FROM_NAND_FLASH0; - break; - } - break; - } - } - - /*-------------------------------------------------------------------------+ - | - | PART 3 : Compute EBC settings depending on selected boot device - | ====== ====================================================== - | - | Resulting EBC init will be among following configurations : - | - | - Boot from EBC 8bits => boot from SMALL FLASH selected - | EBC-CS0 = Small Flash - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Soft Config - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from EBC 16bits => boot from Large Flash or SRAM selected - | EBC-CS0 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Software Configuration - | EBC-CS4 = Small Flash - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from NAND Flash - | EBC-CS0 = NAND Flash0 - | EBC-CS1,2,3 = NAND Flash1 - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - | - Boot from PCI - | EBC-CS0 = ... - | EBC-CS1,2,3 = NAND Flash or - | Exp.Slot depending on Software Configuration - | EBC-CS4 = SRAM/Large Flash or - | Large Flash/SRAM or - | Small Flash depending on jumpers - | EBC-CS5 = NVRAM / EPLD - | - +-------------------------------------------------------------------------*/ - - switch(computed_boot_device) { - /*------------------------------------------------------------------------- */ - case BOOT_FROM_SMALL_FLASH: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0; - if ((is_nand_selected()) == true) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_LARGE_FLASH_OR_SRAM: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0; - if ((is_nand_selected()) == true) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_NAND_FLASH0: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - - /* Large Flash or SRAM */ - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_FROM_PCI: - /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = 0; - ebc0_cs0_bncr_value = 0; - - if ((is_nand_selected()) == true) { - /* NAND Flash */ - ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } else { - /* Expansion Slot */ - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; - ebc0_cs2_bnap_value = 0; - ebc0_cs2_bncr_value = 0; - ebc0_cs3_bnap_value = 0; - ebc0_cs3_bncr_value = 0; - } - - if ((config_on_ebc_cs4_is_small_flash()) == true) { - /* Small Flash */ - ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; - ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; - } else { - /* Large Flash or SRAM */ - ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; - ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; - } - - break; - - /*------------------------------------------------------------------------- */ - case BOOT_DEVICE_UNKNOWN: - /*------------------------------------------------------------------------- */ - /* Error */ - break; - - } - - - /*-------------------------------------------------------------------------+ - | Initialize EBC CONFIG - +-------------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN | - EBC0_CFG_PTD_ENABLED | - EBC0_CFG_RTC_2048PERCLK | - EBC0_CFG_EMPL_LOW | - EBC0_CFG_EMPH_LOW | - EBC0_CFG_CSTC_DRIVEN | - EBC0_CFG_BPF_ONEDW | - EBC0_CFG_EMS_8BIT | - EBC0_CFG_PME_DISABLED | - EBC0_CFG_PMT_ENCODE(0) ); - - /*-------------------------------------------------------------------------+ - | Initialize EBC Bank 0-4 - +-------------------------------------------------------------------------*/ - /* EBC Bank0 */ - mtebc(PB0AP, ebc0_cs0_bnap_value); - mtebc(PB0CR, ebc0_cs0_bncr_value); - /* EBC Bank1 */ - mtebc(PB1AP, ebc0_cs1_bnap_value); - mtebc(PB1CR, ebc0_cs1_bncr_value); - /* EBC Bank2 */ - mtebc(PB2AP, ebc0_cs2_bnap_value); - mtebc(PB2CR, ebc0_cs2_bncr_value); - /* EBC Bank3 */ - mtebc(PB3AP, ebc0_cs3_bnap_value); - mtebc(PB3CR, ebc0_cs3_bncr_value); - /* EBC Bank4 */ - mtebc(PB4AP, ebc0_cs4_bnap_value); - mtebc(PB4CR, ebc0_cs4_bncr_value); - - return; -} - - -/*----------------------------------------------------------------------------+ - | get_uart_configuration. - +----------------------------------------------------------------------------*/ -uart_config_nb_t get_uart_configuration(void) -{ - return (L4); -} - -/*----------------------------------------------------------------------------+ - | set_phy_configuration_through_fpga => to EPLD - +----------------------------------------------------------------------------*/ -void set_phy_configuration_through_fpga(zmii_config_t config) -{ - - unsigned long fpga_selection_reg; - - fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK; - - switch(config) - { - case ZMII_CONFIGURATION_IS_MII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII; - break; - case ZMII_CONFIGURATION_IS_RMII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII; - break; - case ZMII_CONFIGURATION_IS_SMII: - fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII; - break; - case ZMII_CONFIGURATION_UNKNOWN: - default: - break; - } - out8(FPGA_SELECTION_1_REG,fpga_selection_reg); - -} - -/*----------------------------------------------------------------------------+ - | scp_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void scp_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; - fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | iic1_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void iic1_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; - fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_a_b_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_a_b_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_a_b_unselect_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_a_b_unselect_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_c_d_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_c_d_selection_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | dma_c_d_unselect_in_fpga. - +----------------------------------------------------------------------------*/ -void dma_c_d_unselect_in_fpga(void) -{ - unsigned long fpga_selection_2_reg; - - fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D; - out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_device_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void usb2_device_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_device_reset_through_fpga. - +----------------------------------------------------------------------------*/ -void usb2_device_reset_through_fpga(void) -{ - /* Perform soft Reset pulse */ - unsigned long fpga_reset_reg; - int i; - - fpga_reset_reg = in8(FPGA_RESET_REG); - out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV); - for (i=0; i<500; i++) - udelay(1000); - out8(FPGA_RESET_REG,fpga_reset_reg); -} - -/*----------------------------------------------------------------------------+ - | usb2_host_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void usb2_host_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | ndfc_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void ndfc_selection_in_fpga(void) -{ - unsigned long fpga_selection_1_reg; - - fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK; - fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1; - fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; - out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); -} - -/*----------------------------------------------------------------------------+ - | uart_selection_in_fpga. - +----------------------------------------------------------------------------*/ -void uart_selection_in_fpga(uart_config_nb_t uart_config) -{ - /* FPGA register */ - unsigned char fpga_selection_3_reg; - - /* Read FPGA Reagister */ - fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG); - - switch (uart_config) - { - case L1: - /* ----------------------------------------------------------------------- */ - /* L1 configuration: UART0 = 8 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - case L2: - /* ----------------------------------------------------------------------- */ - /* L2 configuration: UART0 = 4 pins */ - /* UART1 = 4 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - case L3: - /* ----------------------------------------------------------------------- */ - /* L3 configuration: UART0 = 4 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ - /* ----------------------------------------------------------------------- */ - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - break; - - case L4: - /* Configure FPGA */ - fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; - fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4; - out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); - - break; - - default: - /* Unsupported UART configuration number */ - for (;;) - ; - break; - - } -} - - -/*----------------------------------------------------------------------------+ - | init_default_gpio - +----------------------------------------------------------------------------*/ -void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - int i; - - /* Init GPIO0 */ - for(i=0; i<GPIO_MAX; i++) - { - gpio_tab[GPIO0][i].add = GPIO0_BASE; - gpio_tab[GPIO0][i].in_out = GPIO_DIS; - gpio_tab[GPIO0][i].alt_nb = GPIO_SEL; - } - - /* Init GPIO1 */ - for(i=0; i<GPIO_MAX; i++) - { - gpio_tab[GPIO1][i].add = GPIO1_BASE; - gpio_tab[GPIO1][i].in_out = GPIO_DIS; - gpio_tab[GPIO1][i].alt_nb = GPIO_SEL; - } - - /* EBC_CS_N(5) - GPIO0_10 */ - gpio_tab[GPIO0][10].in_out = GPIO_OUT; - gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1; - - /* EBC_CS_N(4) - GPIO0_9 */ - gpio_tab[GPIO0][9].in_out = GPIO_OUT; - gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | update_uart_ios - +------------------------------------------------------------------------------ - | - | Set UART Configuration in PowerPC440EP - | - | +---------------------------------------------------------------------+ - | | Configuartion | Connector | Nb of pins | Pins | Associated | - | | Number | Port Name | available | naming | CORE | - | +-----------------+---------------+------------+--------+-------------+ - | | L1 | Port_A | 8 | UART | UART core 0 | - | +-----------------+---------------+------------+--------+-------------+ - | | L2 | Port_A | 4 | UART1 | UART core 0 | - | | (L2D) | Port_B | 4 | UART2 | UART core 1 | - | +-----------------+---------------+------------+--------+-------------+ - | | L3 | Port_A | 4 | UART1 | UART core 0 | - | | (L3D) | Port_B | 2 | UART2 | UART core 1 | - | | | Port_C | 2 | UART3 | UART core 2 | - | +-----------------+---------------+------------+--------+-------------+ - | | | Port_A | 2 | UART1 | UART core 0 | - | | L4 | Port_B | 2 | UART2 | UART core 1 | - | | (L4D) | Port_C | 2 | UART3 | UART core 2 | - | | | Port_D | 2 | UART4 | UART core 3 | - | +-----------------+---------------+------------+--------+-------------+ - | - | Involved GPIOs - | - | +------------------------------------------------------------------------------+ - | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O | - | +---------+------------------+-----+-----------------+-----+-------------+-----+ - | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O | - | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I | - | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I | - | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O | - | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA | - | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA | - | +------------------------------------------------------------------------------+ - | - | - +----------------------------------------------------------------------------*/ - -void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - switch (uart_config) - { - case L1: - /* ----------------------------------------------------------------------- */ - /* L1 configuration: UART0 = 8 pins */ - /* ----------------------------------------------------------------------- */ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO1][2].in_out = GPIO_IN; - gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][3].in_out = GPIO_IN; - gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][4].in_out = GPIO_IN; - gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][5].in_out = GPIO_OUT; - gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][6].in_out = GPIO_OUT; - gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][7].in_out = GPIO_IN; - gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1; - - break; - - case L2: - /* ----------------------------------------------------------------------- */ - /* L2 configuration: UART0 = 4 pins */ - /* UART1 = 4 pins */ - /* ----------------------------------------------------------------------- */ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO1][2].in_out = GPIO_IN; - gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][3].in_out = GPIO_OUT; - gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][4].in_out = GPIO_IN; - gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][5].in_out = GPIO_OUT; - gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][6].in_out = GPIO_OUT; - gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][7].in_out = GPIO_IN; - gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; - - break; - - case L3: - /* ----------------------------------------------------------------------- */ - /* L3 configuration: UART0 = 4 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ - /* ----------------------------------------------------------------------- */ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO1][2].in_out = GPIO_OUT; - gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][3].in_out = GPIO_IN; - gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][4].in_out = GPIO_IN; - gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][5].in_out = GPIO_OUT; - gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][6].in_out = GPIO_OUT; - gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][7].in_out = GPIO_IN; - gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; - - break; - - case L4: - /* ----------------------------------------------------------------------- */ - /* L4 configuration: UART0 = 2 pins */ - /* UART1 = 2 pins */ - /* UART2 = 2 pins */ - /* UART3 = 2 pins */ - /* ----------------------------------------------------------------------- */ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO1][2].in_out = GPIO_OUT; - gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][3].in_out = GPIO_IN; - gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][4].in_out = GPIO_IN; - gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][5].in_out = GPIO_OUT; - gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3; - - gpio_tab[GPIO1][6].in_out = GPIO_OUT; - gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][7].in_out = GPIO_IN; - gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; - - break; - - default: - /* Unsupported UART configuration number */ - printf("ERROR - Unsupported UART configuration number.\n\n"); - for (;;) - ; - break; - - } - - /* Set input Selection Register on Alt_Receive for UART Input Core */ - out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000)); - out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000)); - out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000)); -} - -/*----------------------------------------------------------------------------+ - | update_ndfc_ios(void). - +----------------------------------------------------------------------------*/ -void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ - gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */ - gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; - -#if 0 - gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */ - gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; -#endif -} - -/*----------------------------------------------------------------------------+ - | update_zii_ios(void). - +----------------------------------------------------------------------------*/ -void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - /* Update GPIO Configuration Table */ - gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ - gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */ - gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */ - gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */ - gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */ - gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */ - gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */ - gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */ - gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */ - gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */ - gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */ - gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */ - gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */ - gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */ - gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1; - -} - -/*----------------------------------------------------------------------------+ - | update_uic_0_3_irq_ios(). - +----------------------------------------------------------------------------*/ -void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ - gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */ - gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */ - gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */ - gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | update_uic_4_9_irq_ios(). - +----------------------------------------------------------------------------*/ -void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ - gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */ - gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */ - gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */ - gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */ - gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | update_dma_a_b_ios(). - +----------------------------------------------------------------------------*/ -void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ - gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */ - gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */ - gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */ - gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */ - gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2; -} - -/*----------------------------------------------------------------------------+ - | update_dma_c_d_ios(). - +----------------------------------------------------------------------------*/ -void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ - gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */ - gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */ - gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */ - gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */ - gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */ - gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2; - -} - -/*----------------------------------------------------------------------------+ - | update_ebc_master_ios(). - +----------------------------------------------------------------------------*/ -void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ - gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ - gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */ - gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */ - gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | update_usb2_device_ios(). - +----------------------------------------------------------------------------*/ -void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ - gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */ - gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */ - gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */ - gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */ - gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */ - gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2; - - gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */ - gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1; - - gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */ - gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1; - -} - -/*----------------------------------------------------------------------------+ - | update_pci_patch_ios(). - +----------------------------------------------------------------------------*/ -void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ - gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; -} - -/*----------------------------------------------------------------------------+ - | set_chip_gpio_configuration(unsigned char gpio_core, - | gpio_param_s (*gpio_tab)[GPIO_MAX]) - | Put the core impacted by clock modification and sharing in reset. - | Config the select registers to resolve the sharing depending of the config. - | Configure the GPIO registers. - | - +----------------------------------------------------------------------------*/ -void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX]) -{ - unsigned char i=0, j=0, reg_offset = 0; - unsigned long gpio_reg, gpio_core_add; - - /* GPIO config of the GPIOs 0 to 31 */ - for (i=0; i<GPIO_MAX; i++, j++) - { - if (i == GPIO_MAX/2) - { - reg_offset = 4; - j = i-16; - } - - gpio_core_add = gpio_tab[gpio_core][i].add; - - if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) || - (gpio_tab[gpio_core][i].in_out == GPIO_BI )) - { - switch (gpio_tab[gpio_core][i].alt_nb) - { - case GPIO_SEL: - break; - - case GPIO_ALT1: - gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT2: - gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); - break; - - case GPIO_ALT3: - gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) || - (gpio_tab[gpio_core][i].in_out == GPIO_BI )) - { - - switch (gpio_tab[gpio_core][i].alt_nb) - { - case GPIO_SEL: - break; - case GPIO_ALT1: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - case GPIO_ALT2: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - case GPIO_ALT3: - gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); - gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); - gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); - break; - } - } - } -} - -/*----------------------------------------------------------------------------+ - | force_bup_core_selection. - +----------------------------------------------------------------------------*/ -void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P) -{ - /* Pointer invalid */ - if (core_select_P == NULL) - { - printf("Configuration invalid pointer 1\n"); - for (;;) - ; - } - - /* L4 Selection */ - *(core_select_P+UART_CORE0) = CORE_SELECTED; - *(core_select_P+UART_CORE1) = CORE_SELECTED; - *(core_select_P+UART_CORE2) = CORE_SELECTED; - *(core_select_P+UART_CORE3) = CORE_SELECTED; - - /* RMII Selection */ - *(core_select_P+RMII_SEL) = CORE_SELECTED; - - /* External Interrupt 0-9 selection */ - *(core_select_P+UIC_0_3) = CORE_SELECTED; - *(core_select_P+UIC_4_9) = CORE_SELECTED; - - *(core_select_P+SCP_CORE) = CORE_SELECTED; - *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; - *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; - *(core_select_P+USB1_DEVICE) = CORE_SELECTED; - - if (is_nand_selected()) { - *(core_select_P+NAND_FLASH) = CORE_SELECTED; - } - - *config_val_P = CONFIG_IS_VALID; - -} - -/*----------------------------------------------------------------------------+ - | configure_ppc440ep_pins. - +----------------------------------------------------------------------------*/ -void configure_ppc440ep_pins(void) -{ - uart_config_nb_t uart_configuration; - config_validity_t config_val = CONFIG_IS_INVALID; - - /* Create Core Selection Table */ - core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] = - { - CORE_NOT_SELECTED, /* IIC_CORE, */ - CORE_NOT_SELECTED, /* SPC_CORE, */ - CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */ - CORE_NOT_SELECTED, /* UIC_4_9, */ - CORE_NOT_SELECTED, /* USB2_HOST, */ - CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */ - CORE_NOT_SELECTED, /* USB2_DEVICE, */ - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */ - CORE_NOT_SELECTED, /* USB1_DEVICE, */ - CORE_NOT_SELECTED, /* EBC_MASTER, */ - CORE_NOT_SELECTED, /* NAND_FLASH, */ - CORE_NOT_SELECTED, /* UART_CORE0, */ - CORE_NOT_SELECTED, /* UART_CORE1, */ - CORE_NOT_SELECTED, /* UART_CORE2, */ - CORE_NOT_SELECTED, /* UART_CORE3, */ - CORE_NOT_SELECTED, /* MII_SEL, */ - CORE_NOT_SELECTED, /* RMII_SEL, */ - CORE_NOT_SELECTED, /* SMII_SEL, */ - CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */ - CORE_NOT_SELECTED, /* UIC_0_3 */ - CORE_NOT_SELECTED, /* USB1_HOST */ - CORE_NOT_SELECTED /* PCI_PATCH */ - }; - - gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; - - /* Table Default Initialisation + FPGA Access */ - init_default_gpio(gpio_tab); - set_chip_gpio_configuration(GPIO0, gpio_tab); - set_chip_gpio_configuration(GPIO1, gpio_tab); - - /* Update Table */ - force_bup_core_selection(ppc440ep_core_selection, &config_val); -#if 0 /* test-only */ - /* If we are running PIBS 1, force known configuration */ - update_core_selection_table(ppc440ep_core_selection, &config_val); -#endif - - /*----------------------------------------------------------------------------+ - | SDR + ios table update + fpga initialization - +----------------------------------------------------------------------------*/ - unsigned long sdr0_pfc1 = 0; - unsigned long sdr0_usb0 = 0; - unsigned long sdr0_mfr = 0; - - /* PCI Always selected */ - - /* I2C Selection */ - if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; - iic1_selection_in_fpga(); - } - - /* SCP Selection */ - if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; - scp_selection_in_fpga(); - } - - /* UIC 0:3 Selection */ - if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) - { - update_uic_0_3_irq_ios(gpio_tab); - dma_a_b_unselect_in_fpga(); - } - - /* UIC 4:9 Selection */ - if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; - update_uic_4_9_irq_ios(gpio_tab); - } - - /* DMA AB Selection */ - if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; - update_dma_a_b_ios(gpio_tab); - dma_a_b_selection_in_fpga(); - } - - /* DMA CD Selection */ - if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) - { - update_dma_c_d_ios(gpio_tab); - dma_c_d_selection_in_fpga(); - } - - /* EBC Master Selection */ - if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_ebc_master_ios(gpio_tab); - } - - /* PCI Patch Enable */ - if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) - { - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_pci_patch_ios(gpio_tab); - } - - /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ - if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED) - { - /* Not Implemented in PowerPC 440EP Pass1-Pass2 */ - printf("Invalid configuration => USB2 Host selected\n"); - for (;;) - ; - /*usb2_host_selection_in_fpga(); */ - } - - /* USB2.0 Device Selection */ - if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) - { - update_usb2_device_ios(gpio_tab); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; - - mfsdr(SDR0_USB0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; - mtsdr(SDR0_USB0, sdr0_usb0); - - usb2_device_selection_in_fpga(); - } - - /* USB1.1 Device Selection */ - if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) - { - mfsdr(SDR0_USB0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; - mtsdr(SDR0_USB0, sdr0_usb0); - } - - /* USB1.1 Host Selection */ - if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) - { - mfsdr(SDR0_USB0, sdr0_usb0); - sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; - sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; - mtsdr(SDR0_USB0, sdr0_usb0); - } - - /* NAND Flash Selection */ - if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) - { - update_ndfc_ios(gpio_tab); - mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_CHIPSELGAT_EN1 | - SDR0_CUST0_CHIPSELGAT_EN2); - ndfc_selection_in_fpga(); - } - else - { - /* Set Mux on EMAC */ - mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL); - } - - /* MII Selection */ - if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) - { - update_zii_ios(gpio_tab); - mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; - mtsdr(SDR0_MFR, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); - } - - /* RMII Selection */ - if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) - { - update_zii_ios(gpio_tab); - mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; - mtsdr(SDR0_MFR, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); - } - - /* SMII Selection */ - if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) - { - update_zii_ios(gpio_tab); - mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; - mtsdr(SDR0_MFR, sdr0_mfr); - - set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); - } - - /* UART Selection */ - uart_configuration = get_uart_configuration(); - switch (uart_configuration) - { - case L1: /* L1 Selection */ - /* UART0 8 pins Only */ - /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS; - break; - case L2: /* L2 Selection */ - /* UART0 and UART1 4 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - case L3: /* L3 Selection */ - /* UART0 4 pins, UART1 and UART2 2 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - case L4: /* L4 Selection */ - /* UART0, UART1, UART2 and UART3 2 pins */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; - break; - } - update_uart_ios(uart_configuration, gpio_tab); - - /* UART Selection in all cases */ - uart_selection_in_fpga(uart_configuration); - - /* Packet Reject Function Available */ - if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED) - { - /* Set UPR Bit in SDR0_PFC1 Register */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE; - } - - /* Packet Reject Function Enable */ - if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) - { - mfsdr(SDR0_MFR, sdr0_mfr); - sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN; - mtsdr(SDR0_MFR, sdr0_mfr); - } - - /* Perform effective access to hardware */ - mtsdr(SDR0_PFC1, sdr0_pfc1); - set_chip_gpio_configuration(GPIO0, gpio_tab); - set_chip_gpio_configuration(GPIO1, gpio_tab); - - /* USB2.0 Device Reset must be done after GPIO setting */ - if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) - usb2_device_reset_through_fpga(); - -} diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h deleted file mode 100644 index 49f200a..0000000 --- a/board/amcc/bamboo/bamboo.h +++ /dev/null @@ -1,348 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*----------------------------------------------------------------------------+ - | FPGA registers and bit definitions - +----------------------------------------------------------------------------*/ -/* - * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0. - * TLB initialization makes it correspond to logical address 0x80001FF0. - * => Done init_chip.s in bootlib - */ -#define FPGA_BASE_ADDR 0x80002000 - -/*----------------------------------------------------------------------------+ - | Board Jumpers Setting Register - | Board Settings provided by jumpers - +----------------------------------------------------------------------------*/ -#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3) -/* Boot from small flash */ -#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80 -/* Operational Flash versus SRAM position in Memory Map */ -#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40 -#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40 -#define FPGA_SET_REG_SRAM_ABOVE 0x00 -/* Boot From NAND Flash */ -#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40 -#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00 -/* On Board PCI Arbiter Select */ -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10 -#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00 - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 1 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4) -#define FPGA_SEL_1_REG_PHY_MASK 0xE0 -#define FPGA_SEL_1_REG_MII 0x80 -#define FPGA_SEL_1_REG_RMII 0x40 -#define FPGA_SEL_1_REG_SMII 0x20 -#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */ -#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */ -#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */ -#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */ -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */ -#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */ - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 2 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5) -#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */ -#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */ -#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */ -#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */ -#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */ -#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */ -#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */ - /* 1 = TC - output from 440EP */ -#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */ - /* 1 = TC (output from 440EP) */ -#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */ -#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */ -#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */ - -/*----------------------------------------------------------------------------+ - | Functions Selection Register 3 - +----------------------------------------------------------------------------*/ -#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6) -#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70 -#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */ -#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */ -#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */ -#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */ - -/*----------------------------------------------------------------------------+ - | Soft Reset Register - +----------------------------------------------------------------------------*/ -#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7) -#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */ -#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */ -#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */ -#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */ - - -/*----------------------------------------------------------------------------+ -| SDR Configuration registers -+----------------------------------------------------------------------------*/ -#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */ -#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ - -#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */ -#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ -#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */ -#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */ - -/* Serial Device Enabled - Addr = 0xA8 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 -/* Serial Device Enabled - Addr = 0xA4 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 - -/* Pin Straps Reg */ -#define SDR0_PSTRP0 0x0040 -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ - -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ - -/*----------------------------------------------------------------------------+ -| EBC Configuration Register - EBC0_CFG -+----------------------------------------------------------------------------*/ -/* External Bus Three-State Control */ -#define EBC0_CFG_EBTC_DRIVEN 0x80000000 -/* Device-Paced Time-out Disable */ -#define EBC0_CFG_PTD_ENABLED 0x00000000 -/* Ready Timeout Count */ -#define EBC0_CFG_RTC_MASK 0x38000000 -#define EBC0_CFG_RTC_16PERCLK 0x00000000 -#define EBC0_CFG_RTC_32PERCLK 0x08000000 -#define EBC0_CFG_RTC_64PERCLK 0x10000000 -#define EBC0_CFG_RTC_128PERCLK 0x18000000 -#define EBC0_CFG_RTC_256PERCLK 0x20000000 -#define EBC0_CFG_RTC_512PERCLK 0x28000000 -#define EBC0_CFG_RTC_1024PERCLK 0x30000000 -#define EBC0_CFG_RTC_2048PERCLK 0x38000000 -/* External Master Priority Low */ -#define EBC0_CFG_EMPL_LOW 0x00000000 -#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 -#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 -#define EBC0_CFG_EMPL_HIGH 0x06000000 -/* External Master Priority High */ -#define EBC0_CFG_EMPH_LOW 0x00000000 -#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 -#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 -#define EBC0_CFG_EMPH_HIGH 0x01800000 -/* Chip Select Three-State Control */ -#define EBC0_CFG_CSTC_DRIVEN 0x00400000 -/* Burst Prefetch */ -#define EBC0_CFG_BPF_ONEDW 0x00000000 -#define EBC0_CFG_BPF_TWODW 0x00100000 -#define EBC0_CFG_BPF_FOURDW 0x00200000 -/* External Master Size */ -#define EBC0_CFG_EMS_8BIT 0x00000000 -/* Power Management Enable */ -#define EBC0_CFG_PME_DISABLED 0x00000000 -#define EBC0_CFG_PME_ENABLED 0x00020000 -/* Power Management Timer */ -#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) - -/*----------------------------------------------------------------------------+ -| Peripheral Bank Configuration Register - EBC0_BnCR -+----------------------------------------------------------------------------*/ -/* BAS - Base Address Select */ -#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) -/* BS - Bank Size */ -#define EBC0_BNCR_BS_MASK 0x000E0000 -#define EBC0_BNCR_BS_1MB 0x00000000 -#define EBC0_BNCR_BS_2MB 0x00020000 -#define EBC0_BNCR_BS_4MB 0x00040000 -#define EBC0_BNCR_BS_8MB 0x00060000 -#define EBC0_BNCR_BS_16MB 0x00080000 -#define EBC0_BNCR_BS_32MB 0x000A0000 -#define EBC0_BNCR_BS_64MB 0x000C0000 -#define EBC0_BNCR_BS_128MB 0x000E0000 -/* BU - Bank Usage */ -#define EBC0_BNCR_BU_MASK 0x00018000 -#define EBC0_BNCR_BU_RO 0x00008000 -#define EBC0_BNCR_BU_WO 0x00010000 -#define EBC0_BNCR_BU_RW 0x00018000 -/* BW - Bus Width */ -#define EBC0_BNCR_BW_MASK 0x00006000 -#define EBC0_BNCR_BW_8BIT 0x00000000 -#define EBC0_BNCR_BW_16BIT 0x00002000 -#define EBC0_BNCR_BW_32BIT 0x00004000 - -/*----------------------------------------------------------------------------+ -| Peripheral Bank Access Parameters - EBC0_BnAP -+----------------------------------------------------------------------------*/ -/* Burst Mode Enable */ -#define EBC0_BNAP_BME_ENABLED 0x80000000 -#define EBC0_BNAP_BME_DISABLED 0x00000000 -/* Transfert Wait */ -#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */ -/* Chip Select On Timing */ -#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */ -/* Output Enable On Timing */ -#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */ -/* Write Back Enable On Timing */ -#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */ -/* Write Back Enable Off Timing */ -#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */ -/* Transfert Hold */ -#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */ -/* PerReady Enable */ -#define EBC0_BNAP_RE_ENABLED 0x00000100 -#define EBC0_BNAP_RE_DISABLED 0x00000000 -/* Sample On Ready */ -#define EBC0_BNAP_SOR_DELAYED 0x00000000 -#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080 -/* Byte Enable Mode */ -#define EBC0_BNAP_BEM_WRITEONLY 0x00000000 -#define EBC0_BNAP_BEM_RW 0x00000040 -/* Parity Enable */ -#define EBC0_BNAP_PEN_DISABLED 0x00000000 -#define EBC0_BNAP_PEN_ENABLED 0x00000020 - -/*----------------------------------------------------------------------------+ -| Define Boot devices -+----------------------------------------------------------------------------*/ -/* */ -#define BOOT_FROM_SMALL_FLASH 0x00 -#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 -#define BOOT_FROM_NAND_FLASH0 0x02 -#define BOOT_FROM_PCI 0x03 -#define BOOT_DEVICE_UNKNOWN 0x04 - - -#define PVR_POWERPC_440EP_PASS1 0x42221850 -#define PVR_POWERPC_440EP_PASS2 0x422218D3 - -#define GPIO0 0 -#define GPIO1 1 - -/*#define MAX_SELECTION_NB CORE_NB */ -#define MAX_CORE_SELECT_NB 22 - -/*----------------------------------------------------------------------------+ - | PPC440EP GPIOs addresses. - +----------------------------------------------------------------------------*/ -#define GPIO0_REAL 0xEF600B00 - -#define GPIO1_REAL 0xEF600C00 - -/* Offsets */ -#define GPIOx_OR 0x00 /* GPIO Output Register */ -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ -#define GPIOx_IR 0x1C /* GPIO Input Register */ -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ - -/* GPIO0 */ -#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L) -#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H) -#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L) -#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H) -#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L) -#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L) - -/* GPIO1 */ -#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L) -#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H) -#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L) -#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H) -#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L) -#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L) - -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ - - -/*----------------------------------------------------------------------------+ - | XX XX - | - | XXXXXX XXX XX XXX XXX - | XX XX X XX XX XX - | XX XX X XX XX XX - | XX XX XX XX XX - | XXXXXX XXX XXX XXXX XXXX - +----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ - | Defines - +----------------------------------------------------------------------------*/ -typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN, - ZMII_CONFIGURATION_IS_MII, - ZMII_CONFIGURATION_IS_RMII, - ZMII_CONFIGURATION_IS_SMII -} zmii_config_t; - -/*----------------------------------------------------------------------------+ - | Declare Configuration values - +----------------------------------------------------------------------------*/ -typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t; -typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t; -typedef enum config_list { IIC_CORE, - SCP_CORE, - DMA_CHANNEL_AB, - UIC_4_9, - USB2_HOST, - DMA_CHANNEL_CD, - USB2_DEVICE, - PACKET_REJ_FUNC_AVAIL, - USB1_DEVICE, - EBC_MASTER, - NAND_FLASH, - UART_CORE0, - UART_CORE1, - UART_CORE2, - UART_CORE3, - MII_SEL, - RMII_SEL, - SMII_SEL, - PACKET_REJ_FUNC_EN, - UIC_0_3, - USB1_HOST, - PCI_PATCH, - CORE_NB -} core_list_t; - -typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5, - B3_V6, B3_V7, B3_V8, B3_V9, B3_V10, - B3_V11, B3_V12, B3_V13, B3_V14, B3_V15, - B3_V16, B3_VALUE_UNKNOWN -} block3_value_t; - -typedef enum config_validity { CONFIG_IS_VALID, - CONFIG_IS_INVALID -} config_validity_t; diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk deleted file mode 100644 index 9cb071e..0000000 --- a/board/amcc/bamboo/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c deleted file mode 100644 index 6dbe09f..0000000 --- a/board/amcc/bamboo/flash.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/ppc440.h> -#include "bamboo.h" - -#undef DEBUG - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 - */ -static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ - {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ - {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */ - {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ - {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ - {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ - {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ - {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - unsigned long val; - unsigned long ebc_boot_size; - unsigned long boot_selection; - - mfsdr(SDR0_PINSTP, val); - index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29; - - if ((index == 5) || (index == 7)) { - /* - * Boot Settings in IIC EEprom address 0xA8 or 0xA4 - * Read Serial Device Strap Register1 in PPC440EP - */ - mfsdr(SDR0_SDSTP1, val); - boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - index = 3; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - index = 0; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - index = 1; - break; - - case SDR0_SDSTP1_BOOT_SEL_NDFC: - index = 2; - break; - } - } else if (index == 0) { - if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) { - index = 8; /* sram below op code flash -> new index 8 */ - } - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) - continue; - - DEBUGF("Detection bank %d...\n", i); - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S deleted file mode 100644 index 5c7c839..0000000 --- a/board/amcc/bamboo/init.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) - - /* PCI base & peripherals */ - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I) - tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I) - - /* PCI */ - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG) - - /* USB 2.0 Device */ - tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG) - - tlbtab_end diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig deleted file mode 100644 index 540d9b6..0000000 --- a/board/amcc/bubinga/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_BUBINGA - -config SYS_BOARD - default "bubinga" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "bubinga" - -endif diff --git a/board/amcc/bubinga/MAINTAINERS b/board/amcc/bubinga/MAINTAINERS deleted file mode 100644 index 3299cc3..0000000 --- a/board/amcc/bubinga/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BUBINGA BOARD -#M: - -S: Maintained -F: board/amcc/bubinga/ -F: include/configs/bubinga.h -F: configs/bubinga_defconfig diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile deleted file mode 100644 index 0e7ebca..0000000 --- a/board/amcc/bubinga/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = bubinga.o flash.o diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c deleted file mode 100644 index c73424d..0000000 --- a/board/amcc/bubinga/bubinga.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -long int spd_sdram(void); - -int board_early_init_f(void) -{ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000010); - mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */ - mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * Configure CPC0_PCI to enable PerWE as output - * and enable the internal PCI arbiter if selected - */ - if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) - mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); - else - mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: Bubinga - AMCC PPC405EP Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- - dram_init() reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration - ------------------------------------------------------------------------- */ -int dram_init(void) -{ - gd->ram_size = spd_sdram(); - - return 0; -} diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c deleted file mode 100644 index a9d0ed8..0000000 --- a/board/amcc/bubinga/flash.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - size_b1 = 0; - flash_info[0].size = size_b0; - } - - /* 2 banks */ - else { - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr(EBC0_CFGADDR, PB1CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB0CR = %x\n", pbcr); */ - } - - size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets(base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN, - base_b0 + size_b0 - 1, &flash_info[0]); - /* Also protect sector containing initial power-up instruction */ - /* (flash_protect() checks address range - other call ignored) */ - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets(base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN, - base_b1 + size_b1 - 1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN, - base_b0 + size_b0 - 1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - } /* else 2 banks */ - return (size_b0 + size_b1); -} - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig deleted file mode 100644 index cea6009..0000000 --- a/board/amcc/canyonlands/Kconfig +++ /dev/null @@ -1,33 +0,0 @@ -if TARGET_CANYONLANDS - -config SYS_BOARD - default "canyonlands" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "canyonlands" - -choice BOARD_TYPE - prompt "Select which board to build for" - optional - -config CANYONLANDS - bool "Glacier" - help - Select this to build for the Canyonlands 460EX board. - -config GLACIER - bool "Glacier" - help - Select this to build for the Glacier 460GT board. - -config ARCHES - bool "Arches" - help - Select this to build for the Arches dual 460GT board. - -endchoice - -endif diff --git a/board/amcc/canyonlands/MAINTAINERS b/board/amcc/canyonlands/MAINTAINERS deleted file mode 100644 index 8be8a52..0000000 --- a/board/amcc/canyonlands/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -CANYONLANDS BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/canyonlands/ -F: include/configs/canyonlands.h -F: configs/arches_defconfig -F: configs/canyonlands_defconfig -F: configs/glacier_defconfig -F: configs/glacier_ramboot_defconfig diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile deleted file mode 100644 index ba0765f..0000000 --- a/board/amcc/canyonlands/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := canyonlands.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c deleted file mode 100644 index 6ea004c..0000000 --- a/board/amcc/canyonlands/canyonlands.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc440.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <i2c.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/4xx_pcie.h> -#include <asm/ppc4xx-gpio.h> -#include <linux/errno.h> -#include <usb.h> - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -DECLARE_GLOBAL_DATA_PTR; - -struct board_bcsr { - u8 board_id; - u8 cpld_rev; - u8 led_user; - u8 board_status; - u8 reset_ctrl; - u8 flash_ctrl; - u8 eth_ctrl; - u8 usb_ctrl; - u8 irq_ctrl; -}; - -#define BOARD_CANYONLANDS_PCIE 1 -#define BOARD_CANYONLANDS_SATA 2 -#define BOARD_GLACIER 3 -#define BOARD_ARCHES 4 - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -#if defined(CONFIG_ARCHES) -u32 ddr_wrdtr(u32 default_val) { - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823); -} -#else -u32 ddr_wrdtr(u32 default_val) { - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); -} - -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_90_DEG_ADV); -} -#endif - -#if defined(CONFIG_ARCHES) -/* - * FPGA read/write helper macros - */ -static inline int board_fpga_read(int offset) -{ - return in_8((void *)(CONFIG_SYS_FPGA_BASE + offset)); -} - -static inline void board_fpga_write(int offset, int data) -{ - out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data); -} - -/* - * CPLD read/write helper macros - */ -static inline int board_cpld_read(int offset) -{ - int data; - - out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); - data = in_8((void *)(CONFIG_SYS_CPLD_DATA)); - - return data; -} - -static inline void board_cpld_write(int offset, int data) -{ - out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); - out_8((void *)(CONFIG_SYS_CPLD_DATA), data); -} -#else -static int pvr_460ex(void) -{ - u32 pvr = get_pvr(); - - if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) || - (pvr == PVR_460EX_RB)) - return 1; - - return 0; -} -#endif /* defined(CONFIG_ARCHES) */ - -int board_early_init_f(void) -{ -#if !defined(CONFIG_ARCHES) - u32 sdr0_cust0; - struct board_bcsr *bcsr_data = - (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; - -#endif - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - -#if !defined(CONFIG_ARCHES) - /* SDR Setting - enable NDFC */ - mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_NDFC_BAC_ENCODE(3) | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); -#endif - - /* - * Configure PFC (Pin Function Control) registers - * UART0: 4 pins - */ - mtsdr(SDR0_PFC1, 0x00040000); - - /* Enable PCI host functionality in SDR0_PCI0 */ - mtsdr(SDR0_PCI0, 0xe0000000); - -#if !defined(CONFIG_ARCHES) - /* Enable ethernet and take out of reset */ - out_8(&bcsr_data->eth_ctrl, 0) ; - - /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ - out_8(&bcsr_data->flash_ctrl, 0) ; - mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - -#endif - - return 0; -} - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) -int board_usb_init(int index, enum usb_init_type init) -{ - struct board_bcsr *bcsr_data = - (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; - u8 val; - - /* Enable USB host & USB-OTG */ - val = in_8(&bcsr_data->usb_ctrl); - val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); - out_8(&bcsr_data->usb_ctrl, val); - - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - - return 0; -} - -int usb_board_stop(void) -{ - struct board_bcsr *bcsr_data = - (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; - u8 val; - - /* Disable USB host & USB-OTG */ - val = in_8(&bcsr_data->usb_ctrl); - val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); - out_8(&bcsr_data->usb_ctrl, val); - - /* Reconfigure USB-STP pins as input */ - gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0); - gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0); - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return usb_board_stop(); -} -#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */ - -#if !defined(CONFIG_ARCHES) -static void canyonlands_sata_init(int board_type) -{ - u32 reg; - - if (board_type == BOARD_CANYONLANDS_SATA) { - /* Put SATA in reset */ - SDR_WRITE(SDR0_SRST1, 0x00020001); - - /* Set the phy for SATA, not PCI-E port 0 */ - reg = SDR_READ(PESDR0_PHY_CTL_RST); - SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001); - reg = SDR_READ(PESDR0_L0CLK); - SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007); - SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111); - SDR_WRITE(PESDR0_L0DRV, 0x00000104); - - /* Bring SATA out of reset */ - SDR_WRITE(SDR0_SRST1, 0x00000000); - } -} -#endif /* !defined(CONFIG_ARCHES) */ - -int get_cpu_num(void) -{ - int cpu = NA_OR_UNKNOWN_CPU; - -#if defined(CONFIG_ARCHES) - int cpu_num; - - cpu_num = board_fpga_read(0x3); - - /* sanity check; assume cpu numbering starts and increments from 0 */ - if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS)) - cpu = cpu_num; -#endif - - return cpu; -} - -#if !defined(CONFIG_ARCHES) -int checkboard(void) -{ - struct board_bcsr *bcsr_data = - (struct board_bcsr *)CONFIG_SYS_BCSR_BASE; - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - if (pvr_460ex()) { - printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); - if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE) - gd->board_type = BOARD_CANYONLANDS_PCIE; - else - gd->board_type = BOARD_CANYONLANDS_SATA; - } else { - printf("Board: Glacier - AMCC PPC460GT Evaluation Board"); - gd->board_type = BOARD_GLACIER; - } - - switch (gd->board_type) { - case BOARD_CANYONLANDS_PCIE: - case BOARD_GLACIER: - puts(", 2*PCIe"); - break; - - case BOARD_CANYONLANDS_SATA: - puts(", 1*PCIe/1*SATA"); - break; - } - - printf(", Rev. %X", in_8(&bcsr_data->cpld_rev)); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - canyonlands_sata_init(gd->board_type); - - return (0); -} - -#else /* defined(CONFIG_ARCHES) */ - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n"); - printf(" Revision %02x.%02x ", - board_fpga_read(0x0), board_fpga_read(0x1)); - - gd->board_type = BOARD_ARCHES; - - /* Only CPU0 has access to CPLD registers */ - if (get_cpu_num() == 0) { - u8 cfg_sw = board_cpld_read(0x1); - printf("(FPGA=%02x, CPLD=%02x)\n", - board_fpga_read(0x2), board_cpld_read(0x0)); - printf(" Configuration Switch %d%d%d%d\n", - ((cfg_sw >> 3) & 0x01), - ((cfg_sw >> 2) & 0x01), - ((cfg_sw >> 1) & 0x01), - ((cfg_sw >> 0) & 0x01)); - } else - printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2)); - - - if (s != NULL) - printf(" Serial# %s\n", s); - - return 0; -} -#endif /* !defined(CONFIG_ARCHES) */ - -#if defined(CONFIG_PCI) -int board_pcie_first(void) -{ - /* - * Canyonlands with SATA enabled has only one PCIe slot - * (2nd one). - */ - if (gd->board_type == BOARD_CANYONLANDS_SATA) - return 1; - - return 0; -} -#endif /* CONFIG_PCI */ - -int board_early_init_r (void) -{ - /* - * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the - * boot EBC mapping only supports a maximum of 16MBytes - * (4.ff00.0000 - 4.ffff.ffff). - * To solve this problem, the FLASH has to get remapped to another - * EBC address which accepts bigger regions: - * - * 0xfc00.0000 -> 4.cc00.0000 - */ - - /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ - mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); - - /* Remove TLB entry of boot EBC mapping */ - remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); - - /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */ - program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE, - TLB_WORD2_I_ENABLE); - - /* - * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address - * 0xfc00.0000 is possible - */ - - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return 0; -} - -#if !defined(CONFIG_ARCHES) -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - u32 eth_cfg; - u8 val; - - /* - * Set EMAC mode/configuration (GMII, SGMII, RGMII...). - * This is board specific, so let's do it here. - */ - mfsdr(SDR0_ETH_CFG, eth_cfg); - /* disable SGMII mode */ - eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | - SDR0_ETH_CFG_SGMII1_ENABLE | - SDR0_ETH_CFG_SGMII0_ENABLE); - /* Set the for 2 RGMII mode */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ - eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - if (pvr_460ex()) - eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; - else - eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; - mtsdr(SDR0_ETH_CFG, eth_cfg); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - /* - * RTC/M41T62: - * Disable square wave output: Batterie will be drained - * quickly, when this output is not disabled - */ - val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa); - val &= ~0x40; - i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val); - - return 0; -} - -#else /* defined(CONFIG_ARCHES) */ - -int misc_init_r(void) -{ - u32 eth_cfg = 0; - u32 eth_pll; - u32 reg; - - /* - * Set EMAC mode/configuration (GMII, SGMII, RGMII...). - * This is board specific, so let's do it here. - */ - - /* enable SGMII mode */ - eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE | - SDR0_ETH_CFG_SGMII1_ENABLE | - SDR0_ETH_CFG_SGMII2_ENABLE); - - /* Set EMAC for MDIO */ - eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; - - /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ - eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); - - mtsdr(SDR0_ETH_CFG, eth_cfg); - - /* reset all SGMII interfaces */ - mfsdr(SDR0_SRST1, reg); - reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2); - mtsdr(SDR0_SRST1, reg); - mtsdr(SDR0_ETH_STS, 0xFFFFFFFF); - mtsdr(SDR0_SRST1, 0x00000000); - - do { - mfsdr(SDR0_ETH_PLL, eth_pll); - } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK)); - - return 0; -} -#endif /* !defined(CONFIG_ARCHES) */ - -#ifdef CONFIG_OF_BOARD_SETUP -extern int __ft_board_setup(void *blob, bd_t *bd); - -int ft_board_setup(void *blob, bd_t *bd) -{ - __ft_board_setup(blob, bd); - - if (gd->board_type == BOARD_CANYONLANDS_SATA) { - /* - * When SATA is selected we need to disable the first PCIe - * node in the device tree, so that Linux doesn't initialize - * it. - */ - fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", - "disabled", sizeof("disabled"), 1); - } - - if (gd->board_type == BOARD_CANYONLANDS_PCIE) { - /* - * When PCIe is selected we need to disable the SATA - * node in the device tree, so that Linux doesn't initialize - * it. - */ - fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", - "disabled", sizeof("disabled"), 1); - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/amcc/canyonlands/chip_config.c b/board/amcc/canyonlands/chip_config.c deleted file mode 100644 index e485570..0000000 --- a/board/amcc/canyonlands/chip_config.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, -#if !defined(CONFIG_ARCHES) - { - "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, -#endif -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk deleted file mode 100644 index 5cc90d2..0000000 --- a/board/amcc/canyonlands/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2008-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 460EX/460GT Evaluation Board (Canyonlands) board -# - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S deleted file mode 100644 index bf00bd6..0000000 --- a/board/amcc/canyonlands/init.S +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to - * use the speed up boot process. It is patched after relocation to - * enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */ - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) -#endif - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) - - /* PCIe UTL register */ - tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG) - -#if !defined(CONFIG_ARCHES) - /* TLB-entry for NAND */ - tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG) - - /* TLB-entry for CPLD */ - tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG) -#else - /* TLB-entry for FPGA */ - tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG) -#endif - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG) - - /* AHB: Internal USB Peripherals (USB, SATA) */ - tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG) - -#if defined(CONFIG_RAPIDIO) - /* TLB-entries for RapidIO (SRIO) */ - tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR, - 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR, - 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR, - 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000, - 0x4, AC_RW | SA_IG) -#endif - - tlbtab_end diff --git a/board/amcc/canyonlands/u-boot-ram.lds b/board/amcc/canyonlands/u-boot-ram.lds deleted file mode 100644 index 1750c74..0000000 --- a/board/amcc/canyonlands/u-boot-ram.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - _image_copy_start = .; - arch/powerpc/cpu/ppc4xx/start.o (.text*) - board/amcc/canyonlands/init.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { - *(.data.init) - . = ALIGN(256); - LONG(0) LONG(0) /* Extend u-boot.bin to here */ - } - __init_end = .; - _end = .; - _image_binary_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c deleted file mode 100644 index 4b2300b..0000000 --- a/board/amcc/common/flash.c +++ /dev/null @@ -1,934 +0,0 @@ -/* - * (C) Copyright 2004-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_MX: - printf ("MACRONIX "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_MXLV320T: - printf ("MXLV320T (32 Mbit, top sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) { - return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); - } else { - return flash_get_size_1(addr, info); - } -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; /* => 2 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; /* => 4 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; /* => 512 KiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; /* => 1 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MiB */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; /* => 2 MiB */ - break; - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV - -#undef CONFIG_SYS_FLASH_WORD_SIZE -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - int n; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MiB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MiB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = 0x00400000; break; /* => 4 MiB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T: - info->flash_id += FLASH_MXLV320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - /* 1 x 16k boot sector */ - base -= 16 << 10; - --i; - info->start[i] = base; - /* 2 x 8k boot sectors */ - for (n=0; n<2; ++n) { - base -= 8 << 10; - --i; - info->start[i] = base; - } - /* 1 x 32k boot sector */ - base -= 32 << 10; - --i; - info->start[i] = base; - - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - info->start[i--] = base + info->size - 0x00010000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000a000; - info->start[6] = base + 0x0000c000; - info->start[7] = base + 0x0000e000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + ((i-7) * 0x00010000); - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} -#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig deleted file mode 100644 index fc606cf..0000000 --- a/board/amcc/katmai/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KATMAI - -config SYS_BOARD - default "katmai" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "katmai" - -endif diff --git a/board/amcc/katmai/MAINTAINERS b/board/amcc/katmai/MAINTAINERS deleted file mode 100644 index f089352..0000000 --- a/board/amcc/katmai/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -KATMAI BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/katmai/ -F: include/configs/katmai.h -F: configs/katmai_defconfig diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile deleted file mode 100644 index b738def..0000000 --- a/board/amcc/katmai/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := katmai.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/amcc/katmai/chip_config.c b/board/amcc/katmai/chip_config.c deleted file mode 100644 index 5e711c4..0000000 --- a/board/amcc/katmai/chip_config.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "400-133","CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "500-166","CPU: 500 PLB: 166 OPB: 83 EBC: 83", - { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "533-133","CPU: 533 PLB: 133 OPB: 66 EBC: 66", - { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "667-133","CPU: 667 PLB: 133 OPB: 66 EBC: 66", - { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "667-166","CPU: 667 PLB: 166 OPB: 83 EBC: 83", - { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "800-160","CPU: 800 PLB: 160 OPB: 53 EBC: 17", - { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk deleted file mode 100644 index 6108f79..0000000 --- a/board/amcc/katmai/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440SPe Evaluation (Katmai) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S deleted file mode 100644 index 32f2667..0000000 --- a/board/amcc/katmai/init.S +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - -/************************************************************************** - * TLB table for revA - *************************************************************************/ - .globl tlbtabA -tlbtabA: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG) - tlbtab_end - -/************************************************************************** - * TLB table for revB - * - * Notice: revB of the 440SPe chip is very strict about PLB real addresses - * and ranges to be mapped for config space: it seems to only work with - * d_nnnn_nnnn range (hangs the core upon config transaction attempts when - * set otherwise) while revA uses c_nnnn_nnnn. - *************************************************************************/ - .globl tlbtabB -tlbtabB: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG) - tlbtab_end diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c deleted file mode 100644 index 7582d40..0000000 --- a/board/amcc/katmai/katmai.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * (C) Copyright 2007-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <i2c.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/4xx_pcie.h> -#include <linux/errno.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f (void) -{ - unsigned long mfr; - - /*----------------------------------------------------------------------+ - * Interrupt controller setup for the Katmai 440SPe Evaluation board. - *-----------------------------------------------------------------------+ - *-----------------------------------------------------------------------+ - * Interrupt | Source | Pol. | Sensi.| Crit. | - *-----------+-----------------------------------+-------+-------+-------+ - * IRQ 00 | UART0 | High | Level | Non | - * IRQ 01 | UART1 | High | Level | Non | - * IRQ 02 | IIC0 | High | Level | Non | - * IRQ 03 | IIC1 | High | Level | Non | - * IRQ 04 | PCI0X0 MSG IN | High | Level | Non | - * IRQ 05 | PCI0X0 CMD Write | High | Level | Non | - * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | - * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | - * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | - * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | - * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | - * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | - * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | - * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | - * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | - * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | - * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | - * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | - * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | - * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | - * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | - * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | - * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | - * IRQ 23 | I2O Inbound Doorbell | High | Level | Non | - * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | - * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | - * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | - * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | - * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | - * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | - * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | - * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | - *------------------------------------------------------------------------ - * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | - * IRQ 33 | MAL Serr | High | Level | Non | - * IRQ 34 | MAL Txde | High | Level | Non | - * IRQ 35 | MAL Rxde | High | Level | Non | - * IRQ 36 | DMC CE or DMC UE | High | Level | Non | - * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | - * IRQ 38 | MAL TX EOB | High | Level | Non | - * IRQ 39 | MAL RX EOB | High | Level | Non | - * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | - * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | - * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | - * IRQ 43 | L2 Cache | Risin | Edge | Non | - * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | - * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | - * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | - * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | - * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | - * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | - * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | - * IRQ 54 | DMA Error | High | Level | Non | - * IRQ 55 | DMA I2O Error | High | Level | Non | - * IRQ 56 | Serial ROM | High | Level | Non | - * IRQ 57 | PCIX0 Error | High | Edge | Non | - * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | - * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | - * IRQ 60 | EMAC0 Interrupt | High | Level | Non | - * IRQ 61 | EMAC0 Wake-up | High | Level | Non | - * IRQ 62 | Reserved | High | Level | Non | - * IRQ 63 | XOR | High | Level | Non | - *----------------------------------------------------------------------- - * IRQ 64 | PE0 AL | High | Level | Non | - * IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - * IRQ 68 | PE0 TCR | High | Level | Non | - * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - * IRQ 70 | PE0 DCR Error | High | Level | Non | - * IRQ 71 | Reserved | N/A | N/A | Non | - * IRQ 72 | PE1 AL | High | Level | Non | - * IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - * IRQ 76 | PE1 TCR | High | Level | Non | - * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - * IRQ 78 | PE1 DCR Error | High | Level | Non | - * IRQ 79 | Reserved | N/A | N/A | Non | - * IRQ 80 | PE2 AL | High | Level | Non | - * IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - * IRQ 84 | PE2 TCR | High | Level | Non | - * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - * IRQ 86 | PE2 DCR Error | High | Level | Non | - * IRQ 87 | Reserved | N/A | N/A | Non | - * IRQ 88 | External IRQ(5) | Progr | Progr | Non | - * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - * IRQ 94 | Reserved | N/A | N/A | Non | - * IRQ 95 | Reserved | N/A | N/A | Non | - *----------------------------------------------------------------------- - * IRQ 96 | PE0 INTA | High | Level | Non | - * IRQ 97 | PE0 INTB | High | Level | Non | - * IRQ 98 | PE0 INTC | High | Level | Non | - * IRQ 99 | PE0 INTD | High | Level | Non | - * IRQ 100 | PE1 INTA | High | Level | Non | - * IRQ 101 | PE1 INTB | High | Level | Non | - * IRQ 102 | PE1 INTC | High | Level | Non | - * IRQ 103 | PE1 INTD | High | Level | Non | - * IRQ 104 | PE2 INTA | High | Level | Non | - * IRQ 105 | PE2 INTB | High | Level | Non | - * IRQ 106 | PE2 INTC | High | Level | Non | - * IRQ 107 | PE2 INTD | Risin | Edge | Non | - * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | - * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | - * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | - * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | - * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | - * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | - * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | - * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | - * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | - * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | - * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | - * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | - * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | - * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | - * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | - * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | - * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | - * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | - * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | - * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | - *-----------+-----------------------------------+-------+-------+-------+ */ - /*-------------------------------------------------------------------------+ - * Put UICs in PowerPC440SPemode. - * Initialise UIC registers. Clear all interrupts. Disable all interrupts. - * Set critical interrupt values. Set interrupt polarities. Set interrupt - * trigger levels. Make bit 0 High priority. Clear all interrupts again. - *------------------------------------------------------------------------*/ - mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */ - mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/ - - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ - mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */ - mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/ - mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/ - - mfsdr(SDR0_MFR, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(SDR0_MFR, mfr); - - mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); - - out32(GPIO0_OR, CONFIG_SYS_GPIO_OR); - out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR); - out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR); - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Katmai - AMCC 440SPe Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -u32 ddr_wrdtr(u32 default_val) { - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); -} - -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_90_DEG_ADV); -} - -#if defined(CONFIG_PCI) -int board_pcie_card_present(int port) -{ - u32 val; - - val = in32(GPIO0_IR); - switch (port) { - case 0: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0)); - case 1: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1)); - case 2: - return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2)); - default: - return 0; - } -} -#endif /* defined(CONFIG_PCI) */ - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig deleted file mode 100644 index 3f2f434..0000000 --- a/board/amcc/kilauea/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KILAUEA - -config SYS_BOARD - default "kilauea" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "kilauea" - -endif diff --git a/board/amcc/kilauea/MAINTAINERS b/board/amcc/kilauea/MAINTAINERS deleted file mode 100644 index 12bbcb1..0000000 --- a/board/amcc/kilauea/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KILAUEA BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/kilauea/ -F: include/configs/kilauea.h -F: configs/haleakala_defconfig -F: configs/kilauea_defconfig diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile deleted file mode 100644 index 754dadc..0000000 --- a/board/amcc/kilauea/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := kilauea.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o diff --git a/board/amcc/kilauea/chip_config.c b/board/amcc/kilauea/chip_config.c deleted file mode 100644 index 7e9dd3b..0000000 --- a/board/amcc/kilauea/chip_config.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "333-nor","NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", - { - 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { - 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", - { - 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", - { - 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/amcc/kilauea/config.mk b/board/amcc/kilauea/config.mk deleted file mode 100644 index 0dc15c1..0000000 --- a/board/amcc/kilauea/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2007-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c deleted file mode 100644 index 2937217..0000000 --- a/board/amcc/kilauea/kilauea.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/ppc405.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <linux/errno.h> - -#if defined(CONFIG_PCI) -#include <pci.h> -#include <asm/4xx_pcie.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static int board_cpld_version(void) -{ - u32 cpld; - - cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE); - if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) { - /* - * Magic not found -> "old" CPLD revision which needs - * the "old" EBC configuration - */ - mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) | - EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE | - EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) | - EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) | - EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) | - EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED | - EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - - /* - * Return 0 for "old" CPLD version - */ - return 0; - } - - /* - * Magic found -> "new" CPLD revision which needs no new - * EBC configuration - */ - return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8; -} - -/* - * Board early initialization function - */ -int board_early_init_f (void) -{ - u32 val; - - /*--------------------------------------------------------------------+ - | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. - +--------------------------------------------------------------------+ - +---------------------------------------------------------------------+ - |Interrupt| Source | Pol. | Sensi.| Crit. | - +---------+-----------------------------------+-------+-------+-------+ - | IRQ 00 | UART0 | High | Level | Non | - | IRQ 01 | UART1 | High | Level | Non | - | IRQ 02 | IIC0 | High | Level | Non | - | IRQ 03 | TBD | High | Level | Non | - | IRQ 04 | TBD | High | Level | Non | - | IRQ 05 | EBM | High | Level | Non | - | IRQ 06 | BGI | High | Level | Non | - | IRQ 07 | IIC1 | Rising| Edge | Non | - | IRQ 08 | SPI | High | Lvl/ed| Non | - | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | - | IRQ 10 | MAL TX EOB | High | Level | Non | - | IRQ 11 | MAL RX EOB | High | Level | Non | - | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | - | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | - | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | - | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | - | IRQ 16 | PCIE0 AL | high | Level | Non | - | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | - | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | - | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | - | IRQ 20 | PCIE0 TCR | High | Level | Non | - | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | - | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | - | IRQ 23 | Security EIP-94 | High | Level | Non | - | IRQ 24 | EMAC0 interrupt | High | Level | Non | - | IRQ 25 | EMAC1 interrupt | High | Level | Non | - | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | - | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | - | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | - | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | - | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | - | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | - |---------------------------------------------------------------------- - | IRQ 32 | MAL Serr | High | Level | Non | - | IRQ 33 | MAL Txde | High | Level | Non | - | IRQ 34 | MAL Rxde | High | Level | Non | - | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | - | IRQ 36 | PCIE0 DCR Error | High | Level | Non | - | IRQ 37 | EBC | High |Lvl Edg| Non | - | IRQ 38 | NDFC | High | Level | Non | - | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | - | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | - | IRQ 41 | PCIE1 AL | high | Level | Non | - | IRQ 42 | PCIE1 VPD access | rising| edge | Non | - | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | - | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | - | IRQ 45 | PCIE1 TCR | High | Level | Non | - | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | - | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | - | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | - | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | - | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | - | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | - | IRQ 55 | Serial ROM | High | Level | Non | - | IRQ 56 | GPT Decrement Pulse | High | Level | Non | - | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | - | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | - | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | - | IRQ 60 | EMAC0 Wake-up | High | Level | Non | - | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | - | IRQ 62 | EMAC1 Wake-up | High | Level | Non | - |---------------------------------------------------------------------- - | IRQ 64 | PE0 AL | High | Level | Non | - | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - | IRQ 68 | PE0 TCR | High | Level | Non | - | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - | IRQ 70 | PE0 DCR Error | High | Level | Non | - | IRQ 71 | Reserved | N/A | N/A | Non | - | IRQ 72 | PE1 AL | High | Level | Non | - | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - | IRQ 76 | PE1 TCR | High | Level | Non | - | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - | IRQ 78 | PE1 DCR Error | High | Level | Non | - | IRQ 79 | Reserved | N/A | N/A | Non | - | IRQ 80 | PE2 AL | High | Level | Non | - | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - | IRQ 84 | PE2 TCR | High | Level | Non | - | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - | IRQ 86 | PE2 DCR Error | High | Level | Non | - | IRQ 87 | Reserved | N/A | N/A | Non | - | IRQ 88 | External IRQ(5) | Progr | Progr | Non | - | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - | IRQ 94 | Reserved | N/A | N/A | Non | - | IRQ 95 | Reserved | N/A | N/A | Non | - |--------------------------------------------------------------------- - +---------+-----------------------------------+-------+-------+------*/ - /*--------------------------------------------------------------------+ - | Initialise UIC registers. Clear all interrupts. Disable all - | interrupts. - | Set critical interrupt values. Set interrupt polarities. Set - | interrupt trigger levels. Make bit 0 High priority. Clear all - | interrupts again. - +-------------------------------------------------------------------*/ - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ - /* Except cascade UIC0 and UIC1 */ - mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ - - /* - * Note: Some cores are still in reset when the chip starts, so - * take them out of reset - */ - mtsdr(SDR0_SRST, 0); - - /* Configure 405EX for NAND usage */ - val = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NRB_BUSY | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, val); - - /* - * Configure PFC (Pin Function Control) registers - * -> Enable USB - */ - val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; - mtsdr(SDR0_PFC1, val); - - /* - * The CPLD version detection has to be the first access to - * the CPLD, so we need to make this access this early and - * save the CPLD version for later. - */ - gd->board_type = board_cpld_version(); - - /* - * Configure FPGA register with PCIe reset - */ - out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ - mdelay(50); - out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ - - return 0; -} - -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); -#endif - - return 0; -} - -static int is_405exr(void) -{ - u32 pvr = get_pvr(); - - if (pvr & 0x00000004) - return 0; /* bit 2 set -> 405EX */ - - return 1; /* bit 2 cleared -> 405EXr */ -} - -int board_emac_count(void) -{ - /* - * 405EXr only has one EMAC interface, 405EX has two - */ - if (is_405exr()) - return 1; - else - return 2; -} - -/* - * Override the weak default implementation and return the - * last PCIe slot number (max number - 1). - */ -int board_pcie_last(void) -{ - /* - * 405EXr only has one EMAC interface, 405EX has two - */ - if (is_405exr()) - return 1 - 1; - else - return 2 - 1; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - if (is_405exr()) - printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); - else - printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - printf(" (CPLD rev. %ld)\n", gd->board_type); - - return (0); -} diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig deleted file mode 100644 index 3df90af..0000000 --- a/board/amcc/luan/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_LUAN - -config SYS_BOARD - default "luan" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "luan" - -endif diff --git a/board/amcc/luan/MAINTAINERS b/board/amcc/luan/MAINTAINERS deleted file mode 100644 index a23296d..0000000 --- a/board/amcc/luan/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -LUAN BOARD -M: John Otken <jotken@softadvances.com> -S: Maintained -F: board/amcc/luan/ -F: include/configs/luan.h -F: configs/luan_defconfig diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile deleted file mode 100644 index 345ad56..0000000 --- a/board/amcc/luan/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = luan.o flash.o -extra-y += init.o diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk deleted file mode 100644 index f18b097..0000000 --- a/board/amcc/luan/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h deleted file mode 100644 index 569d78c..0000000 --- a/board/amcc/luan/epld.h +++ /dev/null @@ -1,85 +0,0 @@ -#define EPLD0_FSEL_FB2 0x80 -#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */ -#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */ -#define EPLD0_RAW_CARD_BIT1 0x10 -#define EPLD0_RAW_CARD_BIT2 0x08 -#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */ -#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */ -#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */ - -#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */ -#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */ -#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */ -#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */ -#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */ -#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */ -#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */ -#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */ - -#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */ -#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */ -#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */ -#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */ -#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */ -#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */ -#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */ - -#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */ -#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */ -#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */ -#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */ - -#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */ -#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */ -#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */ -#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */ -#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */ -#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */ -#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */ -#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */ - -#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ -#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ -#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ -#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ -#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */ -#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */ -#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */ -#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */ - -#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */ -#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */ -#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */ -#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */ -#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */ -#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */ - -#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */ -#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */ -#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */ -#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */ -#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */ -#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */ -#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */ -#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */ - - -typedef struct { - unsigned char status; /* misc status */ - unsigned char clock; /* clock status, PCI-X clock control */ - unsigned char ethuart; /* Ethernet, UART status */ - unsigned char leds; /* LED register */ - unsigned char vth01; /* PCI0, PCI1 VTH register */ - unsigned char pciints; /* PCI0, PCI1 interrupts */ - unsigned char pci2; /* PCI2 interrupts, clock control */ - unsigned char vth2; /* PCI2 VTH register */ - unsigned char filler1[4096-8]; - unsigned char gpio00; /* GPIO bits 0-7 */ - unsigned char gpio08; /* GPIO bits 8-15 */ - unsigned char gpio16; /* GPIO bits 16-23 */ - unsigned char gpio24; /* GPIO bits 24-31 */ - unsigned char filler2[4096-4]; - unsigned char version; /* EPLD version */ -} epld_t; diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c deleted file mode 100644 index a242bef..0000000 --- a/board/amcc/luan/flash.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */ -}; - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - - /* read FPGA base register FPGA_REG0 */ - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) - flash_addr_table[index][i], - &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[2]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[2]); -#endif - - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S deleted file mode 100644 index 0f4a78e..0000000 --- a/board/amcc/luan/init.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G) - - tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG) - tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG) - tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG) - tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG) - tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - /* internal ram (l2 cache) */ - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I) - - /* peripherals at f0000000 */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG) - - /* PCI */ - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG) - tlbtab_end diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c deleted file mode 100644 index f98231a..0000000 --- a/board/amcc/luan/luan.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (C) Copyright 2005 - * John Otken, jotken@softadvances.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/ppc4xx-isram.h> -#include <spd_sdram.h> -#include "epld.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/************************************************************************* - * int board_early_init_f() - * - ************************************************************************/ -int board_early_init_f(void) -{ - u32 mfr; - - mtebc( PB0AP, 0x03800000 ); /* set chip selects */ - mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ - mtebc( PB1AP, 0x03800000 ); - mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ - mtebc( PB2AP, 0x03800000 ); - mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ - - mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */ - mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */ - mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */ - mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */ - mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */ - mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */ - mtdcr( UIC1SR, 0xffffffff ); - - mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */ - mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */ - mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */ - mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */ - mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */ - mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ - mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */ - mtdcr( UIC0SR, 0xffffffff ); - - mfsdr(SDR0_MFR, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(SDR0_MFR, mfr); - - return 0; -} - - -/************************************************************************* - * int misc_init_r() - * - ************************************************************************/ -int misc_init_r(void) -{ - volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE; - - /* set modes of operation */ - x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | - EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; - /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ - x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; - - /* put Ethernet+PHY in reset */ - x->ethuart &= ~EPLD2_RESET_ETH_N; - udelay(10000); - /* take Ethernet+PHY out of reset */ - x->ethuart |= EPLD2_RESET_ETH_N; - - return 0; -} - - -/************************************************************************* - * int checkboard() - * - ************************************************************************/ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Luan - AMCC PPC440SP Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_180_DEG_ADV); -} - -/************************************************************************* - * hw_watchdog_reset - * - * This routine is called to reset (keep alive) the watchdog timer - * - ************************************************************************/ -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ -} -#endif - - -/************************************************************************* - * int on_off() - * - ************************************************************************/ -static int on_off( const char *s ) -{ - if (strcmp(s, "on") == 0) { - return 1; - } else if (strcmp(s, "off") == 0) { - return 0; - } - return -1; -} - - -/************************************************************************* - * void l2cache_disable() - * - ************************************************************************/ -static void l2cache_disable(void) -{ - mtdcr( L2_CACHE_CFG, 0 ); -} - - -/************************************************************************* - * void l2cache_enable() - * - ************************************************************************/ -static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ -{ - mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ - - mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */ - - mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ - - while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ; /* poll L2_SR for completion */ - - mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ - - mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ - - mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */ - mtdcr( L2_CACHE_SNP1, 0 ); - - __asm__ volatile ("sync"); /* msync */ - - mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */ - - __asm__ volatile ("sync"); -} - - -/************************************************************************* - * int l2cache_status() - * - ************************************************************************/ -static int l2cache_status(void) -{ - return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0; -} - - -/************************************************************************* - * int do_l2cache() - * - ************************************************************************/ -int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ) -{ - switch (argc) { - case 2: /* on / off */ - switch (on_off(argv[1])) { - case 0: l2cache_disable(); - break; - case 1: l2cache_enable(); - break; - } - /* FALL TROUGH */ - case 1: /* get status */ - printf ("L2 Cache is %s\n", - l2cache_status() ? "ON" : "OFF"); - return 0; - default: - return cmd_usage(cmdtp); - } - - return 0; -} - - -U_BOOT_CMD( - l2cache, 2, 1, do_l2cache, - "enable or disable L2 cache", - "[on, off]\n" - " - enable or disable L2 cache" -); diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig deleted file mode 100644 index 31ce5f1..0000000 --- a/board/amcc/makalu/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MAKALU - -config SYS_BOARD - default "makalu" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "makalu" - -endif diff --git a/board/amcc/makalu/MAINTAINERS b/board/amcc/makalu/MAINTAINERS deleted file mode 100644 index ecd5e19..0000000 --- a/board/amcc/makalu/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MAKALU BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/makalu/ -F: include/configs/makalu.h -F: configs/makalu_defconfig diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile deleted file mode 100644 index dcf162c..0000000 --- a/board/amcc/makalu/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = makalu.o cmd_pll.o -obj-y += init.o diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c deleted file mode 100644 index f12655b..0000000 --- a/board/amcc/makalu/cmd_pll.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * ehnus: change pll frequency. - * Wed Sep 5 11:45:17 CST 2007 - * hsun@udtech.com.cn - */ - - -#include <common.h> -#include <config.h> -#include <command.h> -#include <i2c.h> - -#ifdef CONFIG_CMD_EEPROM - -#define EEPROM_CONF_OFFSET 0 -#define EEPROM_TEST_OFFSET 16 -#define EEPROM_SDSTP_PARAM 16 - -#define PLL_NAME_MAX 12 -#define BUF_STEP 8 - -/* eeprom_wirtes 8Byte per op. */ -#define EEPROM_ALTER_FREQ(freq) \ - do { \ - int __i; \ - for (__i = 0; __i < 2; __i++) \ - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \ - EEPROM_CONF_OFFSET + __i*BUF_STEP, \ - pll_select[freq], \ - BUF_STEP + __i*BUF_STEP); \ - } while (0) - -#define PDEBUG -#ifdef PDEBUG -#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET) -#else -#define PLL_DEBUG -#endif - -typedef enum { - PLL_ebc20, - PLL_333, - PLL_4001, - PLL_4002, - PLL_533, - PLL_600, - PLL_666, /* For now, kilauea can't support */ - RCONF, - WTEST, - PLL_TOTAL -} pll_freq_t; - -static const char -pll_name[][PLL_NAME_MAX] = { - "PLL_ebc20", - "PLL_333", - "PLL_400@1", - "PLL_400@2", - "PLL_533", - "PLL_600", - "PLL_666", - "RCONF", - "WTEST", - "" -}; - -/* - * ehnus: - */ -static uchar -pll_select[][EEPROM_SDSTP_PARAM] = { - /* 0: CPU 333MHz EBC 20MHz, for test only */ - { - 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 0: 333 */ - { - 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 1: 400_266 */ - { - 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 2: 400 */ - { - 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 3: 533 */ - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 4: 600 */ - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - /* 5: 666 */ - { - 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - }, - - {} -}; - -static uchar -testbuf[EEPROM_SDSTP_PARAM] = { - 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, - 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff -}; - -static void -pll_debug(int off) -{ - int i; - uchar buffer[EEPROM_SDSTP_PARAM]; - - memset(buffer, 0, sizeof(buffer)); - eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, - buffer, EEPROM_SDSTP_PARAM); - - printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); - for (i = 0; i < EEPROM_SDSTP_PARAM; i++) - printf("%02x ", buffer[i]); - printf("\n"); -} - -static void -test_write(void) -{ - printf("Debug: test eeprom_write ... "); - - /* - * Write twice, 8 bytes per write - */ - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, - testbuf, 8); - eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, - testbuf, 16); - printf("done\n"); - - pll_debug(EEPROM_TEST_OFFSET); -} - -int -do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char c = '\0'; - pll_freq_t pll_freq; - - if (argc < 2) - return cmd_usage(cmdtp); - - for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) { - if (!strcmp(pll_name[pll_freq], argv[1])) - break; - } - - switch (pll_freq) { - case PLL_ebc20: - case PLL_333: - case PLL_4001: - case PLL_4002: - case PLL_533: - case PLL_600: - EEPROM_ALTER_FREQ(pll_freq); - break; - - case PLL_666: /* not support */ - printf("Choose this option will result in a boot failure." - "\nContinue? (Y/N): "); - - c = getc(); putc('\n'); - - if ((c == 'y') || (c == 'Y')) { - EEPROM_ALTER_FREQ(pll_freq); - break; - } - goto ret; - - case RCONF: - pll_debug(EEPROM_CONF_OFFSET); - goto ret; - case WTEST: - printf("DEBUG: write test\n"); - test_write(); - goto ret; - - default: - printf("Invalid options\n\n"); - return cmd_usage(cmdtp); - } - - printf("PLL set to %s, " - "reset the board to take effect\n", pll_name[pll_freq]); - - PLL_DEBUG; -ret: - return 0; -} - -U_BOOT_CMD( - pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter, - "change pll frequence", - "pllalter <selection> - change pll frequence \n\n\ - ** New freq take effect after reset. ** \n\ - ----------------------------------------------\n\ - PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\ - \t Same as PLL_333 \n\ - \t except \n\ - \t EBC: 20 MHz \n\ - ----------------------------------------------\n\ - PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 666 MHz \n\ - \t CPU: 333 MHz \n\ - \t PLB: 166 MHz \n\ - \t OPB: 83 MHz \n\ - \t DDR: 83 MHz \n\ - ------------------------------------------------\n\ - PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 800 MHz \n\ - \t CPU: 400 MHz \n\ - \t PLB: 133 MHz \n\ - \t OPB: 66 MHz \n\ - \t DDR: 133 MHz \n\ - ------------------------------------------------\n\ - PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 800 MHz \n\ - \t CPU: 400 MHz \n\ - \t PLB: 200 MHz \n\ - \t OPB: 100 MHz \n\ - \t DDR: 200 MHz \n\ - ----------------------------------------------\n\ - PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 1066 MHz \n\ - \t CPU: 533 MHz \n\ - \t PLB: 177 MHz \n\ - \t OPB: 88 MHz \n\ - \t DDR: 177 MHz \n\ - ----------------------------------------------\n\ - PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 1200 MHz \n\ - \t CPU: 600 MHz \n\ - \t PLB: 200 MHz \n\ - \t OPB: 100 MHz \n\ - \t DDR: 200 MHz \n\ - ----------------------------------------------\n\ - PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\ - \t VCO: 1333 MHz \n\ - \t CPU: 666 MHz \n\ - \t PLB: 166 MHz \n\ - \t OPB: 83 MHz \n\ - \t DDR: 166 MHz \n\ - -----------------------------------------------\n\ - RCONF: Read current eeprom configuration. \n\ - -----------------------------------------------\n\ - WTEST: Test EEPROM write with predefined values\n\ - -----------------------------------------------" -); - -#endif /* CONFIG_CMD_EEPROM */ diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S deleted file mode 100644 index e15c622..0000000 --- a/board/amcc/makalu/init.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson <gerickson@nuovations.com> - * - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Originally based on code provided from Senao and AMCC - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - blr diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c deleted file mode 100644 index 2194942..0000000 --- a/board/amcc/makalu/makalu.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/ppc405.h> -#include <libfdt.h> -#include <asm/processor.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/io.h> -#include <fdt_support.h> -#include <linux/errno.h> - -#if defined(CONFIG_PCI) -#include <pci.h> -#include <asm/4xx_pcie.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Board early initialization function - */ -int board_early_init_f (void) -{ - u32 val; - - /*--------------------------------------------------------------------+ - | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. - +--------------------------------------------------------------------+ - +---------------------------------------------------------------------+ - |Interrupt| Source | Pol. | Sensi.| Crit. | - +---------+-----------------------------------+-------+-------+-------+ - | IRQ 00 | UART0 | High | Level | Non | - | IRQ 01 | UART1 | High | Level | Non | - | IRQ 02 | IIC0 | High | Level | Non | - | IRQ 03 | TBD | High | Level | Non | - | IRQ 04 | TBD | High | Level | Non | - | IRQ 05 | EBM | High | Level | Non | - | IRQ 06 | BGI | High | Level | Non | - | IRQ 07 | IIC1 | Rising| Edge | Non | - | IRQ 08 | SPI | High | Lvl/ed| Non | - | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | - | IRQ 10 | MAL TX EOB | High | Level | Non | - | IRQ 11 | MAL RX EOB | High | Level | Non | - | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | - | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | - | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | - | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | - | IRQ 16 | PCIE0 AL | high | Level | Non | - | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | - | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | - | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | - | IRQ 20 | PCIE0 TCR | High | Level | Non | - | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | - | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | - | IRQ 23 | Security EIP-94 | High | Level | Non | - | IRQ 24 | EMAC0 interrupt | High | Level | Non | - | IRQ 25 | EMAC1 interrupt | High | Level | Non | - | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | - | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | - | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | - | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | - | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | - | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | - |---------------------------------------------------------------------- - | IRQ 32 | MAL Serr | High | Level | Non | - | IRQ 33 | MAL Txde | High | Level | Non | - | IRQ 34 | MAL Rxde | High | Level | Non | - | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | - | IRQ 36 | PCIE0 DCR Error | High | Level | Non | - | IRQ 37 | EBC | High |Lvl Edg| Non | - | IRQ 38 | NDFC | High | Level | Non | - | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | - | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | - | IRQ 41 | PCIE1 AL | high | Level | Non | - | IRQ 42 | PCIE1 VPD access | rising| edge | Non | - | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | - | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | - | IRQ 45 | PCIE1 TCR | High | Level | Non | - | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | - | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | - | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | - | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | - | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | - | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | - | IRQ 55 | Serial ROM | High | Level | Non | - | IRQ 56 | GPT Decrement Pulse | High | Level | Non | - | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | - | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | - | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | - | IRQ 60 | EMAC0 Wake-up | High | Level | Non | - | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | - | IRQ 62 | EMAC1 Wake-up | High | Level | Non | - |---------------------------------------------------------------------- - | IRQ 64 | PE0 AL | High | Level | Non | - | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - | IRQ 68 | PE0 TCR | High | Level | Non | - | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - | IRQ 70 | PE0 DCR Error | High | Level | Non | - | IRQ 71 | Reserved | N/A | N/A | Non | - | IRQ 72 | PE1 AL | High | Level | Non | - | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - | IRQ 76 | PE1 TCR | High | Level | Non | - | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - | IRQ 78 | PE1 DCR Error | High | Level | Non | - | IRQ 79 | Reserved | N/A | N/A | Non | - | IRQ 80 | PE2 AL | High | Level | Non | - | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - | IRQ 84 | PE2 TCR | High | Level | Non | - | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - | IRQ 86 | PE2 DCR Error | High | Level | Non | - | IRQ 87 | Reserved | N/A | N/A | Non | - | IRQ 88 | External IRQ(5) | Progr | Progr | Non | - | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - | IRQ 94 | Reserved | N/A | N/A | Non | - | IRQ 95 | Reserved | N/A | N/A | Non | - |--------------------------------------------------------------------- - +---------+-----------------------------------+-------+-------+------*/ - /*--------------------------------------------------------------------+ - | Initialise UIC registers. Clear all interrupts. Disable all - | interrupts. - | Set critical interrupt values. Set interrupt polarities. Set - | interrupt trigger levels. Make bit 0 High priority. Clear all - | interrupts again. - +-------------------------------------------------------------------*/ - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ - /* Except cascade UIC0 and UIC1 */ - mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ - - /* - * Note: Some cores are still in reset when the chip starts, so - * take them out of reset - */ - mtsdr(SDR0_SRST, 0); - - /* Reset PCIe slots */ - gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0); - udelay(100); - gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1); - - /* - * Configure PFC (Pin Function Control) registers - * -> Enable USB - */ - val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; - mtsdr(SDR0_PFC1, val); - - return 0; -} - -int misc_init_r(void) -{ -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); -#endif - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Makalu - AMCC PPC405EX Evaluation Board"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig deleted file mode 100644 index d710590..0000000 --- a/board/amcc/redwood/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_REDWOOD - -config SYS_BOARD - default "redwood" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "redwood" - -endif diff --git a/board/amcc/redwood/MAINTAINERS b/board/amcc/redwood/MAINTAINERS deleted file mode 100644 index 756b301..0000000 --- a/board/amcc/redwood/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -REDWOOD BOARD -M: Feng Kan <fkan@amcc.com> -S: Maintained -F: board/amcc/redwood/ -F: include/configs/redwood.h -F: configs/redwood_defconfig diff --git a/board/amcc/redwood/Makefile b/board/amcc/redwood/Makefile deleted file mode 100644 index 2bc632b..0000000 --- a/board/amcc/redwood/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2008 -# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = redwood.o -extra-y += init.o diff --git a/board/amcc/redwood/config.mk b/board/amcc/redwood/config.mk deleted file mode 100644 index 42b3e5f..0000000 --- a/board/amcc/redwood/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2008 -# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 460SX Reference Platform (redwood) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S deleted file mode 100644 index fd05130..0000000 --- a/board/amcc/redwood/init.S +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2008 - * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - /* Although 512 KB, map 256k at a time */ - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I) - - tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) - - /* - * Peripheral base - */ - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG) - tlbtab_end diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c deleted file mode 100644 index 15c3884..0000000 --- a/board/amcc/redwood/redwood.c +++ /dev/null @@ -1,440 +0,0 @@ -/* - * This is the main board level file for the Redwood AMCC board. - * - * (C) Copyright 2008 - * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include "redwood.h" -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <i2c.h> -#include <asm/io.h> - -int compare_to_true(char *str); -char *remove_l_w_space(char *in_str); -char *remove_t_w_space(char *in_str); -int get_console_port(void); - -static void early_init_EBC(void); -static int bootdevice_selected(void); -static void early_reinit_EBC(int); -static void early_init_UIC(void); - -/* - * Define Boot devices - */ -#define BOOT_FROM_8BIT_SRAM 0x00 -#define BOOT_FROM_16BIT_SRAM 0x01 -#define BOOT_FROM_32BIT_SRAM 0x02 -#define BOOT_FROM_8BIT_NAND 0x03 -#define BOOT_FROM_16BIT_NOR 0x04 -#define BOOT_DEVICE_UNKNOWN 0xff - -/* - * EBC Devices Characteristics - * Peripheral Bank Access Parameters - EBC_BxAP - * Peripheral Bank Configuration Register - EBC_BxCR - */ - -/* - * 8 bit width SRAM - * BU Value - * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 - * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 - */ -#define EBC_BXAP_8BIT_SRAM \ - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM -#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM - -/* - * NAND flash - * BU Value - * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 - * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 -*/ -#define EBC_BXAP_NAND \ - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -/* - * NOR flash - * BU Value - * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 - * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 -*/ -#define EBC_BXAP_NOR \ - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -/* - * FPGA - * BU value : - * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 - * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 - */ -#define EBC_BXAP_FPGA \ - EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \ - EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \ - EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \ - EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXCR_8BIT_SRAM_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT - -#define EBC_BXCR_32BIT_SRAM_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT - -#define EBC_BXCR_NAND_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT - -#define EBC_BXCR_16BIT_SRAM_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -#define EBC_BXCR_NOR_CS0 \ - EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -#define EBC_BXCR_NOR_CS1 \ - EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -#define EBC_BXCR_NAND_CS1 \ - EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT - -#define EBC_BXCR_NAND_CS2 \ - EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT - -#define EBC_BXCR_SRAM_CS2 \ - EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT - -#define EBC_BXCR_LARGE_FLASH_CS2 \ - EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -#define EBC_BXCR_FPGA_CS3 \ - EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT - -/***************************************************************************** - * UBOOT initiated board specific function calls - ****************************************************************************/ - -int board_early_init_f(void) -{ - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - - /* - * Initialise EBC - */ - early_init_EBC(); - - /* - * Determine which boot device was selected - */ - computed_boot_device = bootdevice_selected(); - - /* - * Reinit EBC based on selected boot device - */ - early_reinit_EBC(computed_boot_device); - - /* - * Setup for UIC on 460SX redwood board - */ - early_init_UIC(); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Redwood - AMCC 460SX Reference Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -static void early_init_EBC(void) -{ - /* - * Initialize EBC CONFIG - - * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC - * default value : - * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 - */ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_16PERCLK | - EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | - EBC_CFG_OEO_PREVIOUS | - EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16); - - /* - * PART 1 : Initialize EBC Bank 3 - * ============================== - * Bank1 is always associated to the EPLD. - * It has to be initialized prior to other banks settings computation - * since some board registers values may be needed to determine the - * boot type - */ - mtebc(PB1AP, EBC_BXAP_FPGA); - mtebc(PB1CR, EBC_BXCR_FPGA_CS3); - -} - -static int bootdevice_selected(void) -{ - unsigned long sdr0_pinstp; - unsigned long bootstrap_settings; - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - - /* - * Determine which boot device was selected - * ================================================= - * - * Read Pin Strap Register in PPC460SX - * Result can either be : - * - Boot strap = boot from EBC 8bits => Small Flash - * - Boot strap = boot from PCI - * - Boot strap = IIC - * In case of boot from IIC, read Serial Device Strap Register1 - * - * Result can either be : - * - Boot from EBC - EBC Bus Width = 8bits => Small Flash - * - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM - * - Boot from PCI - */ - - /* Read Pin Strap Register in PPC460SX */ - mfsdr(SDR0_PINSTP, sdr0_pinstp); - bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK; - - switch (bootstrap_settings) { - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: - /* - * Boot from SRAM, 8bit width - */ - computed_boot_device = BOOT_FROM_8BIT_SRAM; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: - /* - * Boot from SRAM, 32bit width - */ - computed_boot_device = BOOT_FROM_32BIT_SRAM; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: - /* - * Boot from NAND, 8bit width - */ - computed_boot_device = BOOT_FROM_8BIT_NAND; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: - /* - * Boot from SRAM, 16bit width - * Boot setting in IIC EEPROM 0x50 - */ - computed_boot_device = BOOT_FROM_16BIT_SRAM; - break; - case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5: - /* - * Boot from NOR, 16bit width - * Boot setting in IIC EEPROM 0x54 - */ - computed_boot_device = BOOT_FROM_16BIT_NOR; - break; - default: - /* should not be */ - computed_boot_device = BOOT_DEVICE_UNKNOWN; - break; - } - - return computed_boot_device; -} - -static void early_reinit_EBC(int computed_boot_device) -{ - /* - * Compute EBC settings depending on selected boot device - * ====================================================== - * - * Resulting EBC init will be among following configurations : - * - * - Boot from EBC 8bits => boot from Small Flash selected - * EBC-CS0 = Small Flash - * EBC-CS2 = Large Flash and SRAM - * - * - Boot from EBC 16bits => boot from Large Flash or SRAM - * EBC-CS0 = Large Flash or SRAM - * EBC-CS2 = Small Flash - * - * - Boot from PCI - * EBC-CS0 = not initialized to avoid address contention - * EBC-CS2 = same as boot from Small Flash selected - */ - - unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; - unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0; - unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; - - switch (computed_boot_device) { - /*-------------------------------------------------------------------*/ - case BOOT_FROM_8BIT_SRAM: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM; - ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NOR; - ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_NAND; - ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_16BIT_SRAM: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM; - ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NOR; - ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_NAND; - ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_32BIT_SRAM: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM; - ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NOR; - ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_NAND; - ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_16BIT_NOR: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_NOR; - ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NAND; - ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM; - ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_8BIT_NAND: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_NAND; - ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0; - ebc0_cs1_bxap_value = EBC_BXAP_NOR; - ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; - ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM; - ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2; - break; - - /*-------------------------------------------------------------------*/ - default: - /*-------------------------------------------------------------------*/ - /* BOOT_DEVICE_UNKNOWN */ - break; - } - - mtebc(PB0AP, ebc0_cs0_bxap_value); - mtebc(PB0CR, ebc0_cs0_bxcr_value); - mtebc(PB1AP, ebc0_cs1_bxap_value); - mtebc(PB1CR, ebc0_cs1_bxcr_value); - mtebc(PB2AP, ebc0_cs2_bxap_value); - mtebc(PB2CR, ebc0_cs2_bxcr_value); -} - -static void early_init_UIC(void) -{ - /* - * Initialise UIC registers. Clear all interrupts. Disable all - * interrupts. - * Set critical interrupt values. Set interrupt polarities. Set - * interrupt trigger levels. Make bit 0 High priority. Clear all - * interrupts again. - */ - mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted - * cascade to be checked */ - mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical - * interrupts */ - mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ - -} diff --git a/board/amcc/redwood/redwood.h b/board/amcc/redwood/redwood.h deleted file mode 100644 index 9c36073..0000000 --- a/board/amcc/redwood/redwood.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __REDWOOD_H_ -#define __REDWOOD_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------------------------+ -| Defines -+----------------------------------------------------------------------------*/ -/* Pin Straps Reg */ -#define SDR0_PSTRP0 0x0040 -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ - -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ - -#ifdef __cplusplus -} -#endif -#endif /* __REDWOOD_H_ */ diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig deleted file mode 100644 index 67ee3ca..0000000 --- a/board/amcc/sequoia/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_SEQUOIA - -config SYS_BOARD - default "sequoia" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "sequoia" - -endif diff --git a/board/amcc/sequoia/MAINTAINERS b/board/amcc/sequoia/MAINTAINERS deleted file mode 100644 index 6c28a37..0000000 --- a/board/amcc/sequoia/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -SEQUOIA BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/sequoia/ -F: include/configs/sequoia.h -F: configs/rainier_defconfig -F: configs/rainier_ramboot_defconfig -F: configs/sequoia_defconfig -F: configs/sequoia_ramboot_defconfig diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile deleted file mode 100644 index b4ab5da..0000000 --- a/board/amcc/sequoia/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = sequoia.o sdram.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/amcc/sequoia/chip_config.c b/board/amcc/sequoia/chip_config.c deleted file mode 100644 index eef9316..0000000 --- a/board/amcc/sequoia/chip_config.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66", - { - 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { - 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53", - { - 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55", - { - 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55", - { - 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55", - { - 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66", - { - 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66", - { - 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55", - { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55", - { - 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk deleted file mode 100644 index 824e78f..0000000 --- a/board/amcc/sequoia/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2002-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EPx Reference Platform (Sequoia) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S deleted file mode 100644 index f876639..0000000 --- a/board/amcc/sequoia/init.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - */ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* vxWorks needs this as first entry for the Machine Check interrupt */ - tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) - - /* - * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This - * entry is already configured for SDRAM via the JTAG debugger and mustn't - * be re-initialized by this RAM-booting U-Boot version. - */ -#ifndef CONFIG_SYS_RAMBOOT - /* TLB-entry for DDR SDRAM (Up to 2GB) */ -#ifdef CONFIG_4xx_DCACHE - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G) -#else - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) -#endif -#endif /* CONFIG_SYS_RAMBOOT */ - - /* TLB-entry for EBC */ - tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG ) - - /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) - - /* TLB-entry for NAND */ - tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) - - /* TLB-entry for Internal Registers & OCM */ - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) - - /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - /* TLB-entry PCI IO Space - from sr@denx.de */ - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) - - tlbtab_end diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c deleted file mode 100644 index ea98717..0000000 --- a/board/amcc/sequoia/sdram.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debug output */ -#undef DEBUG - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc440.h> - -DECLARE_GLOBAL_DATA_PTR; - -/*-----------------------------------------------------------------------------+ - * Prototypes - *-----------------------------------------------------------------------------*/ -extern int denali_wait_for_dlllock(void); -extern void denali_core_search_data_eye(void); - -/************************************************************************* - * - * dram_init -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -int dram_init(void) -{ -#if !defined(CONFIG_SYS_RAMBOOT) - ulong speed = get_bus_freq(0); - - mtsdram(DDR0_02, 0x00000000); - - mtsdram(DDR0_00, 0x0000190A); - mtsdram(DDR0_01, 0x01000000); - mtsdram(DDR0_03, 0x02030602); - mtsdram(DDR0_04, 0x0A020200); - mtsdram(DDR0_05, 0x02020308); - mtsdram(DDR0_06, 0x0102C812); - mtsdram(DDR0_07, 0x000D0100); - mtsdram(DDR0_08, 0x02430001); - mtsdram(DDR0_09, 0x00011D5F); - mtsdram(DDR0_10, 0x00000100); - mtsdram(DDR0_11, 0x0027C800); - mtsdram(DDR0_12, 0x00000003); - mtsdram(DDR0_14, 0x00000000); - mtsdram(DDR0_17, 0x19000000); - mtsdram(DDR0_18, 0x19191919); - mtsdram(DDR0_19, 0x19191919); - mtsdram(DDR0_20, 0x0B0B0B0B); - mtsdram(DDR0_21, 0x0B0B0B0B); - mtsdram(DDR0_22, 0x00267F0B); - mtsdram(DDR0_23, 0x00000000); - mtsdram(DDR0_24, 0x01010002); - if (speed > 133333334) - mtsdram(DDR0_26, 0x5B26050C); - else - mtsdram(DDR0_26, 0x5B260408); - mtsdram(DDR0_27, 0x0000682B); - mtsdram(DDR0_28, 0x00000000); - mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000006); - mtsdram(DDR0_43, 0x030A0200); - mtsdram(DDR0_44, 0x00000003); - mtsdram(DDR0_02, 0x00000001); - - denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_SYS_RAMBOOT */ - -#ifdef CONFIG_DDR_DATA_EYE - /* -----------------------------------------------------------+ - * Perform data eye search if requested. - * ----------------------------------------------------------*/ - denali_core_search_data_eye(); -#endif - - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20; - - return 0; -} diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c deleted file mode 100644 index 1e45774..0000000 --- a/board/amcc/sequoia/sequoia.c +++ /dev/null @@ -1,413 +0,0 @@ -/* - * (C) Copyright 2006-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <errno.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/ppc4xx.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/bitops.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_MTD_NOR_FLASH) -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#endif - -extern void __ft_board_setup(void *blob, bd_t *bd); -ulong flash_get_size(ulong base, int banknum); - -static inline u32 get_async_pci_freq(void) -{ - if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & - CONFIG_SYS_BCSR5_PCI66EN) - return 66666666; - else - return 33333333; -} - -int board_early_init_f(void) -{ - u32 sdr0_cust0; - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; - - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, 0xb8400000); - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* Check and reconfigure the PCI sync clock if necessary */ - ppc4xx_pci_sync_clock_config(get_async_pci_freq()); - - /* 50MHz tmrclk */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); - - /* clear write protects */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00); - - /* enable Ethernet */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00); - - /* enable USB device */ - out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20); - - /* select Ethernet (and optionally IIC1) pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_4; -#ifdef CONFIG_I2C_MULTI_BUS - sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); -#endif - /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS; - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS; - - mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_4; - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* PCI arbiter enabled */ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); - - /* setup NAND FLASH */ - mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); - - return 0; -} - -int misc_init_r(void) -{ -#if defined(CONFIG_MTD_NOR_FLASH) - uint pbcr; - int size_val = 0; -#endif -#ifdef CONFIG_440EPX - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; - char *act = getenv("usbact"); -#endif - u32 reg; - -#if defined(CONFIG_MTD_NOR_FLASH) - /* Re-do flash sizing to get full correct info */ - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - -#if defined(CONFIG_SYS_RAMBOOT) - mtdcr(EBC0_CFGADDR, PB3CR); -#else - mtdcr(EBC0_CFGADDR, PB0CR); -#endif - pbcr = mfdcr(EBC0_CFGDATA); - size_val = ffs(gd->bd->bi_flashsize) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_SYS_RAMBOOT) - mtdcr(EBC0_CFGADDR, PB3CR); -#else - mtdcr(EBC0_CFGADDR, PB0CR); -#endif - mtdcr(EBC0_CFGDATA, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif -#endif /* CONFIG_MTD_NOR_FLASH */ - - /* - * USB suff... - */ -#ifdef CONFIG_440EPX - if (act == NULL || strcmp(act, "hostdev") == 0) { - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - - /* - * An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; - - /* - * To enable the USB 2.0 Device function - * through the UTMI interface - */ - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /*clear resets*/ - udelay (1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Host(int phy) Device(ext phy)\n"); - - } else if (strcmp(act, "dev") == 0) { - /*-------------------PATCH-------------------------------*/ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x672c6000); - - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000080); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60206000); - - *(unsigned int *)(0xe0000350) = 0x00000001; - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60306000); - /*-------------------PATCH-------------------------------*/ - - /* SDR Setting */ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_PFC1, sdr0_pfc1); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; - - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; - - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; - - mtsdr(SDR0_USB2H0CR, usb2h0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* clear resets */ - udelay (1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Device(int phy)\n"); - } -#endif /* CONFIG_440EPX */ - - mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ - reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); - mtsdr(SDR0_SRST1, reg); - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 rev; - u32 clock = get_async_pci_freq(); - -#ifdef CONFIG_440EPX - printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); -#else - printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); -#endif - - rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - /* - * Reconfiguration of the PCI sync clock is already done, - * now check again if everything is in range: - */ - if (ppc4xx_pci_sync_clock_config(clock)) { - printf("ERROR: PCI clocking incorrect (async=%d " - "sync=%ld)!\n", clock, get_PCI_freq()); - } - - return (0); -} - -#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) -/* - * Assign interrupts to PCI devices. - */ -void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); -} -#endif - -#if defined(CONFIG_SYS_RAMBOOT) -/* - * On NAND-booting sequoia, we need to patch the chips select numbers - * in the dtb (CS0 - NAND, CS3 - NOR) - */ -int ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - int len; - int nodeoffset; - struct fdt_property *prop; - u32 *reg; - char path[32]; - - /* First do common fdt setup */ - __ft_board_setup(blob, bd); - - /* And now configure NOR chip select to 3 instead of 0 */ - strcpy(path, "/plb/opb/ebc/nor_flash@0,0"); - nodeoffset = fdt_path_offset(blob, path); - prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); - if (prop == NULL) { - printf("Unable to update NOR chip select for NAND booting\n"); - return -FDT_ERR_NOTFOUND; - } - reg = (u32 *)&prop->data[0]; - reg[0] = 3; - rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); - if (rc) { - printf("Unable to update property NOR mappings\n"); - return rc; - } - - /* And now configure NAND chip select to 0 instead of 3 */ - strcpy(path, "/plb/opb/ebc/ndfc@3,0"); - nodeoffset = fdt_path_offset(blob, path); - prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); - if (prop == NULL) { - printf("Unable to update NDFC chip select for NAND booting\n"); - return len; - } - reg = (u32 *)&prop->data[0]; - reg[0] = 0; - rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); - if (rc) { - printf("Unable to update property NDFC mapping\n"); - return rc; - } - - return 0; -} -#endif /* CONFIG_SYS_RAMBOOT */ diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds deleted file mode 100644 index ef08be8..0000000 --- a/board/amcc/sequoia/u-boot-ram.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/ppc4xx/start.o (.text*) - board/amcc/sequoia/init.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - KEEP(*(.got)) - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig deleted file mode 100644 index 94e3dc9..0000000 --- a/board/amcc/walnut/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_WALNUT - -config SYS_BOARD - default "walnut" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "walnut" - -endif diff --git a/board/amcc/walnut/MAINTAINERS b/board/amcc/walnut/MAINTAINERS deleted file mode 100644 index 2a98c85..0000000 --- a/board/amcc/walnut/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -WALNUT BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/walnut/ -F: include/configs/walnut.h -F: configs/sycamore_defconfig -F: configs/walnut_defconfig diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile deleted file mode 100644 index 9228170..0000000 --- a/board/amcc/walnut/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = walnut.o flash.o diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c deleted file mode 100644 index cc0f425..0000000 --- a/board/amcc/walnut/flash.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -/* - * include common flash code (for amcc boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); - -unsigned long flash_init(void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = - flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#ifdef CONFIG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - size_b1 = 0; - flash_info[0].size = size_b0; - } else { - /* 2 banks */ - size_b1 = - flash_get_size((vu_long *) FLASH_BASE1_PRELIM, - &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b1 = -size_b1; - pbcr = - (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr(EBC0_CFGADDR, PB1CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB1CR); - base_b0 = base_b1 - size_b0; - pbcr = - (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB0CR = %x\n", pbcr); */ - } - - size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets(base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets(base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b1 + size_b1 - - monitor_flash_len, - base_b1 + size_b1 - 1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - - monitor_flash_len, - base_b0 + size_b0 - 1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - } /* else 2 banks */ - return (size_b0 + size_b1); -} - - -static void flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c deleted file mode 100644 index b21daa0..0000000 --- a/board/amcc/walnut/walnut.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <spd_sdram.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut/Sycamore board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* set UART1 control to select CTS/RTS */ -#define FPGA_BRDC 0xF0300004 - *(volatile char *)(FPGA_BRDC) |= 0x1; - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - uint pvr = get_pvr(); - - if (pvr == PVR_405GPR_RB) { - puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); - } else { - puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); - } - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -/* - * dram_init() reads EEPROM via I2c. EEPROM contains all of - * the necessary info for SDRAM controller configuration - */ -int dram_init(void) -{ - gd->ram_size = spd_sdram(); - - return 0; -} diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig deleted file mode 100644 index dfa1068..0000000 --- a/board/amcc/yosemite/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_YOSEMITE - -config SYS_BOARD - default "yosemite" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "yosemite" - -endif diff --git a/board/amcc/yosemite/MAINTAINERS b/board/amcc/yosemite/MAINTAINERS deleted file mode 100644 index 3f553e1..0000000 --- a/board/amcc/yosemite/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -YOSEMITE BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/amcc/yosemite/ -F: include/configs/yosemite.h -F: configs/yellowstone_defconfig -F: configs/yosemite_defconfig diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile deleted file mode 100644 index daf020a..0000000 --- a/board/amcc/yosemite/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = yosemite.o -extra-y += init.o diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk deleted file mode 100644 index f18b097..0000000 --- a/board/amcc/yosemite/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S deleted file mode 100644 index 529cc65..0000000 --- a/board/amcc/yosemite/init.S +++ /dev/null @@ -1,49 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) - - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I ) - - /* PCI */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG ) - - /* USB 2.0 Device */ - tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG ) - - tlbtab_end diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c deleted file mode 100644 index f46aacf..0000000 --- a/board/amcc/yosemite/yosemite.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <spd_sdram.h> -#include <libfdt.h> -#include <fdt_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static inline u32 get_async_pci_freq(void) -{ - if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & - CONFIG_SYS_BCSR5_PCI66EN) - return 66666666; - else - return 33333333; -} - -int board_early_init_f(void) -{ - register uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - reg = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - - /*-------------------------------------------------------------------- - * Setup the GPIO pins - *-------------------------------------------------------------------*/ - /*CPLD cs */ - /*setup Address lines for flash size 64Meg. */ - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000); - - /*setup emac */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); - out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); - - /*UART1 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); - out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); - - /* external interrupts IRQ0...3 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); - out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00); - out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); - -#ifdef CONFIG_440EP - /*setup USB 2.0 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); - out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); -#endif - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - /*-------------------------------------------------------------------- - * Setup other serial configuration - *-------------------------------------------------------------------*/ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ - mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ - - /* Check and reconfigure the PCI sync clock if necessary */ - ppc4xx_pci_sync_clock_config(get_async_pci_freq()); - - /*clear tmrclk divisor */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00; - - /*enable ethernet */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0; - -#ifdef CONFIG_440EP - /*enable usb 1.1 fs device and remove usb 2.0 reset */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00; -#endif - - /*get rid of flash write protect */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00; - - return 0; -} - -int misc_init_r (void) -{ - uint pbcr; - int size_val = 0; - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, pbcr); - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 rev; - u32 clock = get_async_pci_freq(); - -#ifdef CONFIG_440EP - printf("Board: Yosemite - AMCC PPC440EP Evaluation Board"); -#else - printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); -#endif - - rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); - printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - /* - * Reconfiguration of the PCI sync clock is already done, - * now check again if everything is in range: - */ - if (ppc4xx_pci_sync_clock_config(clock)) { - printf("ERROR: PCI clocking incorrect (async=%d " - "sync=%ld)!\n", clock, get_PCI_freq()); - } - - return (0); -} - -/************************************************************************* - * dram_init -- doesn't use serial presence detect. - * - * Assumes: 256 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -#define NUM_TRIES 64 -#define NUM_READS 10 - -void sdram_tr1_set(int ram_address, int* tr1_value) -{ - int i; - int j, k; - volatile unsigned int* ram_pointer = (unsigned int*)ram_address; - int first_good = -1, last_bad = 0x1ff; - - unsigned long test[NUM_TRIES] = { - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, - 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; - - /* go through all possible SDRAM0_TR1[RDCT] values */ - for (i=0; i<=0x1ff; i++) { - /* set the current value for TR1 */ - mtsdram(SDRAM0_TR1, (0x80800800 | i)); - - /* write values */ - for (j=0; j<NUM_TRIES; j++) { - ram_pointer[j] = test[j]; - - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - } - - /* read values back */ - for (j=0; j<NUM_TRIES; j++) { - for (k=0; k<NUM_READS; k++) { - /* clear any cache at ram location */ - __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); - - if (ram_pointer[j] != test[j]) - break; - } - - /* read error */ - if (k != NUM_READS) { - break; - } - } - - /* we have a SDRAM0_TR1[RDCT] that is part of the window */ - if (j == NUM_TRIES) { - if (first_good == -1) - first_good = i; /* found beginning of window */ - } else { /* bad read */ - /* if we have not had a good read then don't care */ - if(first_good != -1) { - /* first failure after a good read */ - last_bad = i-1; - break; - } - } - } - - /* return the current value for TR1 */ - *tr1_value = (first_good + last_bad) / 2; -} - -int dram_init(void) -{ - register uint reg; - int tr1_bank1, tr1_bank2; - - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ - mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */ - mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */ - - /*clear this first, if the DDR is enabled by a debugger - then you can not make changes. */ - mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ - - mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */ - mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */ - mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ - mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */ - udelay(400); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */ - - for (;;) { - mfsdram(SDRAM0_MCSTS, reg); - if (reg & 0x80000000) - break; - } - - sdram_tr1_set(0x00000000, &tr1_bank1); - sdram_tr1_set(0x08000000, &tr1_bank2); - mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); - - gd->ram_size = CONFIG_SYS_SDRAM_BANKS * - (CONFIG_SYS_KBYTES_SDRAM * 1024); /* set bytes */ - - return 0; -} - -/************************************************************************* - * hw_watchdog_reset - * - * This routine is called to reset (keep alive) the watchdog timer - * - ************************************************************************/ -#if defined(CONFIG_HW_WATCHDOG) -void hw_watchdog_reset(void) -{ - -} -#endif - -void board_reset(void) -{ - /* give reset to BCSR */ - *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09; -} diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig deleted file mode 100644 index 61d9589..0000000 --- a/board/amcc/yucca/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_YUCCA - -config SYS_BOARD - default "yucca" - -config SYS_VENDOR - default "amcc" - -config SYS_CONFIG_NAME - default "yucca" - -endif diff --git a/board/amcc/yucca/MAINTAINERS b/board/amcc/yucca/MAINTAINERS deleted file mode 100644 index 1cbdb0e7..0000000 --- a/board/amcc/yucca/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -YUCCA BOARD -#M: - -S: Maintained -F: board/amcc/yucca/ -F: include/configs/yucca.h -F: configs/yucca_defconfig diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile deleted file mode 100644 index 5b1af32..0000000 --- a/board/amcc/yucca/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = yucca.o flash.o cmd_yucca.o -extra-y += init.o diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c deleted file mode 100644 index cc78284..0000000 --- a/board/amcc/yucca/cmd_yucca.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * hacked for evb440spe - */ - -#include <common.h> -#include <cli.h> -#include <command.h> -#include <console.h> -#include "yucca.h" -#include <i2c.h> -#include <asm/byteorder.h> - -extern void print_evb440spe_info(void); -static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, - int flag, int argc, char * const argv[]); - -/* ------------------------------------------------------------------------- */ -int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - return setBootStrapClock (cmdtp, 1, flag, argc, argv); -} - -/* ------------------------------------------------------------------------- */ -/* Modify memory. - * - * Syntax: - * evb440spe wrclk prom0,prom1 - */ -static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, - int argc, char * const argv[]) -{ - uchar chip; - ulong data; - int nbytes; - - char sysClock[4]; - char cpuClock[4]; - char plbClock[4]; - char pcixClock[4]; - - if (argc < 3) - return cmd_usage(cmdtp); - - if (strcmp(argv[2], "prom0") == 0) - chip = IIC0_BOOTPROM_ADDR; - else - chip = IIC0_ALT_BOOTPROM_ADDR; - - do { - printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n"); - nbytes = cli_readline(" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if ((strcmp(console_buffer, "33") != 0) & - (strcmp(console_buffer, "66") != 0)) - nbytes=0; - - strcpy(sysClock, console_buffer); - - } while (nbytes == 0); - - do { - if (strcmp(sysClock, "66") == 0) { - printf("enter cpu clock frequency 400, 533 MHz or quit to abort\n"); - } else { -#ifdef CONFIG_STRESS - printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n"); -#else - printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); -#endif - } - nbytes = cli_readline(" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if (strcmp(sysClock, "66") == 0) { - if ((strcmp(console_buffer, "400") != 0) & - (strcmp(console_buffer, "533") != 0) -#ifdef CONFIG_STRESS - & (strcmp(console_buffer, "667") != 0) -#endif - ) { - nbytes = 0; - } - } else { - if ((strcmp(console_buffer, "400") != 0) & - (strcmp(console_buffer, "500") != 0) & - (strcmp(console_buffer, "533") != 0) -#ifdef CONFIG_STRESS - & (strcmp(console_buffer, "667") != 0) -#endif - ) { - nbytes = 0; - } - } - - strcpy(cpuClock, console_buffer); - - } while (nbytes == 0); - - if (strcmp(cpuClock, "500") == 0){ - strcpy(plbClock, "166"); - } else if (strcmp(cpuClock, "533") == 0){ - strcpy(plbClock, "133"); - } else { - do { - if (strcmp(cpuClock, "400") == 0) - printf("enter plb clock frequency 100, 133 MHz or quit to abort\n"); - -#ifdef CONFIG_STRESS - if (strcmp(cpuClock, "667") == 0) - printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); - -#endif - nbytes = cli_readline(" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if (strcmp(cpuClock, "400") == 0) { - if ((strcmp(console_buffer, "100") != 0) & - (strcmp(console_buffer, "133") != 0)) - nbytes = 0; - } -#ifdef CONFIG_STRESS - if (strcmp(cpuClock, "667") == 0) { - if ((strcmp(console_buffer, "133") != 0) & - (strcmp(console_buffer, "166") != 0)) - nbytes = 0; - } -#endif - strcpy(plbClock, console_buffer); - - } while (nbytes == 0); - } - - do { - printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); - nbytes = cli_readline(" ? "); - - if (strcmp(console_buffer, "quit") == 0) - return 0; - - if ((strcmp(console_buffer, "33") != 0) & - (strcmp(console_buffer, "66") != 0) & - (strcmp(console_buffer, "100") != 0) & - (strcmp(console_buffer, "133") != 0)) { - nbytes = 0; - } - strcpy(pcixClock, console_buffer); - - } while (nbytes == 0); - - printf("\nsys clk = %s MHz\n", sysClock); - printf("cpu clk = %s MHz\n", cpuClock); - printf("plb clk = %s MHz\n", plbClock); - printf("Pci-X clk = %s MHz\n", pcixClock); - - do { - printf("\npress [y] to write I2C bootstrap\n"); - printf("or [n] to abort.\n"); - printf("Don't forget to set board switches\n"); - printf("according to your choice before re-starting\n"); - printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n"); - - nbytes = cli_readline(" ? "); - if (strcmp(console_buffer, "n") == 0) - return 0; - - } while (nbytes == 0); - - if (strcmp(sysClock, "33") == 0) { - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "100") == 0)) - data = 0x8678c206; - - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x8678c2c6; - - if ((strcmp(cpuClock, "500") == 0)) - data = 0x8778f2c6; - - if ((strcmp(cpuClock, "533") == 0)) - data = 0x87790252; - -#ifdef CONFIG_STRESS - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x87794256; - - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "166") == 0)) - data = 0x87794206; - -#endif - } - if (strcmp(sysClock, "66") == 0) { - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "100") == 0)) - data = 0x84706206; - - if ((strcmp(cpuClock, "400") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x847062c6; - - if ((strcmp(cpuClock, "533") == 0)) - data = 0x85708206; - -#ifdef CONFIG_STRESS - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "133") == 0)) - data = 0x8570a256; - - if ((strcmp(cpuClock, "667") == 0) & - (strcmp(plbClock, "166") == 0)) - data = 0x8570a206; - -#endif - } - -#ifdef DEBUG - printf(" pin strap0 to write in i2c = %x\n", data); -#endif /* DEBUG */ - - if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0) - printf("Error writing strap0 in %s\n", argv[2]); - - if (strcmp(pcixClock, "33") == 0) - data = 0x00000701; - - if (strcmp(pcixClock, "66") == 0) - data = 0x00000601; - - if (strcmp(pcixClock, "100") == 0) - data = 0x00000501; - - if (strcmp(pcixClock, "133") == 0) - data = 0x00000401; - - if (strcmp(plbClock, "166") == 0) - data = data | 0x05950000; - else - data = data | 0x05A50000; - -#ifdef DEBUG - printf(" pin strap1 to write in i2c = %x\n", data); -#endif /* DEBUG */ - - udelay(1000); - if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0) - printf("Error writing strap1 in %s\n", argv[2]); - - return 0; -} - -U_BOOT_CMD( - evb440spe, 3, 1, do_evb440spe, - "program the serial device strap", - "wrclk [prom0|prom1] - program the serial device strap" -); diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk deleted file mode 100644 index 53d3f34..0000000 --- a/board/amcc/yucca/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# AMCC 440SPe Reference Platform (yucca) board -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c deleted file mode 100644 index b1fd657..0000000 --- a/board/amcc/yucca/flash.c +++ /dev/null @@ -1,1033 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/ppc440.h> -#include "yucca.h" - -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 - */ -static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { - {0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */ - {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ - {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ - {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ - {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ - {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ - {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ - {0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */ -}; - -/* - * include common flash code (for amcc boards) - */ -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word_1(flash_info_t * info, ulong dest, ulong data); -static int write_word_2(flash_info_t * info, ulong dest, ulong data); -static int flash_erase_1(flash_info_t * info, int s_first, int s_last); -static int flash_erase_2(flash_info_t * info, int s_first, int s_last); -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); -#endif - -void flash_print_info(flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_MX: - printf("MIXC "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - printf("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: - printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: - printf("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: - printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: - printf("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AMD016: - printf("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM160B: - printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: - printf("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: - printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: - printf("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AM033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: - printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: - printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_STMW320DT: - printf ("M29W320DT (32 M, top sector)\n"); - break; - case FLASH_MXLV320T: - printf ("MXLV320T (32 Mbit, top sector)\n"); - break; - default: - printf("Unknown Chip Type\n"); - break; - } - - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf("\n"); - return; -} - - -/* - * The following code cannot be run from FLASH! - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -{ - /* bit 0 used for big flash marking */ - if ((ulong)addr & 0x1) - return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); - else - return flash_get_size_1(addr, info); -} - -static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) -#else -static ulong flash_get_size(vu_long * addr, flash_info_t * info) -#endif -{ - short i; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_1(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -int flash_erase(flash_info_t * info, int s_first, int s_last) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { - return flash_erase_2(info, s_first, s_last); - } else { - return flash_erase_1(info, s_first, s_last); - } -} - -static int flash_erase_1(flash_info_t * info, int s_first, int s_last) -#else -int flash_erase(flash_info_t * info, int s_first, int s_last) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!", prot); - - printf("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_1(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - - for (; cnt == 0 && i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) - data = (data << 8) | *src++; - - if ((rc = write_word(info, wp, data)) != 0) - return (rc); - - wp += 4; - cnt -= 4; - } - - if (cnt == 0) - return (0); - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) - data = (data << 8) | (*(uchar *) cp); - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -static int write_word(flash_info_t * info, ulong dest, ulong data) -{ - if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { - return write_word_2(info, dest, data); - } else { - return write_word_1(info, dest, data); - } -} - -static int write_word_1(flash_info_t * info, ulong dest, ulong data) -#else -static int write_word(flash_info_t * info, ulong dest, ulong data) -#endif -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; - ulong start; - int i, flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} - -#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV - -#undef CONFIG_SYS_FLASH_WORD_SIZE -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) -{ - short i; - int n; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; - udelay(1000); - - value = addr2[0]; - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[1]; /* device ID */ - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT: - info->flash_id += FLASH_STMW320DT; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T: - info->flash_id += FLASH_MXLV320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - /* 1 x 16k boot sector */ - base -= 16 << 10; - --i; - info->start[i] = base; - /* 2 x 8k boot sectors */ - for (n = 0; n < 2; ++n) { - base -= 8 << 10; - --i; - info->start[i] = base; - } - /* 1 x 32k boot sector */ - base -= 32 << 10; - --i; - info->start[i] = base; - - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - info->start[i--] = base + info->size - 0x00010000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - - for (i = 4; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if (i == 32) { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* issue bank reset to return to read mode */ - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; - - return (info->size); -} - -static int wait_for_DQ7_2(flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = - (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer(0); - last = start; - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - return 0; -} - -static int flash_erase_2(flash_info_t * info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) - printf("- missing\n"); - else - printf("- no sectors to erase\n"); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) - printf("- Warning: %d protected sectors will not be erased!", prot); - - printf("\n"); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7_2(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay(1000); - - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf(" done\n"); - return 0; -} - -static int write_word_2(flash_info_t * info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) - return (2); - - for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer(0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - } - - return (0); -} -#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_long * addr, flash_info_t * info); -static int write_word(flash_info_t * info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init(void) -{ - unsigned long total_b = 0; - unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; - unsigned short index = 0; - int i; - unsigned long val; - unsigned long ebc_boot_size; - unsigned long boot_selection; - - mfsdr(sdr_pstrp0, val); - index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28; - - if ((index == 0xc) || (index == 8)) { - /* - * Boot Settings in IIC EEprom address 0xA8 or 0xA0 - * Read Serial Device Strap Register1 in PPC440SPe - */ - mfsdr(SDR0_SDSTP1, val); - boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; - ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; - - switch(boot_selection) { - case SDR0_SDSTP1_BOOT_SEL_EBC: - switch(ebc_boot_size) { - case SDR0_SDSTP1_EBC_ROM_BS_16BIT: - index = 3; - break; - case SDR0_SDSTP1_EBC_ROM_BS_8BIT: - index = 0; - break; - } - break; - - case SDR0_SDSTP1_BOOT_SEL_PCI: - index = 1; - break; - - } - } /*else if (index == 0) {*/ -/* if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/ -/* index = 8;*/ /* sram below op code flash -> new index 8*/ -/* }*/ - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) - continue; - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], - &flash_info[i]); - - flash_info[i].size = size_b[i]; - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#if defined(CONFIG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[i]); -#endif -#endif - total_b += flash_info[i].size; - } - - return total_b; -} diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S deleted file mode 100644 index 7da5c0d..0000000 --- a/board/amcc/yucca/init.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - -/************************************************************************** - * TLB table for revA - *************************************************************************/ - .globl tlbtabA -tlbtabA: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I) - - tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG) - tlbtab_end - -/************************************************************************** - * TLB table for revB - * - * Notice: revB of the 440SPe chip is very strict about PLB real addresses - * and ranges to be mapped for config space: it seems to only work with - * d_nnnn_nnnn range (hangs the core upon config transaction attempts when - * set otherwise) while revA uses c_nnnn_nnnn. - *************************************************************************/ - .globl tlbtabB -tlbtabB: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) - tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I) - - tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG) - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG) - tlbtab_end diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c deleted file mode 100644 index 8ee3851..0000000 --- a/board/amcc/yucca/yucca.c +++ /dev/null @@ -1,714 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Port to AMCC-440SPE Evaluation Board SOP - April 2005 - * - * PCIe supporting routines derived from Linux 440SPe PCIe driver. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <i2c.h> -#include <netdev.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/4xx_pcie.h> -#include <linux/errno.h> - -#include "yucca.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fpga_init (void); - -#define DEBUG_ENV -#ifdef DEBUG_ENV -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif - -int board_early_init_f (void) -{ -/*----------------------------------------------------------------------------+ -| Define Boot devices -+----------------------------------------------------------------------------*/ -#define BOOT_FROM_SMALL_FLASH 0x00 -#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 -#define BOOT_FROM_PCI 0x02 -#define BOOT_DEVICE_UNKNOWN 0x03 - -/*----------------------------------------------------------------------------+ -| EBC Devices Characteristics -| Peripheral Bank Access Parameters - EBC_BxAP -| Peripheral Bank Configuration Register - EBC_BxCR -+----------------------------------------------------------------------------*/ - -/* - * Small Flash and FRAM - * BU Value - * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 - * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 - */ -#define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | \ - EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | \ - EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ - EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_8BIT - -#define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \ - EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_8BIT - -/* - * Large Flash and SRAM - * BU Value - * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 - * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 - * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 -*/ -#define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | \ - EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(0) | \ - EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \ - EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_16BIT - -#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \ - EBC_BXCR_BS_16MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_16BIT - -/* - * FPGA - * BU value : - * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 - * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 - */ -#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(11) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(10) | \ - EBC_BXAP_OEN_ENCODE(1) | \ - EBC_BXAP_WBN_ENCODE(1) | \ - EBC_BXAP_WBF_ENCODE(1) | \ - EBC_BXAP_TH_ENCODE(1) | \ - EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_DELAYED | \ - EBC_BXAP_BEM_RW | \ - EBC_BXAP_PEN_DISABLED - -#define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \ - EBC_BXCR_BS_1MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_16BIT - - unsigned long mfr; - /* - * Define Variables for EBC initialization depending on BOOTSTRAP option - */ - unsigned long sdr0_pinstp, sdr0_sdstp1 ; - unsigned long bootstrap_settings, ebc_data_width, boot_selection; - int computed_boot_device = BOOT_DEVICE_UNKNOWN; - - /*-------------------------------------------------------------------+ - | Initialize EBC CONFIG - - | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC - | default value : - | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 - | - +-------------------------------------------------------------------*/ - mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | - EBC_CFG_PTD_ENABLE | - EBC_CFG_RTC_16PERCLK | - EBC_CFG_ATC_PREVIOUS | - EBC_CFG_DTC_PREVIOUS | - EBC_CFG_CTC_PREVIOUS | - EBC_CFG_OEO_PREVIOUS | - EBC_CFG_EMC_DEFAULT | - EBC_CFG_PME_DISABLE | - EBC_CFG_PR_16); - - /*-------------------------------------------------------------------+ - | - | PART 1 : Initialize EBC Bank 1 - | ============================== - | Bank1 is always associated to the EPLD. - | It has to be initialized prior to other banks settings computation - | since some board registers values may be needed to determine the - | boot type - | - +-------------------------------------------------------------------*/ - mtebc(PB1AP, EBC_BXAP_FPGA); - mtebc(PB1CR, EBC_BXCR_FPGA_CS1); - - /*-------------------------------------------------------------------+ - | - | PART 2 : Determine which boot device was selected - | ================================================= - | - | Read Pin Strap Register in PPC440SPe - | Result can either be : - | - Boot strap = boot from EBC 8bits => Small Flash - | - Boot strap = boot from PCI - | - Boot strap = IIC - | In case of boot from IIC, read Serial Device Strap Register1 - | - | Result can either be : - | - Boot from EBC - EBC Bus Width = 8bits => Small Flash - | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM - | - Boot from PCI - | - +-------------------------------------------------------------------*/ - /* Read Pin Strap Register in PPC440SP */ - mfsdr(SDR0_PINSTP, sdr0_pinstp); - bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK; - - switch (bootstrap_settings) { - case SDR0_PINSTP_BOOTSTRAP_SETTINGS0: - /* - * Strapping Option A - * Boot from EBC - 8 bits , Small Flash - */ - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - case SDR0_PINSTP_BOOTSTRAP_SETTINGS1: - /* - * Strappping Option B - * Boot from PCI - */ - computed_boot_device = BOOT_FROM_PCI; - break; - case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN: - case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN: - /* - * Strapping Option C or D - * Boot Settings in IIC EEprom address 0x50 or 0x54 - * Read Serial Device Strap Register1 in PPC440SPe - */ - mfsdr(SDR0_SDSTP1, sdr0_sdstp1); - boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK; - ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK; - - switch (boot_selection) { - case SDR0_SDSTP1_ERPN_EBC: - switch (ebc_data_width) { - case SDR0_SDSTP1_EBCW_16_BITS: - computed_boot_device = - BOOT_FROM_LARGE_FLASH_OR_SRAM; - break; - case SDR0_SDSTP1_EBCW_8_BITS : - computed_boot_device = BOOT_FROM_SMALL_FLASH; - break; - } - break; - - case SDR0_SDSTP1_ERPN_PCI: - computed_boot_device = BOOT_FROM_PCI; - break; - default: - /* should not occure */ - computed_boot_device = BOOT_DEVICE_UNKNOWN; - } - break; - default: - /* should not be */ - computed_boot_device = BOOT_DEVICE_UNKNOWN; - break; - } - - /*-------------------------------------------------------------------+ - | - | PART 3 : Compute EBC settings depending on selected boot device - | ====== ====================================================== - | - | Resulting EBC init will be among following configurations : - | - | - Boot from EBC 8bits => boot from Small Flash selected - | EBC-CS0 = Small Flash - | EBC-CS2 = Large Flash and SRAM - | - | - Boot from EBC 16bits => boot from Large Flash or SRAM - | EBC-CS0 = Large Flash or SRAM - | EBC-CS2 = Small Flash - | - | - Boot from PCI - | EBC-CS0 = not initialized to avoid address contention - | EBC-CS2 = same as boot from Small Flash selected - | - +-------------------------------------------------------------------*/ - unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; - unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; - - switch (computed_boot_device) { - /*-------------------------------------------------------------------*/ - case BOOT_FROM_PCI: - /*-------------------------------------------------------------------*/ - /* - * By Default CS2 is affected to LARGE Flash - * do not initialize SMALL FLASH to avoid address contention - * Large Flash - */ - ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; - ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_SMALL_FLASH: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH; - ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0; - - /* - * Large Flash or SRAM - */ - /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */ - ebc0_cs2_bxap_value = 0x048ff240; - ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2; - break; - - /*-------------------------------------------------------------------*/ - case BOOT_FROM_LARGE_FLASH_OR_SRAM: - /*-------------------------------------------------------------------*/ - ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH; - ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0; - - /* Small flash */ - ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH; - ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2; - break; - - /*-------------------------------------------------------------------*/ - default: - /*-------------------------------------------------------------------*/ - /* BOOT_DEVICE_UNKNOWN */ - break; - } - - mtebc(PB0AP, ebc0_cs0_bxap_value); - mtebc(PB0CR, ebc0_cs0_bxcr_value); - mtebc(PB2AP, ebc0_cs2_bxap_value); - mtebc(PB2CR, ebc0_cs2_bxcr_value); - - /*--------------------------------------------------------------------+ - | Interrupt controller setup for the AMCC 440SPe Evaluation board. - +--------------------------------------------------------------------+ - +---------------------------------------------------------------------+ - |Interrupt| Source | Pol. | Sensi.| Crit. | - +---------+-----------------------------------+-------+-------+-------+ - | IRQ 00 | UART0 | High | Level | Non | - | IRQ 01 | UART1 | High | Level | Non | - | IRQ 02 | IIC0 | High | Level | Non | - | IRQ 03 | IIC1 | High | Level | Non | - | IRQ 04 | PCI0X0 MSG IN | High | Level | Non | - | IRQ 05 | PCI0X0 CMD Write | High | Level | Non | - | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | - | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | - | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | - | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | - | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | - | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | - | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | - | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | - | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | - | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | - | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | - | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | - | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | - | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | - | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | - | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | - | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | - | IRQ 23 | I2O Inbound Doorbell | High | Level | Non | - | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | - | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | - | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | - | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | - | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | - | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | - | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | - | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | - |---------------------------------------------------------------------- - | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | - | IRQ 33 | MAL Serr | High | Level | Non | - | IRQ 34 | MAL Txde | High | Level | Non | - | IRQ 35 | MAL Rxde | High | Level | Non | - | IRQ 36 | DMC CE or DMC UE | High | Level | Non | - | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | - | IRQ 38 | MAL TX EOB | High | Level | Non | - | IRQ 39 | MAL RX EOB | High | Level | Non | - | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | - | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | - | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | - | IRQ 43 | L2 Cache | Risin | Edge | Non | - | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | - | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | - | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | - | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | - | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | - | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | - | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | - | IRQ 54 | DMA Error | High | Level | Non | - | IRQ 55 | DMA I2O Error | High | Level | Non | - | IRQ 56 | Serial ROM | High | Level | Non | - | IRQ 57 | PCIX0 Error | High | Edge | Non | - | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | - | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | - | IRQ 60 | EMAC0 Interrupt | High | Level | Non | - | IRQ 61 | EMAC0 Wake-up | High | Level | Non | - | IRQ 62 | Reserved | High | Level | Non | - | IRQ 63 | XOR | High | Level | Non | - |---------------------------------------------------------------------- - | IRQ 64 | PE0 AL | High | Level | Non | - | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - | IRQ 68 | PE0 TCR | High | Level | Non | - | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - | IRQ 70 | PE0 DCR Error | High | Level | Non | - | IRQ 71 | Reserved | N/A | N/A | Non | - | IRQ 72 | PE1 AL | High | Level | Non | - | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - | IRQ 76 | PE1 TCR | High | Level | Non | - | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - | IRQ 78 | PE1 DCR Error | High | Level | Non | - | IRQ 79 | Reserved | N/A | N/A | Non | - | IRQ 80 | PE2 AL | High | Level | Non | - | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - | IRQ 84 | PE2 TCR | High | Level | Non | - | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - | IRQ 86 | PE2 DCR Error | High | Level | Non | - | IRQ 87 | Reserved | N/A | N/A | Non | - | IRQ 88 | External IRQ(5) | Progr | Progr | Non | - | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - | IRQ 94 | Reserved | N/A | N/A | Non | - | IRQ 95 | Reserved | N/A | N/A | Non | - |--------------------------------------------------------------------- - | IRQ 96 | PE0 INTA | High | Level | Non | - | IRQ 97 | PE0 INTB | High | Level | Non | - | IRQ 98 | PE0 INTC | High | Level | Non | - | IRQ 99 | PE0 INTD | High | Level | Non | - | IRQ 100 | PE1 INTA | High | Level | Non | - | IRQ 101 | PE1 INTB | High | Level | Non | - | IRQ 102 | PE1 INTC | High | Level | Non | - | IRQ 103 | PE1 INTD | High | Level | Non | - | IRQ 104 | PE2 INTA | High | Level | Non | - | IRQ 105 | PE2 INTB | High | Level | Non | - | IRQ 106 | PE2 INTC | High | Level | Non | - | IRQ 107 | PE2 INTD | Risin | Edge | Non | - | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | - | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | - | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | - | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | - | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | - | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | - | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | - | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | - | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | - | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | - | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | - | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | - | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | - | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | - | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | - | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | - | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | - | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | - | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | - | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | - +---------+-----------------------------------+-------+-------+------*/ - /*--------------------------------------------------------------------+ - | Put UICs in PowerPC440SPemode. - | Initialise UIC registers. Clear all interrupts. Disable all - | interrupts. - | Set critical interrupt values. Set interrupt polarities. Set - | interrupt trigger levels. Make bit 0 High priority. Clear all - | interrupts again. - +-------------------------------------------------------------------*/ - mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest - * priority */ - mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ - mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest - * priority */ - mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical - * interrupts */ - mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */ - mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest - * priority */ - mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted - * cascade to be checked */ - mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical - * interrupts */ - mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest - * priority */ - mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ - mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ - - mfsdr(SDR0_MFR, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(SDR0_MFR, mfr); - - fpga_init(); - - return 0; -} - -int checkboard (void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: Yucca - AMCC 440SPe Evaluation Board"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -static int ppc440spe_rev_a(void) -{ - if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) - return 1; - else - return 0; -} - -u32 ddr_wrdtr(u32 default_val) { - /* - * Yucca boards with 440SPe rev. A need a slightly different setup - * for the MCIF0_WRDTR register. - */ - if (ppc440spe_rev_a()) - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); - - return default_val; -} - -u32 ddr_clktr(u32 default_val) { - /* - * Yucca boards with 440SPe rev. A need a slightly different setup - * for the MCIF0_CLKTR register. - */ - if (ppc440spe_rev_a()) - return (SDRAM_CLKTR_CLKP_180_DEG_ADV); - - return default_val; -} - -#if defined(CONFIG_PCI) -int board_pcie_card_present(int port) -{ - u16 reg; - - reg = in_be16((u16 *)FPGA_REG1C); - switch(port) { - case 0: - return !(reg & FPGA_REG1C_PE0_PRSNT); - case 1: - return !(reg & FPGA_REG1C_PE1_PRSNT); - case 2: - return !(reg & FPGA_REG1C_PE2_PRSNT); - default: - return 0; - } -} - -/* - * For the given slot, set endpoint mode, send power to the slot, - * turn on the green LED and turn off the yellow LED, enable the - * clock. In endpoint mode reset bit is read only. - */ -void board_pcie_setup_port(int port, int rootpoint) -{ - u16 power, clock, green_led, yellow_led, - reset_off, rp, ep; - - switch (port) { - case 0: - rp = FPGA_REG1C_PE0_ROOTPOINT; - ep = 0; - break; - case 1: - rp = 0; - ep = FPGA_REG1C_PE1_ENDPOINT; - break; - case 2: - rp = 0; - ep = FPGA_REG1C_PE2_ENDPOINT; - break; - - default: - return; - } - - power = FPGA_REG1A_PWRON_ENCODE(port); - green_led = FPGA_REG1A_GLED_ENCODE(port); - clock = FPGA_REG1A_REFCLK_ENCODE(port); - yellow_led = FPGA_REG1A_YLED_ENCODE(port); - reset_off = FPGA_REG1C_PERST_ENCODE(port); - - out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) & - (yellow_led | in_be16((u16 *)FPGA_REG1A))); - - out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) & - (rp | in_be16((u16 *)FPGA_REG1C))); - - if (rootpoint) { - /* - * Leave device in reset for a while after powering on the - * slot to give it a chance to initialize. - */ - udelay(250 * 1000); - - out_be16((u16 *)FPGA_REG1C, - reset_off | in_be16((u16 *)FPGA_REG1C)); - } -} -#endif /* defined(CONFIG_PCI) */ - -int misc_init_f (void) -{ - uint reg; - - out16(FPGA_REG10, (in16(FPGA_REG10) & - ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | - FPGA_REG10_10MHZ_ENABLE | - FPGA_REG10_100MHZ_ENABLE | - FPGA_REG10_GIGABIT_ENABLE | - FPGA_REG10_FULL_DUPLEX ); - - udelay(10000); /* wait 10ms */ - - out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH)); - - /* minimal init for PCIe */ - /* pci express 0 Endpoint Mode */ - mfsdr(SDRN_PESDR_DLPSET(0), reg); - reg &= (~0x00400000); - mtsdr(SDRN_PESDR_DLPSET(0), reg); - /* pci express 1 Rootpoint Mode */ - mfsdr(SDRN_PESDR_DLPSET(1), reg); - reg |= 0x00400000; - mtsdr(SDRN_PESDR_DLPSET(1), reg); - /* pci express 2 Rootpoint Mode */ - mfsdr(SDRN_PESDR_DLPSET(2), reg); - reg |= 0x00400000; - mtsdr(SDRN_PESDR_DLPSET(2), reg); - - out16(FPGA_REG1C,(in16 (FPGA_REG1C) & - ~FPGA_REG1C_PE0_ROOTPOINT & - ~FPGA_REG1C_PE1_ENDPOINT & - ~FPGA_REG1C_PE2_ENDPOINT)); - - return 0; -} - -void fpga_init(void) -{ - /* - * by default sdram access is disabled by fpga - */ - out16(FPGA_REG10, (in16 (FPGA_REG10) | - FPGA_REG10_SDRAM_ENABLE | - FPGA_REG10_ENABLE_DISPLAY )); - - return; -} - -/*---------------------------------------------------------------------------+ - | onboard_pci_arbiter_selected => from EPLD - +---------------------------------------------------------------------------*/ -int onboard_pci_arbiter_selected(int core_pci) -{ -#if 0 - unsigned long onboard_pci_arbiter_sel; - - onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK; - - if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL) - return (BOARD_OPTION_SELECTED); - else -#endif - return (BOARD_OPTION_NOT_SELECTED); -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); - return pci_eth_init(bis); -} diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h deleted file mode 100644 index ac9e5ae..0000000 --- a/board/amcc/yucca/yucca.h +++ /dev/null @@ -1,350 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __YUCCA_H_ -#define __YUCCA_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------------------------+ -| Defines -+----------------------------------------------------------------------------*/ - -#define TMR_FREQ_EXT 25000000 -#define BOARD_UART_CLOCK 11059200 - -#define BOARD_OPTION_SELECTED 1 -#define BOARD_OPTION_NOT_SELECTED 0 - -#define ENGINEERING_CLOCK_CHECKING "clk_chk" -#define ENGINEERING_EXTERNAL_CLOCK "ext_clk" - -#define ENGINEERING_CLOCK_CHECKING_DATA 1 -#define ENGINEERING_EXTERNAL_CLOCK_DATA 2 - -/* ethernet definition */ -#define MAX_ENETMODE_PARM 3 -#define ENETMODE_NEG 0 -#define ENETMODE_SPEED 1 -#define ENETMODE_DUPLEX 2 - -#define ENETMODE_AUTONEG 0 -#define ENETMODE_NO_AUTONEG 1 -#define ENETMODE_10 2 -#define ENETMODE_100 3 -#define ENETMODE_1000 4 -#define ENETMODE_HALF 5 -#define ENETMODE_FULL 6 - -#define NUM_TLB_ENTRIES 64 - -/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */ -#define MICRON_SPD_JEDEC_ID 0x2c - -/*----------------------------------------------------------------------------+ -| TLB specific defines. -+----------------------------------------------------------------------------*/ -#define TLB_256MB_ALIGN_MASK 0xF0000000 -#define TLB_16MB_ALIGN_MASK 0xFF000000 -#define TLB_1MB_ALIGN_MASK 0xFFF00000 -#define TLB_256KB_ALIGN_MASK 0xFFFC0000 -#define TLB_64KB_ALIGN_MASK 0xFFFF0000 -#define TLB_16KB_ALIGN_MASK 0xFFFFC000 -#define TLB_4KB_ALIGN_MASK 0xFFFFF000 -#define TLB_1KB_ALIGN_MASK 0xFFFFFC00 -#define TLB_256MB_SIZE 0x10000000 -#define TLB_16MB_SIZE 0x01000000 -#define TLB_1MB_SIZE 0x00100000 -#define TLB_256KB_SIZE 0x00040000 -#define TLB_64KB_SIZE 0x00010000 -#define TLB_16KB_SIZE 0x00004000 -#define TLB_4KB_SIZE 0x00001000 -#define TLB_1KB_SIZE 0x00000400 - -#define TLB_WORD0_EPN_MASK 0xFFFFFC00 -#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_V_MASK 0x00000200 -#define TLB_WORD0_V_ENABLE 0x00000200 -#define TLB_WORD0_V_DISABLE 0x00000000 -#define TLB_WORD0_TS_MASK 0x00000100 -#define TLB_WORD0_TS_1 0x00000100 -#define TLB_WORD0_TS_0 0x00000000 -#define TLB_WORD0_SIZE_MASK 0x000000F0 -#define TLB_WORD0_SIZE_1KB 0x00000000 -#define TLB_WORD0_SIZE_4KB 0x00000010 -#define TLB_WORD0_SIZE_16KB 0x00000020 -#define TLB_WORD0_SIZE_64KB 0x00000030 -#define TLB_WORD0_SIZE_256KB 0x00000040 -#define TLB_WORD0_SIZE_1MB 0x00000050 -#define TLB_WORD0_SIZE_16MB 0x00000070 -#define TLB_WORD0_SIZE_256MB 0x00000090 -#define TLB_WORD0_TPAR_MASK 0x0000000F -#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD1_RPN_MASK 0xFFFFFC00 -#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_PAR1_MASK 0x00000300 -#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) -#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03) -#define TLB_WORD1_PAR1_0 0x00000000 -#define TLB_WORD1_PAR1_1 0x00000100 -#define TLB_WORD1_PAR1_2 0x00000200 -#define TLB_WORD1_PAR1_3 0x00000300 -#define TLB_WORD1_ERPN_MASK 0x0000000F -#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD2_PAR2_MASK 0xC0000000 -#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30) -#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03) -#define TLB_WORD2_PAR2_0 0x00000000 -#define TLB_WORD2_PAR2_1 0x40000000 -#define TLB_WORD2_PAR2_2 0x80000000 -#define TLB_WORD2_PAR2_3 0xC0000000 -#define TLB_WORD2_U0_MASK 0x00008000 -#define TLB_WORD2_U0_ENABLE 0x00008000 -#define TLB_WORD2_U0_DISABLE 0x00000000 -#define TLB_WORD2_U1_MASK 0x00004000 -#define TLB_WORD2_U1_ENABLE 0x00004000 -#define TLB_WORD2_U1_DISABLE 0x00000000 -#define TLB_WORD2_U2_MASK 0x00002000 -#define TLB_WORD2_U2_ENABLE 0x00002000 -#define TLB_WORD2_U2_DISABLE 0x00000000 -#define TLB_WORD2_U3_MASK 0x00001000 -#define TLB_WORD2_U3_ENABLE 0x00001000 -#define TLB_WORD2_U3_DISABLE 0x00000000 -#define TLB_WORD2_W_MASK 0x00000800 -#define TLB_WORD2_W_ENABLE 0x00000800 -#define TLB_WORD2_W_DISABLE 0x00000000 -#define TLB_WORD2_I_MASK 0x00000400 -#define TLB_WORD2_I_ENABLE 0x00000400 -#define TLB_WORD2_I_DISABLE 0x00000000 -#define TLB_WORD2_M_MASK 0x00000200 -#define TLB_WORD2_M_ENABLE 0x00000200 -#define TLB_WORD2_M_DISABLE 0x00000000 -#define TLB_WORD2_G_MASK 0x00000100 -#define TLB_WORD2_G_ENABLE 0x00000100 -#define TLB_WORD2_G_DISABLE 0x00000000 -#define TLB_WORD2_E_MASK 0x00000080 -#define TLB_WORD2_E_ENABLE 0x00000080 -#define TLB_WORD2_E_DISABLE 0x00000000 -#define TLB_WORD2_UX_MASK 0x00000020 -#define TLB_WORD2_UX_ENABLE 0x00000020 -#define TLB_WORD2_UX_DISABLE 0x00000000 -#define TLB_WORD2_UW_MASK 0x00000010 -#define TLB_WORD2_UW_ENABLE 0x00000010 -#define TLB_WORD2_UW_DISABLE 0x00000000 -#define TLB_WORD2_UR_MASK 0x00000008 -#define TLB_WORD2_UR_ENABLE 0x00000008 -#define TLB_WORD2_UR_DISABLE 0x00000000 -#define TLB_WORD2_SX_MASK 0x00000004 -#define TLB_WORD2_SX_ENABLE 0x00000004 -#define TLB_WORD2_SX_DISABLE 0x00000000 -#define TLB_WORD2_SW_MASK 0x00000002 -#define TLB_WORD2_SW_ENABLE 0x00000002 -#define TLB_WORD2_SW_DISABLE 0x00000000 -#define TLB_WORD2_SR_MASK 0x00000001 -#define TLB_WORD2_SR_ENABLE 0x00000001 -#define TLB_WORD2_SR_DISABLE 0x00000000 - -/*----------------------------------------------------------------------------+ -| Board specific defines. -+----------------------------------------------------------------------------*/ -#define NONCACHE_MEMORY_SIZE (64*1024) -#define NONCACHE_AREA0_ENDOFFSET (64*1024) -#define NONCACHE_AREA1_ENDOFFSET (32*1024) - -#define FLASH_SECTORSIZE 0x00010000 - -/* SDRAM MICRON */ -#define SDRAM_MICRON 0x2C - -#define SDRAM_TRUE 1 -#define SDRAM_FALSE 0 -#define SDRAM_DDR1 1 -#define SDRAM_DDR2 2 -#define SDRAM_NONE 0 -#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */ -#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */ -#define MAXBANKSPERDIMM 2 -#define MAXRANKSPERDIMM 2 -#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */ -#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */ -#define ERROR_STR_LENGTH 256 -#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ - -/*----------------------------------------------------------------------------+ -| SDR Configuration registers -+----------------------------------------------------------------------------*/ -/* Serial Device Strap Reg 0 */ -#define sdr_pstrp0 0x0040 - -#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */ -#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */ -#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ - -#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */ -#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ -#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */ - -#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */ -#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */ -#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */ -#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */ -#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */ - -/* Serial Device Enabled - Addr = 0xA8 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 -/* Serial Device Enabled - Addr = 0xA4 */ -#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 - -/* Pin Straps Reg */ -#define SDR0_PSTRP0 0x0040 -#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ - -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ -#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ - -/* fpgareg - defines are in include/config/YUCCA.h */ - -#define SDR0_CUST0_ENET3_MASK 0x00000080 -#define SDR0_CUST0_ENET3_COPPER 0x00000000 -#define SDR0_CUST0_ENET3_FIBER 0x00000080 -#define SDR0_CUST0_RGMII3_MASK 0x00000070 -#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) -#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) -#define SDR0_CUST0_RGMII3_DISAB 0x00000000 -#define SDR0_CUST0_RGMII3_RTBI 0x00000040 -#define SDR0_CUST0_RGMII3_RGMII 0x00000050 -#define SDR0_CUST0_RGMII3_TBI 0x00000060 -#define SDR0_CUST0_RGMII3_GMII 0x00000070 -#define SDR0_CUST0_ENET2_MASK 0x00000008 -#define SDR0_CUST0_ENET2_COPPER 0x00000000 -#define SDR0_CUST0_ENET2_FIBER 0x00000008 -#define SDR0_CUST0_RGMII2_MASK 0x00000007 -#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) -#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) -#define SDR0_CUST0_RGMII2_DISAB 0x00000000 -#define SDR0_CUST0_RGMII2_RTBI 0x00000004 -#define SDR0_CUST0_RGMII2_RGMII 0x00000005 -#define SDR0_CUST0_RGMII2_TBI 0x00000006 -#define SDR0_CUST0_RGMII2_GMII 0x00000007 - -#define ONE_MILLION 1000000 -#define ONE_BILLION 1000000000 - -/*----------------------------------------------------------------------------+ -| X -| XX -| XX XXX XXXXX XX XXX XXXXX -| XX XX X XXX XX XX -| XX XX XXXXXX XX XX -| XX XX X XX XX XX XX -| XXX XX XXXXX X XXXX XXX -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| Declare Configuration values -+----------------------------------------------------------------------------*/ - -typedef enum config_selection { - CONFIG_NOT_SELECTED, - CONFIG_SELECTED -} config_selection_t; - -typedef enum config_list { - UART2_IN_SERVICE_MODE, - CPU_TRACE_MODE, - UART1_CTS_RTS, - CONFIG_NB -} config_list_t; - -#define MAX_CONFIG_SELECT_NB 3 - -#define BOARD_INFO_UART2_IN_SERVICE_MODE 1 -#define BOARD_INFO_CPU_TRACE_MODE 2 -#define BOARD_INFO_UART1_CTS_RTS_MODE 4 - -void force_bup_config_selection(config_selection_t *confgi_select_P); -void update_config_selection_table(config_selection_t *config_select_P); -void display_config_selection(config_selection_t *config_select_P); - -/*----------------------------------------------------------------------------+ -| XX -| -| XXXX XX XXX XXX XXXX -| XX XX XX XX XX XX -| XX XXX XX XX XX XX XX -| XX XX XXXXX XX XX XX -| XXXX XX XXXX XXXX -| XXXX -| -| -| -| +------------------------------------------------------------------+ -| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O | -| +----------------------+------------------+-----+------------+-----+ -| | | | | | | -| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | | -| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | | -| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | | -| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | | -| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | | -| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | | -| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA | -| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA | -| | GPIO0_8 | PERREADY | I | TRCES4 | NA | -| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA | -| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA | -| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA | -| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA | -| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA | -| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA | -| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA | -| | GPIO0_16 | IRQ5 | I | UART2RX | I | -| | GPIO0_17 | PERBE0_N | O | UART2TX | O | -| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA | -| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA | -| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA | -| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA | -| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA | -| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA | -| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA | -| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA | -| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA | -| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA | -| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA | -| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA | -| | GPIO0_30 | UART1RX | I | NA | NA | -| | GPIO0_31 | UART1TX | O | NA | NA | -| | | | | | | -| +----------------------+------------------+-----+------------+-----+ -| -+----------------------------------------------------------------------------*/ - -unsigned long auto_calc_speed(void); -/*----------------------------------------------------------------------------+ -| Prototypes -+----------------------------------------------------------------------------*/ -void print_evb440spe_info(void); - -int onboard_pci_arbiter_selected(int core_pci); - -#ifdef __cplusplus -} -#endif -#endif /* __YUCCA_H_ */ diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c deleted file mode 100644 index 9541817..0000000 --- a/board/esd/common/cmd_loadpci.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * (C) Copyright 2005-2008 - * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <console.h> -#if !defined(CONFIG_440) -#include <asm/4xx_pci.h> -#endif - -#if defined(CONFIG_CMD_BSP) -#define ADDRMASK 0xfffff000 - -/* - * Command loadpci: wait for signal from host and boot image. - */ -int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 *ptr = 0; - int count = 0; - int count2 = 0; - char addr[16]; - char str[] = "\\|/-"; - u32 la, ptm1la; - -#if defined(CONFIG_440) - ptm1la = in32r(PCIL0_PTM1LA); -#else - ptm1la = in32r(PTM1LA); -#endif - while(1) { - /* - * Mark sync address - */ - ptr = (u32 *)ptm1la; - memset(ptr, 0, 0x20); - - *ptr = 0xffffffff; - puts("\nWaiting for action from pci host -"); - - /* - * Wait for host to write the start address - */ - while (*ptr == 0xffffffff) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - udelay(1000); - } - - printf("\nGot bootcode %08x: ", *ptr); - la = ptm1la + (*ptr & ADDRMASK); - sprintf(addr, "%08x", la); - - switch (*ptr & ~ADDRMASK) { - case 0: - /* - * Boot image via bootm - */ - printf("booting image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - do_bootm(cmdtp, 0, 0, NULL); - break; - - case 1: - /* - * Boot image via "source" command - */ - printf("executing script at addr 0x%s ...\n", addr); - source(la, NULL); - break; - - case 2: - /* - * Call run_cmd - */ - printf("running command at addr 0x%s ...\n", addr); - run_command((char *)la, 0); - break; - - default: - printf("unhandled boot method\n"); - break; - } - } -} - -U_BOOT_CMD( - loadpci, 1, 1, do_loadpci, - "Wait for pci bootcmd and boot it", - "" -); - -#endif diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c deleted file mode 100644 index 51ac10c..0000000 --- a/board/esd/common/esd405ep_nand.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if defined(CONFIG_CMD_NAND) -#include <asm/io.h> -#include <nand.h> - -/* - * hardware specific access to control-lines - */ -static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE); - else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE); - if ( ctrl & NAND_ALE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE); - else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE); - if ( ctrl & NAND_NCE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE); - else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - - -/* - * read device ready pin - */ -static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) -{ - if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY) - return 1; - return 0; -} - - -int board_nand_init(struct nand_chip *nand) -{ - /* - * Set NAND-FLASH GPIO signals to defaults - */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); - - /* - * Initialize nand_chip structure - */ - nand->cmd_ctrl = esd405ep_nand_hwcontrol; - nand->dev_ready = esd405ep_nand_device_ready; - nand->ecc.mode = NAND_ECC_SOFT; - nand->chip_delay = NAND_BIG_DELAY_US; - nand->options = NAND_SAMSUNG_LP_OPTIONS; - return 0; -} -#endif diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c deleted file mode 100644 index e3512c7..0000000 --- a/board/esd/common/flash.c +++ /dev/null @@ -1,659 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#ifdef __PPC__ -#include <asm/ppc4xx.h> -#endif -#include <asm/processor.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - short n; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_SST320: printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n"); - break; - case FLASH_SST640: printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - short n; - CONFIG_SYS_FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - - value = addr2[CONFIG_SYS_FLASH_READ0]; - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: - info->flash_id = FLASH_MAN_EXCEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ - - switch (value) { - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000; break; /* => 8 MB */ - -#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM)) - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A: - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601: - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201: - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202: - info->flash_id += FLASH_SST320; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401: - case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402: - info->flash_id += FLASH_SST640; - info->sector_count = 128; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) { - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (i < info->sector_count) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) { - /* set sector offsets for top boot block type */ - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) - info->protect[i] = 0; - else - info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - ulong start, now, last; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - if (sect == s_first) { - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; - addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - } - addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - ulong *data_ptr = &data; - volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); - volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; - volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr; - ulong start; - int flag; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) - { - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; - addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c deleted file mode 100644 index 5c70b47..0000000 --- a/board/esd/common/fpga.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -#ifdef FPGA_DEBUG -#define DBG(x...) printf(x) -#else -#define DBG(x...) -#endif /* DEBUG */ - -#define MAX_ONES 226 - -#ifdef CONFIG_SYS_FPGA_PRG -# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */ -# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */ -#else -# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ -#endif - -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ - -#ifndef SET_FPGA -# define SET_FPGA(data) out_be32((void *)GPIO0_OR, data) -#endif - -#ifdef FPGA_PROG_ACTIVE_HIGH -# define FPGA_PRG_LOW FPGA_PRG -# define FPGA_PRG_HIGH 0 -#else -# define FPGA_PRG_LOW 0 -# define FPGA_PRG_HIGH FPGA_PRG -#endif - -#define FPGA_CLK_LOW 0 -#define FPGA_CLK_HIGH FPGA_CLK - -#define FPGA_DATA_LOW 0 -#define FPGA_DATA_HIGH FPGA_DATA - -#define FPGA_WRITE_1 { \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ - -#define FPGA_WRITE_0 { \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ - -#ifndef FPGA_DONE_STATE -# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE) -#endif -#ifndef FPGA_INIT_STATE -# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT) -#endif - - -static int fpga_boot (const unsigned char *fpgadata, int size) -{ - int i, index, len; - int count; - unsigned char b; - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - int j; -#else - int bit; -#endif - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - DBG ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } -#else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; -#endif - - DBG ("FPGA: configdata starts at position 0x%x\n", index); - DBG ("FPGA: length of fpga-data %d\n", size - index); - - /* - * Setup port pins for fpga programming - */ -#ifndef CONFIG_M5249 - out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ - /* setup for output */ - out_be32 ((void *)GPIO0_TCR, - in_be32 ((void *)GPIO0_TCR) | - FPGA_PRG | FPGA_CLK | FPGA_DATA); -#endif - SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */ - - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); - - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */ - - /* Wait for FPGA init line low */ - count = 0; - while (FPGA_INIT_STATE) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } - } - - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); - - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */ - - /* Wait for FPGA end of init period . */ - count = 0; - while (!(FPGA_INIT_STATE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } - } - - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); - - DBG ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ - -#ifdef CONFIG_SYS_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { - b = fpgadata[i]; - for (j = 0; j < 8; j++) { - if ((b & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - b <<= 1; - } - } -#else - /* send 0xff 0x20 */ - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_1; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - FPGA_WRITE_0; - - /* - ** Bit_DeCompression - ** Code 1 .. maxOnes : n '1's followed by '0' - ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' - ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' - ** 255 : '1' - */ - - for (i = index; i < size; i++) { - b = fpgadata[i]; - if ((b >= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } - } -#endif - - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); - - /* - * Check if fpga's DONE signal - correctly booted ? - */ - - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(FPGA_DONE_STATE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } - } - - DBG ("FPGA: Booting successful!\n"); - return 0; -} diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c deleted file mode 100644 index 29421fc..0000000 --- a/board/esd/common/lcd.c +++ /dev/null @@ -1,359 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/io.h> -#include "lcd.h" - - -extern int video_display_bitmap (ulong, int, int); - - -int palette_index; -int palette_value; -int lcd_depth; -unsigned char *glob_lcd_reg; -unsigned char *glob_lcd_mem; - -#if defined(CONFIG_SYS_LCD_ENDIAN) -void lcd_setup(int lcd, int config) -{ - if (lcd == 0) { - /* - * Set endianess and reset lcd controller 0 (small) - */ - - /* set reset to low */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST); - udelay(10); /* wait 10us */ - if (config == 1) { - /* big-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); - } else { - /* little-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN); - } - udelay(10); /* wait 10us */ - /* set reset to high */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST); - } else { - /* - * Set endianess and reset lcd controller 1 (big) - */ - - /* set reset to low */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST); - udelay(10); /* wait 10us */ - if (config == 1) { - /* big-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); - } else { - /* little-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN); - } - udelay(10); /* wait 10us */ - /* set reset to high */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST); - } - - /* - * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); -} -#endif /* CONFIG_SYS_LCD_ENDIAN */ - - -int lcd_bmp(uchar *logo_bmp) -{ - int i; - uchar *ptr; - ushort *ptr2; - ushort val; - unsigned char *dst = NULL; - int x, y; - int width, height, bpp, colors, line_size; - int header_size; - unsigned char *bmp; - unsigned char r, g, b; - BITMAPINFOHEADER *bm_info; - ulong len; - - /* - * Check for bmp mark 'BM' - */ - if (*(ushort *)logo_bmp != 0x424d) { - /* - * Decompress bmp image - */ - len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; - dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); - if (dst == NULL) { - printf("Error: malloc for gunzip failed!\n"); - return 1; - } - if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, - (uchar *)logo_bmp, &len) != 0) { - free(dst); - return 1; - } - if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) { - printf("Image could be truncated" - " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); - } - - /* - * Check for bmp mark 'BM' - */ - if (*(ushort *)dst != 0x424d) { - printf("LCD: Unknown image format!\n"); - free(dst); - return 1; - } - } else { - /* - * Uncompressed BMP image, just use this pointer - */ - dst = (uchar *)logo_bmp; - } - - /* - * Get image info from bmp-header - */ - bm_info = (BITMAPINFOHEADER *)(dst + 14); - bpp = LOAD_SHORT(bm_info->biBitCount); - width = LOAD_LONG(bm_info->biWidth); - height = LOAD_LONG(bm_info->biHeight); - switch (bpp) { - case 1: - colors = 1; - line_size = width >> 3; - break; - case 4: - colors = 16; - line_size = width >> 1; - break; - case 8: - colors = 256; - line_size = width; - break; - case 24: - colors = 0; - line_size = width * 3; - break; - default: - printf("LCD: Unknown bpp (%d) im image!\n", bpp); - if ((dst != NULL) && (dst != (uchar *)logo_bmp)) - free(dst); - return 1; - } - printf(" (%d*%d, %dbpp)\n", width, height, bpp); - - /* - * Write color palette - */ - if ((colors <= 256) && (lcd_depth <= 8)) { - ptr = (unsigned char *)(dst + 14 + 40); - for (i = 0; i < colors; i++) { - b = *ptr++; - g = *ptr++; - r = *ptr++; - ptr++; - S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b); - } - } - - /* - * Write bitmap data into framebuffer - */ - ptr = glob_lcd_mem; - ptr2 = (ushort *)glob_lcd_mem; - header_size = 14 + 40 + 4*colors; /* skip bmp header */ - for (y = 0; y < height; y++) { - bmp = &dst[(height-1-y)*line_size + header_size]; - if (lcd_depth == 16) { - if (bpp == 24) { - for (x = 0; x < width; x++) { - /* - * Generate epson 16bpp fb-format - * from 24bpp image - */ - b = *bmp++ >> 3; - g = *bmp++ >> 2; - r = *bmp++ >> 3; - val = ((r & 0x1f) << 11) | - ((g & 0x3f) << 5) | - (b & 0x1f); - *ptr2++ = val; - } - } else if (bpp == 8) { - for (x = 0; x < line_size; x++) { - /* query rgb value from palette */ - ptr = (unsigned char *)(dst + 14 + 40); - ptr += (*bmp++) << 2; - b = *ptr++ >> 3; - g = *ptr++ >> 2; - r = *ptr++ >> 3; - val = ((r & 0x1f) << 11) | - ((g & 0x3f) << 5) | - (b & 0x1f); - *ptr2++ = val; - } - } - } else { - for (x = 0; x < line_size; x++) - *ptr++ = *bmp++; - } - } - - if ((dst != NULL) && (dst != (uchar *)logo_bmp)) - free(dst); - return 0; -} - - -int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, - uchar *logo_bmp, ulong len) -{ - int i; - ushort s1dReg; - uchar s1dValue; - int reg_byte_swap; - - /* - * Detect epson - */ - out_8(&lcd_reg[0], 0x00); - out_8(&lcd_reg[1], 0x00); - - if (in_8(&lcd_reg[0]) == 0x1c) { - /* - * Big epson detected - */ - reg_byte_swap = false; - palette_index = 0x1e2; - palette_value = 0x1e4; - lcd_depth = 16; - puts("LCD: S1D13806"); - } else if (in_8(&lcd_reg[1]) == 0x1c) { - /* - * Big epson detected (with register swap bug) - */ - reg_byte_swap = true; - palette_index = 0x1e3; - palette_value = 0x1e5; - lcd_depth = 16; - puts("LCD: S1D13806S"); - } else if (in_8(&lcd_reg[0]) == 0x18) { - /* - * Small epson detected (704) - */ - reg_byte_swap = false; - palette_index = 0x15; - palette_value = 0x17; - lcd_depth = 8; - puts("LCD: S1D13704"); - } else if (in_8(&lcd_reg[0x10000]) == 0x24) { - /* - * Small epson detected (705) - */ - reg_byte_swap = false; - palette_index = 0x15; - palette_value = 0x17; - lcd_depth = 8; - lcd_reg += 0x10000; /* add offset for 705 regs */ - puts("LCD: S1D13705"); - } else { - out_8(&lcd_reg[0x1a], 0x00); - udelay(1000); - if (in_8(&lcd_reg[1]) == 0x0c) { - /* - * S1D13505 detected - */ - reg_byte_swap = true; - palette_index = 0x25; - palette_value = 0x27; - lcd_depth = 16; - - puts("LCD: S1D13505"); - } else { - puts("LCD: No controller detected!\n"); - return 1; - } - } - - /* - * Setup lcd controller regs - */ - for (i = 0; i < reg_count; i++) { - s1dReg = regs[i].Index; - if (reg_byte_swap) { - if ((s1dReg & 0x0001) == 0) - s1dReg |= 0x0001; - else - s1dReg &= ~0x0001; - } - s1dValue = regs[i].Value; - out_8(&lcd_reg[s1dReg], s1dValue); - } - - /* - * Save reg & mem pointer for later usage (e.g. bmp command) - */ - glob_lcd_reg = lcd_reg; - glob_lcd_mem = lcd_mem; - - /* - * Display bmp image - */ - return lcd_bmp(logo_bmp); -} - -int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; -#ifdef CONFIG_VIDEO_SM501 - char *str; -#endif - if (argc != 2) - return cmd_usage(cmdtp); - - addr = simple_strtoul(argv[1], NULL, 16); - -#ifdef CONFIG_VIDEO_SM501 - str = getenv("bd_type"); - if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) { - /* - * SM501 available, use standard bmp command - */ - return video_display_bitmap(addr, 0, 0); - } else { - /* - * No SM501 available, use esd epson bmp command - */ - return lcd_bmp((uchar *)addr); - } -#else - return lcd_bmp((uchar *)addr); -#endif -} - -U_BOOT_CMD( - esdbmp, 2, 1, do_esdbmp, - "display BMP image", - "<imageAddr> - display image" -); diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h deleted file mode 100644 index 5b14bf9..0000000 --- a/board/esd/common/lcd.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Neutralize little endians. - */ -#define SWAP_LONG(data) ((unsigned long) \ - (((unsigned long)(data) >> 24) | \ - ((unsigned long)(data) << 24) | \ - (((unsigned long)(data) >> 8) & 0x0000ff00 ) | \ - (((unsigned long)(data) << 8) & 0x00ff0000 ))) -#define SWAP_SHORT(data) ((unsigned short) \ - (((unsigned short)(data) >> 8 ) | \ - ((unsigned short)(data) << 8 ))) -#define LOAD_LONG(data) SWAP_LONG(data) -#define LOAD_SHORT(data) SWAP_SHORT(data) - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ - { \ - out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \ - out_8(&((uchar*)(p))[palette_index], (uchar)(r)); \ - out_8(&((uchar*)(p))[palette_index], (uchar)(g)); \ - out_8(&((uchar*)(p))[palette_index], (uchar)(b)); \ - } - -typedef struct -{ - ushort Index; - uchar Value; -} S1D_REGS; - -typedef struct /**** BMP file info structure ****/ -{ - unsigned int biSize; /* Size of info header */ - int biWidth; /* Width of image */ - int biHeight; /* Height of image */ - unsigned short biPlanes; /* Number of color planes */ - unsigned short biBitCount; /* Number of bits per pixel */ - unsigned int biCompression; /* Type of compression to use */ - unsigned int biSizeImage; /* Size of image data */ - int biXPelsPerMeter; /* X pixels per meter */ - int biYPelsPerMeter; /* Y pixels per meter */ - unsigned int biClrUsed; /* Number of colors used */ - unsigned int biClrImportant; /* Number of important colors */ -} BITMAPINFOHEADER; diff --git a/board/esd/common/misc.c b/board/esd/common/misc.c deleted file mode 100644 index 79cd612..0000000 --- a/board/esd/common/misc.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#ifdef CONFIG_LXT971_NO_SLEEP -#include <miiphy.h> -#endif - - -#ifdef CONFIG_LXT971_NO_SLEEP -void lxt971_no_sleep(void) -{ - unsigned short reg; - - miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, ®); - reg &= ~0x0040; /* disable sleep mode */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg); -} -#endif /* CONFIG_LXT971_NO_SLEEP */ diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c deleted file mode 100644 index faebdb1..0000000 --- a/board/esd/common/pci.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <pci.h> - - -u_long pci9054_iobase; - - -#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */ -#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */ - - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_read_config_dword -| Description: Read a PCI configuration register -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| value Address of the configuration register value -| Return value: -| 0 Successful -+-----------------------------------------------------------------------------*/ -int pci9054_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32* value) -{ - unsigned long conAdrVal; - unsigned long val; - - /* generate coded value for CON_ADR register */ - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */ - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - /* Note: *pResult comes back as -1 if machine check happened */ - val = in32r(PCI_PRIMARY_CDR); - - *value = (unsigned long) val; - - out32r(PCI_PRIMARY_CAR, 0); - - if ((*(unsigned long *)0x50000304) & 0x60000000) - { - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - } - - return 0; -} - -/*-----------------------------------------------------------------------------+ -| Subroutine: pci9054_write_config_dword -| Description: Write a PCI configuration register. -| Inputs: -| hose PCI Controller -| dev PCI Bus+Device+Function number -| offset Configuration register number -| Value Configuration register value -| Return value: -| 0 Successful -| Updated for pass2 errata #6. Need to disable interrupts and clear the -| PCICFGADR reg after writing the PCICFGDATA reg. -+-----------------------------------------------------------------------------*/ -int pci9054_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - unsigned long conAdrVal; - - conAdrVal = dev | (offset & 0xfc) | 0x80000000; - - *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal; - - out32r(PCI_PRIMARY_CDR, value); - - out32r(PCI_PRIMARY_CAR, 0); - - /* clear pci master/target abort bits */ - *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304; - - return (0); -} - -/*----------------------------------------------------------------------- - */ - -#ifdef CONFIG_DASA_SIM -static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *_) -{ - unsigned int iobase; - unsigned short status = 0; - unsigned char timer; - - /* - * Configure PLX PCI9054 - */ - pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status); - status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status); - - /* Check the latency timer for values >= 0x60. - */ - pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); - if (timer < 0x60) - { - pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); - } - - /* Set I/O base register. - */ - pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE); - pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - - pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); - - if (pci9054_iobase == 0xffffffff) - { - printf("Error: Can not set I/O base register.\n"); - return; - } -} -#endif - -static struct pci_config_table pci9054_config_table[] = { -#ifndef CONFIG_PCI_PNP - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN), - pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE, - CONFIG_SYS_ETH_IOBASE, - PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, -#ifdef CONFIG_DASA_SIM - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN), - pci_dasa_sim_config_pci9054 }, -#endif -#endif - { } -}; - -static struct pci_controller pci9054_hose = { - config_table: pci9054_config_table, -}; - -void pci_init_board(void) -{ - struct pci_controller *hose = &pci9054_hose; - - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* System memory space */ - pci_set_region(hose->regions + 0, - 0x00000000, 0x00000000, 0x01000000, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI Memory space */ - pci_set_region(hose->regions + 1, - 0x00000000, 0xc0000000, 0x10000000, - PCI_REGION_MEM); - - pci_set_ops(hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - pci9054_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - pci9054_write_config_dword); - - hose->region_count = 2; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -} diff --git a/board/esd/common/s1d13505_640_480_16bpp.h b/board/esd/common/s1d13505_640_480_16bpp.h deleted file mode 100644 index ca11683..0000000 --- a/board/esd/common/s1d13505_640_480_16bpp.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2008 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz) - * Memory: DRAM (MCLK=40.000 MHz) - */ -static S1D_REGS regs_13505_640_480_16bpp[] = -{ - {0x1B,0x00}, /* Miscellaneous Register */ - {0x23,0x20}, /* Performance Enhancement Register 1 */ - {0x01,0x30}, /* Memory Configuration Register */ - {0x22,0x24}, /* Performance Enhancement Register 0 */ - {0x02,0x25}, /* Panel Type Register */ - {0x03,0x00}, /* MOD Rate Register */ - {0x04,0x4F}, /* Horizontal Display Width Register */ - {0x05,0x0c}, /* Horizontal Non-Display Period Register */ - {0x06,0x00}, /* HRTC/FPLINE Start Position Register */ - {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */ - {0x08,0xDF}, /* Vertical Display Height Register 0 */ - {0x09,0x01}, /* Vertical Display Height Register 1 */ - {0x0A,0x3E}, /* Vertical Non-Display Period Register */ - {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */ - {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */ - {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */ - {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */ - {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */ - {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */ - {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */ - {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */ - {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */ - {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */ - {0x16,0x80}, /* Memory Address Offset Register 0 */ - {0x17,0x02}, /* Memory Address Offset Register 1 */ - {0x18,0x00}, /* Pixel Panning Register */ - {0x19,0x01}, /* Clock Configuration Register */ - {0x1A,0x00}, /* Power Save Configuration Register */ - {0x1C,0x00}, /* MD Configuration Readback Register 0 */ - {0x1E,0x06}, /* General IO Pins Configuration Register 0 */ - {0x1F,0x00}, /* General IO Pins Configuration Register 1 */ - {0x20,0x00}, /* General IO Pins Control Register 0 */ - {0x21,0x00}, /* General IO Pins Control Register 1 */ - {0x23,0x20}, /* Performance Enhancement Register 1 */ - {0x0D,0x15}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13704_320_240_4bpp.h b/board/esd/common/s1d13704_320_240_4bpp.h deleted file mode 100644 index bd910e8..0000000 --- a/board/esd/common/s1d13704_320_240_4bpp.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Generic Header information generated by 13704CFG.EXE (Build 10) - * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz) - */ - -static S1D_REGS regs_13704_320_240_4bpp[] = -{ - { 0x00, 0x00 }, /* Revision Code Register */ - { 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */ - { 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */ - { 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */ - { 0x04, 0x27 }, /* Horizontal Panel Size Register */ - { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ - { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ - { 0x07, 0x00 }, /* FPLINE Start Position Register */ - { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ - { 0x09, 0x00 }, /* FPFRAME Start Position Register */ - { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ - { 0x0B, 0x00 }, /* MOD Rate Register */ - { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ - { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ - { 0x0E, 0x00 }, /* Not Used */ - { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ - { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ - { 0x11, 0x00 }, /* Not Used */ - { 0x12, 0x00 }, /* Memory Address Offset Register */ - { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ - { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ - { 0x15, 0x00 }, /* Look-Up Table Address Register */ - { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ - { 0x17, 0x00 }, /* Look-Up Table Data Register */ - { 0x18, 0x01 }, /* GPIO Configuration Control Register */ - { 0x19, 0x01 }, /* GPIO Status/Control Register */ - { 0x1A, 0x00 }, /* Scratch Pad Register */ - { 0x1B, 0x00 }, /* SwivelView Mode Register */ - { 0x1C, 0xA0 }, /* Line Byte Count Register */ - { 0x1D, 0x00 }, /* Not Used */ - { 0x1E, 0x00 }, /* Not Used */ - { 0x1F, 0x00 }, /* Not Used */ -}; diff --git a/board/esd/common/s1d13705_320_240_8bpp.h b/board/esd/common/s1d13705_320_240_8bpp.h deleted file mode 100644 index 041b4a9..0000000 --- a/board/esd/common/s1d13705_320_240_8bpp.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Generic Header information generated by 13704CFG.EXE (Build 10) - * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz) - */ - -static S1D_REGS regs_13705_320_240_8bpp[] = -{ - { 0x00, 0x00 }, /* Revision Code Register */ - { 0x01, 0x23 }, /* Mode Register 0 Register */ - { 0x02, 0xE0 }, /* Mode Register 1 Register */ - { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */ - { 0x04, 0x27 }, /* Horizontal Panel Size Register */ - { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ - { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ - { 0x07, 0x00 }, /* FPLINE Start Position Register */ - { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ - { 0x09, 0x01 }, /* FPFRAME Start Position Register */ - { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ - { 0x0B, 0x00 }, /* MOD Rate Register */ - { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ - { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ - { 0x0E, 0x00 }, /* Not Used */ - { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ - { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ - { 0x11, 0x00 }, /* Not Used */ - { 0x12, 0x00 }, /* Memory Address Offset Register */ - { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ - { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ - { 0x15, 0x00 }, /* Look-Up Table Address Register */ - { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ - { 0x17, 0x00 }, /* Look-Up Table Data Register */ - { 0x18, 0x01 }, /* GPIO Configuration Control Register */ - { 0x19, 0x01 }, /* GPIO Status/Control Register */ - { 0x1A, 0x00 }, /* Scratch Pad Register */ - { 0x1B, 0x00 }, /* SwivelView Mode Register */ - { 0x1C, 0xFF }, /* Line Byte Count Register */ - { 0x1D, 0x00 }, /* Not Used */ - { 0x1E, 0x00 }, /* Not Used */ - { 0x1F, 0x00 }, /* Not Used */ -}; diff --git a/board/esd/common/s1d13806_1024_768_8bpp.h b/board/esd/common/s1d13806_1024_768_8bpp.h deleted file mode 100644 index 615fa33..0000000 --- a/board/esd/common/s1d13806_1024_768_8bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_1024_768_8bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x00}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x00}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x01}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x55}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x7F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x02}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x03}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x00}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13806_320_240_4bpp.h b/board/esd/common/s1d13806_320_240_4bpp.h deleted file mode 100644 index 2531f47..0000000 --- a/board/esd/common/s1d13806_320_240_4bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_320_240_4bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x08}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x08}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x08}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x32}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x00}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x27}, /* LCD Horizontal Display Width Register */ - {0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x01}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x00}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x02}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x50}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x00}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x03}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/s1d13806_640_480_16bpp.h b/board/esd/common/s1d13806_640_480_16bpp.h deleted file mode 100644 index 38fc1a7..0000000 --- a/board/esd/common/s1d13806_640_480_16bpp.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2000,2001 Epson Research and Development, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * File generated by S1D13806CFG.EXE - * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) - * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) - */ - -static S1D_REGS regs_13806_640_480_16bpp[] = -{ - {0x0001,0x00}, /* Miscellaneous Register */ - {0x01FC,0x00}, /* Display Mode Register */ - {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ - {0x0008,0x18}, /* General IO Pins Control Register 0 */ - {0x0009,0x00}, /* General IO Pins Control Register 1 */ - {0x0010,0x00}, /* Memory Clock Configuration Register */ - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ - {0x0021,0x03}, /* DRAM Refresh Rate Register */ - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ - {0x0020,0x80}, /* Memory Configuration Register */ - {0x0030,0x25}, /* Panel Type Register */ - {0x0031,0x00}, /* MOD Rate Register */ - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ - {0x0035,0x00}, /* TFT FPLINE Start Position Register */ - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ - {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ - {0x0040,0x05}, /* LCD Display Mode Register */ - {0x0041,0x00}, /* LCD Miscellaneous Register */ - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ - {0x0048,0x00}, /* LCD Pixel Panning Register */ - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ - {0x005B,0x10}, /* TV Output Control Register */ - {0x0060,0x05}, /* CRT/TV Display Mode Register */ - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ - {0x0100,0x00}, /* BitBlt Control Register 0 */ - {0x0101,0x00}, /* BitBlt Control Register 1 */ - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ - {0x0103,0x00}, /* BitBlt Operation Register */ - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ - {0x0110,0x00}, /* BitBlt Width Register 0 */ - {0x0111,0x00}, /* BitBlt Width Register 1 */ - {0x0112,0x00}, /* BitBlt Height Register 0 */ - {0x0113,0x00}, /* BitBlt Height Register 1 */ - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ - {0x01E0,0x00}, /* Look-Up Table Mode Register */ - {0x01E2,0x00}, /* Look-Up Table Address Register */ - {0x01F0,0x10}, /* Power Save Configuration Register */ - {0x01F1,0x00}, /* Power Save Status Register */ - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ - {0x01FC,0x01}, /* Display Mode Register */ -}; diff --git a/board/esd/common/xilinx_jtag/lenval.c b/board/esd/common/xilinx_jtag/lenval.c deleted file mode 100644 index 5405efb..0000000 --- a/board/esd/common/xilinx_jtag/lenval.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*******************************************************/ -/* file: lenval.c */ -/* abstract: This file contains routines for using */ -/* the lenVal data structure. */ -/*******************************************************/ - -#include <common.h> -#include <asm/processor.h> - -#include "lenval.h" -#include "ports.h" - - -/***************************************************************************** - * Function: value - * Description: Extract the long value from the lenval array. - * Parameters: plvValue - ptr to lenval. - * Returns: long - the extracted value. - *****************************************************************************/ -long value( lenVal* plvValue ) -{ - long lValue; /* result to hold the accumulated result */ - short sIndex; - - lValue = 0; - for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex ) - { - lValue <<= 8; /* shift the accumulated result */ - lValue |= plvValue->val[ sIndex]; /* get the last byte first */ - } - - return( lValue ); -} - -/***************************************************************************** - * Function: initLenVal - * Description: Initialize the lenval array with the given value. - * Assumes lValue is less than 256. - * Parameters: plv - ptr to lenval. - * lValue - the value to set. - * Returns: void. - *****************************************************************************/ -void initLenVal( lenVal* plv, - long lValue ) -{ - plv->len = 1; - plv->val[0] = (unsigned char)lValue; -} - -/***************************************************************************** - * Function: EqualLenVal - * Description: Compare two lenval arrays with an optional mask. - * Parameters: plvTdoExpected - ptr to lenval #1. - * plvTdoCaptured - ptr to lenval #2. - * plvTdoMask - optional ptr to mask (=0 if no mask). - * Returns: short - 0 = mismatch; 1 = equal. - *****************************************************************************/ -short EqualLenVal( lenVal* plvTdoExpected, - lenVal* plvTdoCaptured, - lenVal* plvTdoMask ) -{ - short sEqual; - short sIndex; - unsigned char ucByteVal1; - unsigned char ucByteVal2; - unsigned char ucByteMask; - - sEqual = 1; - sIndex = plvTdoExpected->len; - - while ( sEqual && sIndex-- ) - { - ucByteVal1 = plvTdoExpected->val[ sIndex ]; - ucByteVal2 = plvTdoCaptured->val[ sIndex ]; - if ( plvTdoMask ) - { - ucByteMask = plvTdoMask->val[ sIndex ]; - ucByteVal1 &= ucByteMask; - ucByteVal2 &= ucByteMask; - } - if ( ucByteVal1 != ucByteVal2 ) - { - sEqual = 0; - } - } - - return( sEqual ); -} - - -/***************************************************************************** - * Function: RetBit - * Description: return the (byte, bit) of lv (reading from left to right). - * Parameters: plv - ptr to lenval. - * iByte - the byte to get the bit from. - * iBit - the bit number (0=msb) - * Returns: short - the bit value. - *****************************************************************************/ -short RetBit( lenVal* plv, - int iByte, - int iBit ) -{ - /* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */ - /* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */ - return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) ); -} - -/***************************************************************************** - * Function: SetBit - * Description: set the (byte, bit) of lv equal to val - * Example: SetBit("00000000",byte, 1) equals "01000000". - * Parameters: plv - ptr to lenval. - * iByte - the byte to get the bit from. - * iBit - the bit number (0=msb). - * sVal - the bit value to set. - * Returns: void. - *****************************************************************************/ -void SetBit( lenVal* plv, - int iByte, - int iBit, - short sVal ) -{ - unsigned char ucByteVal; - unsigned char ucBitMask; - - ucBitMask = (unsigned char)(1 << ( 7 - iBit )); - ucByteVal = (unsigned char)(plv->val[ iByte ] & (~ucBitMask)); - - if ( sVal ) - { - ucByteVal |= ucBitMask; - } - plv->val[ iByte ] = ucByteVal; -} - -/***************************************************************************** - * Function: AddVal - * Description: add val1 to val2 and store in resVal; - * assumes val1 and val2 are of equal length. - * Parameters: plvResVal - ptr to result. - * plvVal1 - ptr of addendum. - * plvVal2 - ptr of addendum. - * Returns: void. - *****************************************************************************/ -void addVal( lenVal* plvResVal, - lenVal* plvVal1, - lenVal* plvVal2 ) -{ - unsigned char ucCarry; - unsigned short usSum; - unsigned short usVal1; - unsigned short usVal2; - short sIndex; - - plvResVal->len = plvVal1->len; /* set up length of result */ - - /* start at least significant bit and add bytes */ - ucCarry = 0; - sIndex = plvVal1->len; - while ( sIndex-- ) - { - usVal1 = plvVal1->val[ sIndex ]; /* i'th byte of val1 */ - usVal2 = plvVal2->val[ sIndex ]; /* i'th byte of val2 */ - - /* add the two bytes plus carry from previous addition */ - usSum = (unsigned short)( usVal1 + usVal2 + ucCarry ); - - /* set up carry for next byte */ - ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 ); - - /* set the i'th byte of the result */ - plvResVal->val[ sIndex ] = (unsigned char)usSum; - } -} - -/***************************************************************************** - * Function: readVal - * Description: read from XSVF numBytes bytes of data into x. - * Parameters: plv - ptr to lenval in which to put the bytes read. - * sNumBytes - the number of bytes to read. - * Returns: void. - *****************************************************************************/ -void readVal( lenVal* plv, - short sNumBytes ) -{ - unsigned char* pucVal; - - plv->len = sNumBytes; /* set the length of the lenVal */ - for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal ) - { - /* read a byte of data into the lenVal */ - readByte( pucVal ); - } -} diff --git a/board/esd/common/xilinx_jtag/lenval.h b/board/esd/common/xilinx_jtag/lenval.h deleted file mode 100644 index 3273eec..0000000 --- a/board/esd/common/xilinx_jtag/lenval.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*******************************************************/ -/* file: lenval.h */ -/* abstract: This file contains a description of the */ -/* data structure "lenval". */ -/*******************************************************/ - -#ifndef lenval_dot_h -#define lenval_dot_h - -/* the lenVal structure is a byte oriented type used to store an */ -/* arbitrary length binary value. As an example, the hex value */ -/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes */ -/* and val[0]=0e and val[1]=3d. val[2-MAX_LEN] are undefined */ - -/* maximum length (in bytes) of value to read in */ -/* this needs to be at least 4, and longer than the */ -/* length of the longest SDR instruction. If there is, */ -/* only 1 device in the chain, MAX_LEN must be at least */ -/* ceil(27/8) == 4. For 6 devices in a chain, MAX_LEN */ -/* must be 5, for 14 devices MAX_LEN must be 6, for 20 */ -/* devices MAX_LEN must be 7, etc.. */ -/* You can safely set MAX_LEN to a smaller number if you*/ -/* know how many devices will be in your chain. */ -#define MAX_LEN 7000 - - -typedef struct var_len_byte -{ - short len; /* number of chars in this value */ - unsigned char val[MAX_LEN+1]; /* bytes of data */ -} lenVal; - - -/* return the long representation of a lenVal */ -extern long value(lenVal *x); - -/* set lenVal equal to value */ -extern void initLenVal(lenVal *x, long value); - -/* check if expected equals actual (taking the mask into account) */ -extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask); - -/* add val1+val2 and put the result in resVal */ -extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2); - -/* return the (byte, bit) of lv (reading from left to right) */ -extern short RetBit(lenVal *lv, int byte, int bit); - -/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1) - equals "01000000" */ -extern void SetBit(lenVal *lv, int byte, int bit, short val); - -/* read from XSVF numBytes bytes of data into x */ -extern void readVal(lenVal *x, short numBytes); - -#endif diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c deleted file mode 100644 index 556636c..0000000 --- a/board/esd/common/xilinx_jtag/micro.c +++ /dev/null @@ -1,1854 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/***************************************************************************** - * file: micro.c - * abstract: This file contains the function, xsvfExecute(), - * call for interpreting the XSVF commands. - * Usage: Call xsvfExecute() to process XSVF data. - * The XSVF data is retrieved by readByte() in ports.c - * Remove the main function if you already have one. - * Options: XSVF_SUPPORT_COMPRESSION - * This define supports the XC9500/XL compression scheme. - * This define adds support for XSDRINC and XSETSDRMASKS. - * XSVF_SUPPORT_ERRORCODES - * This define causes the xsvfExecute function to return - * an error code for specific errors. See error codes below. - * If this is not defined, the return value defaults to the - * legacy values for backward compatibility: - * 1 = success; 0 = failure. - * Debugging: DEBUG_MODE (Legacy name) - * Define DEBUG_MODE to compile with debugging features. - * Both micro.c and ports.c must be compiled with the DEBUG_MODE - * defined to enable the standalone main implementation in - * micro.c that reads XSVF from a file. - * History: v2.00 - Original XSVF implementation. - * v4.04 - Added delay at end of XSIR for XC18v00 support. - * Added new commands for CoolRunner support: - * XSTATE, XENDIR, XENDDR - * v4.05 - Cleanup micro.c but leave ports.c intact. - * v4.06 - Fix xsvfGotoTapState for retry transition. - * v4.07 - Update example waitTime implementations for - * compatibility with Virtex-II. - * v4.10 - Add new XSIR2 command that supports a 2-byte - * IR-length parameter for IR shifts > 255 bits. - * v4.11 - No change. Update version to match SVF2XSVF xlator. - * v4.14 - Added XCOMMENT. - * v5.00 - Improve XSTATE support. - * Added XWAIT. - *****************************************************************************/ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> - -#include "micro.h" -#include "lenval.h" -#include "ports.h" - -const unsigned char *xsvfdata; - -/*============================================================================ - * XSVF #define - ============================================================================*/ - -#define XSVF_VERSION "5.00" - -/***************************************************************************** - * Define: XSVF_SUPPORT_COMPRESSION - * Description: Define this to support the XC9500/XL XSVF data compression - * scheme. - * Code size can be reduced by NOT supporting this feature. - * However, you must use the -nc (no compress) option when - * translating SVF to XSVF using the SVF2XSVF translator. - * Corresponding, uncompressed XSVF may be larger. - *****************************************************************************/ -#ifndef XSVF_SUPPORT_COMPRESSION -#define XSVF_SUPPORT_COMPRESSION 1 -#endif - -/***************************************************************************** - * Define: XSVF_SUPPORT_ERRORCODES - * Description: Define this to support the new XSVF error codes. - * (The original XSVF player just returned 1 for success and - * 0 for an unspecified failure.) - *****************************************************************************/ -#ifndef XSVF_SUPPORT_ERRORCODES -#define XSVF_SUPPORT_ERRORCODES 1 -#endif - -#ifdef XSVF_SUPPORT_ERRORCODES -#define XSVF_ERRORCODE(errorCode) errorCode -#else /* Use legacy error code */ -#define XSVF_ERRORCODE(errorCode) ((errorCode==XSVF_ERROR_NONE)?1:0) -#endif /* XSVF_SUPPORT_ERRORCODES */ - - -/*============================================================================ - * DEBUG_MODE #define - ============================================================================*/ -#define DEBUG_MODE - -#ifdef DEBUG_MODE -#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat ); } -#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1 ); } -#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1, arg2 ); } -#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - printf( pzFormat, arg1, arg2, arg3 ); } -#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \ - { if ( xsvf_iDebugLevel >= iDebugLevel ) \ - xsvfPrintLenVal(plenVal); } -#else /* !DEBUG_MODE */ -#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) -#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) -#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) -#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) -#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) -#endif /* DEBUG_MODE */ - - -/*============================================================================ - * XSVF Type Declarations - ============================================================================*/ - -/***************************************************************************** - * Struct: SXsvfInfo - * Description: This structure contains all of the data used during the - * execution of the XSVF. Some data is persistent, predefined - * information (e.g. lRunTestTime). The bulk of this struct's - * size is due to the lenVal structs (defined in lenval.h) - * which contain buffers for the active shift data. The MAX_LEN - * #define in lenval.h defines the size of these buffers. - * These buffers must be large enough to store the longest - * shift data in your XSVF file. For example: - * MAX_LEN >= ( longest_shift_data_in_bits / 8 ) - * Because the lenVal struct dominates the space usage of this - * struct, the rough size of this struct is: - * sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals) - * xsvfInitialize() contains initialization code for the data - * in this struct. - * xsvfCleanup() contains cleanup code for the data in this - * struct. - *****************************************************************************/ -typedef struct tagSXsvfInfo -{ - /* XSVF status information */ - unsigned char ucComplete; /* 0 = running; 1 = complete */ - unsigned char ucCommand; /* Current XSVF command byte */ - long lCommandCount; /* Number of commands processed */ - int iErrorCode; /* An error code. 0 = no error. */ - - /* TAP state/sequencing information */ - unsigned char ucTapState; /* Current TAP state */ - unsigned char ucEndIR; /* ENDIR TAP state (See SVF) */ - unsigned char ucEndDR; /* ENDDR TAP state (See SVF) */ - - /* RUNTEST information */ - unsigned char ucMaxRepeat; /* Max repeat loops (for xc9500/xl) */ - long lRunTestTime; /* Pre-specified RUNTEST time (usec) */ - - /* Shift Data Info and Buffers */ - long lShiftLengthBits; /* Len. current shift data in bits */ - short sShiftLengthBytes; /* Len. current shift data in bytes */ - - lenVal lvTdi; /* Current TDI shift data */ - lenVal lvTdoExpected; /* Expected TDO shift data */ - lenVal lvTdoCaptured; /* Captured TDO shift data */ - lenVal lvTdoMask; /* TDO mask: 0=dontcare; 1=compare */ - -#ifdef XSVF_SUPPORT_COMPRESSION - /* XSDRINC Data Buffers */ - lenVal lvAddressMask; /* Address mask for XSDRINC */ - lenVal lvDataMask; /* Data mask for XSDRINC */ - lenVal lvNextData; /* Next data for XSDRINC */ -#endif /* XSVF_SUPPORT_COMPRESSION */ -} SXsvfInfo; - -/* Declare pointer to functions that perform XSVF commands */ -typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* ); - -/*============================================================================ - * XSVF Command Bytes - ============================================================================*/ - -/* encodings of xsvf instructions */ -#define XCOMPLETE 0 -#define XTDOMASK 1 -#define XSIR 2 -#define XSDR 3 -#define XRUNTEST 4 -/* Reserved 5 */ -/* Reserved 6 */ -#define XREPEAT 7 -#define XSDRSIZE 8 -#define XSDRTDO 9 -#define XSETSDRMASKS 10 -#define XSDRINC 11 -#define XSDRB 12 -#define XSDRC 13 -#define XSDRE 14 -#define XSDRTDOB 15 -#define XSDRTDOC 16 -#define XSDRTDOE 17 -#define XSTATE 18 /* 4.00 */ -#define XENDIR 19 /* 4.04 */ -#define XENDDR 20 /* 4.04 */ -#define XSIR2 21 /* 4.10 */ -#define XCOMMENT 22 /* 4.14 */ -#define XWAIT 23 /* 5.00 */ -/* Insert new commands here */ -/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */ -#define XLASTCMD 24 /* Last command marker */ - - -/*============================================================================ - * XSVF Command Parameter Values - ============================================================================*/ - -#define XSTATE_RESET 0 /* 4.00 parameter for XSTATE */ -#define XSTATE_RUNTEST 1 /* 4.00 parameter for XSTATE */ - -#define XENDXR_RUNTEST 0 /* 4.04 parameter for XENDIR/DR */ -#define XENDXR_PAUSE 1 /* 4.04 parameter for XENDIR/DR */ - -/* TAP states */ -#define XTAPSTATE_RESET 0x00 -#define XTAPSTATE_RUNTEST 0x01 /* a.k.a. IDLE */ -#define XTAPSTATE_SELECTDR 0x02 -#define XTAPSTATE_CAPTUREDR 0x03 -#define XTAPSTATE_SHIFTDR 0x04 -#define XTAPSTATE_EXIT1DR 0x05 -#define XTAPSTATE_PAUSEDR 0x06 -#define XTAPSTATE_EXIT2DR 0x07 -#define XTAPSTATE_UPDATEDR 0x08 -#define XTAPSTATE_IRSTATES 0x09 /* All IR states begin here */ -#define XTAPSTATE_SELECTIR 0x09 -#define XTAPSTATE_CAPTUREIR 0x0A -#define XTAPSTATE_SHIFTIR 0x0B -#define XTAPSTATE_EXIT1IR 0x0C -#define XTAPSTATE_PAUSEIR 0x0D -#define XTAPSTATE_EXIT2IR 0x0E -#define XTAPSTATE_UPDATEIR 0x0F - -/*============================================================================ - * XSVF Function Prototypes - ============================================================================*/ - -int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ); /* Illegal command function */ -int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSIR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo ); -int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo ); -int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo ); -int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo ); -int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo ); -/* Insert new command functions here */ - -/*============================================================================ - * XSVF Global Variables - ============================================================================*/ - -/* Array of XSVF command functions. Must follow command byte value order! */ -/* If your compiler cannot take this form, then convert to a switch statement*/ -TXsvfDoCmdFuncPtr xsvf_pfDoCmd[] = -{ - xsvfDoXCOMPLETE, /* 0 */ - xsvfDoXTDOMASK, /* 1 */ - xsvfDoXSIR, /* 2 */ - xsvfDoXSDR, /* 3 */ - xsvfDoXRUNTEST, /* 4 */ - xsvfDoIllegalCmd, /* 5 */ - xsvfDoIllegalCmd, /* 6 */ - xsvfDoXREPEAT, /* 7 */ - xsvfDoXSDRSIZE, /* 8 */ - xsvfDoXSDRTDO, /* 9 */ -#ifdef XSVF_SUPPORT_COMPRESSION - xsvfDoXSETSDRMASKS, /* 10 */ - xsvfDoXSDRINC, /* 11 */ -#else - xsvfDoIllegalCmd, /* 10 */ - xsvfDoIllegalCmd, /* 11 */ -#endif /* XSVF_SUPPORT_COMPRESSION */ - xsvfDoXSDRBCE, /* 12 */ - xsvfDoXSDRBCE, /* 13 */ - xsvfDoXSDRBCE, /* 14 */ - xsvfDoXSDRTDOBCE, /* 15 */ - xsvfDoXSDRTDOBCE, /* 16 */ - xsvfDoXSDRTDOBCE, /* 17 */ - xsvfDoXSTATE, /* 18 */ - xsvfDoXENDXR, /* 19 */ - xsvfDoXENDXR, /* 20 */ - xsvfDoXSIR2, /* 21 */ - xsvfDoXCOMMENT, /* 22 */ - xsvfDoXWAIT /* 23 */ -/* Insert new command functions here */ -}; - -#ifdef DEBUG_MODE -char* xsvf_pzCommandName[] = -{ - "XCOMPLETE", - "XTDOMASK", - "XSIR", - "XSDR", - "XRUNTEST", - "Reserved5", - "Reserved6", - "XREPEAT", - "XSDRSIZE", - "XSDRTDO", - "XSETSDRMASKS", - "XSDRINC", - "XSDRB", - "XSDRC", - "XSDRE", - "XSDRTDOB", - "XSDRTDOC", - "XSDRTDOE", - "XSTATE", - "XENDIR", - "XENDDR", - "XSIR2", - "XCOMMENT", - "XWAIT" -}; - -char* xsvf_pzErrorName[] = -{ - "No error", - "ERROR: Unknown", - "ERROR: TDO mismatch", - "ERROR: TDO mismatch and exceeded max retries", - "ERROR: Unsupported XSVF command", - "ERROR: Illegal state specification", - "ERROR: Data overflows allocated MAX_LEN buffer size" -}; - -char* xsvf_pzTapState[] = -{ - "RESET", /* 0x00 */ - "RUNTEST/IDLE", /* 0x01 */ - "DRSELECT", /* 0x02 */ - "DRCAPTURE", /* 0x03 */ - "DRSHIFT", /* 0x04 */ - "DREXIT1", /* 0x05 */ - "DRPAUSE", /* 0x06 */ - "DREXIT2", /* 0x07 */ - "DRUPDATE", /* 0x08 */ - "IRSELECT", /* 0x09 */ - "IRCAPTURE", /* 0x0A */ - "IRSHIFT", /* 0x0B */ - "IREXIT1", /* 0x0C */ - "IRPAUSE", /* 0x0D */ - "IREXIT2", /* 0x0E */ - "IRUPDATE" /* 0x0F */ -}; -#endif /* DEBUG_MODE */ - -/*#ifdef DEBUG_MODE */ -/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */ -int xsvf_iDebugLevel; -/*#endif /XXX* DEBUG_MODE */ - -/*============================================================================ - * Utility Functions - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfPrintLenVal - * Description: Print the lenval value in hex. - * Parameters: plv - ptr to lenval. - * Returns: void. - *****************************************************************************/ -#ifdef DEBUG_MODE -void xsvfPrintLenVal( lenVal *plv ) -{ - int i; - - if ( plv ) - { - printf( "0x" ); - for ( i = 0; i < plv->len; ++i ) - { - printf( "%02x", ((unsigned int)(plv->val[ i ])) ); - } - } -} -#endif /* DEBUG_MODE */ - - -/***************************************************************************** - * Function: xsvfInfoInit - * Description: Initialize the xsvfInfo data. - * Parameters: pXsvfInfo - ptr to the XSVF info structure. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfInfoInit( SXsvfInfo* pXsvfInfo ) -{ - XSVFDBG_PRINTF1( 4, " sizeof( SXsvfInfo ) = %d bytes\n", - sizeof( SXsvfInfo ) ); - - pXsvfInfo->ucComplete = 0; - pXsvfInfo->ucCommand = XCOMPLETE; - pXsvfInfo->lCommandCount = 0; - pXsvfInfo->iErrorCode = XSVF_ERROR_NONE; - pXsvfInfo->ucMaxRepeat = 0; - pXsvfInfo->ucTapState = XTAPSTATE_RESET; - pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST; - pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST; - pXsvfInfo->lShiftLengthBits = 0L; - pXsvfInfo->sShiftLengthBytes= 0; - pXsvfInfo->lRunTestTime = 0L; - - return( 0 ); -} - -/***************************************************************************** - * Function: xsvfInfoCleanup - * Description: Cleanup the xsvfInfo data. - * Parameters: pXsvfInfo - ptr to the XSVF info structure. - * Returns: void. - *****************************************************************************/ -void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo ) -{ -} - -/***************************************************************************** - * Function: xsvfGetAsNumBytes - * Description: Calculate the number of bytes the given number of bits - * consumes. - * Parameters: lNumBits - the number of bits. - * Returns: short - the number of bytes to store the number of bits. - *****************************************************************************/ -short xsvfGetAsNumBytes( long lNumBits ) -{ - return( (short)( ( lNumBits + 7L ) / 8L ) ); -} - -/***************************************************************************** - * Function: xsvfTmsTransition - * Description: Apply TMS and transition TAP controller by applying one TCK - * cycle. - * Parameters: sTms - new TMS value. - * Returns: void. - *****************************************************************************/ -void xsvfTmsTransition( short sTms ) -{ - setPort( TMS, sTms ); - setPort( TCK, 0 ); - setPort( TCK, 1 ); -} - -/***************************************************************************** - * Function: xsvfGotoTapState - * Description: From the current TAP state, go to the named TAP state. - * A target state of RESET ALWAYS causes TMS reset sequence. - * All SVF standard stable state paths are supported. - * All state transitions are supported except for the following - * which cause an XSVF_ERROR_ILLEGALSTATE: - * - Target==DREXIT2; Start!=DRPAUSE - * - Target==IREXIT2; Start!=IRPAUSE - * Parameters: pucTapState - Current TAP state; returns final TAP state. - * ucTargetState - New target TAP state. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfGotoTapState( unsigned char* pucTapState, - unsigned char ucTargetState ) -{ - int i; - int iErrorCode; - - iErrorCode = XSVF_ERROR_NONE; - if ( ucTargetState == XTAPSTATE_RESET ) - { - /* If RESET, always perform TMS reset sequence to reset/sync TAPs */ - xsvfTmsTransition( 1 ); - for ( i = 0; i < 5; ++i ) - { - setPort( TCK, 0 ); - setPort( TCK, 1 ); - } - *pucTapState = XTAPSTATE_RESET; - XSVFDBG_PRINTF( 3, " TMS Reset Sequence -> Test-Logic-Reset\n" ); - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } else if ( ( ucTargetState != *pucTapState ) && - ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) || - ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) ) - { - /* Trap illegal TAP state path specification */ - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - } else { - if ( ucTargetState == *pucTapState ) - { - /* Already in target state. Do nothing except when in DRPAUSE - or in IRPAUSE to comply with SVF standard */ - if ( ucTargetState == XTAPSTATE_PAUSEDR ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2DR; - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - else if ( ucTargetState == XTAPSTATE_PAUSEIR ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2IR; - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - } - - /* Perform TAP state transitions to get to the target state */ - while ( ucTargetState != *pucTapState ) - { - switch ( *pucTapState ) - { - case XTAPSTATE_RESET: - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - break; - case XTAPSTATE_RUNTEST: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - break; - case XTAPSTATE_SELECTDR: - if ( ucTargetState >= XTAPSTATE_IRSTATES ) - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTIR; - } - else - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_CAPTUREDR; - } - break; - case XTAPSTATE_CAPTUREDR: - if ( ucTargetState == XTAPSTATE_SHIFTDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1DR; - } - break; - case XTAPSTATE_SHIFTDR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1DR; - break; - case XTAPSTATE_EXIT1DR: - if ( ucTargetState == XTAPSTATE_PAUSEDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_PAUSEDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEDR; - } - break; - case XTAPSTATE_PAUSEDR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2DR; - break; - case XTAPSTATE_EXIT2DR: - if ( ucTargetState == XTAPSTATE_SHIFTDR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTDR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEDR; - } - break; - case XTAPSTATE_UPDATEDR: - if ( ucTargetState == XTAPSTATE_RUNTEST ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - } - break; - case XTAPSTATE_SELECTIR: - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_CAPTUREIR; - break; - case XTAPSTATE_CAPTUREIR: - if ( ucTargetState == XTAPSTATE_SHIFTIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1IR; - } - break; - case XTAPSTATE_SHIFTIR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT1IR; - break; - case XTAPSTATE_EXIT1IR: - if ( ucTargetState == XTAPSTATE_PAUSEIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_PAUSEIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEIR; - } - break; - case XTAPSTATE_PAUSEIR: - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_EXIT2IR; - break; - case XTAPSTATE_EXIT2IR: - if ( ucTargetState == XTAPSTATE_SHIFTIR ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_SHIFTIR; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_UPDATEIR; - } - break; - case XTAPSTATE_UPDATEIR: - if ( ucTargetState == XTAPSTATE_RUNTEST ) - { - xsvfTmsTransition( 0 ); - *pucTapState = XTAPSTATE_RUNTEST; - } - else - { - xsvfTmsTransition( 1 ); - *pucTapState = XTAPSTATE_SELECTDR; - } - break; - default: - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - *pucTapState = ucTargetState; /* Exit while loop */ - break; - } - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - } - } - - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfShiftOnly - * Description: Assumes that starting TAP state is SHIFT-DR or SHIFT-IR. - * Shift the given TDI data into the JTAG scan chain. - * Optionally, save the TDO data shifted out of the scan chain. - * Last shift cycle is special: capture last TDO, set last TDI, - * but does not pulse TCK. Caller must pulse TCK and optionally - * set TMS=1 to exit shift state. - * Parameters: lNumBits - number of bits to shift. - * plvTdi - ptr to lenval for TDI data. - * plvTdoCaptured - ptr to lenval for storing captured TDO data. - * iExitShift - 1=exit at end of shift; 0=stay in Shift-DR. - * Returns: void. - *****************************************************************************/ -void xsvfShiftOnly( long lNumBits, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - int iExitShift ) -{ - unsigned char* pucTdi; - unsigned char* pucTdo; - unsigned char ucTdiByte; - unsigned char ucTdoByte; - unsigned char ucTdoBit; - int i; - - /* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */ - - /* Initialize TDO storage len == TDI len */ - pucTdo = 0; - if ( plvTdoCaptured ) - { - plvTdoCaptured->len = plvTdi->len; - pucTdo = plvTdoCaptured->val + plvTdi->len; - } - - /* Shift LSB first. val[N-1] == LSB. val[0] == MSB. */ - pucTdi = plvTdi->val + plvTdi->len; - while ( lNumBits ) - { - /* Process on a byte-basis */ - ucTdiByte = (*(--pucTdi)); - ucTdoByte = 0; - for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i ) - { - --lNumBits; - if ( iExitShift && !lNumBits ) - { - /* Exit Shift-DR state */ - setPort( TMS, 1 ); - } - - /* Set the new TDI value */ - setPort( TDI, (short)(ucTdiByte & 1) ); - ucTdiByte >>= 1; - - /* Set TCK low */ - setPort( TCK, 0 ); - - if ( pucTdo ) - { - /* Save the TDO value */ - ucTdoBit = readTDOBit(); - ucTdoByte |= ( ucTdoBit << i ); - } - - /* Set TCK high */ - setPort( TCK, 1 ); - } - - /* Save the TDO byte value */ - if ( pucTdo ) - { - (*(--pucTdo)) = ucTdoByte; - } - } -} - -/***************************************************************************** - * Function: xsvfShift - * Description: Goes to the given starting TAP state. - * Calls xsvfShiftOnly to shift in the given TDI data and - * optionally capture the TDO data. - * Compares the TDO captured data against the TDO expected - * data. - * If a data mismatch occurs, then executes the exception - * handling loop upto ucMaxRepeat times. - * Parameters: pucTapState - Ptr to current TAP state. - * ucStartState - Starting shift state: Shift-DR or Shift-IR. - * lNumBits - number of bits to shift. - * plvTdi - ptr to lenval for TDI data. - * plvTdoCaptured - ptr to lenval for storing TDO data. - * plvTdoExpected - ptr to expected TDO data. - * plvTdoMask - ptr to TDO mask. - * ucEndState - state in which to end the shift. - * lRunTestTime - amount of time to wait after the shift. - * ucMaxRepeat - Maximum number of retries on TDO mismatch. - * Returns: int - 0 = success; otherwise TDO mismatch. - * Notes: XC9500XL-only Optimization: - * Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1] - * is NOT all zeros and sMatch==1. - *****************************************************************************/ -int xsvfShift( unsigned char* pucTapState, - unsigned char ucStartState, - long lNumBits, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - lenVal* plvTdoExpected, - lenVal* plvTdoMask, - unsigned char ucEndState, - long lRunTestTime, - unsigned char ucMaxRepeat ) -{ - int iErrorCode; - int iMismatch; - unsigned char ucRepeat; - int iExitShift; - - iErrorCode = XSVF_ERROR_NONE; - iMismatch = 0; - ucRepeat = 0; - iExitShift = ( ucStartState != ucEndState ); - - XSVFDBG_PRINTF1( 3, " Shift Length = %ld\n", lNumBits ); - XSVFDBG_PRINTF( 4, " TDI = "); - XSVFDBG_PRINTLENVAL( 4, plvTdi ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoExpected ); - XSVFDBG_PRINTF( 4, "\n"); - - if ( !lNumBits ) - { - /* Compatibility with XSVF2.00: XSDR 0 = no shift, but wait in RTI */ - if ( lRunTestTime ) - { - /* Wait for prespecified XRUNTEST time */ - xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST ); - XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime ); - waitTime( lRunTestTime ); - } - } - else - { - do - { - /* Goto Shift-DR or Shift-IR */ - xsvfGotoTapState( pucTapState, ucStartState ); - - /* Shift TDI and capture TDO */ - xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift ); - - if ( plvTdoExpected ) - { - /* Compare TDO data to expected TDO data */ - iMismatch = !EqualLenVal( plvTdoExpected, - plvTdoCaptured, - plvTdoMask ); - } - - if ( iExitShift ) - { - /* Update TAP state: Shift->Exit */ - ++(*pucTapState); - XSVFDBG_PRINTF1( 3, " TAP State = %s\n", - xsvf_pzTapState[ *pucTapState ] ); - - if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) ) - { - XSVFDBG_PRINTF( 4, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoExpected ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Captured = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF( 4, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 4, plvTdoMask ); - XSVFDBG_PRINTF( 4, "\n"); - XSVFDBG_PRINTF1( 3, " Retry #%d\n", ( ucRepeat + 1 ) ); - /* Do exception handling retry - ShiftDR only */ - xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR ); - /* Shift 1 extra bit */ - xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR ); - /* Increment RUNTEST time by an additional 25% */ - lRunTestTime += ( lRunTestTime >> 2 ); - } - else - { - /* Do normal exit from Shift-XR */ - xsvfGotoTapState( pucTapState, ucEndState ); - } - - if ( lRunTestTime ) - { - /* Wait for prespecified XRUNTEST time */ - xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST ); - XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime ); - waitTime( lRunTestTime ); - } - } - } while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) ); - } - - if ( iMismatch ) - { - XSVFDBG_PRINTF( 1, " TDO Expected = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoExpected ); - XSVFDBG_PRINTF( 1, "\n"); - XSVFDBG_PRINTF( 1, " TDO Captured = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured ); - XSVFDBG_PRINTF( 1, "\n"); - XSVFDBG_PRINTF( 1, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 1, plvTdoMask ); - XSVFDBG_PRINTF( 1, "\n"); - if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) ) - { - iErrorCode = XSVF_ERROR_MAXRETRIES; - } - else - { - iErrorCode = XSVF_ERROR_TDOMISMATCH; - } - } - - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfBasicXSDRTDO - * Description: Get the XSDRTDO parameters and execute the XSDRTDO command. - * This is the common function for all XSDRTDO commands. - * Parameters: pucTapState - Current TAP state. - * lShiftLengthBits - number of bits to shift. - * sShiftLengthBytes - number of bytes to read. - * plvTdi - ptr to lenval for TDI data. - * lvTdoCaptured - ptr to lenval for storing TDO data. - * iEndState - state in which to end the shift. - * lRunTestTime - amount of time to wait after the shift. - * ucMaxRepeat - maximum xc9500/xl retries. - * Returns: int - 0 = success; otherwise TDO mismatch. - *****************************************************************************/ -int xsvfBasicXSDRTDO( unsigned char* pucTapState, - long lShiftLengthBits, - short sShiftLengthBytes, - lenVal* plvTdi, - lenVal* plvTdoCaptured, - lenVal* plvTdoExpected, - lenVal* plvTdoMask, - unsigned char ucEndState, - long lRunTestTime, - unsigned char ucMaxRepeat ) -{ - readVal( plvTdi, sShiftLengthBytes ); - if ( plvTdoExpected ) - { - readVal( plvTdoExpected, sShiftLengthBytes ); - } - return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits, - plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask, - ucEndState, lRunTestTime, ucMaxRepeat ) ); -} - -/***************************************************************************** - * Function: xsvfDoSDRMasking - * Description: Update the data value with the next XSDRINC data and address. - * Example: dataVal=0x01ff, nextData=0xab, addressMask=0x0100, - * dataMask=0x00ff, should set dataVal to 0x02ab - * Parameters: plvTdi - The current TDI value. - * plvNextData - the next data value. - * plvAddressMask - the address mask. - * plvDataMask - the data mask. - * Returns: void. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -void xsvfDoSDRMasking( lenVal* plvTdi, - lenVal* plvNextData, - lenVal* plvAddressMask, - lenVal* plvDataMask ) -{ - int i; - unsigned char ucTdi; - unsigned char ucTdiMask; - unsigned char ucDataMask; - unsigned char ucNextData; - unsigned char ucNextMask; - short sNextData; - - /* add the address Mask to dataVal and return as a new dataVal */ - addVal( plvTdi, plvTdi, plvAddressMask ); - - ucNextData = 0; - ucNextMask = 0; - sNextData = plvNextData->len; - for ( i = plvDataMask->len - 1; i >= 0; --i ) - { - /* Go through data mask in reverse order looking for mask (1) bits */ - ucDataMask = plvDataMask->val[ i ]; - if ( ucDataMask ) - { - /* Retrieve the corresponding TDI byte value */ - ucTdi = plvTdi->val[ i ]; - - /* For each bit in the data mask byte, look for 1's */ - ucTdiMask = 1; - while ( ucDataMask ) - { - if ( ucDataMask & 1 ) - { - if ( !ucNextMask ) - { - /* Get the next data byte */ - ucNextData = plvNextData->val[ --sNextData ]; - ucNextMask = 1; - } - - /* Set or clear the data bit according to the next data */ - if ( ucNextData & ucNextMask ) - { - ucTdi |= ucTdiMask; /* Set bit */ - } - else - { - ucTdi &= ( ~ucTdiMask ); /* Clear bit */ - } - - /* Update the next data */ - ucNextMask <<= 1; - } - ucTdiMask <<= 1; - ucDataMask >>= 1; - } - - /* Update the TDI value */ - plvTdi->val[ i ] = ucTdi; - } - } -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/*============================================================================ - * XSVF Command Functions (type = TXsvfDoCmdFuncPtr) - * These functions update pXsvfInfo->iErrorCode only on an error. - * Otherwise, the error code is left alone. - * The function returns the error code from the function. - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfDoIllegalCmd - * Description: Function place holder for illegal/unsupported commands. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ) -{ - XSVFDBG_PRINTF2( 0, "ERROR: Encountered unsupported command #%d (%s)\n", - ((unsigned int)(pXsvfInfo->ucCommand)), - ((pXsvfInfo->ucCommand < XLASTCMD) - ? (xsvf_pzCommandName[pXsvfInfo->ucCommand]) - : "Unknown") ); - pXsvfInfo->iErrorCode = XSVF_ERROR_ILLEGALCMD; - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXCOMPLETE - * Description: XCOMPLETE (no parameters) - * Update complete status for XSVF player. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo ) -{ - pXsvfInfo->ucComplete = 1; - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXTDOMASK - * Description: XTDOMASK <lenVal.TdoMask[XSDRSIZE]> - * Prespecify the TDO compare mask. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo ) -{ - readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes ); - XSVFDBG_PRINTF( 4, " TDO Mask = "); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) ); - XSVFDBG_PRINTF( 4, "\n"); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXSIR - * Description: XSIR <(byte)shiftlen> <lenVal.TDI[shiftlen]> - * Get the instruction and shift the instruction into the TAP. - * If prespecified XRUNTEST!=0, goto RUNTEST and wait after - * the shift for XRUNTEST usec. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSIR( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucShiftIrBits; - short sShiftIrBytes; - int iErrorCode; - - /* Get the shift length and store */ - readByte( &ucShiftIrBits ); - sShiftIrBytes = xsvfGetAsNumBytes( ucShiftIrBits ); - XSVFDBG_PRINTF1( 3, " XSIR length = %d\n", - ((unsigned int)ucShiftIrBits) ); - - if ( sShiftIrBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - } - else - { - /* Get and store instruction to shift in */ - readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) ); - - /* Shift the data */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR, - ucShiftIrBits, &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, pXsvfInfo->ucEndIR, - pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 ); - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSIR2 - * Description: XSIR <(2-byte)shiftlen> <lenVal.TDI[shiftlen]> - * Get the instruction and shift the instruction into the TAP. - * If prespecified XRUNTEST!=0, goto RUNTEST and wait after - * the shift for XRUNTEST usec. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo ) -{ - long lShiftIrBits; - short sShiftIrBytes; - int iErrorCode; - - /* Get the shift length and store */ - readVal( &(pXsvfInfo->lvTdi), 2 ); - lShiftIrBits = value( &(pXsvfInfo->lvTdi) ); - sShiftIrBytes = xsvfGetAsNumBytes( lShiftIrBits ); - XSVFDBG_PRINTF1( 3, " XSIR2 length = %d\n", (int)lShiftIrBits); - - if ( sShiftIrBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - } - else - { - /* Get and store instruction to shift in */ - readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) ); - - /* Shift the data */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR, - lShiftIrBits, &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, pXsvfInfo->ucEndIR, - pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 ); - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDR - * Description: XSDR <lenVal.TDI[XSDRSIZE]> - * Shift the given TDI data into the JTAG scan chain. - * Compare the captured TDO with the expected TDO from the - * previous XSDRTDO command using the previously specified - * XTDOMASK. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDR( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes ); - /* use TDOExpected from last XSDRTDO instruction */ - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXRUNTEST - * Description: XRUNTEST <uint32> - * Prespecify the XRUNTEST wait time for shift operations. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo ) -{ - readVal( &(pXsvfInfo->lvTdi), 4 ); - pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) ); - XSVFDBG_PRINTF1( 3, " XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime ); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXREPEAT - * Description: XREPEAT <byte> - * Prespecify the maximum number of XC9500/XL retries. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo ) -{ - readByte( &(pXsvfInfo->ucMaxRepeat) ); - XSVFDBG_PRINTF1( 3, " XREPEAT = %d\n", - ((unsigned int)(pXsvfInfo->ucMaxRepeat)) ); - return( XSVF_ERROR_NONE ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRSIZE - * Description: XSDRSIZE <uint32> - * Prespecify the XRUNTEST wait time for shift operations. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - iErrorCode = XSVF_ERROR_NONE; - readVal( &(pXsvfInfo->lvTdi), 4 ); - pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) ); - pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits ); - XSVFDBG_PRINTF1( 3, " XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits ); - if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN ) - { - iErrorCode = XSVF_ERROR_DATAOVERFLOW; - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRTDO - * Description: XSDRTDO <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]> - * Get the TDI and expected TDO values. Then, shift. - * Compare the expected TDO with the captured TDO using the - * prespecified XTDOMASK. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), - pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, - pXsvfInfo->ucMaxRepeat ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSETSDRMASKS - * Description: XSETSDRMASKS <lenVal.AddressMask[XSDRSIZE]> - * <lenVal.DataMask[XSDRSIZE]> - * Get the prespecified address and data mask for the XSDRINC - * command. - * Used for xc9500/xl compressed XSVF data. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo ) -{ - /* read the addressMask */ - readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes ); - /* read the dataMask */ - readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes ); - - XSVFDBG_PRINTF( 4, " Address Mask = " ); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) ); - XSVFDBG_PRINTF( 4, "\n" ); - XSVFDBG_PRINTF( 4, " Data Mask = " ); - XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) ); - XSVFDBG_PRINTF( 4, "\n" ); - - return( XSVF_ERROR_NONE ); -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/***************************************************************************** - * Function: xsvfDoXSDRINC - * Description: XSDRINC <lenVal.firstTDI[XSDRSIZE]> <byte(numTimes)> - * <lenVal.data[XSETSDRMASKS.dataMask.len]> ... - * Get the XSDRINC parameters and execute the XSDRINC command. - * XSDRINC starts by loading the first TDI shift value. - * Then, for numTimes, XSDRINC gets the next piece of data, - * replaces the bits from the starting TDI as defined by the - * XSETSDRMASKS.dataMask, adds the address mask from - * XSETSDRMASKS.addressMask, shifts the new TDI value, - * and compares the TDO to the expected TDO from the previous - * XSDRTDO command using the XTDOMASK. - * Used for xc9500/xl compressed XSVF data. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -#ifdef XSVF_SUPPORT_COMPRESSION -int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - int iDataMaskLen; - unsigned char ucDataMask; - unsigned char ucNumTimes; - unsigned char i; - - readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes ); - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, - &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat ); - if ( !iErrorCode ) - { - /* Calculate number of data mask bits */ - iDataMaskLen = 0; - for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i ) - { - ucDataMask = pXsvfInfo->lvDataMask.val[ i ]; - while ( ucDataMask ) - { - iDataMaskLen += ( ucDataMask & 1 ); - ucDataMask >>= 1; - } - } - - /* Get the number of data pieces, i.e. number of times to shift */ - readByte( &ucNumTimes ); - - /* For numTimes, get data, fix TDI, and shift */ - for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i ) - { - readVal( &(pXsvfInfo->lvNextData), - xsvfGetAsNumBytes( iDataMaskLen ) ); - xsvfDoSDRMasking( &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvNextData), - &(pXsvfInfo->lvAddressMask), - &(pXsvfInfo->lvDataMask) ); - iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), - XTAPSTATE_SHIFTDR, - pXsvfInfo->lShiftLengthBits, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - &(pXsvfInfo->lvTdoMask), - pXsvfInfo->ucEndDR, - pXsvfInfo->lRunTestTime, - pXsvfInfo->ucMaxRepeat ); - } - } - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} -#endif /* XSVF_SUPPORT_COMPRESSION */ - -/***************************************************************************** - * Function: xsvfDoXSDRBCE - * Description: XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> - * If not already in SHIFTDR, goto SHIFTDR. - * Shift the given TDI data into the JTAG scan chain. - * Ignore TDO. - * If cmd==XSDRE, then goto ENDDR. Otherwise, stay in ShiftDR. - * XSDRB, XSDRC, and XSDRE are the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucEndDR; - int iErrorCode; - ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ? - pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR); - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - /*plvTdoCaptured*/0, /*plvTdoExpected*/0, - /*plvTdoMask*/0, ucEndDR, - /*lRunTestTime*/0, /*ucMaxRepeat*/0 ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSDRTDOBCE - * Description: XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]> - * If not already in SHIFTDR, goto SHIFTDR. - * Shift the given TDI data into the JTAG scan chain. - * Compare TDO, but do NOT use XTDOMASK. - * If cmd==XSDRTDOE, then goto ENDDR. Otherwise, stay in ShiftDR. - * XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucEndDR; - int iErrorCode; - ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ? - pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR); - iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState), - pXsvfInfo->lShiftLengthBits, - pXsvfInfo->sShiftLengthBytes, - &(pXsvfInfo->lvTdi), - &(pXsvfInfo->lvTdoCaptured), - &(pXsvfInfo->lvTdoExpected), - /*plvTdoMask*/0, ucEndDR, - /*lRunTestTime*/0, /*ucMaxRepeat*/0 ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXSTATE - * Description: XSTATE <byte> - * <byte> == XTAPSTATE; - * Get the state parameter and transition the TAP to that state. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucNextState; - int iErrorCode; - readByte( &ucNextState ); - iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState ); - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXENDXR - * Description: XENDIR/XENDDR <byte> - * <byte>: 0 = RUNTEST; 1 = PAUSE. - * Get the prespecified XENDIR or XENDDR. - * Both XENDIR and XENDDR use the same implementation. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo ) -{ - int iErrorCode; - unsigned char ucEndState; - - iErrorCode = XSVF_ERROR_NONE; - readByte( &ucEndState ); - if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) ) - { - iErrorCode = XSVF_ERROR_ILLEGALSTATE; - } - else - { - - if ( pXsvfInfo->ucCommand == XENDIR ) - { - if ( ucEndState == XENDXR_RUNTEST ) - { - pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST; - } - else - { - pXsvfInfo->ucEndIR = XTAPSTATE_PAUSEIR; - } - XSVFDBG_PRINTF1( 3, " ENDIR State = %s\n", - xsvf_pzTapState[ pXsvfInfo->ucEndIR ] ); - } - else /* XENDDR */ - { - if ( ucEndState == XENDXR_RUNTEST ) - { - pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST; - } - else - { - pXsvfInfo->ucEndDR = XTAPSTATE_PAUSEDR; - } - XSVFDBG_PRINTF1( 3, " ENDDR State = %s\n", - xsvf_pzTapState[ pXsvfInfo->ucEndDR ] ); - } - } - - if ( iErrorCode != XSVF_ERROR_NONE ) - { - pXsvfInfo->iErrorCode = iErrorCode; - } - return( iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXCOMMENT - * Description: XCOMMENT <text string ending in \0> - * <text string ending in \0> == text comment; - * Arbitrary comment embedded in the XSVF. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo ) -{ - /* Use the comment for debugging */ - /* Otherwise, read through the comment to the end '\0' and ignore */ - unsigned char ucText; - - if ( xsvf_iDebugLevel > 0 ) - { - putc( ' ' ); - } - - do - { - readByte( &ucText ); - if ( xsvf_iDebugLevel > 0 ) - { - putc( ucText ? ucText : '\n' ); - } - } while ( ucText ); - - pXsvfInfo->iErrorCode = XSVF_ERROR_NONE; - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfDoXWAIT - * Description: XWAIT <wait_state> <end_state> <wait_time> - * If not already in <wait_state>, then go to <wait_state>. - * Wait in <wait_state> for <wait_time> microseconds. - * Finally, if not already in <end_state>, then goto <end_state>. - * Parameters: pXsvfInfo - XSVF information pointer. - * Returns: int - 0 = success; non-zero = error. - *****************************************************************************/ -int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo ) -{ - unsigned char ucWaitState; - unsigned char ucEndState; - long lWaitTime; - - /* Get Parameters */ - /* <wait_state> */ - readVal( &(pXsvfInfo->lvTdi), 1 ); - ucWaitState = pXsvfInfo->lvTdi.val[0]; - - /* <end_state> */ - readVal( &(pXsvfInfo->lvTdi), 1 ); - ucEndState = pXsvfInfo->lvTdi.val[0]; - - /* <wait_time> */ - readVal( &(pXsvfInfo->lvTdi), 4 ); - lWaitTime = value( &(pXsvfInfo->lvTdi) ); - XSVFDBG_PRINTF2( 3, " XWAIT: state = %s; time = %ld\n", - xsvf_pzTapState[ ucWaitState ], lWaitTime ); - - /* If not already in <wait_state>, go to <wait_state> */ - if ( pXsvfInfo->ucTapState != ucWaitState ) - { - xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState ); - } - - /* Wait for <wait_time> microseconds */ - waitTime( lWaitTime ); - - /* If not already in <end_state>, go to <end_state> */ - if ( pXsvfInfo->ucTapState != ucEndState ) - { - xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState ); - } - - return( XSVF_ERROR_NONE ); -} - - -/*============================================================================ - * Execution Control Functions - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfInitialize - * Description: Initialize the xsvf player. - * Call this before running the player to initialize the data - * in the SXsvfInfo struct. - * xsvfCleanup is called to clean up the data in SXsvfInfo - * after the XSVF is played. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfInitialize( SXsvfInfo* pXsvfInfo ) -{ - /* Initialize values */ - pXsvfInfo->iErrorCode = xsvfInfoInit( pXsvfInfo ); - - if ( !pXsvfInfo->iErrorCode ) - { - /* Initialize the TAPs */ - pXsvfInfo->iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), - XTAPSTATE_RESET ); - } - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfRun - * Description: Run the xsvf player for a single command and return. - * First, call xsvfInitialize. - * Then, repeatedly call this function until an error is detected - * or until the pXsvfInfo->ucComplete variable is non-zero. - * Finally, call xsvfCleanup to cleanup any remnants. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: int - 0 = success; otherwise error. - *****************************************************************************/ -int xsvfRun( SXsvfInfo* pXsvfInfo ) -{ - /* Process the XSVF commands */ - if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) ) - { - /* read 1 byte for the instruction */ - readByte( &(pXsvfInfo->ucCommand) ); - ++(pXsvfInfo->lCommandCount); - - if ( pXsvfInfo->ucCommand < XLASTCMD ) - { - /* Execute the command. Func sets error code. */ - XSVFDBG_PRINTF1( 2, " %s\n", - xsvf_pzCommandName[pXsvfInfo->ucCommand] ); - /* If your compiler cannot take this form, - then convert to a switch statement */ -#if 0 /* test-only */ - xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo ); -#else - switch (pXsvfInfo->ucCommand) { - case 0: - xsvfDoXCOMPLETE(pXsvfInfo); /* 0 */ - break; - case 1: - xsvfDoXTDOMASK(pXsvfInfo); /* 1 */ - break; - case 2: - xsvfDoXSIR(pXsvfInfo); /* 2 */ - break; - case 3: - xsvfDoXSDR(pXsvfInfo); /* 3 */ - break; - case 4: - xsvfDoXRUNTEST(pXsvfInfo); /* 4 */ - break; - case 5: - xsvfDoIllegalCmd(pXsvfInfo); /* 5 */ - break; - case 6: - xsvfDoIllegalCmd(pXsvfInfo); /* 6 */ - break; - case 7: - xsvfDoXREPEAT(pXsvfInfo); /* 7 */ - break; - case 8: - xsvfDoXSDRSIZE(pXsvfInfo); /* 8 */ - break; - case 9: - xsvfDoXSDRTDO(pXsvfInfo); /* 9 */ - break; -#ifdef XSVF_SUPPORT_COMPRESSION - case 10: - xsvfDoXSETSDRMASKS(pXsvfInfo); /* 10 */ - break; - case 11: - xsvfDoXSDRINC(pXsvfInfo); /* 11 */ - break; -#else - case 10: - xsvfDoIllegalCmd(pXsvfInfo); /* 10 */ - break; - case 11: - xsvfDoIllegalCmd(pXsvfInfo); /* 11 */ - break; -#endif /* XSVF_SUPPORT_COMPRESSION */ - case 12: - xsvfDoXSDRBCE(pXsvfInfo); /* 12 */ - break; - case 13: - xsvfDoXSDRBCE(pXsvfInfo); /* 13 */ - break; - case 14: - xsvfDoXSDRBCE(pXsvfInfo); /* 14 */ - break; - case 15: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 15 */ - break; - case 16: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 16 */ - break; - case 17: - xsvfDoXSDRTDOBCE(pXsvfInfo); /* 17 */ - break; - case 18: - xsvfDoXSTATE(pXsvfInfo); /* 18 */ - break; - case 19: - xsvfDoXENDXR(pXsvfInfo); /* 19 */ - break; - case 20: - xsvfDoXENDXR(pXsvfInfo); /* 20 */ - break; - case 21: - xsvfDoXSIR2(pXsvfInfo); /* 21 */ - break; - case 22: - xsvfDoXCOMMENT(pXsvfInfo); /* 22 */ - break; - case 23: - xsvfDoXWAIT(pXsvfInfo); /* 23 */ - break; - } -#endif - } - else - { - /* Illegal command value. Func sets error code. */ - xsvfDoIllegalCmd( pXsvfInfo ); - } - } - - return( pXsvfInfo->iErrorCode ); -} - -/***************************************************************************** - * Function: xsvfCleanup - * Description: cleanup remnants of the xsvf player. - * Parameters: pXsvfInfo - ptr to the XSVF information. - * Returns: void. - *****************************************************************************/ -void xsvfCleanup( SXsvfInfo* pXsvfInfo ) -{ - xsvfInfoCleanup( pXsvfInfo ); -} - - -/*============================================================================ - * xsvfExecute() - The primary entry point to the XSVF player - ============================================================================*/ - -/***************************************************************************** - * Function: xsvfExecute - * Description: Process, interpret, and apply the XSVF commands. - * See port.c:readByte for source of XSVF data. - * Parameters: none. - * Returns: int - Legacy result values: 1 == success; 0 == failed. - *****************************************************************************/ -int xsvfExecute(void) -{ - SXsvfInfo xsvfInfo; - - xsvfInitialize( &xsvfInfo ); - - while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) ) - { - xsvfRun( &xsvfInfo ); - } - - if ( xsvfInfo.iErrorCode ) - { - XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[ - ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST ) - ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] ); - XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld. See line #%ld in the XSVF ASCII file.\n", - xsvfInfo.lCommandCount, xsvfInfo.lCommandCount ); - } - else - { - XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" ); - } - - xsvfCleanup( &xsvfInfo ); - - return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) ); -} - - -/***************************************************************************** - * Function: do_cpld - * Description: main function. - * Specified here for creating stand-alone debug executable. - * Embedded users should call xsvfExecute() directly. - * Parameters: iArgc - number of command-line arguments. - * ppzArgv - array of ptrs to strings (command-line arguments). - * Returns: int - Legacy return value: 1 = success; 0 = error. - *****************************************************************************/ -int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int iErrorCode; - unsigned long duration; - unsigned long long startClock, endClock; - - if (argc == 2) - xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16); - else { -#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR - xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR; -#else - printf("Usage:\ncpld %s\n", cmdtp->help); - return -1; -#endif - } - - iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE ); - xsvf_iDebugLevel = 0; - - printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION); - printf("Reading XSVF data @ %p\n", xsvfdata); - - /* Initialize the I/O. SetPort initializes I/O on first call */ - setPort( TMS, 1 ); - - /* Execute the XSVF in the file */ - startClock = get_ticks(); - iErrorCode = xsvfExecute(); - endClock = get_ticks(); - duration = (unsigned long)(endClock - startClock); - printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk())); - - return( iErrorCode ); -} -U_BOOT_CMD( - cpld, 2, 1, do_cpld, - "program onboard CPLD", - "<xsvf-addr>" -); diff --git a/board/esd/common/xilinx_jtag/micro.h b/board/esd/common/xilinx_jtag/micro.h deleted file mode 100644 index e9a7612..0000000 --- a/board/esd/common/xilinx_jtag/micro.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/***************************************************************************** - * File: micro.h - * Description: This header file contains the function prototype to the - * primary interface function for the XSVF player. - * Usage: FIRST - PORTS.C - * Customize the ports.c function implementations to establish - * the correct protocol for communicating with your JTAG ports - * (setPort() and readTDOBit()) and tune the waitTime() delay - * function. Also, establish access to the XSVF data source - * in the readByte() function. - * FINALLY - Call xsvfExecute(). - *****************************************************************************/ -#ifndef XSVF_MICRO_H -#define XSVF_MICRO_H - -/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */ -#define XSVF_LEGACY_SUCCESS 1 -#define XSVF_LEGACY_ERROR 0 - -/* 4.04 [NEW] Error codes for xsvfExecute. */ -/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */ -#define XSVF_ERROR_NONE 0 -#define XSVF_ERROR_UNKNOWN 1 -#define XSVF_ERROR_TDOMISMATCH 2 -#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */ -#define XSVF_ERROR_ILLEGALCMD 4 -#define XSVF_ERROR_ILLEGALSTATE 5 -#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/ -/* Insert new errors here */ -#define XSVF_ERROR_LAST 7 - -/***************************************************************************** - * Function: xsvfExecute - * Description: Process, interpret, and apply the XSVF commands. - * See port.c:readByte for source of XSVF data. - * Parameters: none. - * Returns: int - For error codes see above. - *****************************************************************************/ -int xsvfExecute(void); - -#endif /* XSVF_MICRO_H */ diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c deleted file mode 100644 index d79dbd1..0000000 --- a/board/esd/common/xilinx_jtag/ports.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*******************************************************/ -/* file: ports.c */ -/* abstract: This file contains the routines to */ -/* output values on the JTAG ports, to read */ -/* the TDO bit, and to read a byte of data */ -/* from the prom */ -/* */ -/*******************************************************/ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> - -#include "ports.h" - -static unsigned long output = 0; -static int filepos = 0; -static int oldstate = 0; -static int newstate = 0; -static int readptr = 0; - -extern const unsigned char *xsvfdata; - -/* if in debugging mode, then just set the variables */ -void setPort(short p,short val) -{ - if (p==TMS) { - if (val) { - output |= JTAG_TMS; - } else { - output &= ~JTAG_TMS; - } - } - if (p==TDI) { - if (val) { - output |= JTAG_TDI; - } else { - output &= ~JTAG_TDI; - } - } - if (p==TCK) { - if (val) { - output |= JTAG_TCK; - } else { - output &= ~JTAG_TCK; - } - out_be32((void *)GPIO0_OR, output); - } -} - - -/* toggle tck LH */ -void pulseClock(void) -{ - setPort(TCK,0); /* set the TCK port to low */ - setPort(TCK,1); /* set the TCK port to high */ -} - - -/* read in a byte of data from the prom */ -void readByte(unsigned char *data) -{ - /* pretend reading using a file */ - *data = xsvfdata[readptr++]; - newstate = filepos++ >> 10; - if (newstate != oldstate) { - printf("%4d kB\r\r\r\r", newstate); - oldstate = newstate; - } -} - -/* read the TDO bit from port */ -unsigned char readTDOBit(void) -{ - unsigned long inputs; - - inputs = in_be32((void *)GPIO0_IR); - if (inputs & JTAG_TDO) - return 1; - else - return 0; -} - - -/* Wait at least the specified number of microsec. */ -/* Use a timer if possible; otherwise estimate the number of instructions */ -/* necessary to be run based on the microcontroller speed. For this example */ -/* we pulse the TCK port a number of times based on the processor speed. */ -void waitTime(long microsec) -{ - udelay(microsec); /* esd */ -} diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h deleted file mode 100644 index 8ee7de9..0000000 --- a/board/esd/common/xilinx_jtag/ports.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/*******************************************************/ -/* file: ports.h */ -/* abstract: This file contains extern declarations */ -/* for providing stimulus to the JTAG ports.*/ -/*******************************************************/ - -#ifndef ports_dot_h -#define ports_dot_h - -/* these constants are used to send the appropriate ports to setPort */ -/* they should be enumerated types, but some of the microcontroller */ -/* compilers don't like enumerated types */ -#define TCK (short) 0 -#define TMS (short) 1 -#define TDI (short) 2 - -/* - * Use CONFIG_SYS_FPGA_xxx defines from board include file. - */ -#define JTAG_TMS CONFIG_SYS_FPGA_PRG /* output */ -#define JTAG_TCK CONFIG_SYS_FPGA_CLK /* output */ -#define JTAG_TDI CONFIG_SYS_FPGA_DATA /* output */ -#define JTAG_TDO CONFIG_SYS_FPGA_DONE /* input */ - -/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */ -void setPort(short p, short val); - -/* read the TDO bit and store it in val */ -unsigned char readTDOBit(void); - -/* make clock go down->up->down*/ -void pulseClock(void); - -/* read the next byte of data from the xsvf file */ -void readByte(unsigned char *data); - -void waitTime(long microsec); - -#endif diff --git a/board/esd/cpci2dp/Kconfig b/board/esd/cpci2dp/Kconfig deleted file mode 100644 index 646e8ff..0000000 --- a/board/esd/cpci2dp/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CPCI2DP - -config SYS_BOARD - default "cpci2dp" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "CPCI2DP" - -endif diff --git a/board/esd/cpci2dp/MAINTAINERS b/board/esd/cpci2dp/MAINTAINERS deleted file mode 100644 index 660e185..0000000 --- a/board/esd/cpci2dp/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CPCI2DP BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/cpci2dp/ -F: include/configs/CPCI2DP.h -F: configs/CPCI2DP_defconfig diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile deleted file mode 100644 index ce2c6dd..0000000 --- a/board/esd/cpci2dp/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c deleted file mode 100644 index 336c551..0000000 --- a/board/esd/cpci2dp/cpci2dp.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * (C) Copyright 2005 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f (void) -{ - unsigned long CPC0_CR0Reg; - - /* - * Setup GPIO pins - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | - ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | - CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); - - /* set output pins to high */ - out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP); - /* setup for output (LED=off) */ - out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED); - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) unused - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -int misc_init_r (void) -{ - unsigned long CPC0_CR0Reg; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Select cts (and not dsr) on uart1 - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); - - return (0); -} - - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming CPCI2DP"); - } else { - puts(str); - } - - printf(" (Ver 1.0)"); - - putc ('\n'); - - return 0; -} - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) { - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) & - CONFIG_SYS_EEPROM_WP)); - break; - } - } - return state; -} -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD( - eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c deleted file mode 100644 index 34bdc05..0000000 --- a/board/esd/cpci2dp/flash.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -monitor_flash_len, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/cpci405/Kconfig b/board/esd/cpci405/Kconfig deleted file mode 100644 index 0df2755..0000000 --- a/board/esd/cpci405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CPCI4052 - -config SYS_BOARD - default "cpci405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "CPCI4052" - -endif diff --git a/board/esd/cpci405/MAINTAINERS b/board/esd/cpci405/MAINTAINERS deleted file mode 100644 index 1da58dc..0000000 --- a/board/esd/cpci405/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -CPCI405 BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/cpci405/ -F: include/configs/CPCI405.h -F: configs/CPCI405_defconfig -F: include/configs/CPCI4052.h -F: configs/CPCI4052_defconfig -F: include/configs/CPCI405AB.h -F: configs/CPCI405AB_defconfig -F: include/configs/CPCI405DT.h -F: configs/CPCI405DT_defconfig diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile deleted file mode 100644 index 7490b78..0000000 --- a/board/esd/cpci405/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpci405.o flash.o ../common/misc.o -obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c deleted file mode 100644 index c510ab1..0000000 --- a/board/esd/cpci405/cpci405.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <console.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> -#include <net.h> -#include <pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void __ft_board_setup(void *blob, bd_t *bd); - -#undef FPGA_DEBUG - -/* fpga configuration data - generated by bin2cc */ -const unsigned char fpgadata[] = -{ -#if defined(CONFIG_CPCI405_VER2) -# include "fpgadata_cpci4052.c" -#endif -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -/* Prototypes */ -int cpci405_version(void); -void lxt971_no_sleep(void); - -int board_early_init_f(void) -{ -#ifndef CONFIG_CPCI405_VER2 - int index, len, i; - int status; -#endif - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void)get_clocks(); - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - console_init_f(); -#endif - - /* - * First pull fpga-prg pin low, - * to disable fpga logic (on version 2 board) - */ - out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ - out_be32((void *)GPIO0_OR, 0); /* pull prg low */ - - /* - * Boot onboard FPGA - */ -#ifndef CONFIG_CPCI405_VER2 - if (cpci405_version() == 1) { - status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void)get_clocks(); - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - console_init_f(); -#endif - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after " - "asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after " - "deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after " - "programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index = 0; index < 1000; index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - } -#endif /* !CONFIG_CPCI405_VER2 */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens. - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ -#if defined(CONFIG_CPCI405_6U) - if (cpci405_version() == 3) { - mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ - } else { - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ - } -#else - mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ -#endif - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, - * INT0 highest priority */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -int ctermm2(void) -{ -#if defined(CONFIG_CPCI405_VER2) - return 0; /* no, board is cpci405 */ -#else - if ((in_8((void*)0xf0000400) == 0x00) && - (in_8((void*)0xf0000401) == 0x01)) - return 0; /* no, board is cpci405 */ - else - return -1; /* yes, board is cterm-m2 */ -#endif -} - -int cpci405_host(void) -{ - if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) - return -1; /* yes, board is cpci405 host */ - else - return 0; /* no, board is cpci405 adapter */ -} - -int cpci405_version(void) -{ - unsigned long CPC0_CR0Reg; - unsigned long value; - - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ - - /* - * Restore GPIO settings - */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - switch (value) { - case 0x00180000: - /* CS2==1 && CS3==1 -> version 1 */ - return 1; - case 0x00080000: - /* CS2==0 && CS3==1 -> version 2 */ - return 2; - case 0x00100000: - /* CS2==1 && CS3==0 -> version 3 or 6U board */ - return 3; - case 0x00000000: - /* CS2==0 && CS3==0 -> version 4 */ - return 4; - default: - /* should not be reached! */ - return 2; - } -} - -int misc_init_r (void) -{ - unsigned long CPC0_CR0Reg; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - -#if defined(CONFIG_CPCI405_VER2) - { - unsigned char *dst; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - /* - * On CPCI-405 version 2 the environment is saved in eeprom! - * FPGA can be gzip compressed (malloc) and booted this late. - */ - if (cpci405_version() >= 2) { - /* - * Setup GPIO pins (CS6+CS7 as GPIO) - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, - (uchar *)fpgadata, &len) != 0) { - printf("GUNZIP ERROR - must RESET board to recover\n"); - do_reset(NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after " - "asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after " - "deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after " - "programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index + 1])); - index += len + 3; - } - putc('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - - /* restore gpio/cs settings */ - mtdcr(CPC0_CR0, CPC0_CR0Reg); - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = dst[index]; - printf("%s ", &(dst[index + 1])); - index += len + 3; - } - putc('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - -#if defined(CONFIG_CPCI405_6U) -#error HIER GETH ES WEITER MIT IO ACCESSORS - if (cpci405_version() == 3) { - /* - * Enable outputs in fpga on version 3 board - */ - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | - CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT); - - /* - * Set outputs to 0 - */ - out_8((void*)CONFIG_SYS_LED_ADDR, 0x00); - - /* - * Reset external DUART - */ - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | - CONFIG_SYS_FPGA_MODE_DUART_RESET); - udelay(100); - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & - ~CONFIG_SYS_FPGA_MODE_DUART_RESET); - } -#endif - } - else { - puts("\n*** U-Boot Version does not match Board Version!\n"); - puts("*** CPCI-405 Version 1.x detected!\n"); - puts("*** Please use correct U-Boot version " - "(CPCI405 instead of CPCI4052)!\n\n"); - } - } -#else /* CONFIG_CPCI405_VER2 */ - if (cpci405_version() >= 2) { - puts("\n*** U-Boot Version does not match Board Version!\n"); - puts("*** CPCI-405 Board Version 2.x detected!\n"); - puts("*** Please use correct U-Boot version " - "(CPCI4052 instead of CPCI405)!\n\n"); - } -#endif /* CONFIG_CPCI405_VER2 */ - - /* - * Select cts (and not dsr) on uart1 - */ - CPC0_CR0Reg = mfdcr(CPC0_CR0); - mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); - - return 0; -} - -/* - * Check Board Identity: - */ - -int checkboard(void) -{ -#ifndef CONFIG_CPCI405_VER2 - int index; - int len; -#endif - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - unsigned short ver; - - puts("Board: "); - - if (i == -1) - puts("### No HW ID - assuming CPCI405"); - else - puts(str); - - ver = cpci405_version(); - printf(" (Ver %d.x, ", ver); - - if (ctermm2()) { - char str[4]; - - /* - * Read board-id and save in env-variable - */ - sprintf(str, "%d", *(unsigned char *)0xf0000400); - setenv("boardid", str); - printf("CTERM-M2 - Id=%s)", str); - } else { - if (cpci405_host()) - puts("PCI Host Version)"); - else - puts("PCI Adapter Version)"); - } - -#ifndef CONFIG_CPCI405_VER2 - puts("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf("%s ", &(fpgadata[index + 1])); - index += len + 3; - } -#endif - - putc('\n'); - return 0; -} - -void reset_phy(void) -{ -#if defined(CONFIG_LXT971_NO_SLEEP) - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} - -#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET) -void ide_set_reset(int on) -{ - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & - ~CONFIG_SYS_FPGA_MODE_CF_RESET); - } else { /* release RESET */ - out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, - in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | - CONFIG_SYS_FPGA_MODE_CF_RESET); - } -} - -#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */ - -#if defined(CONFIG_PCI) -void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = 0xff; - - /* - * Write pci interrupt line register (cpci405 specific) - */ - switch (PCI_DEV(dev) & 0x03) { - case 0: - int_line = 27 + 2; - break; - case 1: - int_line = 27 + 3; - break; - case 2: - int_line = 27 + 0; - break; - case 3: - int_line = 27 + 1; - break; - } - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -int pci_pre_init(struct pci_controller *hose) -{ - hose->fixup_irq = cpci405_pci_fixup_irq; - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - - __ft_board_setup(blob, bd); - - /* - * Disable PCI in adapter mode. - */ - if (!cpci405_host()) { - rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", - "disabled", sizeof("disabled"), 1); - if (rc) { - printf("Unable to update property status in PCI node, " - "err=%s\n", - fdt_strerror(rc)); - } - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c deleted file mode 100644 index 091652b..0000000 --- a/board/esd/cpci405/flash.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long calc_size(unsigned long size) -{ - switch (size) { - case 1 << 20: - return 0; - case 2 << 20: - return 1; - case 4 << 20: - return 2; - case 8 << 20: - return 3; - case 16 << 20: - return 4; - default: - return 0; - } -} - - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - base_b0 = FLASH_BASE0_PRELIM; - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - base_b1 = FLASH_BASE1_PRELIM; - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - if (size_b1 < (1 << 20)) { - /* minimum CS size on PPC405GP is 1MB !!! */ - size_b1 = 1 << 20; - } - base_b1 = -size_b1; - mtdcr (EBC0_CFGADDR, PB0CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB0CR); - pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17); - mtdcr (EBC0_CFGDATA, pbcr); -#if 0 /* test-only */ - printf("size_b1=%x base_b1=%x PB1CR = %x\n", - size_b1, base_b1, pbcr); /* test-only */ -#endif - } - - if (size_b0) { - if (size_b0 < (1 << 20)) { - /* minimum CS size on PPC405GP is 1MB !!! */ - size_b0 = 1 << 20; - } - base_b0 = base_b1 - size_b0; - mtdcr (EBC0_CFGADDR, PB1CR); - pbcr = mfdcr (EBC0_CFGDATA); - mtdcr (EBC0_CFGADDR, PB1CR); - pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17); - mtdcr (EBC0_CFGDATA, pbcr); -#if 0 /* test-only */ - printf("size_b0=%x base_b0=%x PB0CR = %x\n", - size_b0, base_b0, pbcr); /* test-only */ -#endif - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - monitor_flash_len, - base_b1 + size_b1 - 1, &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - monitor_flash_len, - base_b0 + size_b0 - 1, &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} diff --git a/board/esd/cpci405/fpgadata_cpci4052.c b/board/esd/cpci405/fpgadata_cpci4052.c deleted file mode 100644 index bedbb1f..0000000 --- a/board/esd/cpci405/fpgadata_cpci4052.c +++ /dev/null @@ -1,1529 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0xe9, 0xf4, 0x75, 0x3e, -0x00, 0x03, 0x63, 0x70, 0x63, 0x69, 0x34, 0x30, -0x35, 0x5f, 0x32, 0x5f, 0x30, 0x34, 0x2e, 0x62, -0x69, 0x74, 0x00, 0xed, 0x7c, 0x0f, 0x74, 0x14, -0xd7, 0x79, 0xef, 0x37, 0x77, 0x66, 0xc5, 0x68, -0x77, 0xa5, 0x1d, 0xad, 0x56, 0xce, 0xda, 0x16, -0xf2, 0x68, 0x25, 0xc8, 0xa2, 0xae, 0xc4, 0xb2, -0xc2, 0x58, 0x96, 0xc5, 0x6a, 0xb4, 0x92, 0xe9, -0xda, 0xe0, 0xb0, 0x26, 0x6e, 0xc3, 0x6b, 0xfd, -0x92, 0xc5, 0x26, 0xad, 0xfa, 0x0e, 0x71, 0x85, -0xd3, 0xe6, 0xa9, 0x6e, 0x5f, 0xdf, 0xd5, 0x6a, -0x31, 0x02, 0x61, 0x58, 0xff, 0x69, 0xa3, 0xb8, -0x24, 0x59, 0x88, 0xda, 0x28, 0x2e, 0xc9, 0x5b, -0x04, 0x01, 0x61, 0x1c, 0x7b, 0x50, 0x65, 0x2c, -0x40, 0x06, 0x85, 0xfa, 0xbc, 0x87, 0x6d, 0x6a, -0x2f, 0x8e, 0xea, 0xa7, 0x60, 0x99, 0xca, 0x40, -0x1d, 0xf1, 0xcf, 0x7a, 0xdf, 0x9d, 0x7f, 0xbb, -0x22, 0x89, 0xdb, 0xd3, 0xd7, 0x73, 0xfa, 0xce, -0x79, 0x9e, 0xc4, 0xc7, 0xd7, 0xba, 0xba, 0x33, -0xf7, 0x7e, 0xf3, 0xdd, 0xdf, 0xf7, 0xfb, 0x7d, -0xdf, 0x1d, 0x41, 0xa1, 0x6b, 0x5a, 0xff, 0x1f, -0x00, 0xb7, 0x0e, 0x4a, 0x1e, 0xed, 0x78, 0xf4, -0x0f, 0x96, 0x06, 0xef, 0xfc, 0x4a, 0xe8, 0x2b, -0xc1, 0xa5, 0x75, 0x8f, 0x3d, 0xba, 0x1e, 0x1e, -0x01, 0x7b, 0xe8, 0xeb, 0x4b, 0xee, 0xfc, 0xa3, -0x8d, 0x4b, 0x96, 0x2e, 0x85, 0x47, 0xc1, 0x11, -0x0a, 0x06, 0xeb, 0x17, 0xe3, 0xff, 0x97, 0xdc, -0x05, 0xeb, 0xa1, 0x70, 0xc9, 0x5d, 0x8d, 0x4b, -0x96, 0x35, 0x2e, 0x0d, 0xc2, 0x57, 0x01, 0xe2, -0x3d, 0xb3, 0x78, 0xbd, 0xf0, 0xad, 0xdf, 0xfa, -0xbd, 0x20, 0x50, 0x0e, 0x00, 0xe6, 0x05, 0xb9, -0x38, 0xfb, 0x77, 0x41, 0x90, 0x93, 0x39, 0xa0, -0xcd, 0xb5, 0x41, 0x50, 0xd9, 0x7f, 0x83, 0xd1, -0x5f, 0x18, 0x04, 0x39, 0xff, 0xbf, 0xb9, 0x20, -0x28, 0x10, 0x03, 0xcf, 0xd7, 0xc0, 0x1d, 0x84, -0x9b, 0x2e, 0x0e, 0x04, 0xaa, 0xb7, 0x3e, 0xad, -0x8f, 0xdc, 0xdc, 0xc5, 0xae, 0x7f, 0x45, 0x9f, -0xfb, 0x57, 0x74, 0x09, 0xff, 0xd6, 0x3e, 0xfd, -0x5f, 0xb3, 0x6e, 0xf0, 0xe0, 0xcc, 0x38, 0x6d, -0x45, 0x60, 0x63, 0x0d, 0xa9, 0x79, 0x44, 0x1f, -0xa7, 0xda, 0x2e, 0xc1, 0x58, 0x72, 0x99, 0xbc, -0x6a, 0x0b, 0xa9, 0x22, 0x63, 0xea, 0x37, 0x82, -0xae, 0x3e, 0x3e, 0x08, 0x1d, 0xfa, 0x8c, 0xa4, -0xf7, 0x68, 0xcf, 0x80, 0xcf, 0x27, 0x8a, 0xa4, -0x1a, 0x7a, 0x40, 0xa6, 0x8e, 0xe7, 0x13, 0x69, -0xd0, 0xd7, 0xdc, 0x63, 0x9b, 0xa4, 0xbb, 0x64, -0x19, 0x44, 0x72, 0x9b, 0xd8, 0xd5, 0x93, 0x96, -0xa3, 0x0e, 0x42, 0x7c, 0x9c, 0x3e, 0x4e, 0x2d, -0x19, 0x20, 0x3f, 0x00, 0xec, 0x03, 0xe2, 0xe4, -0x7a, 0x38, 0x9f, 0xea, 0xa0, 0x24, 0x23, 0xc4, -0xf5, 0xc9, 0x94, 0xa9, 0x70, 0x1e, 0x0e, 0xa8, -0x81, 0xdd, 0xbc, 0x0c, 0xc3, 0x64, 0x19, 0xb8, -0x32, 0xbc, 0x24, 0xe8, 0xe3, 0xb2, 0x5c, 0x1a, -0xde, 0x81, 0x57, 0x54, 0x57, 0x96, 0xbf, 0x0c, -0x7f, 0x0e, 0x77, 0x50, 0xd7, 0x34, 0x3f, 0x03, -0xfa, 0x38, 0x45, 0x1a, 0x80, 0x13, 0x10, 0xca, -0x16, 0x0d, 0xf0, 0x7e, 0xbc, 0x41, 0x48, 0x71, -0xa6, 0x71, 0x9c, 0xac, 0xf5, 0x8d, 0xda, 0xfc, -0xf0, 0x1b, 0x31, 0x5f, 0x56, 0x1c, 0x20, 0x01, -0x38, 0x2f, 0xf8, 0x54, 0x31, 0xcd, 0x3f, 0x8e, -0xef, 0x4f, 0xbb, 0xa7, 0xad, 0x0d, 0x7a, 0x14, -0x19, 0x0a, 0x25, 0x02, 0xb6, 0x5d, 0xd0, 0xce, -0x89, 0x29, 0x32, 0x84, 0x76, 0x60, 0x97, 0xcc, -0x2d, 0xa3, 0x7b, 0xd2, 0x95, 0xd5, 0xe2, 0xef, -0x92, 0x5b, 0x1e, 0xfa, 0x21, 0xad, 0x4c, 0x8b, -0x6b, 0xc9, 0x5a, 0x63, 0x5c, 0x34, 0xea, 0x4a, -0x1d, 0x49, 0xef, 0x5e, 0x54, 0x74, 0x9b, 0xc3, -0x4e, 0xcf, 0xa5, 0x83, 0x71, 0x67, 0x0f, 0x6f, -0x9a, 0x58, 0x99, 0xbf, 0x47, 0xf9, 0x67, 0x29, -0x0c, 0xae, 0xf1, 0xd6, 0xeb, 0xb0, 0x44, 0x6a, -0x3e, 0xb6, 0x78, 0xb4, 0x7e, 0xbc, 0x40, 0x9f, -0xe7, 0x80, 0x6d, 0x02, 0x8e, 0xc3, 0x8b, 0xaa, -0x33, 0xc3, 0xfb, 0xe0, 0x44, 0x32, 0x24, 0x07, -0x32, 0x55, 0x35, 0x86, 0x3d, 0xa3, 0x25, 0xcf, -0x09, 0x4f, 0x42, 0xa5, 0x2a, 0x4e, 0x47, 0x96, -0xc2, 0x66, 0xa8, 0xa2, 0xe2, 0x34, 0x71, 0x1b, -0x76, 0x51, 0xe1, 0x3b, 0xf0, 0x4d, 0xba, 0x28, -0xdb, 0xde, 0x59, 0xf0, 0xbc, 0x63, 0x33, 0xad, -0x8c, 0x17, 0xb6, 0x93, 0x0e, 0xd0, 0xd7, 0x17, -0xf5, 0x4c, 0x91, 0xc3, 0xd4, 0x77, 0x56, 0xbc, -0xbb, 0xc0, 0x09, 0xdd, 0x20, 0xab, 0x85, 0x7e, -0xfb, 0x1a, 0x41, 0x7f, 0x0f, 0x93, 0x65, 0x93, -0xf0, 0xd6, 0xae, 0xc6, 0xcc, 0xb6, 0xf4, 0x3c, -0xbf, 0x70, 0x9c, 0x84, 0x68, 0xd1, 0x0b, 0xfc, -0x13, 0xc6, 0x3d, 0xa3, 0x90, 0x26, 0x3d, 0x80, -0xf3, 0xa4, 0x8e, 0x2c, 0xcc, 0x60, 0xa3, 0x58, -0xe5, 0x9f, 0x31, 0xde, 0x9f, 0x28, 0x4d, 0x90, -0x63, 0x74, 0x50, 0x81, 0x14, 0x59, 0x0f, 0x3f, -0x87, 0x70, 0xcb, 0xbc, 0xa7, 0x79, 0x62, 0xdc, -0x93, 0x0a, 0xeb, 0x61, 0x0b, 0xec, 0x8e, 0x89, -0xcf, 0xe1, 0x7b, 0x3f, 0x24, 0xd4, 0x29, 0x8e, -0x9d, 0x44, 0x06, 0x49, 0xeb, 0xf3, 0xda, 0x96, -0x92, 0xa7, 0xe4, 0x2a, 0xc5, 0x1e, 0xb3, 0xef, -0x17, 0x7f, 0x02, 0x8b, 0x15, 0x47, 0xac, 0xa0, -0xc0, 0xb0, 0x99, 0x28, 0x78, 0x60, 0x13, 0x54, -0xc6, 0xed, 0x6b, 0x89, 0x07, 0x7e, 0x0c, 0xb5, -0xca, 0xed, 0x6b, 0x09, 0xe1, 0x74, 0x9b, 0x0d, -0x15, 0x1d, 0x51, 0xd4, 0x35, 0x41, 0x4f, 0xdd, -0x26, 0x7e, 0x57, 0x5b, 0x76, 0x4d, 0xd8, 0xe3, -0x7a, 0xd5, 0x51, 0xc7, 0xeb, 0x76, 0xe9, 0x9b, -0x3f, 0x51, 0x70, 0x05, 0xc2, 0x4a, 0x51, 0x6a, -0xe5, 0x7a, 0x60, 0x8d, 0x95, 0x29, 0xfe, 0xfd, -0x82, 0x0e, 0xe3, 0x79, 0x97, 0xe1, 0x86, 0x50, -0xaf, 0xdc, 0x31, 0xce, 0x57, 0xc3, 0x35, 0x21, -0xac, 0xb8, 0xc6, 0xf9, 0x85, 0x86, 0x3d, 0x1b, -0xa4, 0x6c, 0x72, 0x08, 0x88, 0x28, 0x26, 0x88, -0x4c, 0x87, 0xe4, 0x3a, 0xd1, 0xb1, 0x9b, 0x6c, -0x37, 0xd6, 0x20, 0xda, 0x46, 0xe4, 0xbd, 0x7e, -0x39, 0x62, 0x97, 0x12, 0x82, 0xbc, 0x57, 0x0c, -0x3c, 0xe2, 0x90, 0x12, 0xc4, 0xf0, 0x4f, 0x6f, -0x59, 0xbf, 0x77, 0xaf, 0x22, 0x2b, 0xd1, 0x4c, -0xc1, 0x42, 0xe9, 0x10, 0x14, 0x2b, 0x0e, 0x89, -0x3c, 0x69, 0xd8, 0x2c, 0x2d, 0xf5, 0xe3, 0x14, -0x7c, 0x8a, 0x2b, 0xe5, 0xa8, 0x16, 0xaf, 0x10, -0x7c, 0xde, 0x73, 0xbc, 0xdf, 0xf0, 0x33, 0x3f, -0xfc, 0x8d, 0x72, 0x05, 0x5e, 0x56, 0xe6, 0xa5, -0xf8, 0x09, 0x6d, 0x9e, 0xae, 0x14, 0x7f, 0xdc, -0x78, 0x47, 0x7e, 0x29, 0x1d, 0x1f, 0x85, 0x10, -0xda, 0x9a, 0x4f, 0xa3, 0xad, 0xb1, 0x91, 0x74, -0xd8, 0xcd, 0x71, 0xc2, 0xdd, 0xb0, 0x1d, 0xaa, -0xba, 0xc4, 0x2c, 0xfa, 0xee, 0x8b, 0x9c, 0x8f, -0xae, 0xcc, 0x46, 0xec, 0x86, 0x2f, 0xf9, 0x6d, -0x5f, 0xe0, 0xba, 0x21, 0xad, 0x8a, 0x19, 0xb2, -0x0d, 0xf6, 0x81, 0x5f, 0xc5, 0xb9, 0xd8, 0x2d, -0xff, 0x0c, 0x73, 0xe8, 0x2f, 0x8a, 0x18, 0x73, -0x97, 0xf7, 0x1c, 0x4c, 0x2f, 0x1a, 0xbd, 0x3d, -0x46, 0x44, 0xc3, 0xd6, 0x7e, 0xb1, 0x02, 0x4e, -0xd1, 0xfa, 0x74, 0xf1, 0x24, 0xff, 0x5d, 0x3a, -0x9b, 0xbe, 0x7b, 0xe6, 0x2b, 0x93, 0xa5, 0x76, -0x03, 0x57, 0xc4, 0xf9, 0xdb, 0x4a, 0xaf, 0xe2, -0xeb, 0x7e, 0x99, 0xf2, 0x53, 0x70, 0x4f, 0x6c, -0xd9, 0xb0, 0x2b, 0xcd, 0x0f, 0x1b, 0xfe, 0xa9, -0xd8, 0x3e, 0x81, 0x13, 0xa9, 0xaf, 0x4f, 0x3a, -0x0f, 0xb9, 0x4f, 0xc1, 0xa9, 0x9f, 0x86, 0x27, -0x9c, 0x7d, 0xfc, 0xb8, 0x61, 0xcf, 0x81, 0x92, -0xff, 0x41, 0x13, 0xe9, 0xaa, 0xf5, 0xb8, 0x0d, -0x2a, 0x68, 0x37, 0xad, 0xcd, 0x62, 0xe3, 0xbc, -0xb9, 0x6f, 0x61, 0xe7, 0xf0, 0x0e, 0xa9, 0x92, -0x16, 0x3e, 0xe2, 0x5b, 0xde, 0xb3, 0x19, 0x16, -0x8f, 0xae, 0x5d, 0x4f, 0x46, 0xa8, 0xbe, 0xbe, -0xb8, 0x67, 0xcc, 0x9d, 0x40, 0x3b, 0x14, 0x52, -0xe2, 0x14, 0xba, 0x21, 0xa0, 0x8a, 0x7e, 0x72, -0x26, 0xa9, 0xbf, 0x87, 0x81, 0xb2, 0x34, 0x1c, -0x83, 0x41, 0xf5, 0x81, 0x0c, 0xff, 0x67, 0xde, -0x53, 0x64, 0x39, 0xdb, 0x18, 0x17, 0x92, 0xfa, -0x3d, 0x29, 0x9c, 0x83, 0x2b, 0x4a, 0x78, 0xbc, -0x78, 0xbf, 0x63, 0x0a, 0xde, 0x86, 0x70, 0xd6, -0xb5, 0xb7, 0x34, 0x6b, 0xf8, 0x27, 0x17, 0xbb, -0x24, 0x9d, 0xa2, 0xfb, 0xb2, 0xab, 0x2e, 0xb6, -0x36, 0x09, 0xa7, 0xa0, 0x59, 0x15, 0x66, 0xf8, -0x89, 0x36, 0xbd, 0xaf, 0x4b, 0x58, 0x07, 0xbd, -0x3d, 0xbe, 0xa3, 0xfe, 0x21, 0xe2, 0x84, 0x5e, -0xa8, 0x3b, 0x12, 0xdd, 0x9f, 0xc8, 0x2a, 0xba, -0x7f, 0x52, 0xdb, 0x2a, 0xe8, 0x5a, 0x20, 0xab, -0x7d, 0x19, 0x7b, 0x80, 0xf5, 0xa9, 0xf6, 0x41, -0x92, 0x35, 0xec, 0x29, 0x0a, 0x45, 0x72, 0xd7, -0x7a, 0x79, 0x54, 0x0c, 0x92, 0x5a, 0xb9, 0x5b, -0xae, 0x3b, 0xb3, 0x35, 0x44, 0x86, 0x8d, 0xd5, -0x41, 0xe1, 0xd7, 0xe0, 0x44, 0x74, 0xf0, 0x2d, -0xe7, 0x32, 0x7e, 0xb9, 0x70, 0x6a, 0x7d, 0xf3, -0x78, 0xf1, 0x81, 0xee, 0x2c, 0xd1, 0xef, 0x99, -0x9e, 0x3f, 0x95, 0xf8, 0x85, 0x5c, 0x71, 0xdc, -0xf5, 0xf1, 0xf7, 0xae, 0xd3, 0x6b, 0x4d, 0xcb, -0xcf, 0x14, 0x5d, 0xec, 0x9e, 0x34, 0xfc, 0x53, -0xb5, 0x4d, 0x29, 0xef, 0x76, 0x85, 0xcf, 0xb9, -0x2e, 0x95, 0x7e, 0xa2, 0x5c, 0xa3, 0xf5, 0xd9, -0x3b, 0x66, 0xf8, 0x69, 0x0b, 0x3f, 0x6f, 0x24, -0x0f, 0x27, 0xea, 0xb2, 0x2b, 0xbf, 0x4e, 0xc6, -0xe8, 0xe1, 0x17, 0x7c, 0x59, 0xc7, 0x10, 0xc9, -0x0a, 0x26, 0x7e, 0x8e, 0x29, 0xfb, 0xd0, 0x54, -0x8e, 0x20, 0xf6, 0xed, 0x13, 0xd2, 0xac, 0xf1, -0x9e, 0x89, 0x9f, 0x65, 0x7b, 0xe0, 0x30, 0x4e, -0x7d, 0x65, 0x86, 0x4c, 0xc1, 0x3e, 0xc4, 0x4f, -0x6c, 0x4c, 0x1b, 0xef, 0x41, 0x29, 0x9b, 0x92, -0xd0, 0x54, 0xea, 0xea, 0x0c, 0x37, 0x05, 0xd7, -0x20, 0x84, 0x7d, 0xad, 0xe3, 0x16, 0x7e, 0xbe, -0x04, 0xaf, 0xa0, 0xa9, 0x5c, 0xd3, 0x55, 0xd7, -0x61, 0x56, 0x6b, 0xe4, 0xe1, 0xe7, 0x1e, 0xee, -0x03, 0x1c, 0xe7, 0xcc, 0x94, 0x4e, 0x91, 0x13, -0xd8, 0xa8, 0xcb, 0xf0, 0xe3, 0x46, 0x7c, 0x18, -0xb5, 0x35, 0x31, 0x53, 0x4d, 0xd8, 0xa7, 0x49, -0x40, 0xc4, 0xc6, 0x2f, 0x8a, 0x32, 0xe4, 0xa2, -0x85, 0x9f, 0xab, 0xe0, 0x7b, 0x10, 0xc8, 0x16, -0x06, 0xc9, 0x2a, 0x78, 0x56, 0x0e, 0xa8, 0xde, -0x20, 0x99, 0xb1, 0xfc, 0xb3, 0xa2, 0x67, 0x73, -0xa2, 0x36, 0xeb, 0xf8, 0x13, 0x52, 0x01, 0xdf, -0x4c, 0xd5, 0x66, 0xb9, 0x4e, 0x32, 0x6a, 0xe2, -0xa7, 0x58, 0x07, 0xdf, 0xa3, 0x4d, 0xef, 0x15, -0x35, 0x96, 0x7e, 0x61, 0xfc, 0xef, 0xd3, 0x4d, -0x53, 0xce, 0x7b, 0xf8, 0xd3, 0x86, 0x7f, 0x2a, -0xf3, 0x7f, 0x08, 0xd7, 0xa4, 0x26, 0xf5, 0x64, -0x86, 0xdf, 0x00, 0x1f, 0x40, 0x93, 0x8a, 0x31, -0x20, 0x87, 0x9f, 0x17, 0x12, 0x27, 0x84, 0xb0, -0xfa, 0xc0, 0x8b, 0x2b, 0x03, 0xda, 0xfa, 0xb0, -0xef, 0xbc, 0x85, 0x9f, 0x4f, 0x51, 0x74, 0x3d, -0x55, 0xbc, 0x9c, 0x28, 0x87, 0x83, 0xb0, 0x48, -0x75, 0x74, 0x90, 0xd3, 0x39, 0xfc, 0xa4, 0x9b, -0xe9, 0xe2, 0x6c, 0xe1, 0x13, 0x91, 0x0a, 0x38, -0x48, 0x2b, 0xb3, 0x8e, 0x4e, 0x32, 0x6d, 0xbc, -0xda, 0xa8, 0x67, 0x0c, 0x61, 0x33, 0x70, 0x24, -0x1a, 0x8c, 0x38, 0xd1, 0xb0, 0x7e, 0x66, 0xeb, -0xd3, 0x16, 0x7e, 0x0e, 0x20, 0x5e, 0x87, 0x69, -0x51, 0x1a, 0xf7, 0xe6, 0x55, 0xf0, 0x51, 0xdc, -0x2b, 0x57, 0x2d, 0xfc, 0xd4, 0x61, 0x13, 0xf7, -0xb4, 0xd6, 0x90, 0x5c, 0xb4, 0xf4, 0x74, 0x0e, -0x3f, 0xe1, 0x0a, 0x1f, 0x56, 0x8a, 0x75, 0x2c, -0x08, 0xad, 0x47, 0x2c, 0x18, 0xce, 0xc3, 0xcf, -0x43, 0x5c, 0xa0, 0x03, 0x43, 0xcd, 0x04, 0x1c, -0x82, 0xdd, 0x8a, 0x23, 0x85, 0x3e, 0x68, 0xe2, -0x27, 0x42, 0x2a, 0xd4, 0xad, 0xb5, 0xeb, 0x7d, -0x3e, 0xd6, 0x77, 0xd4, 0xc2, 0x4f, 0x81, 0x2e, -0x11, 0x02, 0x8a, 0xe8, 0x26, 0x23, 0xb0, 0x17, -0x71, 0x1e, 0xb1, 0x60, 0xd8, 0xc2, 0xcf, 0x75, -0x4a, 0x27, 0xce, 0x65, 0xfb, 0x26, 0xfe, 0x9c, -0x32, 0x1d, 0x63, 0x40, 0xf3, 0xe8, 0x05, 0x5e, -0x7f, 0x0f, 0x88, 0x9f, 0xca, 0x15, 0x06, 0x8d, -0x4f, 0xb3, 0xb9, 0xcc, 0x0b, 0x33, 0x80, 0xca, -0xe1, 0xe7, 0x84, 0x7c, 0x0c, 0x9a, 0x95, 0xd5, -0xa9, 0xee, 0x09, 0xb8, 0xa1, 0xd4, 0x2b, 0xce, -0x14, 0x7f, 0xd4, 0xc2, 0xcf, 0x73, 0x89, 0x1e, -0x52, 0x07, 0x7c, 0x32, 0x92, 0x45, 0xfc, 0xac, -0x01, 0x91, 0x92, 0x93, 0x79, 0xf8, 0xd9, 0x05, -0x7e, 0xc5, 0xe1, 0x4e, 0x20, 0x90, 0x82, 0xac, -0x88, 0x6c, 0x2e, 0xc6, 0x3d, 0x4b, 0xfa, 0xc5, -0x2d, 0x50, 0xc7, 0xa6, 0x3e, 0x21, 0xee, 0xc5, -0x86, 0x1f, 0xd7, 0x60, 0xe2, 0x67, 0xd9, 0x04, -0xee, 0xf7, 0x46, 0x06, 0xe1, 0x13, 0xc2, 0x15, -0x16, 0xa7, 0x53, 0xfc, 0xa4, 0xe1, 0x9f, 0x7e, -0x2e, 0x09, 0x1a, 0xa4, 0xea, 0x36, 0x6b, 0xd4, -0xf1, 0x53, 0x5f, 0x3b, 0xe2, 0xa7, 0x30, 0xc3, -0x85, 0x61, 0x35, 0x45, 0x5e, 0x30, 0x4a, 0x31, -0x56, 0x51, 0xfe, 0xb8, 0x89, 0x9f, 0x18, 0xdf, -0x5f, 0x84, 0xc5, 0x83, 0x8e, 0x34, 0xf1, 0x0b, -0xef, 0x70, 0xb5, 0x43, 0xd1, 0x34, 0xb1, 0xc6, -0xa1, 0x7f, 0xe2, 0x3e, 0xea, 0xc1, 0x57, 0x8a, -0xb1, 0x51, 0x0a, 0x44, 0xec, 0xc1, 0xc8, 0x71, -0xc3, 0x3f, 0xd3, 0x5c, 0xb9, 0x78, 0x17, 0xa9, -0xa5, 0x8e, 0x06, 0x7c, 0xe8, 0x37, 0xa1, 0x96, -0xfa, 0x3b, 0xc8, 0xa4, 0x31, 0x6e, 0x40, 0xac, -0x48, 0xff, 0x82, 0x2e, 0xcf, 0xba, 0x3a, 0xf9, -0x70, 0xfa, 0x35, 0xba, 0x5c, 0x2e, 0xee, 0xe4, -0xcf, 0x5b, 0xf8, 0xf9, 0x43, 0x7a, 0x8d, 0x84, -0x8f, 0xb8, 0x0e, 0xf0, 0x1f, 0x0a, 0xd7, 0xa0, -0x89, 0x71, 0x94, 0x61, 0xa2, 0xaf, 0x0f, 0x6c, -0x9f, 0xc4, 0x4f, 0x25, 0xc3, 0xe9, 0xd5, 0x3f, -0xe9, 0xfe, 0x91, 0x72, 0x32, 0x15, 0x92, 0x8b, -0x86, 0x78, 0xd5, 0xc2, 0xcf, 0xef, 0x24, 0xba, -0x9f, 0xae, 0x4d, 0xe3, 0xf3, 0xea, 0xc8, 0x8e, -0x4d, 0x7e, 0x59, 0xbc, 0x27, 0x1f, 0x3f, 0x61, -0xb3, 0x1b, 0xe7, 0x12, 0x24, 0x3b, 0xe9, 0x93, -0x72, 0x25, 0x6c, 0xe9, 0x70, 0xab, 0x92, 0xbe, -0x3e, 0x59, 0xf7, 0x4f, 0xaa, 0xaf, 0x01, 0xc3, -0x0c, 0x02, 0xd4, 0xa8, 0x60, 0xe2, 0xe7, 0x4b, -0xc8, 0x7b, 0xc2, 0x48, 0x85, 0xaa, 0x5e, 0x42, -0xc3, 0xfa, 0x00, 0xf7, 0xa6, 0x79, 0x4f, 0x0a, -0x53, 0xe2, 0x35, 0x2e, 0x9c, 0x5a, 0x9d, 0xe1, -0xa7, 0xd0, 0xd6, 0x68, 0xbc, 0x4c, 0x0e, 0x3f, -0x25, 0x84, 0x00, 0xae, 0x99, 0xee, 0x98, 0xe6, -0xaf, 0xc3, 0x0d, 0xb8, 0x0b, 0xec, 0xd3, 0xbc, -0x6a, 0xe1, 0xe7, 0x06, 0x86, 0x2f, 0xff, 0xd3, -0x81, 0xf8, 0x22, 0x1c, 0xc2, 0x01, 0x18, 0x7c, -0x72, 0xf8, 0x19, 0x80, 0xc3, 0x5c, 0x5d, 0x17, -0xeb, 0x83, 0x41, 0xea, 0xbb, 0xd5, 0x8e, 0x7d, -0x96, 0x7f, 0x3a, 0x95, 0xfa, 0x78, 0xa0, 0xd7, -0xb1, 0x74, 0x78, 0x2c, 0xbe, 0x4f, 0x96, 0x9d, -0xf6, 0x65, 0x96, 0x7f, 0x42, 0xd1, 0xc3, 0xf2, -0x35, 0x08, 0xf7, 0xb8, 0x2e, 0xf2, 0x37, 0xe8, -0x55, 0xf4, 0xcf, 0xe2, 0x0c, 0xaf, 0x1a, 0xfe, -0x99, 0xbe, 0x15, 0xa1, 0x4a, 0x6a, 0xb6, 0xf3, -0x17, 0x79, 0xc4, 0xcf, 0xf5, 0x77, 0x4b, 0x45, -0x1f, 0xf1, 0x39, 0xfc, 0xfc, 0x04, 0x66, 0x4b, -0xee, 0x91, 0x1f, 0xb8, 0x54, 0x58, 0xa7, 0x8e, -0xd1, 0x3f, 0x9f, 0x71, 0x36, 0xe4, 0xe1, 0xe7, -0x8f, 0xa4, 0x83, 0x1d, 0xbe, 0xb8, 0xe3, 0x12, -0x59, 0x10, 0xeb, 0x95, 0xeb, 0x46, 0xec, 0x43, -0x88, 0x83, 0x06, 0x7e, 0x0a, 0x63, 0x80, 0x53, -0xc8, 0xa2, 0xcd, 0x44, 0xd2, 0x5d, 0x18, 0xf8, -0x39, 0xda, 0xec, 0x62, 0x3e, 0x7e, 0x0a, 0x08, -0xb7, 0x19, 0xe2, 0x23, 0xbd, 0xb4, 0xf8, 0x55, -0x7b, 0x0e, 0x3f, 0xc1, 0xa6, 0xc1, 0x66, 0x1c, -0x5f, 0x69, 0x00, 0x56, 0x8e, 0xd6, 0xa5, 0x31, -0x1e, 0xa9, 0x26, 0x7e, 0x96, 0xbc, 0x24, 0xce, -0xc2, 0x2b, 0x0a, 0xc2, 0xe6, 0x04, 0xcc, 0xf2, -0xcb, 0xe7, 0xf2, 0xcf, 0x3d, 0x26, 0x1c, 0x8d, -0x49, 0xf8, 0x42, 0xba, 0x9c, 0x99, 0x3c, 0xfe, -0x19, 0x10, 0x5f, 0x01, 0x7c, 0xde, 0x34, 0xee, -0x69, 0xc4, 0xcf, 0x2e, 0x7c, 0x47, 0x21, 0xc3, -0x66, 0xaa, 0xc0, 0x20, 0x47, 0xce, 0xde, 0x9e, -0x29, 0xd0, 0x80, 0xb4, 0x45, 0x0c, 0xba, 0x1b, -0x4c, 0xfc, 0x94, 0x2a, 0xfa, 0x10, 0xaa, 0x26, -0x11, 0xaa, 0xde, 0x69, 0xfb, 0x3e, 0x0d, 0xb4, -0x17, 0x3e, 0x41, 0x9a, 0x24, 0x7d, 0x5c, 0x54, -0x2c, 0xa6, 0xfb, 0x20, 0x78, 0xde, 0x15, 0xe4, -0x8f, 0xd3, 0x9f, 0xa5, 0x9b, 0xda, 0x9d, 0x8d, -0xbc, 0xdb, 0xc4, 0x4f, 0xcf, 0x4b, 0x38, 0x97, -0x57, 0x46, 0x5c, 0x97, 0xbb, 0x26, 0x0b, 0xde, -0x96, 0x9a, 0x95, 0x3c, 0xfc, 0x14, 0xd9, 0xfa, -0x64, 0xf4, 0xdd, 0x41, 0x86, 0xad, 0x5c, 0xe8, -0x08, 0xce, 0xf3, 0xbc, 0xb1, 0xbe, 0x28, 0xb7, -0x13, 0x0e, 0x46, 0x6b, 0x55, 0x47, 0x08, 0xfd, -0x6c, 0x07, 0x04, 0xd5, 0xad, 0x1d, 0xe4, 0xa2, -0x61, 0x17, 0x19, 0xf9, 0xe7, 0xc1, 0x34, 0x62, -0xf9, 0x13, 0xe4, 0xcb, 0xf0, 0x7d, 0xfa, 0xd5, -0xac, 0xd8, 0x89, 0xef, 0x5d, 0x5f, 0x5f, 0x3b, -0xfa, 0xa7, 0x11, 0xab, 0x9c, 0x52, 0x37, 0x95, -0x55, 0x7b, 0x1e, 0x7e, 0x0a, 0x03, 0x08, 0x9b, -0xcd, 0x0c, 0x36, 0x3b, 0xe1, 0x42, 0xf4, 0xae, -0x64, 0x00, 0xf1, 0xd3, 0xb0, 0x59, 0x54, 0x62, -0x54, 0x28, 0x2c, 0x23, 0x7e, 0xbe, 0x07, 0x33, -0xa2, 0x06, 0xa4, 0x39, 0xfc, 0xec, 0x87, 0x37, -0xa1, 0xb1, 0xbd, 0x48, 0xe2, 0x93, 0x70, 0x4c, -0x08, 0x22, 0x4e, 0x70, 0xc3, 0x60, 0xe2, 0x67, -0x35, 0xec, 0xe5, 0xe4, 0x38, 0xe2, 0x67, 0x35, -0x74, 0x91, 0xdd, 0x8a, 0x78, 0x33, 0x7e, 0xd6, -0x28, 0x85, 0x29, 0xd2, 0x0f, 0x5b, 0x38, 0x5f, -0x8b, 0x38, 0x07, 0x3f, 0x61, 0x6f, 0xb5, 0x8f, -0xe1, 0xa7, 0x40, 0xb7, 0x40, 0x3c, 0x2a, 0xe6, -0xe1, 0xe7, 0xfc, 0x38, 0xcc, 0xc4, 0x1a, 0xa1, -0x08, 0xf9, 0xa7, 0x32, 0x1a, 0x0b, 0x79, 0x02, -0x94, 0x37, 0xf1, 0x73, 0x68, 0x3e, 0xc2, 0x91, -0xd4, 0x7c, 0x04, 0xf1, 0xf3, 0xf2, 0x1a, 0x8c, -0x9b, 0x6d, 0xae, 0x1c, 0x7e, 0x36, 0x20, 0x9f, -0x7f, 0xb3, 0xa5, 0x19, 0x29, 0x62, 0x62, 0x22, -0x7d, 0x9f, 0xb4, 0x6c, 0xd4, 0x39, 0xee, 0x7b, -0xdf, 0xf0, 0x4f, 0x2f, 0x64, 0xa5, 0x21, 0xa5, -0x0e, 0x1c, 0x4f, 0x26, 0x14, 0x4a, 0x41, 0xb6, -0xfb, 0x73, 0xf8, 0x19, 0xb5, 0x25, 0x61, 0x6f, -0x3c, 0xa0, 0xdc, 0x8a, 0x58, 0x9e, 0x46, 0x32, -0xbd, 0x4a, 0x94, 0xe0, 0xb4, 0x89, 0x9f, 0x9e, -0x7e, 0x16, 0x03, 0xe2, 0x2b, 0x53, 0xc2, 0x7a, -0xb2, 0x05, 0x63, 0x80, 0x37, 0x0f, 0x3f, 0x85, -0x7e, 0xef, 0x9b, 0x10, 0x8e, 0x17, 0xa5, 0xd6, -0xfd, 0xe3, 0xd2, 0x23, 0xc9, 0x6f, 0xb4, 0xac, -0x4a, 0xb5, 0x9a, 0xf8, 0xd9, 0x2e, 0xb1, 0x71, -0x1a, 0x7e, 0xb6, 0x49, 0x48, 0x9c, 0x58, 0xe3, -0x2d, 0xc3, 0xd6, 0x7e, 0xcd, 0xd6, 0x3e, 0xa9, -0x88, 0xb6, 0x56, 0xc2, 0x68, 0x24, 0x04, 0x47, -0x69, 0x95, 0x89, 0x9f, 0xa2, 0xe0, 0x87, 0x97, -0xc1, 0x37, 0x20, 0x66, 0x89, 0x1f, 0xb6, 0x62, -0x8c, 0x2b, 0xce, 0x5a, 0xf8, 0x29, 0x22, 0x7e, -0x3e, 0x8b, 0xfe, 0x89, 0xf1, 0x7d, 0x1b, 0x62, -0x4f, 0x8d, 0x5a, 0x28, 0x93, 0xe3, 0x56, 0x7c, -0x2f, 0x17, 0x0e, 0xa6, 0xab, 0xb2, 0x85, 0x9d, -0xe4, 0x2c, 0x6c, 0x96, 0x17, 0x8d, 0x88, 0x71, -0x0b, 0x3f, 0xfd, 0xde, 0x0a, 0xd8, 0x37, 0x50, -0x9f, 0x7d, 0xe0, 0x4f, 0xab, 0xbe, 0x4b, 0x5f, -0x7b, 0xe1, 0xee, 0xac, 0xab, 0x3d, 0x0f, 0x3f, -0x71, 0xff, 0x75, 0xbc, 0xac, 0x16, 0x0f, 0xf2, -0xb5, 0xe8, 0xa8, 0xcb, 0xc6, 0x17, 0xe7, 0xf8, -0x67, 0x5c, 0xf8, 0x11, 0x30, 0x9a, 0xb4, 0xe3, -0x4a, 0xf7, 0xac, 0xf2, 0x41, 0x5f, 0xf3, 0xe5, -0x40, 0x7b, 0x95, 0x64, 0xe2, 0xa7, 0xb4, 0x7d, -0xe4, 0x20, 0x95, 0x27, 0x0b, 0x67, 0x48, 0xb8, -0xba, 0x9b, 0x2e, 0x9e, 0xf4, 0xb6, 0x93, 0x9a, -0x3c, 0xfc, 0xfc, 0xa6, 0x5c, 0x39, 0x8a, 0x7b, -0x0c, 0x9d, 0x18, 0x6a, 0x55, 0x31, 0x5e, 0x53, -0x60, 0xf8, 0xa7, 0xe2, 0xd9, 0x26, 0xec, 0x23, -0xb2, 0xda, 0x1b, 0x24, 0xc5, 0x52, 0xa9, 0x8a, -0xfc, 0x53, 0x26, 0x5e, 0x13, 0x3f, 0x6d, 0x7b, -0xe0, 0x5d, 0x08, 0xbd, 0x31, 0x6f, 0x9a, 0x7f, -0x19, 0x66, 0xa3, 0xcd, 0xaa, 0x33, 0x7d, 0x7b, -0x9d, 0xc5, 0xf5, 0x19, 0x16, 0x84, 0xd5, 0xa2, -0x0c, 0xbf, 0x07, 0x18, 0x39, 0x72, 0xa5, 0xe7, -0xe0, 0xe7, 0x35, 0x68, 0xce, 0xba, 0xa6, 0xed, -0xe5, 0xe4, 0x54, 0xe1, 0x72, 0x15, 0x8d, 0x67, -0x72, 0x37, 0x03, 0x3f, 0x55, 0xc4, 0x17, 0xe4, -0x98, 0xa4, 0x4e, 0x2d, 0x4a, 0xfb, 0x4c, 0xff, -0xa4, 0x36, 0xd6, 0x57, 0x33, 0x82, 0x5b, 0x64, -0x0f, 0x72, 0xa9, 0xc7, 0x54, 0x7b, 0x3a, 0x87, -0x9f, 0x92, 0x53, 0xde, 0x27, 0x06, 0x46, 0x1d, -0xa1, 0x82, 0x6d, 0xe9, 0xee, 0x75, 0x81, 0x9f, -0xf2, 0x0b, 0x13, 0x16, 0x7e, 0x8a, 0x1b, 0x90, -0xbb, 0x35, 0xaa, 0xc5, 0x17, 0xb9, 0x9f, 0xa8, -0xa7, 0xe4, 0xe6, 0xd1, 0xe2, 0x7e, 0x3e, 0x6b, -0xe2, 0x67, 0xd9, 0x75, 0x79, 0x16, 0xc2, 0x6b, -0x90, 0x1e, 0x6f, 0x10, 0x67, 0xe3, 0xe1, 0x31, -0x24, 0x2b, 0x93, 0x11, 0x0b, 0x3f, 0x3d, 0xd3, -0xc9, 0xc3, 0x72, 0x51, 0x94, 0x34, 0xc0, 0x25, -0x7a, 0x57, 0xb6, 0x18, 0xf9, 0xa7, 0xe1, 0x2f, -0x14, 0x2e, 0x88, 0x43, 0xd4, 0x27, 0xa3, 0x5b, -0xfa, 0x00, 0x05, 0x24, 0xe3, 0x9f, 0xd3, 0x96, -0x7e, 0x1f, 0x83, 0x0c, 0x0b, 0x35, 0x80, 0x12, -0x71, 0x1f, 0xf4, 0xb3, 0xcd, 0x9d, 0x8f, 0x9f, -0x38, 0xce, 0x27, 0xf6, 0x3c, 0x33, 0x00, 0xf7, -0x80, 0x8f, 0x2d, 0x34, 0x1f, 0x3f, 0xaf, 0xa4, -0x1b, 0x82, 0x45, 0x4e, 0xfe, 0x07, 0x70, 0x09, -0x96, 0xa9, 0xc5, 0x19, 0x62, 0xea, 0x07, 0xc4, -0x4f, 0xe7, 0x75, 0x68, 0xe6, 0x76, 0x8c, 0xf3, -0x7f, 0x60, 0xf2, 0xcf, 0xeb, 0x79, 0xf8, 0x89, -0xfb, 0x1d, 0x9c, 0xc9, 0xee, 0x01, 0x8d, 0x7f, -0xba, 0x32, 0xe4, 0x0d, 0xe3, 0xfd, 0x21, 0x7e, -0x52, 0x4a, 0x6b, 0x0a, 0xc4, 0xe7, 0xc9, 0x00, -0xe2, 0xa7, 0xf6, 0xbc, 0x8b, 0x39, 0xfc, 0x14, -0x52, 0x6e, 0x3f, 0xe2, 0xa1, 0xd2, 0x83, 0xf8, -0xa9, 0x71, 0x37, 0x93, 0xd7, 0xc9, 0x4a, 0x05, -0x6c, 0xa3, 0x8b, 0x64, 0xf1, 0x18, 0x79, 0x3e, -0xf9, 0x7d, 0x06, 0xa4, 0x4f, 0xc0, 0x75, 0xa3, -0x2f, 0xea, 0x75, 0xc2, 0x78, 0xba, 0x41, 0x0e, -0xd8, 0xf9, 0xde, 0xe4, 0xcf, 0x92, 0x0d, 0x93, -0x2e, 0xe4, 0x9f, 0x05, 0x7a, 0x9f, 0x52, 0xbe, -0x13, 0xae, 0x56, 0x2e, 0x87, 0x1d, 0x09, 0x7e, -0x52, 0x79, 0x1b, 0x8d, 0xee, 0x42, 0x0e, 0x5d, -0x60, 0xec, 0x95, 0xb2, 0x29, 0x61, 0x1a, 0x96, -0xb5, 0x6c, 0xa5, 0x3c, 0x03, 0xfc, 0x85, 0x0c, -0xf0, 0x87, 0x4d, 0xfe, 0x79, 0x5f, 0x39, 0xec, -0x27, 0x95, 0x8a, 0x4d, 0x25, 0x5e, 0xf4, 0xc1, -0x4a, 0xe4, 0x9f, 0x70, 0xd1, 0x58, 0x9f, 0x0c, -0x15, 0xb0, 0x9f, 0x2e, 0x96, 0xed, 0x51, 0x82, -0x40, 0x4a, 0x17, 0x30, 0xfe, 0x79, 0xc6, 0x98, -0x4b, 0x3b, 0xc6, 0xaa, 0xcc, 0x1a, 0x7f, 0x62, -0x4b, 0x6d, 0x82, 0xd9, 0xba, 0x9a, 0xad, 0xe1, -0xad, 0x3c, 0xfe, 0xf9, 0xb1, 0xba, 0xbc, 0xa7, -0x22, 0xcb, 0x7f, 0x4b, 0xbe, 0x0a, 0xcb, 0xa8, -0x83, 0xe1, 0xa7, 0x3e, 0x17, 0xd4, 0xef, 0x30, -0x24, 0x2e, 0x2c, 0xb9, 0x23, 0x59, 0x1a, 0x4f, -0xcd, 0xa0, 0xf1, 0x5c, 0xb4, 0xea, 0xb4, 0xb9, -0xa7, 0x19, 0xff, 0x4c, 0x84, 0x62, 0xfc, 0xf3, -0x7c, 0xb5, 0x74, 0x2c, 0xb2, 0x90, 0x71, 0xbe, -0x61, 0xa3, 0x8f, 0x0a, 0x0b, 0x94, 0x43, 0xf4, -0x85, 0xb5, 0x3d, 0x5e, 0xc4, 0xcf, 0x5d, 0xd4, -0xa7, 0xf3, 0x4f, 0xfd, 0xd2, 0xf0, 0x53, 0xaa, -0x41, 0x48, 0xb5, 0x57, 0x9b, 0x24, 0x6e, 0x0e, -0x7e, 0x22, 0xb6, 0x8a, 0x92, 0xbd, 0x3a, 0x59, -0xc9, 0xc8, 0x1f, 0xc3, 0x4f, 0xfd, 0x9e, 0x43, -0xf3, 0xdb, 0x11, 0xe7, 0x1b, 0xa1, 0xf6, 0xaf, -0x19, 0x3f, 0xd3, 0x49, 0xf1, 0x85, 0x79, 0x39, -0xfc, 0xbc, 0x01, 0xcb, 0x95, 0xa2, 0x71, 0xfe, -0xb2, 0xf2, 0x11, 0xdc, 0xc2, 0xe6, 0x72, 0xc1, -0xc2, 0xcf, 0xfd, 0xf0, 0x0f, 0x64, 0xb9, 0xe2, -0x8c, 0x71, 0xd5, 0xf2, 0x3f, 0x40, 0x85, 0x72, -0x47, 0xaa, 0xea, 0x82, 0xe1, 0x83, 0x88, 0x9f, -0x30, 0x84, 0xae, 0x59, 0x44, 0xa1, 0x12, 0x7a, -0x00, 0x81, 0x94, 0xe2, 0x5c, 0x0c, 0xfc, 0x14, -0x92, 0xc2, 0xb7, 0xa0, 0x5a, 0xf1, 0xbb, 0x13, -0xd5, 0xe4, 0x69, 0x08, 0x28, 0x76, 0x89, 0x9c, -0x36, 0xe6, 0xe2, 0x8d, 0xf5, 0x6b, 0xd4, 0xb9, -0x10, 0xd7, 0x40, 0xd9, 0x1a, 0x56, 0x32, 0xfc, -0xd4, 0xfb, 0xd2, 0x6d, 0xfd, 0xc2, 0x4f, 0xe9, -0xd2, 0x3f, 0xf1, 0x78, 0xb9, 0x6a, 0x74, 0xb8, -0x3f, 0x67, 0x18, 0x39, 0x69, 0xc6, 0xb1, 0x12, -0xd4, 0xf6, 0xfe, 0x70, 0xc7, 0x1d, 0xcf, 0x39, -0x18, 0xff, 0xd4, 0xfa, 0xde, 0x32, 0x39, 0xa6, -0x24, 0xcb, 0xa8, 0xdf, 0xbd, 0x2e, 0xda, 0x9a, -0xd6, 0xd6, 0xf7, 0x54, 0x8e, 0x7f, 0x8a, 0xb6, -0x46, 0x28, 0x56, 0xaa, 0x32, 0xf6, 0xf7, 0x71, -0xaf, 0xbc, 0xd3, 0x56, 0x87, 0xbf, 0x12, 0x31, -0x75, 0xa3, 0x68, 0x5b, 0x01, 0x5d, 0x0f, 0xca, -0x9b, 0x6e, 0x0d, 0x24, 0x9c, 0xb0, 0x3b, 0xab, -0x05, 0xc9, 0xe1, 0x9c, 0x3e, 0xf2, 0x3d, 0x05, -0xeb, 0x90, 0x7a, 0x91, 0x97, 0xe0, 0x2f, 0x8b, -0xbe, 0xc6, 0xf4, 0xca, 0xa8, 0x89, 0xd7, 0x5e, -0x37, 0x42, 0xf4, 0x12, 0xb9, 0xa8, 0x93, 0xaf, -0x80, 0x09, 0x3a, 0x3f, 0xfb, 0xed, 0x4e, 0x2b, -0x97, 0x20, 0xce, 0xa7, 0x30, 0x8d, 0x88, 0xbd, -0x38, 0x33, 0x6f, 0x4c, 0x9a, 0x81, 0x0a, 0x14, -0x7b, 0x7c, 0xe4, 0x16, 0x7d, 0x5c, 0x5c, 0x78, -0x1e, 0xa6, 0xe8, 0x8b, 0xeb, 0xeb, 0x3a, 0xab, -0x2a, 0x50, 0xc8, 0x37, 0x4f, 0xb8, 0x66, 0xf8, -0x33, 0xc6, 0x3c, 0x07, 0xa0, 0x2f, 0x99, 0x94, -0x97, 0xca, 0x45, 0x41, 0x7b, 0x31, 0xdd, 0xbc, -0x2b, 0x90, 0x45, 0x22, 0x7a, 0x9e, 0xc8, 0x86, -0xd3, 0xa7, 0x0a, 0xf6, 0xc0, 0x22, 0xa7, 0xe3, -0x23, 0xd2, 0x44, 0x37, 0x05, 0x6b, 0x47, 0x71, -0x2e, 0x47, 0x15, 0xbd, 0x4f, 0xf1, 0x50, 0xa0, -0x4a, 0xbf, 0x5c, 0xb8, 0x94, 0x14, 0x91, 0x2e, -0x2d, 0xd0, 0xfb, 0xc6, 0x0d, 0x6d, 0x3f, 0x80, -0x9c, 0x3d, 0xab, 0x36, 0x90, 0xe2, 0xfd, 0xbc, -0x8b, 0x24, 0x04, 0xb6, 0x6f, 0xf9, 0x0b, 0x54, -0x9f, 0x4b, 0x1a, 0x7d, 0x70, 0x26, 0x16, 0x96, -0x16, 0xff, 0x98, 0x9f, 0x52, 0xae, 0x46, 0xc2, -0xea, 0x8e, 0x4c, 0xd5, 0xa4, 0xa5, 0xdf, 0xa7, -0x85, 0x29, 0xb1, 0x5e, 0x2e, 0x9a, 0x7e, 0xf6, -0xba, 0x7c, 0x76, 0x77, 0x95, 0xba, 0x7a, 0xba, -0x34, 0x6e, 0x70, 0xcc, 0x2e, 0xe1, 0x11, 0x18, -0x18, 0xf5, 0x85, 0x6a, 0xfb, 0xc8, 0x14, 0xe9, -0x39, 0x57, 0x83, 0xfb, 0xdd, 0x97, 0xe3, 0x9f, -0xd8, 0x97, 0xd8, 0x2d, 0x2e, 0x7a, 0x09, 0xfb, -0x86, 0xa0, 0xe6, 0x48, 0x61, 0xc6, 0x9d, 0xd3, -0xef, 0xf8, 0x4c, 0x48, 0x17, 0xde, 0xb7, 0x84, -0x7c, 0x88, 0xe4, 0xbe, 0x7d, 0xd4, 0xb1, 0xb4, -0x60, 0x58, 0x30, 0x1d, 0x5b, 0x86, 0xc9, 0x58, -0xe8, 0xb6, 0xa2, 0xfd, 0xa5, 0x1f, 0xd2, 0x19, -0xa9, 0xf1, 0x9d, 0xa2, 0x03, 0x5d, 0x71, 0xd9, -0xd4, 0xef, 0xd3, 0x70, 0x19, 0x96, 0xdb, 0x71, -0x0a, 0x53, 0x23, 0x67, 0xdd, 0xe1, 0x51, 0xdc, -0xef, 0x66, 0x4c, 0x55, 0x6d, 0xff, 0x04, 0xa7, -0x68, 0x48, 0x2d, 0x7c, 0x89, 0x7f, 0x5f, 0x79, -0x97, 0x86, 0xc7, 0x03, 0x43, 0x16, 0xff, 0x54, -0xa5, 0x09, 0xd2, 0xdd, 0x53, 0x75, 0x19, 0xa9, -0xe5, 0x18, 0xf4, 0xd2, 0xba, 0x37, 0xc4, 0x21, -0xc8, 0x5a, 0xf1, 0x7d, 0x8a, 0x7e, 0x4f, 0x4e, -0x33, 0x2e, 0x35, 0x46, 0x9f, 0x85, 0xc0, 0xe8, -0xad, 0xf9, 0xfa, 0xbd, 0xbf, 0xfc, 0x6f, 0x11, -0xc6, 0xc4, 0x4c, 0xc1, 0x94, 0xd4, 0xcb, 0xd5, -0xa9, 0x85, 0x39, 0xfc, 0xa4, 0x65, 0x23, 0x18, -0x6a, 0x42, 0x68, 0x2a, 0xfe, 0x82, 0x26, 0xe4, -0x31, 0xf8, 0x98, 0xfa, 0x21, 0xcb, 0xed, 0x17, -0xde, 0x25, 0xcb, 0x19, 0x6c, 0xce, 0x22, 0x7e, -0x2e, 0x57, 0x8b, 0x91, 0x7f, 0x9a, 0xba, 0x1f, -0x63, 0xff, 0x35, 0x18, 0x44, 0xb8, 0xd5, 0x63, -0xd5, 0x11, 0xc6, 0xf9, 0x8c, 0xf7, 0xde, 0x83, -0x7b, 0xfa, 0xf0, 0xd6, 0x2a, 0x7c, 0xde, 0x1a, -0x96, 0xf3, 0x58, 0x7c, 0xc4, 0x31, 0x47, 0xbf, -0x8b, 0xc8, 0x3f, 0x91, 0xb2, 0x45, 0xa6, 0x18, -0xff, 0x3c, 0x92, 0x87, 0x9f, 0xe9, 0xae, 0x5b, -0xd4, 0x83, 0x29, 0xf9, 0x9c, 0xd8, 0xe9, 0xfe, -0xf2, 0xc8, 0x66, 0x5a, 0x8b, 0xf8, 0x49, 0xce, -0x18, 0xf6, 0x8c, 0x46, 0x8b, 0xe1, 0x52, 0x26, -0x98, 0x2d, 0x6e, 0xe0, 0x4f, 0xc2, 0xcf, 0x68, -0xd3, 0xa4, 0xab, 0x31, 0x4f, 0xbf, 0xef, 0x67, -0xb1, 0x71, 0x1c, 0xa7, 0xb0, 0x47, 0xc2, 0xc0, -0x34, 0xec, 0xda, 0x6b, 0xcd, 0x65, 0xc0, 0x36, -0x51, 0x78, 0x02, 0x06, 0xb1, 0xaf, 0x4a, 0xcb, -0x33, 0x64, 0x8b, 0xf2, 0xf0, 0xf3, 0xe9, 0xe7, -0xb8, 0xcd, 0x50, 0x79, 0x06, 0x5d, 0x0f, 0xf9, -0x04, 0x2c, 0x1e, 0x15, 0x51, 0xbf, 0x1b, 0xfb, -0x81, 0xc2, 0x01, 0xd8, 0x9c, 0xd4, 0x64, 0xfb, -0x27, 0x12, 0xce, 0x85, 0x91, 0x8e, 0x51, 0x2b, -0xff, 0xf9, 0x7e, 0xe4, 0x6f, 0x99, 0x1c, 0x66, -0xef, 0x41, 0xcb, 0x2f, 0xcd, 0xc1, 0x4f, 0xe9, -0x38, 0x0a, 0x15, 0xe4, 0x9f, 0x93, 0xa6, 0x90, -0xbf, 0xca, 0xe9, 0xf7, 0x64, 0xfa, 0x7d, 0xad, -0xa1, 0xdf, 0x15, 0x43, 0xc8, 0x9b, 0xf9, 0x02, -0x2d, 0xff, 0x09, 0xa1, 0x16, 0x17, 0xd3, 0xe1, -0xc7, 0x74, 0x52, 0x95, 0xc3, 0xcf, 0xf5, 0xb0, -0x85, 0x68, 0xb0, 0x39, 0x42, 0xb6, 0x70, 0x8f, -0xdd, 0x84, 0x9f, 0xe2, 0x16, 0x5d, 0xb6, 0x4f, -0xc0, 0xcd, 0xf8, 0xd9, 0x26, 0x40, 0x17, 0xa4, -0xa3, 0x08, 0x9b, 0x13, 0xd0, 0xc5, 0x05, 0xa2, -0x73, 0xf5, 0x7b, 0x4c, 0x65, 0xb2, 0x9d, 0xe9, -0xf7, 0x51, 0xa8, 0xf3, 0xec, 0xc8, 0xe1, 0xe7, -0xe8, 0xfc, 0x37, 0x58, 0x3a, 0xb1, 0x6d, 0x75, -0xaa, 0xf5, 0x0d, 0x91, 0x35, 0x5c, 0x39, 0xfc, -0xf4, 0xda, 0x5e, 0x45, 0x6c, 0x0d, 0x99, 0x9a, -0x39, 0x7c, 0xbf, 0x8b, 0xe1, 0xa7, 0xde, 0xd7, -0x29, 0x21, 0x7e, 0xca, 0xbb, 0x19, 0x6c, 0x62, -0x03, 0xea, 0xbc, 0x0e, 0xea, 0x36, 0xf1, 0x13, -0xf5, 0x3b, 0xec, 0x15, 0xe5, 0x18, 0xf2, 0x56, -0xa6, 0xdf, 0x03, 0x11, 0x9c, 0xcb, 0x69, 0xc3, -0x9e, 0xde, 0xb2, 0x7e, 0xc4, 0x79, 0x63, 0x0d, -0x87, 0x8c, 0x35, 0x98, 0xf8, 0xe9, 0x61, 0xf9, -0x4f, 0xed, 0x79, 0xef, 0x03, 0x4b, 0x2a, 0xec, -0xc8, 0xc3, 0x4f, 0xe8, 0x37, 0xd2, 0x9e, 0x8f, -0x4e, 0x28, 0x46, 0xfe, 0x33, 0x87, 0x9f, 0x08, -0x9b, 0x74, 0x90, 0x99, 0xd8, 0x8a, 0x0f, 0x96, -0x7e, 0x47, 0xfe, 0xb9, 0x1d, 0x69, 0x27, 0xd3, -0xef, 0xf0, 0x82, 0x50, 0xc7, 0x1a, 0x26, 0x7e, -0x32, 0xfd, 0xde, 0xad, 0xbd, 0x5b, 0x9f, 0x9e, -0x3b, 0x9c, 0x83, 0x9f, 0x61, 0xba, 0x99, 0x85, -0xd9, 0x4e, 0xd4, 0xef, 0xdf, 0x87, 0xda, 0x57, -0x35, 0xfc, 0xd4, 0x6d, 0xed, 0x17, 0x2b, 0xc8, -0x29, 0xba, 0x24, 0xeb, 0xba, 0xc6, 0x87, 0x55, -0xd4, 0xef, 0x93, 0xae, 0xce, 0xaa, 0xe3, 0x46, -0x7c, 0x47, 0xfe, 0x49, 0x19, 0xaf, 0x43, 0x0d, -0xf4, 0xa1, 0xde, 0xc8, 0xe4, 0xe5, 0x3f, 0xff, -0x29, 0x7e, 0x72, 0x33, 0xe3, 0x9f, 0x3f, 0x43, -0xe1, 0x49, 0x91, 0xe0, 0xcd, 0x94, 0x9e, 0x31, -0xd6, 0x87, 0xfa, 0xdd, 0xb7, 0x15, 0xee, 0x3c, -0xe2, 0xe8, 0x8c, 0x9c, 0xad, 0xde, 0x47, 0x6b, -0xa7, 0x56, 0xfe, 0xa9, 0xfb, 0xbc, 0xb1, 0x06, -0xa0, 0x3b, 0xe9, 0x76, 0x2d, 0xe4, 0xa3, 0xef, -0x1e, 0x14, 0x10, 0x3f, 0x1f, 0x27, 0x23, 0x06, -0x7e, 0xc6, 0x3d, 0x27, 0x91, 0x56, 0x57, 0xb3, -0x6d, 0x87, 0x42, 0x49, 0xa8, 0x53, 0x57, 0x06, -0x89, 0xb5, 0x1f, 0xca, 0x5e, 0x96, 0x8e, 0x31, -0xdd, 0xc8, 0xa8, 0xd0, 0x35, 0x61, 0x31, 0xce, -0xe5, 0x8b, 0xe7, 0x2d, 0x9f, 0x9f, 0x92, 0x8c, -0xe9, 0xe9, 0x44, 0x94, 0x35, 0x84, 0x1c, 0xff, -0xbc, 0x01, 0xf5, 0x6c, 0x5c, 0x93, 0xc6, 0xa5, -0x9c, 0xd3, 0x7c, 0xb6, 0xcd, 0xd4, 0x47, 0x8c, -0x63, 0x32, 0x9a, 0xb4, 0x66, 0x0f, 0x13, 0xeb, -0x2a, 0xea, 0xdb, 0x73, 0x16, 0x7e, 0x6e, 0x80, -0x43, 0x3d, 0x3e, 0x9d, 0x9b, 0x32, 0x92, 0xca, -0xb4, 0xbd, 0x89, 0x9f, 0x80, 0xfc, 0x93, 0xd9, -0x3a, 0xe3, 0x7e, 0x4a, 0xd8, 0x57, 0x55, 0x37, -0x8c, 0x24, 0x35, 0xc7, 0x3f, 0xff, 0x33, 0xbd, -0x22, 0x85, 0x46, 0x5c, 0xff, 0x5c, 0xba, 0x1c, -0xae, 0x29, 0xe1, 0xf1, 0x6d, 0xfb, 0xf8, 0xac, -0xb1, 0xdf, 0xd3, 0xf3, 0xaf, 0xa7, 0x67, 0xab, -0x9b, 0x8f, 0xb9, 0xf6, 0x31, 0xfd, 0xde, 0x10, -0x3e, 0xe1, 0x3a, 0x90, 0xd3, 0xef, 0xdc, 0x27, -0xc8, 0xe7, 0x97, 0xc7, 0x5d, 0x43, 0x7c, 0x0d, -0x8c, 0xe1, 0xfe, 0xbb, 0x63, 0xc8, 0xaa, 0x1f, -0xa9, 0xe2, 0x05, 0x38, 0x9c, 0x40, 0xf7, 0xca, -0x90, 0x1a, 0x78, 0xab, 0xab, 0x8e, 0xf1, 0x4f, -0x99, 0xe8, 0x6b, 0x18, 0x45, 0xfe, 0xb9, 0x8f, -0x6c, 0x50, 0xf0, 0x75, 0xfb, 0xc0, 0x78, 0xef, -0x16, 0x7e, 0xda, 0x98, 0x7e, 0x7f, 0x2c, 0xae, -0xe9, 0xf7, 0xbf, 0x82, 0xba, 0x11, 0x96, 0xff, -0x34, 0x6c, 0x26, 0x95, 0x69, 0xa6, 0x92, 0x4f, -0x05, 0x79, 0x3b, 0x8c, 0x46, 0xc3, 0x69, 0x47, -0xc6, 0x91, 0x97, 0xff, 0xf4, 0xa2, 0xa9, 0x50, -0xbf, 0x3b, 0x66, 0xe0, 0x13, 0x96, 0x4f, 0x9e, -0x76, 0x34, 0x18, 0xe3, 0x62, 0x9a, 0x7e, 0x47, -0xfd, 0xa7, 0xd5, 0x65, 0x20, 0x34, 0xd2, 0x94, -0xc3, 0x4f, 0xa6, 0xdf, 0xd1, 0x54, 0xdf, 0x10, -0x87, 0x50, 0x53, 0xf6, 0xc2, 0xb2, 0xac, 0x18, -0x8c, 0xe4, 0xf8, 0x27, 0xcb, 0x2f, 0xf9, 0x95, -0xc2, 0x06, 0x22, 0x72, 0x5d, 0x44, 0x90, 0xc5, -0x20, 0x4c, 0x73, 0xba, 0x3d, 0xa7, 0xe1, 0xcb, -0xf4, 0x20, 0xad, 0x5d, 0x8f, 0x52, 0xf9, 0xf9, -0xae, 0x1d, 0x5d, 0x0b, 0x3a, 0xb1, 0x31, 0x2a, -0xe9, 0xef, 0x21, 0x0a, 0x5f, 0xa0, 0x97, 0x52, -0x0d, 0x3f, 0x7f, 0x60, 0xa8, 0x97, 0xd0, 0x13, -0x74, 0xe9, 0xa4, 0x88, 0xfc, 0xd3, 0x30, 0xb5, -0x32, 0x1f, 0xf5, 0xbb, 0x3b, 0xcc, 0x64, 0xbb, -0xaa, 0xbd, 0xf7, 0x53, 0x37, 0xe9, 0x77, 0x5c, -0xdf, 0xfc, 0x0c, 0xef, 0x87, 0x63, 0x34, 0x24, -0x3b, 0x73, 0xf8, 0x39, 0x7a, 0xab, 0x26, 0x7d, -0x94, 0xb5, 0xd3, 0xfc, 0x5a, 0xf8, 0x5f, 0x50, -0xa9, 0xf4, 0x74, 0xf8, 0x4e, 0x1b, 0xe3, 0x34, -0xfd, 0x8e, 0xfc, 0xf3, 0xbe, 0xce, 0xd0, 0x60, -0x10, 0x35, 0x3a, 0xd3, 0xef, 0x3d, 0xe6, 0xbe, -0x45, 0xfe, 0x79, 0x18, 0x02, 0x31, 0x31, 0x68, -0x3f, 0x8e, 0x62, 0x2f, 0xad, 0xfa, 0x11, 0x3f, -0x21, 0x57, 0x3f, 0x42, 0xfd, 0x3e, 0x84, 0xb0, -0x39, 0x04, 0x27, 0xa1, 0x9e, 0x3a, 0xd3, 0xfc, -0x8b, 0x56, 0xbe, 0x40, 0xd3, 0xef, 0x6e, 0x17, -0x25, 0x8f, 0x98, 0x89, 0x50, 0x13, 0xaf, 0x45, -0xad, 0x4e, 0x12, 0x8a, 0xbb, 0xfa, 0x4a, 0xab, -0x7f, 0x15, 0x7e, 0x1e, 0x22, 0xbe, 0x0e, 0x47, -0x9f, 0x4f, 0x80, 0x2d, 0x2d, 0x75, 0xb1, 0xbc, -0xfc, 0x67, 0x83, 0xa6, 0xdf, 0x7d, 0x6b, 0x1d, -0x6e, 0xe4, 0xa6, 0x5b, 0x0a, 0xeb, 0x22, 0xd8, -0x77, 0xd2, 0xdc, 0xd3, 0x1e, 0x01, 0xfb, 0x64, -0xa5, 0x57, 0x22, 0x0b, 0xa1, 0x4b, 0xd6, 0xf0, -0xf3, 0xb8, 0x4d, 0xb7, 0xd9, 0x50, 0x51, 0x5c, -0x98, 0x81, 0xc1, 0x32, 0xc4, 0x4f, 0x59, 0x62, -0xf8, 0xb2, 0x23, 0xa7, 0xdf, 0xfb, 0xca, 0x18, -0x34, 0x2e, 0x67, 0x35, 0x9b, 0x37, 0x0a, 0x6e, -0x48, 0xba, 0x7e, 0x37, 0x6c, 0xd6, 0x67, 0x63, -0x7d, 0xcd, 0x8a, 0x73, 0xbc, 0x4a, 0x90, 0x8e, -0x89, 0xe1, 0xfb, 0x9d, 0xe3, 0xfc, 0x51, 0xc3, -0xcf, 0x1a, 0xbc, 0x1a, 0x6c, 0x8a, 0x48, 0xf5, -0xe2, 0xd0, 0xd3, 0xb2, 0x58, 0x62, 0xf9, 0xcf, -0x02, 0x23, 0xbe, 0x03, 0xea, 0x77, 0x08, 0xb4, -0xde, 0x16, 0xa2, 0xfb, 0xc5, 0x4d, 0x5d, 0xb5, -0x71, 0x91, 0xf1, 0x4f, 0x7d, 0xed, 0x5e, 0x81, -0xf1, 0xcf, 0xc7, 0x94, 0xdb, 0x53, 0x35, 0x13, -0xbb, 0x9f, 0x92, 0x17, 0x47, 0xb5, 0x1c, 0x84, -0xb1, 0x57, 0xca, 0x26, 0xa4, 0x2b, 0xd0, 0xa4, -0x6c, 0x4f, 0xb1, 0xbc, 0x46, 0x4b, 0x38, 0x16, -0xc8, 0xe5, 0x3f, 0xa3, 0x9c, 0x86, 0x9f, 0xeb, -0x8b, 0x52, 0x3c, 0xab, 0x73, 0x35, 0x31, 0x9b, -0xe5, 0xec, 0xa9, 0xd9, 0x1a, 0xee, 0xa0, 0xa5, -0x95, 0xc2, 0x28, 0xd4, 0x43, 0x80, 0x5a, 0xf6, -0x34, 0xf2, 0x9f, 0x03, 0x8e, 0x2c, 0x68, 0xfa, -0x3d, 0x2d, 0xfe, 0x52, 0xfe, 0xf3, 0x1c, 0x9f, -0x89, 0x38, 0xa5, 0xee, 0x84, 0x4c, 0x31, 0x36, -0x9a, 0xfa, 0x9d, 0x96, 0x94, 0x6b, 0x52, 0x19, -0x31, 0x6b, 0x29, 0xd9, 0xac, 0x56, 0x26, 0x30, -0xde, 0x66, 0x05, 0x7d, 0x5c, 0x8f, 0x58, 0x01, -0x2c, 0xff, 0xe9, 0xe8, 0x74, 0xdc, 0x06, 0xc3, -0x34, 0x93, 0x75, 0x76, 0xf2, 0xef, 0x99, 0xfa, -0xbd, 0x6c, 0x8f, 0x0e, 0x47, 0xcb, 0xfe, 0x2e, -0x2b, 0x5e, 0x45, 0xae, 0xf1, 0x5d, 0xe6, 0x83, -0xfa, 0x3c, 0x15, 0xa6, 0xdf, 0x91, 0x76, 0x3a, -0xaf, 0xf0, 0x61, 0xee, 0x18, 0xad, 0xaf, 0x76, -0x75, 0xf2, 0x60, 0xe2, 0xa7, 0x77, 0xbb, 0x70, -0x30, 0x5d, 0x37, 0xd9, 0xd3, 0xe9, 0xbb, 0x25, -0xdd, 0x95, 0xa9, 0xf4, 0x23, 0x70, 0xd7, 0x18, -0xba, 0x0a, 0xf5, 0xbb, 0x84, 0x73, 0x19, 0x16, -0x1f, 0x27, 0xde, 0x48, 0x52, 0xae, 0x8c, 0xe3, -0xa4, 0xcc, 0x71, 0x71, 0x61, 0x9b, 0xb4, 0x0f, -0xea, 0xa6, 0x11, 0xaa, 0x98, 0xf3, 0x60, 0xd0, -0x0a, 0x12, 0xd1, 0xe8, 0x1b, 0xd2, 0xe7, 0xf2, -0x6a, 0x20, 0xb3, 0xb2, 0x16, 0x4e, 0xd0, 0xc1, -0x94, 0x2b, 0xe3, 0x30, 0x73, 0x02, 0x49, 0xd0, -0xf6, 0x0a, 0xc5, 0x7d, 0x34, 0x21, 0x5c, 0xa2, -0x4d, 0xac, 0x61, 0xea, 0xf7, 0xb4, 0xa4, 0x95, -0x40, 0x46, 0x9d, 0x33, 0x7c, 0x83, 0x7c, 0x1c, -0xea, 0x87, 0x11, 0x3f, 0x47, 0x0d, 0xfc, 0xdc, -0xa5, 0xeb, 0xf7, 0x71, 0x84, 0x4d, 0x8a, 0xf1, -0x88, 0x11, 0x35, 0x32, 0x99, 0xcb, 0x7f, 0x0a, -0x87, 0x85, 0xba, 0x61, 0x71, 0x10, 0xf1, 0x73, -0x0b, 0xe7, 0xd3, 0x72, 0xa3, 0xb9, 0xfc, 0x27, -0xdd, 0xe7, 0x0b, 0x14, 0xda, 0xdd, 0xa4, 0x3f, -0xb9, 0x2b, 0x22, 0x83, 0xbf, 0x9e, 0x0c, 0x1b, -0xfe, 0x49, 0x8b, 0x36, 0x28, 0x08, 0x8d, 0xef, -0x3a, 0x3f, 0xae, 0xf2, 0x2b, 0xa3, 0xf1, 0xc1, -0xb5, 0xab, 0x06, 0xab, 0xac, 0xfc, 0xe7, 0xb7, -0xaf, 0xab, 0xb3, 0x72, 0xf8, 0x98, 0xab, 0xbe, -0x5b, 0x55, 0xaf, 0xc7, 0xc3, 0x5f, 0x40, 0x20, -0xb5, 0xf8, 0x67, 0xd9, 0x75, 0xd8, 0x80, 0xdb, -0xbc, 0x68, 0x94, 0x0f, 0xb3, 0x78, 0x74, 0xbf, -0x33, 0xa7, 0xdf, 0x55, 0xef, 0xac, 0xb0, 0x95, -0xca, 0x8f, 0x38, 0x7a, 0x48, 0x40, 0x3e, 0x4c, -0xeb, 0xa6, 0xed, 0x39, 0xfd, 0x3e, 0x6a, 0x7b, -0x5d, 0xf4, 0xa3, 0x8d, 0x1c, 0x90, 0x70, 0x6e, -0xd9, 0xa7, 0x73, 0x22, 0x4b, 0xbf, 0x73, 0x7b, -0x98, 0x9b, 0x28, 0xc8, 0x0b, 0xf4, 0x18, 0x60, -0xcf, 0xf8, 0x4c, 0x1e, 0x29, 0x21, 0xbe, 0x9c, -0x83, 0x10, 0x9a, 0xca, 0xc1, 0xfa, 0x2a, 0x58, -0x3d, 0x6e, 0xd4, 0xe2, 0x9f, 0x2f, 0x31, 0x9b, -0x0d, 0x6b, 0xb1, 0x6a, 0x96, 0x2c, 0x9f, 0xce, -0xcf, 0x7f, 0xc2, 0x1e, 0xe5, 0xcd, 0x92, 0x50, -0x7a, 0xd5, 0x10, 0xcf, 0xea, 0x32, 0x8c, 0x43, -0xf3, 0xa6, 0x7e, 0x3f, 0x63, 0x2b, 0x47, 0x7a, -0xec, 0xcb, 0x22, 0x7e, 0x06, 0x90, 0x9b, 0xd6, -0x4d, 0xcf, 0xe1, 0x9f, 0x0f, 0xd4, 0x64, 0x84, -0x6a, 0xc9, 0x4f, 0xc9, 0x36, 0x09, 0xbd, 0xfa, -0x72, 0x1e, 0xff, 0x9c, 0xe6, 0x2a, 0x60, 0x7b, -0x7a, 0x41, 0xbb, 0x18, 0x2d, 0x60, 0xe0, 0x55, -0x9b, 0xe5, 0x3b, 0x23, 0x9f, 0x18, 0x7d, 0x51, -0xd1, 0xa9, 0x4c, 0xd3, 0xa5, 0x72, 0xa0, 0x87, -0xdf, 0xae, 0xe2, 0xbb, 0x55, 0x5d, 0x4b, 0xf8, -0xb7, 0x4c, 0xfd, 0x3e, 0xff, 0x29, 0xf8, 0x98, -0xbb, 0x47, 0x71, 0xa9, 0x8e, 0x3f, 0x83, 0x0f, -0x24, 0x2d, 0xcf, 0x60, 0xea, 0xf7, 0x01, 0x96, -0x9f, 0x40, 0x9f, 0x98, 0xff, 0x22, 0x72, 0x53, -0x23, 0xa6, 0x1e, 0x37, 0xf1, 0xb3, 0x64, 0xa7, -0x70, 0x90, 0xd5, 0x8f, 0x36, 0xda, 0xad, 0x8d, -0x71, 0x51, 0xd2, 0xd7, 0x47, 0xe1, 0x3b, 0x23, -0x3f, 0x4e, 0xd6, 0xa6, 0xa3, 0x9d, 0xa4, 0x42, -0x9b, 0x0b, 0xfa, 0xae, 0x6a, 0xf1, 0x4f, 0x2d, -0xff, 0x39, 0x21, 0xde, 0x4d, 0x9c, 0xac, 0x91, -0x9d, 0x53, 0x3f, 0xea, 0x81, 0xab, 0x42, 0x98, -0xd6, 0xee, 0x21, 0xac, 0xb6, 0x1b, 0x1e, 0x70, -0xe5, 0xeb, 0xf7, 0xac, 0x30, 0x43, 0x19, 0x6c, -0x76, 0xc7, 0x2d, 0xfc, 0xcc, 0xe9, 0x77, 0xf2, -0x73, 0x84, 0xcd, 0x55, 0xcf, 0xf3, 0x8c, 0x7f, -0x36, 0x29, 0x81, 0x9b, 0xf8, 0x27, 0x57, 0x17, -0x8b, 0xee, 0x24, 0x13, 0x02, 0x72, 0xcc, 0x87, -0xc5, 0x39, 0xfc, 0x93, 0xfc, 0x80, 0xd6, 0x2a, -0x85, 0xe3, 0xee, 0x11, 0x8d, 0x7f, 0xce, 0xc9, -0x7f, 0x3a, 0xe9, 0x26, 0xa8, 0x8d, 0xfb, 0xd7, -0x92, 0x91, 0x5b, 0x50, 0xc7, 0xcd, 0xc9, 0x7f, -0x16, 0xc5, 0x61, 0x12, 0xc2, 0x9e, 0x55, 0xf7, -0x7e, 0x1e, 0xf9, 0x27, 0x17, 0x06, 0x67, 0x8e, -0x7f, 0x6a, 0xf5, 0x23, 0xb0, 0xea, 0x32, 0xcd, -0xf9, 0xfc, 0xb3, 0xcf, 0x76, 0x99, 0xbc, 0x0e, -0xf7, 0xb4, 0x39, 0xc7, 0x1d, 0xd5, 0xac, 0xef, -0x7e, 0x04, 0xaf, 0x0b, 0xb9, 0xfa, 0x11, 0xca, -0x76, 0xd4, 0xef, 0x04, 0x71, 0x07, 0x81, 0x94, -0xe1, 0xa7, 0xa5, 0xdf, 0x6d, 0x23, 0x0a, 0xab, -0x1f, 0xd9, 0xdd, 0x3e, 0x21, 0x8d, 0x40, 0xaa, -0x14, 0xce, 0xe1, 0x9f, 0x25, 0x5b, 0x10, 0xe7, -0x11, 0xde, 0xab, 0xb9, 0x43, 0xc6, 0x1a, 0x4c, -0xfe, 0xc9, 0xea, 0x47, 0x42, 0xa3, 0x52, 0xc3, -0x72, 0xbf, 0xc8, 0x3f, 0x5b, 0xbe, 0x8d, 0xf8, -0x69, 0xf8, 0x75, 0x3b, 0xab, 0x1f, 0xe1, 0x3c, -0x9d, 0x38, 0x4f, 0xe9, 0x8a, 0xd0, 0x14, 0xbd, -0x99, 0x7f, 0x42, 0x98, 0xab, 0x65, 0xfc, 0x13, -0x6d, 0x2d, 0x14, 0xe5, 0xf1, 0x4f, 0xae, 0x81, -0x0c, 0xd3, 0xc5, 0xd4, 0x99, 0x25, 0x7e, 0xee, -0x45, 0x6e, 0x31, 0x15, 0x6f, 0xe2, 0x9f, 0x29, -0xb6, 0x7d, 0xec, 0x4e, 0x89, 0xbd, 0x5b, 0x7f, -0x30, 0x32, 0x6c, 0xd5, 0x8f, 0x24, 0x94, 0x29, -0x68, 0xeb, 0x18, 0x29, 0xa7, 0x07, 0x71, 0x0d, -0x62, 0x07, 0x98, 0xfc, 0x73, 0x40, 0x2c, 0x86, -0xd7, 0x68, 0x73, 0x3a, 0xd0, 0x7e, 0xfb, 0x1d, -0xe8, 0x2f, 0xcb, 0x11, 0x3f, 0x2b, 0x2d, 0xfe, -0x79, 0x2b, 0xd3, 0x6a, 0x61, 0xa5, 0x38, 0xcd, -0x7f, 0x98, 0xbe, 0xc6, 0xce, 0x5d, 0x64, 0xe6, -0xd4, 0xdf, 0xaf, 0xd1, 0xe6, 0x89, 0x00, 0xe2, -0x27, 0xd3, 0xef, 0xd9, 0xa2, 0x7c, 0xfe, 0x99, -0x81, 0xee, 0x3e, 0x0c, 0x35, 0x7d, 0xf6, 0x3a, -0xd2, 0x4d, 0x6b, 0xdb, 0xc5, 0x3f, 0xe1, 0xcf, -0x9b, 0x36, 0x83, 0x97, 0xe0, 0xfb, 0x25, 0xb5, -0x3d, 0x3d, 0x8f, 0x90, 0x72, 0xf1, 0x9b, 0x72, -0xed, 0xf1, 0xff, 0xb4, 0x31, 0xaf, 0xfe, 0x3e, -0xc2, 0xd2, 0x90, 0xb1, 0x68, 0x5a, 0xab, 0x1f, -0x05, 0xe4, 0x1e, 0xe6, 0x9f, 0x7a, 0x1f, 0xc3, -0xcf, 0x0f, 0x28, 0xab, 0xfb, 0x3a, 0x9a, 0xe0, -0x6d, 0xa1, 0x89, 0xe9, 0xb1, 0x1c, 0xff, 0x9c, -0x64, 0xdb, 0x75, 0xd8, 0xf5, 0x1c, 0xf2, 0xcf, -0x0f, 0x40, 0x23, 0x24, 0x7b, 0xcc, 0x1a, 0xa6, -0xf4, 0x09, 0x9c, 0x92, 0xef, 0x4a, 0x6f, 0x9b, -0xbe, 0x9d, 0xf1, 0x4f, 0xbc, 0xc1, 0x74, 0xa9, -0xc5, 0x3f, 0x61, 0x15, 0xdb, 0xef, 0x13, 0xe2, -0xfe, 0x52, 0x0d, 0x5f, 0x64, 0x3f, 0x6a, 0xf4, -0x1c, 0x7e, 0x2a, 0xbd, 0xb0, 0x10, 0x21, 0x35, -0xa1, 0x15, 0xb1, 0xb3, 0x22, 0x6a, 0x7b, 0xc3, -0x9e, 0x76, 0x41, 0x84, 0x5e, 0x8f, 0xfc, 0x9a, -0xdf, 0x93, 0xd8, 0x46, 0xf7, 0x31, 0xff, 0x0c, -0x5a, 0xef, 0x01, 0xf1, 0x93, 0x9c, 0xa8, 0x5e, -0xda, 0x13, 0x38, 0xc0, 0xbf, 0x24, 0x5c, 0x5b, -0x17, 0x8e, 0xb6, 0x0d, 0xf2, 0xd9, 0x02, 0x43, -0xbf, 0x7f, 0x1b, 0xb9, 0x70, 0x50, 0x83, 0x9c, -0x40, 0x7c, 0xb6, 0x21, 0x2c, 0xac, 0xde, 0xdb, -0x3a, 0xf9, 0x64, 0x5e, 0xfd, 0x88, 0x86, 0xd3, -0xc8, 0x3f, 0xb3, 0xa8, 0xc4, 0x43, 0x59, 0x57, -0x9e, 0x7e, 0x07, 0xe4, 0x9f, 0xdd, 0x75, 0xbb, -0x1c, 0x43, 0xca, 0x05, 0xd8, 0x42, 0x77, 0x6b, -0xf9, 0x4f, 0x21, 0x8f, 0x7f, 0xea, 0x35, 0xb7, -0x31, 0x76, 0xb6, 0xe9, 0xe6, 0xfc, 0x27, 0x4e, -0x3d, 0xa5, 0xd5, 0xc0, 0xb6, 0xfc, 0x72, 0xfe, -0x13, 0x5f, 0x69, 0x46, 0x0b, 0x35, 0xea, 0xa8, -0x56, 0x10, 0xca, 0xe6, 0xea, 0x47, 0x5a, 0xcc, -0x71, 0x4c, 0x93, 0xeb, 0xc2, 0x4f, 0x52, 0xcd, -0xea, 0xea, 0x9b, 0xeb, 0x47, 0xe1, 0x94, 0xc6, -0xf5, 0x67, 0x94, 0x65, 0x5a, 0xcd, 0xdb, 0xd0, -0xda, 0xaa, 0x2d, 0x60, 0xe6, 0x93, 0xc7, 0x18, -0x39, 0xd2, 0x9e, 0x67, 0xf8, 0xd9, 0xa8, 0xe0, -0x34, 0xe6, 0xe9, 0x56, 0xa5, 0x8c, 0x9e, 0x3b, -0xbc, 0x0a, 0x26, 0xff, 0xac, 0x60, 0xfc, 0xd3, -0x8f, 0xb2, 0xfd, 0x1d, 0x78, 0x89, 0xd5, 0xbc, -0x9f, 0x20, 0xd7, 0x65, 0x7d, 0x5c, 0xd4, 0x5b, -0x4c, 0x11, 0x36, 0x07, 0xbe, 0xd2, 0xd8, 0x7a, -0x12, 0xa6, 0xfb, 0x97, 0x4e, 0xe5, 0xeb, 0xf7, -0xf2, 0x3d, 0xec, 0x95, 0x26, 0x5d, 0x1f, 0xf1, -0xd7, 0x5b, 0xa6, 0x19, 0x7e, 0x7e, 0xc4, 0x8f, -0x3f, 0xa9, 0xcf, 0x13, 0xf9, 0xa7, 0xf8, 0x75, -0xca, 0xe2, 0x43, 0x6b, 0x16, 0x1f, 0xa0, 0xd7, -0xdf, 0xa9, 0x81, 0x9f, 0xac, 0x7e, 0x04, 0x95, -0xb4, 0x97, 0x69, 0xa0, 0xfd, 0x28, 0x86, 0x7e, -0x17, 0xf1, 0xb3, 0x5a, 0x1f, 0xa7, 0xf3, 0xcf, -0xca, 0x34, 0xab, 0x65, 0xc1, 0x01, 0xbd, 0xfe, -0x3e, 0xb7, 0x7e, 0x24, 0x0f, 0x6b, 0xb6, 0xce, -0xe8, 0xb6, 0xb6, 0xf0, 0x13, 0x58, 0xfd, 0x68, -0x5f, 0xca, 0x91, 0x46, 0x53, 0x7d, 0x92, 0x0e, -0xcd, 0xa9, 0xbf, 0x1b, 0x9c, 0x68, 0x9e, 0x56, -0x7f, 0x17, 0x1a, 0x6f, 0xae, 0x1f, 0xe5, 0x61, -0xd6, 0x32, 0x65, 0x4e, 0xfd, 0x1d, 0x39, 0x26, -0xa9, 0x6b, 0xd9, 0xce, 0xf4, 0xed, 0xde, 0x5f, -0x59, 0x7f, 0x37, 0xb5, 0xef, 0xcd, 0xf5, 0x77, -0xd8, 0x2b, 0x68, 0xa9, 0xc6, 0x11, 0x7a, 0x48, -0x07, 0xa8, 0x5c, 0xfd, 0x48, 0x3f, 0x0b, 0x70, -0x3b, 0x6d, 0x65, 0x0d, 0xb7, 0x96, 0xff, 0xe4, -0x25, 0xa3, 0x4f, 0x83, 0x4d, 0xb5, 0x38, 0xc5, -0x5f, 0x8e, 0xde, 0xd0, 0x27, 0x75, 0x71, 0x9e, -0xbe, 0x86, 0x21, 0x1b, 0xcb, 0x8d, 0x86, 0x55, -0x84, 0xcd, 0xcb, 0xf2, 0xeb, 0x28, 0xac, 0x8b, -0x73, 0xdc, 0x54, 0xcb, 0x7f, 0x42, 0x1d, 0x2b, -0xbb, 0x9f, 0x43, 0xb2, 0x5e, 0xc3, 0x0e, 0xd0, -0xbc, 0x63, 0xe2, 0xa7, 0xc6, 0x3f, 0xeb, 0x18, -0x6c, 0x1e, 0x05, 0x06, 0x96, 0x5a, 0xfe, 0xd3, -0xaa, 0x1f, 0x49, 0x6c, 0x0d, 0xde, 0x94, 0xef, -0x7d, 0xd8, 0x22, 0x6b, 0xc5, 0xb0, 0xbc, 0xfa, -0x91, 0x78, 0xc5, 0x16, 0x8e, 0x3f, 0x95, 0x2a, -0x9d, 0x90, 0x8e, 0xe8, 0xcf, 0xb3, 0xea, 0x47, -0x31, 0xcd, 0x66, 0xf7, 0x9e, 0xd2, 0x6c, 0x46, -0x7f, 0x45, 0xfd, 0x88, 0x1d, 0x71, 0xd0, 0xce, -0x3a, 0x84, 0xf2, 0xf5, 0xbb, 0x28, 0xf8, 0xc5, -0x17, 0x99, 0x0f, 0xa6, 0x23, 0xa3, 0xf0, 0x22, -0xa9, 0x62, 0xfa, 0x3d, 0xbf, 0x7e, 0x64, 0x9e, -0x63, 0x61, 0xb9, 0x6d, 0xb6, 0xa1, 0xf2, 0xea, -0x47, 0x92, 0x11, 0x66, 0x51, 0x33, 0xc3, 0x02, -0x8a, 0x8d, 0x49, 0x83, 0x7f, 0xb2, 0xfa, 0x91, -0x51, 0x7f, 0x7f, 0x07, 0x1b, 0x77, 0xa6, 0xb1, -0x71, 0x5e, 0x7f, 0x1c, 0x88, 0x45, 0x3a, 0xff, -0xd4, 0xf6, 0xdf, 0x25, 0x68, 0x44, 0x67, 0x2c, -0x1d, 0xf6, 0xe8, 0xf3, 0x8c, 0x0b, 0x9f, 0xc0, -0xe1, 0xae, 0xdf, 0xc8, 0xce, 0x1b, 0xc2, 0x30, -0x74, 0x2a, 0x15, 0xea, 0x77, 0x0e, 0xe5, 0xce, -0x2f, 0xc1, 0xf6, 0x24, 0xca, 0xf6, 0xf7, 0x99, -0x0f, 0x2a, 0xdd, 0x78, 0x4f, 0xd4, 0x40, 0xe7, -0x8d, 0xb3, 0x46, 0x12, 0xec, 0x54, 0xf4, 0xb9, -0x44, 0x5e, 0x6f, 0xdb, 0x01, 0xeb, 0x7a, 0xec, -0x1d, 0x05, 0x23, 0x73, 0xe3, 0x3b, 0x5b, 0xc3, -0x49, 0xe8, 0x56, 0xfa, 0x29, 0xea, 0xe2, 0x33, -0x79, 0xf5, 0x23, 0xd4, 0x8d, 0x59, 0x6d, 0xdf, -0x9e, 0x48, 0x85, 0x28, 0x62, 0xf9, 0x05, 0xc3, -0xd6, 0x19, 0xbd, 0x7e, 0x34, 0xcc, 0xfa, 0xa2, -0xd7, 0xa4, 0x30, 0xb5, 0xe5, 0xf8, 0x67, 0x97, -0x74, 0xdd, 0x66, 0xc8, 0xf6, 0xb3, 0x70, 0x0a, -0x75, 0x15, 0x2b, 0x2a, 0x9b, 0xf5, 0xa3, 0x24, -0xf2, 0xcf, 0x82, 0x00, 0x93, 0xed, 0x53, 0x88, -0xd7, 0xbb, 0xf1, 0x9e, 0x24, 0xaf, 0x7e, 0xc4, -0xf8, 0x27, 0xa3, 0xa4, 0x53, 0xac, 0x16, 0x42, -0xf3, 0xeb, 0xef, 0x18, 0xb4, 0xf7, 0x29, 0x48, -0xe7, 0x42, 0x89, 0xb1, 0xd1, 0x5e, 0x31, 0xfd, -0x4c, 0x9e, 0x7e, 0xa7, 0xde, 0x0d, 0xea, 0xe1, -0x68, 0x78, 0x64, 0xd5, 0x41, 0xfe, 0x43, 0x7a, -0x22, 0x1e, 0xea, 0x2b, 0xfe, 0xf1, 0xf7, 0xac, -0xfa, 0xd1, 0xb7, 0xa7, 0x46, 0x70, 0xbf, 0x9f, -0x61, 0xb5, 0x79, 0xf1, 0x92, 0x7f, 0x39, 0x2d, -0xbe, 0x98, 0x57, 0x7f, 0xbf, 0x4c, 0x5e, 0x4d, -0x35, 0x83, 0xf3, 0xbd, 0xee, 0x26, 0xe9, 0x94, -0x96, 0x0f, 0xe1, 0xa7, 0x13, 0xfa, 0xfa, 0x54, -0xe9, 0x43, 0xb9, 0x57, 0xc6, 0xb9, 0x24, 0xc9, -0x62, 0x96, 0xff, 0xd4, 0xf0, 0x33, 0x61, 0xe2, -0x67, 0x56, 0xed, 0x96, 0x03, 0x6a, 0x21, 0x90, -0x2d, 0xa6, 0x7e, 0xbf, 0xc8, 0xe9, 0xf6, 0x54, -0xcb, 0x58, 0x19, 0xa7, 0x6e, 0xda, 0x9f, 0xbe, -0x3f, 0xcd, 0xf5, 0x6a, 0xc0, 0xe6, 0x9b, 0x36, -0x6c, 0x4d, 0x3d, 0x54, 0x39, 0x91, 0x0a, 0x67, -0x8b, 0xf6, 0x74, 0xbf, 0x40, 0x4e, 0xe8, 0xf9, -0x64, 0xd5, 0xc8, 0xa3, 0x7c, 0x04, 0x2f, 0x88, -0xb3, 0xec, 0x38, 0xd0, 0x5b, 0xfc, 0x13, 0x8a, -0x51, 0x3f, 0x9a, 0x36, 0x73, 0xd4, 0x52, 0x3f, -0x41, 0xd9, 0x3e, 0xee, 0xa4, 0xa5, 0x4e, 0xd6, -0x60, 0xe3, 0xce, 0x9a, 0xfc, 0x53, 0x58, 0x3e, -0x8a, 0xa6, 0x7a, 0x43, 0xfc, 0x6b, 0x14, 0xce, -0xbd, 0xb0, 0x9b, 0x39, 0xce, 0x55, 0xdd, 0x2c, -0xec, 0xfc, 0x27, 0x61, 0xf9, 0x25, 0xa4, 0x18, -0xc5, 0xac, 0xd0, 0xa9, 0xd5, 0x8f, 0xa8, 0xde, -0x97, 0xe1, 0x2a, 0x84, 0x1d, 0xb4, 0x72, 0x42, -0x7c, 0xd3, 0x5e, 0x01, 0xdf, 0xd5, 0x31, 0xeb, -0x63, 0xa3, 0xef, 0x7e, 0x91, 0x90, 0xbf, 0x23, -0x41, 0x75, 0x55, 0xb0, 0x54, 0x84, 0xb7, 0xa5, -0xe0, 0x11, 0xe4, 0x9f, 0xa6, 0x7e, 0x8f, 0xcc, -0x1f, 0x52, 0x66, 0xa5, 0x97, 0xd5, 0xc5, 0x1d, -0xfc, 0x99, 0xf8, 0x3f, 0x69, 0xf3, 0x2c, 0x1d, -0x37, 0x63, 0xf8, 0x6f, 0x4d, 0xb2, 0xf3, 0x1a, -0x6a, 0x45, 0xaa, 0xd4, 0x8f, 0x8d, 0x46, 0xbd, -0x7e, 0xa4, 0xf7, 0x8d, 0x3e, 0xfd, 0x7c, 0x62, -0x33, 0x59, 0xac, 0x16, 0xc5, 0x88, 0x9d, 0x6e, -0x36, 0xf8, 0xa7, 0xc9, 0xf9, 0xe0, 0x9b, 0x0a, -0x3b, 0xbf, 0x74, 0x7f, 0xc3, 0x6d, 0x15, 0xb0, -0x99, 0x2e, 0xd2, 0xf8, 0xa7, 0x64, 0xfa, 0xe7, -0xeb, 0xd0, 0x4d, 0x02, 0xd3, 0x62, 0x70, 0x77, -0xb1, 0xc8, 0xc3, 0x06, 0x1d, 0x3f, 0xf5, 0xbe, -0x49, 0xdb, 0x10, 0x1c, 0xa7, 0x77, 0x64, 0xec, -0xd9, 0xaa, 0x7b, 0x0a, 0xee, 0x67, 0x7b, 0x25, -0xcd, 0x5f, 0xb4, 0xf8, 0xa7, 0x2a, 0xcf, 0x48, -0x61, 0x27, 0x6e, 0x65, 0x35, 0x6e, 0xe9, 0x77, -0xd9, 0xf0, 0xa5, 0xf7, 0xe9, 0x31, 0xa2, 0x71, -0xa9, 0x85, 0xc8, 0x3f, 0xeb, 0x34, 0xfc, 0x34, -0xdf, 0x91, 0xf0, 0xfb, 0xf6, 0x2d, 0xf3, 0xd8, -0xb1, 0x1e, 0xfb, 0x42, 0x33, 0xc7, 0x99, 0x35, -0xd6, 0xee, 0x15, 0x16, 0xe0, 0x8f, 0x02, 0x5a, -0x8d, 0x48, 0xb1, 0xf2, 0x9f, 0x60, 0xdc, 0x53, -0x48, 0x68, 0xb4, 0xd3, 0x4d, 0xb4, 0xc6, 0x1c, -0xfc, 0x14, 0xd7, 0x45, 0x46, 0xd7, 0x84, 0x3d, -0x7d, 0x9b, 0xea, 0xad, 0xfc, 0xe0, 0xc7, 0xc4, -0xc8, 0x7f, 0x16, 0xbd, 0x81, 0xb0, 0xd9, 0x3c, -0x82, 0x61, 0xe8, 0xb2, 0x49, 0x44, 0xdf, 0x9b, -0xa7, 0xfb, 0xa7, 0xc8, 0x7d, 0xac, 0x1e, 0x83, -0x65, 0x6d, 0xce, 0x3e, 0xfe, 0x1b, 0x5a, 0x9e, -0x81, 0x60, 0x1f, 0x31, 0xf3, 0x9f, 0x3f, 0x23, -0x54, 0x0c, 0x08, 0xe2, 0x30, 0x72, 0xef, 0x9b, -0xeb, 0x47, 0xb6, 0x11, 0x95, 0x4d, 0xa1, 0xe7, -0xa1, 0x84, 0x0d, 0x76, 0xe9, 0x73, 0x79, 0xcb, -0xe2, 0x9f, 0x7f, 0x0d, 0x3f, 0xa0, 0x75, 0x4a, -0xcf, 0x69, 0x7b, 0x35, 0xfc, 0x40, 0x5b, 0x03, -0x32, 0x05, 0xbd, 0x2f, 0xfd, 0x17, 0x13, 0xe4, -0x18, 0x17, 0x6e, 0xf3, 0x3f, 0xc7, 0x2f, 0x20, -0x7f, 0x00, 0xe1, 0x96, 0xef, 0xe4, 0xe7, 0x3f, -0x93, 0xca, 0x9b, 0xd0, 0x14, 0x77, 0x79, 0xf9, -0xa3, 0xf4, 0x4d, 0xed, 0x20, 0x53, 0xd5, 0x69, -0x83, 0x83, 0x21, 0x7e, 0x26, 0xd8, 0xf9, 0x4f, -0x27, 0x85, 0x4a, 0xa2, 0xaf, 0xaf, 0x6a, 0xd8, -0xec, 0xc3, 0xd0, 0xb5, 0x95, 0xf3, 0x75, 0x21, -0xed, 0xac, 0x41, 0x61, 0xd6, 0xa8, 0xe5, 0x3f, -0xab, 0x75, 0xbb, 0xf8, 0x6d, 0x0f, 0x70, 0xa5, -0xcc, 0x3f, 0x1b, 0xdc, 0xdb, 0x59, 0x7e, 0x5e, -0xcf, 0x7f, 0xea, 0x57, 0x25, 0x57, 0xee, 0xdb, -0x9c, 0xae, 0xa4, 0xfe, 0xf5, 0xe4, 0x29, 0xf8, -0xbe, 0x76, 0xde, 0x2d, 0xa2, 0x2a, 0xc6, 0xb8, -0x9e, 0x30, 0x79, 0x8d, 0x2e, 0xc9, 0x3a, 0x67, -0x7a, 0xbf, 0x43, 0xfe, 0x37, 0x02, 0xe9, 0x6b, -0x9d, 0x55, 0xc3, 0xb2, 0xf1, 0x1e, 0xe6, 0x23, -0xff, 0x0c, 0x17, 0x53, 0xd7, 0xee, 0xd6, 0x0d, -0xec, 0x5c, 0xa5, 0xa6, 0x81, 0x92, 0xc6, 0x3e, -0xb2, 0x7d, 0x1c, 0x79, 0x1b, 0x69, 0x27, 0xda, -0x33, 0x0c, 0xda, 0x7e, 0x1f, 0xaa, 0x1a, 0xdf, -0xad, 0xf7, 0xfd, 0xa0, 0x64, 0x73, 0x7a, 0x33, -0xad, 0xed, 0x11, 0xa3, 0x89, 0x72, 0x46, 0x7c, -0xd5, 0x95, 0x4f, 0x90, 0xf3, 0x92, 0xe9, 0x9f, -0x49, 0xcd, 0x65, 0xa3, 0x31, 0xf2, 0xb0, 0xfc, -0x7d, 0xe6, 0xbb, 0x1b, 0xc9, 0x94, 0x95, 0xff, -0x9c, 0x92, 0x7a, 0x21, 0x90, 0x11, 0x81, 0x7c, -0x01, 0xb1, 0xc0, 0x89, 0x6b, 0x88, 0x98, 0xfe, -0x39, 0x50, 0x36, 0x85, 0xf0, 0x57, 0xa7, 0xfa, -0x97, 0x3a, 0x1e, 0x23, 0x1f, 0xa0, 0xde, 0x74, -0x65, 0xbe, 0xf8, 0x9e, 0xe9, 0x67, 0x68, 0xfc, -0x0f, 0x12, 0xe1, 0x27, 0xd1, 0x65, 0x11, 0x64, -0x49, 0x58, 0xbd, 0x03, 0x85, 0xbc, 0xd1, 0xc7, -0xc5, 0xae, 0x8b, 0xef, 0x72, 0x21, 0xfc, 0x51, -0x77, 0x00, 0x4e, 0x69, 0x7b, 0x4c, 0xce, 0x1a, -0xcf, 0x53, 0x85, 0xaf, 0xe2, 0xf3, 0x76, 0xa3, -0x19, 0xed, 0x4e, 0x5c, 0x9f, 0x46, 0x9c, 0xa6, -0x0d, 0xbb, 0x50, 0xa8, 0x86, 0xbf, 0x62, 0x14, -0x2a, 0x45, 0x02, 0xb4, 0x57, 0x3b, 0x44, 0xe9, -0x36, 0x7d, 0x57, 0x84, 0xea, 0x23, 0xdd, 0x10, -0xa7, 0x9a, 0x2e, 0x7e, 0x56, 0xb3, 0xf5, 0x33, -0xa6, 0x7f, 0x2a, 0xe2, 0x57, 0x07, 0xde, 0x85, -0xd0, 0x11, 0x47, 0x0a, 0xf5, 0xad, 0x5e, 0x9f, -0xe6, 0x4d, 0xde, 0xba, 0x7b, 0xfe, 0x14, 0xcc, -0x4a, 0xcd, 0x5d, 0xae, 0x23, 0xfc, 0x65, 0xa3, -0xae, 0xfd, 0x68, 0xb6, 0xd2, 0xd4, 0xda, 0x17, -0x30, 0x7c, 0x0d, 0x9e, 0xab, 0x53, 0xf9, 0x10, -0x1c, 0xe3, 0xea, 0xb3, 0x81, 0x99, 0xbc, 0xfa, -0xd1, 0x05, 0x89, 0x95, 0xdd, 0x31, 0xbe, 0xa7, -0x71, 0xd3, 0x1c, 0x40, 0x81, 0xac, 0x64, 0x21, -0xc7, 0x3f, 0xd9, 0x51, 0x44, 0x3b, 0x52, 0x09, -0xa9, 0xdb, 0xd6, 0x7e, 0x44, 0x0c, 0x16, 0xcc, -0x39, 0xff, 0x49, 0x6b, 0x46, 0x06, 0x20, 0x42, -0x9d, 0x5b, 0x68, 0x31, 0x12, 0xbf, 0x1c, 0xff, -0x44, 0x7b, 0x5e, 0x3a, 0xd6, 0x78, 0x66, 0x7b, -0xc6, 0xe1, 0x23, 0x47, 0x68, 0x03, 0x3b, 0xd0, -0x69, 0xd6, 0x8f, 0xa6, 0x35, 0xfd, 0x7e, 0x50, -0x5d, 0x7d, 0xbd, 0xfb, 0x17, 0xd2, 0x0d, 0xb8, -0x4b, 0x3b, 0xff, 0x69, 0xd5, 0x8f, 0xd0, 0xc4, -0xde, 0x90, 0xea, 0xdc, 0xef, 0xa8, 0x84, 0xb7, -0xe5, 0xd0, 0xb0, 0x2b, 0x77, 0x7e, 0xe9, 0x8c, -0x2d, 0x20, 0x1e, 0x52, 0x14, 0x8c, 0x39, 0x76, -0x36, 0xcf, 0xd0, 0xf8, 0xca, 0x4c, 0xde, 0xf9, -0xf9, 0x55, 0x30, 0x08, 0x69, 0x75, 0x91, 0x44, -0x04, 0x78, 0xfa, 0xa1, 0x6d, 0x4c, 0xbf, 0x77, -0x18, 0xf6, 0x64, 0xfa, 0xfd, 0x95, 0x74, 0x55, -0xf6, 0xd6, 0xdb, 0x12, 0x07, 0x94, 0xcd, 0xbb, -0x17, 0x4d, 0x3a, 0x66, 0x0a, 0xa2, 0x46, 0x5f, -0x14, 0xf5, 0xd1, 0xc5, 0xb4, 0x9c, 0xbd, 0xf7, -0x36, 0x87, 0x1d, 0xde, 0xa2, 0x4d, 0x59, 0xd7, -0x8b, 0xfc, 0x1a, 0x4b, 0xbf, 0xef, 0x51, 0x5e, -0x2c, 0x59, 0x3e, 0x56, 0xfc, 0x2c, 0x7f, 0xa6, -0xed, 0x2a, 0x87, 0x5c, 0x78, 0x6f, 0xbe, 0x7e, -0x17, 0xae, 0x32, 0x5c, 0xca, 0x38, 0x64, 0x78, -0x1d, 0x06, 0xd5, 0xd5, 0x0d, 0xad, 0x24, 0xa7, -0xdf, 0x3d, 0x2c, 0xff, 0x29, 0x4a, 0x05, 0x3b, -0xdd, 0x9b, 0xf5, 0x64, 0xbc, 0xdb, 0xd2, 0x32, -0xdf, 0x41, 0xda, 0xf9, 0xb5, 0x20, 0x74, 0x92, -0x10, 0x74, 0xd3, 0x75, 0xd9, 0xdb, 0x3b, 0xad, -0x1c, 0x12, 0x8b, 0xef, 0x83, 0x10, 0x58, 0xeb, -0x3f, 0x44, 0x06, 0x8c, 0x62, 0x03, 0xb9, 0xcd, -0xe4, 0x9f, 0x25, 0x03, 0xf0, 0x09, 0x34, 0x67, -0x9c, 0x53, 0x8e, 0x7b, 0xe8, 0x49, 0xbd, 0x90, -0xd4, 0x98, 0x57, 0x3f, 0xd2, 0x61, 0xb3, 0x3b, -0x2b, 0xeb, 0x42, 0x9e, 0x9f, 0x53, 0x7f, 0x87, -0x70, 0xfb, 0xaa, 0x3e, 0x9e, 0xe5, 0x3f, 0x1f, -0x67, 0x40, 0x7a, 0xd3, 0xf9, 0x4f, 0xe5, 0x0f, -0xfb, 0xe4, 0x6a, 0xa1, 0x4b, 0x68, 0x57, 0xc4, -0x9b, 0xea, 0xef, 0x50, 0x17, 0x13, 0x0f, 0x90, -0x00, 0xc1, 0xa0, 0x15, 0xbd, 0xf9, 0xfc, 0x12, -0x45, 0xa8, 0x7a, 0x06, 0x6d, 0xdd, 0x85, 0xbc, -0xce, 0x9f, 0x57, 0x7f, 0x2f, 0xd2, 0x53, 0x08, -0xce, 0x4d, 0x8e, 0xca, 0xc8, 0xe8, 0x83, 0x3e, -0x6e, 0xae, 0x7e, 0x87, 0xff, 0xc6, 0x2d, 0x57, -0x5c, 0x3f, 0xe5, 0xdf, 0x80, 0x1b, 0x52, 0xb3, -0xb2, 0x78, 0xae, 0x7e, 0x3f, 0x05, 0xac, 0xfe, -0xde, 0x5b, 0x0d, 0x4f, 0x79, 0xeb, 0x95, 0xd5, -0xe3, 0xfc, 0x49, 0x4b, 0xbf, 0xc7, 0x35, 0xd8, -0xec, 0x49, 0x46, 0xfc, 0x64, 0xab, 0x5c, 0x73, -0x13, 0x7e, 0xb2, 0x3c, 0x99, 0xd2, 0xee, 0x4e, -0x08, 0xbb, 0xb6, 0xc8, 0x1a, 0x17, 0xce, 0xaf, -0x1f, 0x6d, 0x81, 0x62, 0xc5, 0x9f, 0xd1, 0xce, -0x59, 0xd5, 0x28, 0xb7, 0xcf, 0xd1, 0xef, 0xc2, -0xb1, 0x3f, 0xaa, 0x88, 0x6c, 0x4b, 0x15, 0x2e, -0x94, 0x8e, 0xc5, 0x06, 0x5b, 0x56, 0xe7, 0xe1, -0x27, 0xd7, 0x4f, 0x0e, 0x31, 0xd8, 0x7c, 0xbe, -0xea, 0x7d, 0xf8, 0x15, 0xf5, 0xa3, 0x19, 0x25, -0x24, 0x39, 0xe9, 0x17, 0x71, 0xa1, 0xca, 0xa0, -0xe0, 0xcc, 0x3f, 0xff, 0x29, 0x0a, 0x2f, 0xb7, -0x2c, 0xda, 0x62, 0x9f, 0x70, 0xfb, 0xe1, 0x00, -0x54, 0xa5, 0x0a, 0xe6, 0xea, 0xf7, 0xbd, 0xb2, -0x9f, 0x8a, 0x83, 0x8c, 0x7f, 0x52, 0xf9, 0xf4, -0x96, 0x5c, 0xfd, 0x28, 0xcd, 0x95, 0xc3, 0xc1, -0xe4, 0x62, 0x6a, 0x8f, 0x93, 0xf2, 0xfb, 0xf6, -0x8b, 0x95, 0xe7, 0xde, 0xca, 0xd5, 0xdf, 0x07, -0xc4, 0x0a, 0xf8, 0x31, 0xbd, 0x3b, 0xbb, 0x6a, -0x6d, 0xd5, 0x3b, 0xf0, 0xdf, 0xe9, 0xc6, 0xac, -0xad, 0x93, 0xcf, 0xab, 0x1f, 0x31, 0xda, 0xa9, -0x3a, 0xfe, 0x86, 0x9f, 0x92, 0x67, 0xc0, 0xc3, -0xce, 0x87, 0xe4, 0xeb, 0xf7, 0xe7, 0xd2, 0x0d, -0xfd, 0x5f, 0xf8, 0x09, 0xff, 0x58, 0xdb, 0x6b, -0xcf, 0x86, 0x26, 0x9d, 0x0d, 0x2b, 0xbd, 0x26, -0xd6, 0x71, 0xdf, 0x19, 0x19, 0x1c, 0xaf, 0x4c, -0x8b, 0x35, 0xa4, 0x4e, 0x7e, 0x32, 0x2d, 0xf7, -0xfb, 0x1b, 0xed, 0x35, 0x96, 0x7e, 0xdf, 0x09, -0x7f, 0x21, 0x2e, 0x3a, 0xe3, 0x28, 0x21, 0xe5, -0x9b, 0x76, 0x70, 0x9f, 0x57, 0x1d, 0x8f, 0x13, -0x6a, 0xe6, 0x3f, 0x99, 0x7f, 0x72, 0xb2, 0x5a, -0xb8, 0x88, 0x38, 0x0b, 0x12, 0xb0, 0x10, 0xd0, -0x3f, 0x53, 0xa6, 0x7e, 0x2f, 0xd1, 0xce, 0xcd, -0x8c, 0xef, 0x18, 0xa8, 0x59, 0x0e, 0xc7, 0xd3, -0x07, 0x94, 0x3f, 0xcc, 0xf0, 0x2f, 0xe4, 0xce, -0x7f, 0xc2, 0x95, 0xf5, 0x61, 0xb5, 0xb8, 0x1f, -0xf1, 0x73, 0x46, 0x69, 0x54, 0xc4, 0x0c, 0xd7, -0x6e, 0x9e, 0xa1, 0x93, 0xae, 0x73, 0x37, 0xa0, -0x5e, 0x79, 0x20, 0x66, 0x6b, 0x92, 0x4f, 0xc2, -0xe7, 0xe3, 0xce, 0xe9, 0x56, 0x35, 0xaf, 0x7e, -0xb4, 0x57, 0x4d, 0x77, 0x6e, 0xef, 0xbf, 0x2d, -0x00, 0x54, 0x59, 0x16, 0x2f, 0x9a, 0x7b, 0xfe, -0xf3, 0x10, 0xf5, 0xc5, 0xa3, 0xec, 0x7b, 0x84, -0x17, 0x94, 0xba, 0xa8, 0x88, 0xf8, 0x59, 0x62, -0xf8, 0xa7, 0xc7, 0x09, 0x43, 0x1e, 0xdf, 0x4a, -0x7b, 0x95, 0xfd, 0x29, 0x92, 0x40, 0xc7, 0xb9, -0x35, 0x4f, 0xbf, 0xdb, 0x36, 0x28, 0x87, 0x94, -0xd0, 0x5a, 0xe7, 0xe9, 0x82, 0x97, 0x92, 0xe7, -0xe5, 0xf0, 0x1a, 0xe7, 0x01, 0x5e, 0x9d, 0x67, -0xe8, 0xf7, 0x07, 0xa7, 0x94, 0x99, 0x78, 0x73, -0xa4, 0xf8, 0xfd, 0xd2, 0x3f, 0x53, 0xae, 0x96, -0xdf, 0x69, 0x77, 0x7d, 0x9c, 0x77, 0x7e, 0x7e, -0x1a, 0x35, 0x60, 0x3d, 0xb8, 0x54, 0xbe, 0x03, -0xc6, 0x58, 0x00, 0x1d, 0xe7, 0x83, 0x29, 0xe3, -0xfc, 0x92, 0xf7, 0x3c, 0xf4, 0x50, 0x9f, 0xec, -0xe8, 0x21, 0x3e, 0x6c, 0xd4, 0xc8, 0xf6, 0x3e, -0x12, 0x34, 0x6b, 0xde, 0x90, 0x86, 0x5d, 0x44, -0x86, 0x95, 0xe0, 0xd3, 0x41, 0xbf, 0x30, 0x48, -0x42, 0xc6, 0x5e, 0x51, 0x85, 0x01, 0x3f, 0xca, -0x76, 0x74, 0x67, 0x0c, 0x5e, 0xe8, 0xe0, 0x82, -0x3d, 0xe3, 0x36, 0xc7, 0x71, 0x65, 0xe7, 0xd8, -0xe7, 0x43, 0xf1, 0xd5, 0x19, 0xc7, 0x42, 0x72, -0x8c, 0x2e, 0x8b, 0xa3, 0x9f, 0x81, 0x11, 0x57, -0xb2, 0x5c, 0x1f, 0x7c, 0x0c, 0xcd, 0xeb, 0x11, -0x36, 0x3f, 0x56, 0xfe, 0x39, 0xd5, 0x18, 0x77, -0x29, 0x8e, 0x1c, 0xff, 0xdc, 0x25, 0x5f, 0xf3, -0x84, 0x14, 0x67, 0x90, 0x17, 0x84, 0x37, 0x49, -0x50, 0x09, 0xa4, 0x79, 0x8f, 0x75, 0x7e, 0xa9, -0xa6, 0xaf, 0x37, 0xe1, 0x53, 0xc4, 0x21, 0x56, -0xd3, 0x40, 0x4d, 0x89, 0x81, 0xbe, 0x91, 0x82, -0x31, 0x97, 0x7b, 0x49, 0x86, 0xca, 0x54, 0xe4, -0x50, 0xe1, 0x3d, 0x03, 0xd8, 0x90, 0x48, 0x83, -0xd1, 0x17, 0x97, 0xbe, 0x0c, 0x94, 0xca, 0x69, -0x51, 0x24, 0x2f, 0x8a, 0x09, 0xf6, 0xfd, 0x91, -0xb7, 0x20, 0x9c, 0xd4, 0xfb, 0xa2, 0xe2, 0x0a, -0xf8, 0x88, 0x06, 0x69, 0x80, 0x73, 0x0c, 0xc0, -0x69, 0xc8, 0xa4, 0x9d, 0x4b, 0x1c, 0xb7, 0x99, -0xfa, 0xbd, 0x6c, 0x9b, 0x7a, 0x45, 0x0e, 0x27, -0xe7, 0x51, 0xae, 0x5d, 0xb9, 0x8a, 0xba, 0xc3, -0x75, 0xa8, 0x75, 0xdc, 0xd2, 0x6a, 0xfd, 0xce, -0x61, 0x08, 0x65, 0xd9, 0x67, 0x16, 0xec, 0xfb, -0x23, 0x15, 0x31, 0x6b, 0xd8, 0x38, 0x03, 0x12, -0x15, 0xb7, 0xc1, 0x93, 0xb0, 0x4b, 0x15, 0xf5, -0xfa, 0x3b, 0xe2, 0xa7, 0x42, 0x4c, 0xae, 0x28, -0xc3, 0x5f, 0x92, 0xcd, 0x7a, 0xd9, 0x08, 0x35, -0x10, 0xe3, 0xc2, 0xed, 0x56, 0xfe, 0xb3, 0x5d, -0xd8, 0x86, 0x3f, 0x92, 0xc7, 0xc5, 0x26, 0x56, -0x7f, 0x57, 0xe4, 0x33, 0x8e, 0x7e, 0x0b, 0x0b, -0x26, 0xcb, 0x46, 0xc9, 0x71, 0x94, 0xed, 0x81, -0x17, 0xf8, 0x9f, 0xa3, 0xf0, 0x1b, 0x4c, 0xb9, -0xb2, 0x39, 0xfe, 0xa9, 0xd7, 0x8f, 0x88, 0x8e, -0x9f, 0x62, 0x13, 0xec, 0x50, 0xbb, 0x2d, 0xfe, -0x89, 0x7c, 0xfe, 0x1c, 0xab, 0x33, 0xbb, 0xf9, -0x6a, 0x0d, 0x0b, 0x56, 0xa5, 0x4a, 0x89, 0x64, -0xbe, 0xbf, 0xf5, 0x9a, 0x19, 0x1d, 0x7d, 0x3e, -0x5d, 0xac, 0x23, 0x46, 0xca, 0x46, 0xae, 0xa4, -0xc1, 0xb6, 0x14, 0x7e, 0x28, 0x57, 0x29, 0x8e, -0x71, 0xb2, 0x14, 0xd8, 0xf7, 0x47, 0xe2, 0x38, -0x31, 0xb6, 0x2d, 0xf2, 0x2c, 0x0f, 0xdd, 0x24, -0x57, 0x46, 0x1d, 0x6b, 0x88, 0x87, 0xfe, 0x58, -0xae, 0x8d, 0x8a, 0xa7, 0xed, 0xe6, 0xf7, 0x47, -0x33, 0xf3, 0x59, 0xfe, 0x93, 0xd5, 0xa7, 0x1d, -0x5a, 0x7e, 0x10, 0xa3, 0x3f, 0xbf, 0xcc, 0x18, -0xd7, 0x33, 0x7f, 0xe2, 0xa1, 0x2b, 0x9e, 0x70, -0x9b, 0xeb, 0xe9, 0xd6, 0x89, 0x98, 0xde, 0xe0, -0xdf, 0x13, 0x4c, 0xfc, 0x7c, 0x83, 0xbe, 0x2e, -0x87, 0x23, 0xae, 0xd3, 0xdd, 0x13, 0x70, 0x9f, -0xd8, 0x8c, 0x98, 0xd5, 0xed, 0x23, 0xb9, 0xfa, -0xd1, 0x56, 0x46, 0x3b, 0x93, 0x91, 0x2c, 0xf3, -0xb3, 0xb2, 0xde, 0x24, 0x79, 0xd2, 0xd2, 0xef, -0x9b, 0xa0, 0xab, 0x2d, 0xa0, 0xf0, 0x12, 0x79, -0xd5, 0xd3, 0xc5, 0x69, 0xfc, 0xf3, 0x36, 0x63, -0xed, 0x7d, 0x42, 0x3f, 0xd1, 0xa9, 0x73, 0x44, -0x3f, 0x43, 0xd0, 0x9b, 0x22, 0x3f, 0x32, 0xf9, -0x27, 0xcb, 0x7f, 0xea, 0x47, 0x3b, 0xd9, 0x01, -0x05, 0x6c, 0xf4, 0xf1, 0x7e, 0xcb, 0x9e, 0x49, -0xe1, 0x0a, 0x67, 0xe5, 0x3c, 0xb0, 0xf1, 0x0c, -0x6f, 0xf2, 0x4f, 0x56, 0x3f, 0x3a, 0xa3, 0x0c, -0xb2, 0xb2, 0x11, 0x2e, 0x96, 0x60, 0xac, 0x02, -0x9e, 0x98, 0xdf, 0x26, 0xd9, 0xee, 0x86, 0xad, -0x5d, 0x3e, 0x2a, 0x0e, 0xb0, 0x1c, 0x35, 0xd4, -0x51, 0x47, 0x96, 0x8f, 0x98, 0xfc, 0x53, 0xb8, -0x8f, 0x3e, 0x9b, 0x42, 0xfe, 0x79, 0xb7, 0x4f, -0xcb, 0x7f, 0xaa, 0x2b, 0x65, 0x62, 0x8e, 0xa3, -0xd2, 0x5a, 0xd0, 0x7d, 0xa2, 0xa0, 0x9c, 0xd3, -0xc4, 0xb3, 0x4c, 0x14, 0xc5, 0xb0, 0x59, 0xcf, -0xef, 0xc0, 0xdf, 0xa3, 0x9b, 0x38, 0x3b, 0x1d, -0x86, 0x90, 0x6f, 0xe7, 0xcd, 0xa3, 0x46, 0x62, -0xd9, 0x80, 0x70, 0x8d, 0x43, 0x0a, 0x15, 0xe4, -0xa7, 0xc4, 0x3f, 0xd5, 0xce, 0x55, 0x5a, 0xb9, -0x6d, 0xc5, 0xf6, 0x42, 0xc4, 0x90, 0x99, 0x9f, -0xc0, 0x6c, 0x6a, 0x79, 0x56, 0x9c, 0xe4, 0xc7, -0x8d, 0x81, 0x2f, 0xdc, 0xba, 0x55, 0xdd, 0x2c, -0x6b, 0x47, 0x93, 0xce, 0x6a, 0xf9, 0xf9, 0xbe, -0x47, 0x42, 0xe7, 0x8d, 0xfd, 0x27, 0x41, 0x5f, -0x6a, 0xb3, 0x50, 0xab, 0xf6, 0x76, 0x90, 0x87, -0xe1, 0x60, 0x41, 0xad, 0x2a, 0xae, 0x77, 0x4f, -0x50, 0xd3, 0x3f, 0xb7, 0x6a, 0x12, 0x74, 0xa5, -0x9e, 0x83, 0x60, 0xdf, 0x1f, 0x85, 0x2c, 0x3d, -0x56, 0xf6, 0xde, 0x02, 0x43, 0x66, 0x6e, 0xd0, -0x92, 0x0a, 0xce, 0x3d, 0x7f, 0x67, 0xf2, 0xcf, -0x14, 0x37, 0x80, 0x3f, 0x6a, 0xd2, 0xeb, 0xef, -0x97, 0x70, 0xc2, 0x8b, 0xd3, 0xf3, 0xfe, 0xd1, -0x7c, 0x0f, 0x52, 0x4a, 0x3a, 0x95, 0x46, 0xfd, -0xde, 0xc1, 0x97, 0x3b, 0x4f, 0x91, 0x25, 0xaa, -0x98, 0x2d, 0x9d, 0x34, 0xe6, 0xb2, 0x0b, 0x43, -0x3a, 0xca, 0x61, 0xa6, 0xd1, 0x03, 0xc8, 0x3f, -0x7d, 0x47, 0x8a, 0xd2, 0x6b, 0x66, 0xda, 0xf4, -0xb5, 0xd3, 0x16, 0x39, 0xd8, 0x0b, 0xff, 0x45, -0x8d, 0xee, 0x2d, 0x08, 0x68, 0x67, 0x19, 0xb5, -0xf3, 0x9f, 0x86, 0x5d, 0x3c, 0x4e, 0x59, 0x3f, -0xbe, 0x82, 0xbc, 0x15, 0xb5, 0xe8, 0x78, 0xaf, -0xec, 0xce, 0xe5, 0x3f, 0xd7, 0x25, 0x7a, 0x95, -0x46, 0x35, 0x90, 0xe1, 0x03, 0x02, 0x3b, 0x40, -0x53, 0x9c, 0xe6, 0xcd, 0x9c, 0x40, 0xba, 0xec, -0x6c, 0xfa, 0x86, 0x1f, 0x69, 0xe7, 0x38, 0xaf, -0x7f, 0xd7, 0xf3, 0x54, 0x96, 0xcf, 0x26, 0x4d, -0xfc, 0xbc, 0x00, 0x33, 0x05, 0xf5, 0xba, 0x3d, -0xaf, 0x41, 0xbd, 0xea, 0xcc, 0xff, 0xfe, 0xe8, -0x02, 0x0c, 0x15, 0xb0, 0x63, 0x9f, 0xca, 0x05, -0x78, 0x85, 0x7e, 0x4f, 0x15, 0xe7, 0x7c, 0x7f, -0x04, 0x19, 0xa2, 0x7d, 0x76, 0x34, 0xe6, 0x65, -0x87, 0x67, 0xc5, 0xb9, 0xdf, 0x1f, 0x0d, 0xe9, -0x32, 0x7a, 0x8a, 0x1d, 0x5e, 0x67, 0x0b, 0x9d, -0x36, 0xf2, 0x36, 0x8c, 0x7f, 0xce, 0xe8, 0x69, -0xcf, 0x29, 0xf1, 0x1a, 0x09, 0xb1, 0x09, 0xe7, -0xd5, 0xdf, 0x3d, 0x9f, 0x1c, 0xd5, 0x8f, 0x7d, -0x7a, 0xb5, 0xda, 0xcb, 0xdc, 0xfc, 0xe7, 0x01, -0x39, 0x64, 0xd8, 0x1a, 0x79, 0x9d, 0x7f, 0x4e, -0xfd, 0x1d, 0xdd, 0x52, 0x4b, 0x7b, 0x4e, 0x09, -0x48, 0x28, 0x8f, 0x88, 0x99, 0x48, 0xde, 0xf9, -0x25, 0x29, 0xa3, 0x68, 0x67, 0x7b, 0xf1, 0xdd, -0x26, 0x31, 0x48, 0xe6, 0xbe, 0x3f, 0x8a, 0xb7, -0x54, 0xc0, 0x81, 0xcc, 0x2e, 0x26, 0x95, 0xdf, -0xa1, 0x07, 0x53, 0x95, 0x53, 0x85, 0xf9, 0xdf, -0x1f, 0x15, 0xab, 0x57, 0xd2, 0xc1, 0xec, 0x8e, -0x06, 0xfe, 0xa4, 0x72, 0x29, 0x15, 0xcc, 0x16, -0xe5, 0x7f, 0x7f, 0xc4, 0xce, 0xcf, 0x37, 0x33, -0xda, 0xa9, 0x25, 0x70, 0x8e, 0x14, 0xe7, 0x7f, -0x7f, 0x84, 0x31, 0x55, 0x1c, 0x34, 0xce, 0x64, -0xc8, 0xa1, 0xd1, 0x40, 0xfe, 0xf7, 0x47, 0xe5, -0x82, 0x7e, 0xec, 0xd3, 0x7d, 0x56, 0x7c, 0x25, -0xe6, 0x7f, 0x43, 0x9c, 0xf3, 0xfd, 0x11, 0x32, -0x6f, 0x2d, 0x85, 0xf0, 0x0e, 0x92, 0xe2, 0x05, -0x93, 0x22, 0xfb, 0xfe, 0x48, 0x5f, 0x9f, 0x96, -0x5f, 0x3a, 0x22, 0x9b, 0x39, 0xb2, 0x3a, 0x66, -0xeb, 0xfc, 0xef, 0x8f, 0xae, 0xd2, 0x90, 0x7e, -0x7e, 0xe9, 0x22, 0x2c, 0x63, 0xf5, 0xf7, 0x39, -0xdf, 0x1f, 0x55, 0x5a, 0xdf, 0x1f, 0xdd, 0x94, -0xff, 0x9c, 0x80, 0x6b, 0xca, 0xa0, 0xb2, 0x3a, -0xd5, 0x3a, 0xe1, 0xd1, 0xbf, 0xb3, 0x69, 0x9d, -0xc3, 0x3f, 0x61, 0xb7, 0xf2, 0x57, 0x5a, 0x8e, -0x53, 0x62, 0xe7, 0xe7, 0xf9, 0x74, 0x5e, 0xfe, -0x73, 0x2f, 0xa9, 0x51, 0x56, 0x22, 0xf6, 0x70, -0x87, 0x14, 0x8c, 0x55, 0xa9, 0x48, 0x3e, 0xff, -0xdc, 0x27, 0x6b, 0xc7, 0x3e, 0x47, 0x90, 0x54, -0xc9, 0x51, 0xe4, 0x9f, 0x89, 0xbc, 0xfa, 0xd1, -0x74, 0x8c, 0x51, 0xc4, 0xd6, 0x2c, 0x74, 0x42, -0xc8, 0xe3, 0xcc, 0xe5, 0x3f, 0xfb, 0xb4, 0xf3, -0xf3, 0xcb, 0x10, 0xcf, 0x18, 0x2e, 0x49, 0xe1, -0xb6, 0x1d, 0x29, 0xfe, 0x6f, 0x8c, 0xfc, 0x27, -0xab, 0xbf, 0xdf, 0xf0, 0xb3, 0x73, 0x56, 0xd8, -0x77, 0x43, 0xd4, 0x0e, 0x16, 0xe5, 0xbe, 0x3f, -0xca, 0xc2, 0x50, 0x7c, 0x10, 0xef, 0xe9, 0x63, -0x89, 0x50, 0xdf, 0xfc, 0xde, 0x39, 0xdf, 0x1f, -0xc1, 0x5e, 0xa7, 0x46, 0x3b, 0x47, 0xa4, 0xbd, -0x20, 0x47, 0x1c, 0x79, 0xdf, 0x1f, 0x21, 0xff, -0x3c, 0x14, 0x5f, 0x38, 0x37, 0x87, 0x9b, 0xf7, -0xfd, 0xd1, 0x15, 0x45, 0x3f, 0x2f, 0x25, 0x5c, -0x81, 0x41, 0xed, 0xfc, 0xa7, 0xf5, 0xfd, 0x51, -0x3f, 0x5c, 0x11, 0x1a, 0xf3, 0xf0, 0x93, 0x7d, -0x7f, 0xa4, 0x8f, 0x33, 0xf8, 0xa7, 0x66, 0x6b, -0xef, 0x8c, 0x26, 0xe4, 0xe7, 0x7c, 0x7f, 0xf4, -0x72, 0x0f, 0xd3, 0x9b, 0xee, 0x49, 0x38, 0x90, -0xf2, 0xd1, 0x9b, 0xea, 0xef, 0x87, 0xa9, 0xf1, -0x6e, 0x07, 0xb1, 0xd1, 0x93, 0xcb, 0x7f, 0x32, -0xfe, 0x79, 0xc0, 0x3c, 0x33, 0x74, 0x40, 0xac, -0x9c, 0x14, 0x3b, 0xdc, 0x79, 0xdf, 0x1f, 0xc1, -0x2c, 0x3b, 0xbf, 0xc4, 0xf2, 0x9f, 0x97, 0x92, -0xf5, 0x33, 0x81, 0xce, 0x39, 0xe7, 0xe7, 0xaf, -0x02, 0x3b, 0x4e, 0xa9, 0xf9, 0xe7, 0xcb, 0x6f, -0xcd, 0x39, 0xbf, 0x74, 0x01, 0x6e, 0xd0, 0x30, -0xee, 0xf7, 0x79, 0xfa, 0xf7, 0x86, 0xb8, 0xdf, -0xf3, 0xbe, 0x3f, 0xa2, 0xfb, 0xd3, 0x81, 0x49, -0x47, 0xe3, 0x2d, 0x27, 0xe1, 0x60, 0x56, 0x9e, -0x14, 0x1b, 0xad, 0x6f, 0x85, 0x90, 0x7f, 0xd2, -0x83, 0x0c, 0x5b, 0x1f, 0x77, 0x9f, 0xa5, 0x07, -0x25, 0x79, 0x54, 0x7c, 0xdc, 0x8a, 0xef, 0x1a, -0xff, 0xa4, 0x7a, 0x0e, 0x57, 0x60, 0x07, 0x84, -0xe6, 0x7c, 0x7f, 0xb4, 0x87, 0x1d, 0x01, 0xd0, -0xf7, 0xfb, 0x47, 0xb0, 0x8f, 0xed, 0x77, 0xf3, -0x9e, 0x29, 0xe4, 0x9f, 0x48, 0x3f, 0x8c, 0xbd, -0xd2, 0xc2, 0x3e, 0x4a, 0xb4, 0xf2, 0x9f, 0x94, -0xd5, 0xdf, 0x49, 0xbd, 0x71, 0xee, 0x89, 0xe1, -0xd2, 0xdc, 0xef, 0x8f, 0x5e, 0x54, 0x7c, 0x47, -0x7a, 0x33, 0xbe, 0x29, 0xe1, 0xb0, 0xca, 0xea, -0xef, 0xbe, 0x7c, 0xfe, 0x99, 0x51, 0x16, 0x1a, -0xd8, 0x43, 0x65, 0x75, 0x6e, 0xfd, 0x5d, 0xcd, -0x04, 0xe5, 0x31, 0x76, 0xe6, 0xb2, 0x6b, 0x5f, -0x95, 0x3c, 0x3a, 0x19, 0xb4, 0xce, 0xcf, 0xd3, -0xa2, 0x0d, 0xe9, 0x6b, 0x10, 0x1a, 0x75, 0x1d, -0xec, 0xfe, 0x30, 0x73, 0xcd, 0x5d, 0x3f, 0xee, -0x3c, 0x58, 0x6a, 0xd5, 0xdf, 0xe7, 0x5f, 0x4f, -0x5e, 0x8d, 0x37, 0x8f, 0x9d, 0x1a, 0x6c, 0x9d, -0x4a, 0xcf, 0x06, 0xc3, 0x27, 0x5d, 0x83, 0x56, -0xfe, 0x13, 0xd4, 0x16, 0x5b, 0x87, 0x72, 0x56, -0xfa, 0x9c, 0x60, 0x7b, 0x95, 0xdb, 0xb8, 0xe5, -0xe1, 0xe8, 0x97, 0x84, 0xf9, 0xaa, 0x3e, 0x4d, -0x80, 0x57, 0xdb, 0x6c, 0x1b, 0x61, 0x55, 0xcb, -0xe7, 0xa4, 0xb2, 0xa3, 0x05, 0x72, 0xb0, 0x7c, -0x55, 0x95, 0x64, 0x53, 0x97, 0xc4, 0x8c, 0x71, -0x11, 0x0e, 0xc9, 0x9c, 0xec, 0x16, 0x85, 0x27, -0x5b, 0xe4, 0xfd, 0xd1, 0x0d, 0x44, 0x14, 0xa8, -0x71, 0xde, 0x14, 0xf9, 0x28, 0x2a, 0xc8, 0xb5, -0x70, 0x0b, 0xd8, 0x68, 0x65, 0x47, 0x61, 0xd4, -0xee, 0x96, 0x6d, 0xd4, 0xba, 0x67, 0x94, 0x7b, -0x1c, 0x1e, 0xa6, 0x9f, 0x93, 0x6d, 0xa3, 0x9b, -0xfe, 0xb8, 0xe1, 0xbe, 0xa5, 0xee, 0xf5, 0x1e, -0x6a, 0xde, 0xf3, 0xd5, 0x18, 0xc4, 0x39, 0x2f, -0xac, 0x80, 0x12, 0x0a, 0xf1, 0x07, 0x45, 0x21, -0xc2, 0x01, 0x5d, 0x62, 0x8e, 0x53, 0x40, 0xe6, -0x44, 0x88, 0x80, 0x44, 0x85, 0x2a, 0x4e, 0xa4, -0xac, 0x61, 0xf5, 0x7d, 0xb1, 0x4c, 0xe9, 0x8a, -0xc9, 0x0f, 0x89, 0x65, 0x3c, 0x17, 0xc9, 0x2a, -0x93, 0x92, 0xb7, 0x0c, 0x4a, 0x8c, 0x7b, 0x52, -0x27, 0xf7, 0x39, 0x68, 0x51, 0xa5, 0x0e, 0xc1, -0xc9, 0xdd, 0x29, 0xb7, 0xac, 0x95, 0xbe, 0x21, -0x40, 0xa5, 0x31, 0x8e, 0x2a, 0x02, 0x9b, 0x31, -0xb3, 0xae, 0x70, 0x2b, 0x67, 0x8f, 0x22, 0x41, -0xe5, 0x8c, 0xfa, 0x11, 0xbc, 0x1a, 0x27, 0x5e, -0x2e, 0x81, 0xbf, 0x83, 0xce, 0xee, 0x05, 0x22, -0x41, 0xd2, 0xcb, 0x99, 0xf3, 0x3c, 0x12, 0xe3, -0xd6, 0xc3, 0x7d, 0xb0, 0x46, 0x29, 0xa7, 0xb6, -0xf5, 0xdc, 0x7d, 0xa8, 0x7e, 0x1f, 0xa2, 0xe6, -0x3d, 0x5f, 0x85, 0x42, 0xb6, 0xf6, 0x65, 0x50, -0x44, 0x39, 0x56, 0x2e, 0x5d, 0x83, 0x46, 0xb0, -0xe6, 0x19, 0x29, 0x08, 0x76, 0x39, 0x65, 0x5e, -0x04, 0x74, 0x67, 0x34, 0x1e, 0xd2, 0x11, 0xcb, -0x9e, 0x49, 0x31, 0x16, 0x62, 0xa2, 0x8f, 0x65, -0x07, 0x65, 0x41, 0x64, 0x7f, 0x23, 0x41, 0xb5, -0xec, 0xe9, 0xe0, 0x42, 0xea, 0x2a, 0x2d, 0x32, -0x72, 0x41, 0x1a, 0x45, 0xa3, 0xb7, 0xa9, 0xb2, -0x79, 0xcf, 0xd6, 0x05, 0x71, 0x35, 0x1a, 0xbc, -0xc5, 0x29, 0x74, 0xdb, 0x3a, 0xb4, 0x3e, 0x5b, -0xce, 0x9e, 0x11, 0x78, 0xbc, 0x4b, 0x94, 0x57, -0xf8, 0x25, 0xb4, 0x27, 0xa0, 0xf1, 0xc4, 0x3c, -0x9b, 0xad, 0x11, 0x16, 0x76, 0x15, 0xa6, 0x23, -0xed, 0xd2, 0xf3, 0x42, 0x35, 0x2d, 0x0c, 0x46, -0xa2, 0x79, 0x7d, 0xf8, 0x16, 0xb8, 0x08, 0xc4, -0xa8, 0x47, 0x36, 0x1b, 0x60, 0xde, 0x93, 0x16, -0x70, 0x2d, 0x34, 0x16, 0xf7, 0x78, 0x6d, 0x05, -0xdc, 0x7d, 0x94, 0xc4, 0x25, 0xaf, 0x79, 0x02, -0x19, 0xfb, 0xdc, 0x36, 0x01, 0x09, 0x80, 0x14, -0x15, 0x9e, 0x31, 0x1a, 0xa6, 0x44, 0xc0, 0x7b, -0xae, 0xe0, 0x1f, 0xa4, 0x6f, 0xc4, 0xff, 0xd8, -0x3b, 0x9f, 0x35, 0x70, 0x3a, 0x5e, 0x50, 0xac, -0x79, 0xae, 0x28, 0xdc, 0xd8, 0x75, 0x36, 0xfe, -0x25, 0x6f, 0xd9, 0x51, 0x5b, 0x47, 0xd7, 0xc3, -0xf2, 0x7f, 0xf5, 0x96, 0x59, 0x73, 0xb9, 0x37, -0xc2, 0x6d, 0xa4, 0x67, 0xe3, 0x77, 0x79, 0x8b, -0x8e, 0x72, 0x1d, 0xf4, 0x6c, 0xe5, 0x5d, 0xe2, -0x7c, 0xb5, 0xc4, 0xec, 0x5b, 0x51, 0xb0, 0x84, -0x3a, 0xe3, 0xf3, 0xbc, 0xca, 0xd1, 0x82, 0x3f, -0xa6, 0x45, 0xf1, 0x2a, 0xaf, 0x48, 0xcd, 0xf7, -0x0e, 0x84, 0x7b, 0x84, 0xf9, 0xa7, 0x1f, 0xb6, -0xa2, 0xa3, 0x3a, 0xe5, 0x5b, 0xd0, 0x3f, 0x8d, -0x7d, 0x04, 0x50, 0xc0, 0x55, 0x25, 0xa3, 0xd3, -0xee, 0x06, 0x61, 0x3b, 0x57, 0x49, 0xd7, 0xc6, -0xdd, 0x5e, 0xec, 0x33, 0xef, 0xa9, 0x94, 0x75, -0xc0, 0x2a, 0x28, 0x05, 0x41, 0xb5, 0x75, 0xc8, -0x51, 0xc2, 0x1a, 0xe6, 0x3d, 0xef, 0x8d, 0x40, -0x1c, 0xed, 0x89, 0x66, 0x4c, 0x40, 0x3c, 0x2d, -0xfa, 0x89, 0x5d, 0xa2, 0xd6, 0x5c, 0x22, 0x82, -0xdc, 0xe5, 0x95, 0x57, 0x88, 0x25, 0x09, 0x01, -0x37, 0x06, 0xf6, 0x95, 0xe4, 0xf5, 0x55, 0x2a, -0x47, 0x1e, 0x0a, 0xde, 0xeb, 0x2c, 0x8b, 0x70, -0x4a, 0x97, 0x22, 0xbb, 0x9d, 0x36, 0x25, 0x6f, -0x9e, 0x31, 0xfa, 0x90, 0x5c, 0x26, 0xda, 0x22, -0xd8, 0x50, 0xe4, 0x12, 0x71, 0x93, 0x39, 0x4b, -0x96, 0xb1, 0x53, 0x30, 0x6e, 0x15, 0x40, 0x8b, -0x28, 0x20, 0x3e, 0x08, 0xc0, 0x71, 0x56, 0xd7, -0xbd, 0x11, 0x22, 0x77, 0x51, 0x39, 0x2e, 0x7a, -0xdd, 0x09, 0x61, 0x80, 0x5b, 0x08, 0xa2, 0xd7, -0xf2, 0xf9, 0x7b, 0x95, 0x79, 0x71, 0x65, 0x2d, -0xfc, 0xb6, 0x50, 0xd6, 0x75, 0x6f, 0xbc, 0x04, -0x35, 0x29, 0x94, 0x59, 0x73, 0x79, 0x55, 0xe1, -0x82, 0xa0, 0x67, 0x6a, 0x5b, 0x64, 0xf9, 0x4c, -0xd1, 0x2d, 0x50, 0x6e, 0xad, 0x1d, 0x0d, 0x83, -0xaf, 0x8b, 0xa2, 0xeb, 0xf5, 0x2c, 0x94, 0xfd, -0x62, 0x41, 0x81, 0x00, 0xb9, 0x3e, 0x89, 0x89, -0x4c, 0x20, 0x0a, 0xc2, 0xde, 0x02, 0xa9, 0x30, -0x4e, 0x62, 0x79, 0x7d, 0x02, 0xb7, 0x04, 0xa2, -0x8a, 0x5b, 0x12, 0xfa, 0xb9, 0x45, 0x70, 0xbf, -0x52, 0x5a, 0xee, 0x51, 0xad, 0xbe, 0x2a, 0x5b, -0xbb, 0xfa, 0x3b, 0xc1, 0x5b, 0xb6, 0xd9, 0x76, -0xdb, 0xda, 0xe9, 0xfd, 0x71, 0xf7, 0xce, 0x92, -0x39, 0xf7, 0xe4, 0x0a, 0x21, 0xa2, 0x48, 0x29, -0xb8, 0x53, 0xd1, 0x6e, 0x9e, 0xeb, 0x13, 0x85, -0x78, 0x89, 0x57, 0x58, 0xc1, 0x95, 0xf4, 0xb4, -0x05, 0x25, 0xb1, 0x80, 0x70, 0x4f, 0xe7, 0xcd, -0xb3, 0x25, 0x56, 0xe2, 0x11, 0x7e, 0x8b, 0x2b, -0x53, 0x5a, 0xa4, 0x12, 0x45, 0x78, 0x90, 0xb3, -0xe5, 0xd9, 0xac, 0x32, 0x22, 0x3e, 0x94, 0x28, -0x93, 0x37, 0x45, 0x2b, 0x23, 0x7e, 0x05, 0x1b, -0xc9, 0xdc, 0x30, 0x3b, 0x47, 0xa8, 0x92, 0x96, -0xfc, 0x60, 0x5f, 0x80, 0x8d, 0xdd, 0x8a, 0x3f, -0xd7, 0x05, 0x4e, 0xfe, 0x41, 0xee, 0x39, 0x15, -0xfd, 0xb9, 0x8d, 0xff, 0x22, 0xcb, 0x6b, 0x06, -0xbd, 0x79, 0xf7, 0x9c, 0x87, 0x98, 0x05, 0x5f, -0x92, 0xcb, 0x46, 0x6d, 0x8f, 0x97, 0x3c, 0x9c, -0xf8, 0x92, 0xaf, 0x2c, 0xb7, 0x3e, 0x94, 0xcf, -0xaa, 0x14, 0x44, 0x74, 0xa9, 0x32, 0x1b, 0xb9, -0x7b, 0x36, 0xcf, 0xae, 0x9e, 0xfd, 0xfb, 0xd9, -0xcb, 0xb3, 0x37, 0xac, 0x06, 0xfc, 0xab, 0xae, -0x65, 0x6f, 0x3b, 0x96, 0x0d, 0xbf, 0x9e, 0xd9, -0xb7, 0x21, 0xf0, 0xae, 0x3e, 0x6e, 0x2a, 0xd7, -0xf7, 0xf9, 0xa6, 0x55, 0xa7, 0x4a, 0xeb, 0x47, -0xc6, 0x3e, 0xaa, 0x6f, 0xd6, 0xfb, 0x3e, 0xca, -0x7b, 0x9e, 0x37, 0x7a, 0xd4, 0xbd, 0x24, 0xb9, -0x6d, 0xdd, 0x3d, 0x66, 0x23, 0xd7, 0x67, 0x23, -0x1b, 0x95, 0x9d, 0xb1, 0x79, 0x9e, 0xc2, 0x57, -0x59, 0xa3, 0xe3, 0x2e, 0x4f, 0x61, 0x6e, 0x0d, -0xc2, 0xbc, 0x8d, 0xdc, 0xc3, 0xb8, 0xff, 0x6c, -0x23, 0x1c, 0x36, 0xf0, 0x45, 0x96, 0xe4, 0xfa, -0x0a, 0x70, 0xfb, 0x44, 0x81, 0xe1, 0x3c, 0xee, -0x95, 0xe8, 0x9c, 0xbd, 0x82, 0x20, 0xb5, 0x0e, -0xf7, 0xf1, 0x0a, 0x89, 0xd3, 0x37, 0x74, 0x01, -0xe4, 0xb0, 0x00, 0xdf, 0xdf, 0xe3, 0xe8, 0x5a, -0xbf, 0x29, 0x73, 0xa3, 0x08, 0x42, 0xe5, 0xb4, -0xd4, 0x9f, 0x77, 0x4f, 0x80, 0x75, 0x1c, 0xfb, -0x75, 0xdc, 0x2b, 0x6c, 0xdc, 0x0a, 0xe0, 0x72, -0xf7, 0xf4, 0x08, 0x0b, 0xba, 0x34, 0x9f, 0x78, -0x4e, 0x58, 0xc8, 0x15, 0x2a, 0x91, 0x3f, 0x92, -0x72, 0x7d, 0x55, 0x10, 0xed, 0x72, 0x83, 0xd0, -0x57, 0xe2, 0x13, 0xee, 0xe7, 0xdc, 0xf2, 0xbd, -0x03, 0x25, 0xd6, 0xd3, 0x54, 0x27, 0xee, 0x59, -0x94, 0x03, 0x0d, 0xe0, 0x04, 0x9e, 0x22, 0x1f, -0x0d, 0x72, 0x46, 0x48, 0xc5, 0x9f, 0xde, 0x02, -0x65, 0xc0, 0x65, 0x85, 0x98, 0x72, 0x8b, 0x64, -0x63, 0xb1, 0x29, 0xc6, 0x19, 0x61, 0x1a, 0xc7, -0x29, 0x88, 0xed, 0x2c, 0x13, 0xc5, 0xe6, 0x03, -0x3a, 0x4e, 0xe6, 0xfa, 0x84, 0x38, 0xc6, 0x9c, -0xdf, 0x63, 0x31, 0x47, 0x0f, 0x3e, 0x25, 0x66, -0x1c, 0x93, 0x38, 0xc5, 0x13, 0xb7, 0x79, 0x69, -0x01, 0x14, 0xb2, 0x31, 0x7d, 0xf8, 0x4b, 0x85, -0x09, 0xe3, 0x71, 0x0a, 0x62, 0x81, 0xd4, 0xb5, -0x4d, 0x6e, 0x15, 0x25, 0xa4, 0xa4, 0x1a, 0xe0, -0x4b, 0x26, 0x86, 0x28, 0x78, 0xfb, 0x10, 0x9b, -0x22, 0xc3, 0xf9, 0x20, 0x63, 0x59, 0x8c, 0x3b, -0x1b, 0xe3, 0x14, 0x07, 0x84, 0x54, 0x67, 0xb0, -0x95, 0x65, 0xe0, 0x83, 0xd4, 0x99, 0x69, 0x15, -0x8d, 0xbf, 0xd2, 0xc3, 0xee, 0xd9, 0x0a, 0x1d, -0x48, 0x4c, 0x7e, 0x5b, 0xfb, 0x0b, 0x28, 0x5d, -0xde, 0x20, 0x02, 0x0d, 0xb5, 0xee, 0x89, 0xb8, -0x84, 0x58, 0x87, 0x8f, 0xd1, 0xb0, 0x47, 0x26, -0xa2, 0xb5, 0x8f, 0x62, 0x08, 0xdf, 0xec, 0x47, -0x2b, 0xb4, 0x3e, 0x04, 0xa8, 0x88, 0x68, 0xed, -0x3f, 0xe5, 0x5e, 0x3d, 0xfe, 0x71, 0xa0, 0x61, -0x8b, 0x07, 0x9b, 0x0f, 0x46, 0x8c, 0x7b, 0x46, -0x19, 0xea, 0x50, 0x29, 0x2e, 0x78, 0x39, 0xbd, -0x21, 0x79, 0x2d, 0xbf, 0x8e, 0x2a, 0xc4, 0x06, -0x08, 0x63, 0x92, 0x28, 0x60, 0x83, 0x6a, 0x0d, -0xb0, 0xe6, 0xa9, 0xe3, 0xfc, 0x9d, 0xde, 0x22, -0xd6, 0x18, 0x89, 0x7f, 0xd5, 0x5b, 0x94, 0xc3, -0xba, 0x15, 0xb0, 0xb1, 0xab, 0x3c, 0xfe, 0xfb, -0xde, 0x92, 0xa3, 0xc2, 0xc6, 0xae, 0x55, 0xf1, -0xdf, 0xf4, 0x5a, 0x3e, 0xa1, 0x70, 0x2b, 0x60, -0x09, 0xdd, 0x19, 0xff, 0x9c, 0xf7, 0xd6, 0xa3, -0x05, 0x1b, 0xbb, 0x76, 0xc6, 0x3f, 0xef, 0xb5, -0xfc, 0x33, 0xa6, 0xe1, 0xbc, 0x88, 0xbf, 0x1e, -0x3d, 0x0a, 0x4b, 0xba, 0x1e, 0xc6, 0xc8, 0x5c, -0x36, 0x6c, 0xae, 0x9d, 0x73, 0x73, 0xd5, 0xf4, -0x3e, 0xb9, 0x94, 0x05, 0x6f, 0xd6, 0x70, 0x47, -0x05, 0x13, 0xe7, 0x15, 0x5c, 0x43, 0x25, 0x8e, -0x5b, 0xe1, 0x85, 0x27, 0xa1, 0xb2, 0xcb, 0xcb, -0x22, 0x3a, 0x35, 0xbe, 0x2f, 0x86, 0x7b, 0xe3, -0x42, 0x27, 0x14, 0xc3, 0x6f, 0x52, 0x29, 0x2b, -0x34, 0x70, 0xc5, 0xe8, 0x33, 0xb9, 0x77, 0xc4, -0xad, 0x81, 0xf5, 0x5d, 0x85, 0x72, 0x81, 0x7e, -0xcf, 0x42, 0x39, 0x12, 0x45, 0x3e, 0x67, 0xcc, -0xd3, 0x46, 0x4c, 0x33, 0x26, 0x84, 0x47, 0x74, -0xc0, 0xb7, 0xfa, 0x30, 0x3e, 0x28, 0x47, 0x3c, -0x32, 0x42, 0x40, 0xab, 0x10, 0x53, 0x3d, 0x08, -0xf8, 0x25, 0x4a, 0xde, 0x3b, 0xc2, 0x30, 0x1a, -0xb4, 0x89, 0xf8, 0x42, 0xd6, 0x60, 0x60, 0xb5, -0x39, 0xd1, 0x3f, 0x8d, 0x3e, 0x41, 0xc3, 0x79, -0xaa, 0x19, 0x51, 0xd1, 0x5f, 0x86, 0x69, 0x6b, -0xbc, 0x27, 0x01, 0xc4, 0x79, 0x59, 0xf4, 0x92, -0x02, 0x99, 0x22, 0xe0, 0xfb, 0x45, 0xb0, 0xe6, -0x09, 0x05, 0x8c, 0x2f, 0xfd, 0x1e, 0xba, 0xa5, -0x60, 0x11, 0x27, 0xd3, 0x9e, 0xa0, 0xe1, 0xf5, -0x3c, 0xc5, 0x3b, 0x4e, 0xaa, 0xe1, 0x5b, 0xf0, -0x88, 0x52, 0x98, 0x7b, 0xef, 0xf1, 0x02, 0x91, -0xb3, 0xc3, 0x0a, 0x8a, 0x32, 0xdf, 0x8f, 0x6b, -0xf7, 0xe5, 0xd6, 0x1e, 0x13, 0x38, 0xa8, 0x8c, -0x89, 0x31, 0x52, 0xc6, 0xfe, 0x94, 0x4d, 0xcc, -0xf9, 0x10, 0xf1, 0xa0, 0x7f, 0x9a, 0xf6, 0x6c, -0x03, 0x1b, 0x14, 0x76, 0xb4, 0xc6, 0x3c, 0x6f, -0xc0, 0x02, 0x28, 0x8a, 0x93, 0xdf, 0x86, 0x61, -0x6b, 0xed, 0xad, 0x42, 0x5c, 0x91, 0xa4, 0xb6, -0xf2, 0x92, 0x6e, 0x14, 0xa6, 0x5e, 0x69, 0x45, -0x45, 0xce, 0x3f, 0x39, 0x9d, 0xbb, 0x61, 0x5c, -0x49, 0x0a, 0xda, 0x9f, 0x45, 0x92, 0xc1, 0x7a, -0x47, 0x9c, 0xd8, 0x86, 0x38, 0x4f, 0x11, 0xe7, -0xe9, 0x7a, 0x1d, 0xf0, 0x9f, 0xce, 0xd9, 0x53, -0x51, 0x62, 0x1b, 0x3d, 0x60, 0xb3, 0x71, 0x2d, -0x23, 0xb1, 0x07, 0x3d, 0x82, 0x4d, 0xca, 0xd9, -0x53, 0x10, 0xd3, 0x11, 0xd1, 0xb3, 0x55, 0xa8, -0xec, 0x42, 0x9c, 0x07, 0xcf, 0x93, 0x36, 0x19, -0xed, 0x69, 0xbc, 0x5b, 0xce, 0x6e, 0x23, 0xda, -0xda, 0x04, 0x0d, 0xf0, 0xf7, 0x80, 0xdf, 0xc2, -0x25, 0xe5, 0xde, 0x07, 0xf8, 0x2f, 0x2a, 0xc9, -0xd3, 0x77, 0x2e, 0x5d, 0xfb, 0xc0, 0xbc, 0x52, -0xe5, 0xb9, 0xb3, 0xeb, 0x96, 0x16, 0x5a, 0xf7, -0xe4, 0xa2, 0xf2, 0xe3, 0x95, 0x3b, 0xe1, 0xf7, -0x71, 0x2e, 0x6d, 0x8f, 0x94, 0x3c, 0x2c, 0xcc, -0x83, 0x3c, 0x9c, 0xd7, 0xe1, 0x1d, 0x21, 0xb5, -0xca, 0x1b, 0x1d, 0x61, 0xd8, 0xfa, 0xef, 0x80, -0xf3, 0xb5, 0x9f, 0x32, 0xae, 0xfe, 0x53, 0xfa, -0x18, 0xbc, 0x97, 0x1e, 0xd4, 0xe7, 0xf2, 0xda, -0x33, 0x4b, 0x92, 0x4f, 0x5d, 0xc9, 0xf5, 0x91, -0x24, 0xec, 0x62, 0x07, 0x0f, 0x25, 0xab, 0x91, -0xeb, 0xc3, 0x0d, 0xcb, 0x19, 0x1b, 0xd6, 0x68, -0xe4, 0x4d, 0x26, 0x89, 0xbc, 0x58, 0x64, 0x68, -0x68, 0x35, 0x72, 0xd7, 0x5c, 0xd7, 0x54, 0x20, -0xbf, 0x0f, 0xc1, 0x73, 0x4c, 0x7b, 0xb9, 0xdd, -0x41, 0xa3, 0x91, 0x9b, 0x8b, 0xd6, 0x0b, 0x62, -0xae, 0x61, 0xcd, 0x84, 0xf1, 0x0c, 0x59, 0x3b, -0x3e, 0x69, 0xfd, 0x0a, 0xb1, 0xfa, 0xd8, 0x7f, -0x8d, 0x69, 0x3f, 0xe6, 0x43, 0x7a, 0x7f, 0xae, -0xcf, 0x9e, 0x24, 0xbb, 0x60, 0x40, 0xa9, 0x91, -0xf4, 0x06, 0xd4, 0x48, 0xb9, 0x27, 0xde, 0xb4, -0xbe, 0xca, 0xdc, 0xfa, 0xc4, 0x9b, 0xd7, 0x57, -0x49, 0xac, 0x71, 0xa2, 0xc4, 0xfe, 0x3e, 0xda, -0x18, 0x2e, 0xab, 0x5c, 0xc5, 0x86, 0xb6, 0x3e, -0x22, 0x58, 0xe3, 0x36, 0x07, 0xf1, 0xd7, 0xbf, -0x8e, 0xe3, 0xcc, 0x46, 0xee, 0x79, 0x84, 0x11, -0x24, 0x59, 0x11, 0x73, 0x8d, 0x39, 0xf6, 0x94, -0xd9, 0xf3, 0xf2, 0x1a, 0xe6, 0x25, 0x51, 0x9e, -0x85, 0x91, 0x7a, 0xfc, 0x87, 0x37, 0x75, 0x91, -0xf9, 0x9d, 0xcd, 0xa7, 0x5c, 0x4d, 0x4d, 0xbf, -0xfc, 0x33, 0x97, 0xeb, 0x5f, 0x1c, 0xf6, 0x7f, -0x71, 0x35, 0xcf, 0xce, 0xce, 0xaa, 0x73, 0x1a, -0xff, 0x6f, 0xf6, 0x7d, 0x9a, 0xcf, 0x03, 0x73, -0x05, 0xc8, 0xf9, 0x3c, 0xfc, 0x3b, 0xf9, 0x7c, -0xbe, 0x57, 0xe7, 0x79, 0xe0, 0xa7, 0xfa, 0xbc, -0x68, 0xfa, 0xbc, 0xd5, 0x98, 0xeb, 0xf3, 0x73, -0x47, 0xfe, 0x1a, 0x9f, 0x1f, 0x1b, 0xf8, 0x7a, -0x4d, 0xf9, 0x70, 0x6e, 0xdc, 0xaf, 0xdd, 0xd3, -0xbf, 0xe4, 0xf3, 0xca, 0x1c, 0x9f, 0xb7, 0x96, -0xa5, 0x39, 0xff, 0xd7, 0xa1, 0x7c, 0x58, 0xf8, -0x97, 0xc7, 0x7d, 0xda, 0x9e, 0xfe, 0x34, 0xbb, -0x40, 0x1e, 0x8b, 0xcb, 0x59, 0x58, 0xfe, 0xe5, -0x9f, 0xdd, 0x74, 0x7d, 0xe6, 0xf3, 0xbf, 0xae, -0xef, 0xd7, 0x5f, 0xec, 0x6f, 0x39, 0x12, 0xed, -0xdf, 0x2d, 0xaf, 0xfd, 0x6b, 0xc7, 0x7c, 0x76, -0x7d, 0x76, 0x7d, 0x76, 0x7d, 0x76, 0x7d, 0x76, -0x7d, 0x76, 0xfd, 0xff, 0x72, 0x69, 0x71, 0x92, -0x68, 0x71, 0x52, 0xfd, 0x8f, 0x9e, 0xcb, 0x67, -0xd7, 0x67, 0xd7, 0x67, 0xd7, 0x67, 0xd7, 0x67, -0xd7, 0x67, 0xd7, 0x7f, 0xc4, 0x15, 0x64, 0x65, -0x00, 0xd8, 0xfb, 0xb2, 0xf1, 0xf7, 0xff, 0xf9, -0x20, 0x28, 0xf3, 0x3e, 0xfd, 0xf7, 0xb5, 0xdf, -0xb3, 0x05, 0x21, 0xcd, 0xe5, 0xc6, 0xf7, 0xa7, -0x6e, 0x9e, 0xeb, 0xff, 0x01, 0x51, 0x16, 0x5f, -0xd0, 0xd5, 0x60, 0x00, 0x00, diff --git a/board/esd/plu405/Kconfig b/board/esd/plu405/Kconfig deleted file mode 100644 index b3082cb..0000000 --- a/board/esd/plu405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PLU405 - -config SYS_BOARD - default "plu405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "PLU405" - -endif diff --git a/board/esd/plu405/MAINTAINERS b/board/esd/plu405/MAINTAINERS deleted file mode 100644 index ccb3658..0000000 --- a/board/esd/plu405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PLU405 BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/plu405/ -F: include/configs/PLU405.h -F: configs/PLU405_defconfig diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile deleted file mode 100644 index 6ffae67..0000000 --- a/board/esd/plu405/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = plu405.o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c deleted file mode 100644 index 23e8164..0000000 --- a/board/esd/plu405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c deleted file mode 100644 index 485b9a2..0000000 --- a/board/esd/plu405/fpgadata.c +++ /dev/null @@ -1,2358 +0,0 @@ -0x1f, 0x8b, 0x08, 0x08, 0x04, 0x44, 0x9f, 0x46, -0x00, 0x03, 0x70, 0x6c, 0x75, 0x34, 0x30, 0x35, -0x5f, 0x31, 0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74, -0x00, 0x94, 0x9a, 0x0f, 0x70, 0x14, 0x55, 0x9e, -0xc7, 0x7f, 0xfd, 0xba, 0x93, 0x74, 0xa6, 0x3b, -0xe9, 0x36, 0x7f, 0x30, 0xb7, 0x08, 0xd7, 0x19, -0x07, 0x76, 0xc4, 0x61, 0x18, 0x42, 0x80, 0x98, -0x0d, 0x49, 0x33, 0xa4, 0xac, 0x71, 0xc9, 0x1e, -0xf1, 0xce, 0xbb, 0xe2, 0xf6, 0xbc, 0xdd, 0x11, -0x71, 0x8f, 0xbb, 0xe2, 0x2c, 0xd6, 0xdd, 0xb3, -0xb8, 0x3b, 0x4b, 0x5f, 0x66, 0xa2, 0x04, 0x92, -0x92, 0x01, 0x39, 0x37, 0xba, 0xac, 0x35, 0x40, -0x6e, 0x8d, 0x4a, 0x59, 0x11, 0x75, 0x8d, 0x82, -0xbb, 0x4d, 0x0c, 0x3a, 0x60, 0xd4, 0xb9, 0x94, -0x7b, 0x8b, 0x7f, 0x8e, 0x6d, 0xd8, 0xc0, 0x46, -0x89, 0x3a, 0xcb, 0xa2, 0x06, 0x65, 0xcd, 0xbd, -0xd7, 0x3d, 0xdd, 0xd3, 0x99, 0x9e, 0x04, 0x37, -0x5a, 0xc5, 0x2f, 0xaf, 0x1f, 0x8f, 0xf7, 0xfb, -0xcd, 0xef, 0xfd, 0x7e, 0x9f, 0xfe, 0xbe, 0x81, -0x52, 0x29, 0x63, 0xfe, 0x07, 0xc0, 0xdc, 0x06, -0xd2, 0x96, 0xcd, 0xff, 0x56, 0x1f, 0x5a, 0xfe, -0xfd, 0xa5, 0xdf, 0x5f, 0x1a, 0xbc, 0xf3, 0xf6, -0x8d, 0xb0, 0x01, 0x84, 0xba, 0x1f, 0x2d, 0x0f, -0xdd, 0xf1, 0xe3, 0x1f, 0x2e, 0xad, 0xaf, 0x87, -0xdb, 0xc9, 0x6f, 0xa1, 0xd0, 0xca, 0x25, 0xe4, -0xff, 0xa5, 0x37, 0xc0, 0x46, 0x28, 0x5d, 0x5a, -0xd7, 0xb8, 0xfc, 0x86, 0xc6, 0xa5, 0x2b, 0xe1, -0x0e, 0x60, 0x96, 0xf5, 0x4d, 0x91, 0x9f, 0x27, -0x1f, 0xf9, 0xdb, 0x1f, 0x84, 0x00, 0x33, 0x00, -0x50, 0x12, 0x62, 0xa2, 0xf4, 0x4f, 0x21, 0xc4, -0x28, 0x0c, 0xe0, 0x96, 0xc5, 0x21, 0xd0, 0xe8, -0xef, 0x90, 0x7d, 0x5e, 0x1a, 0x02, 0xc5, 0xf9, -0x3b, 0x13, 0x02, 0x15, 0xda, 0x41, 0xed, 0x81, -0x0a, 0x19, 0xae, 0xf8, 0xc3, 0xa8, 0x1c, 0xb6, -0xec, 0x3f, 0x73, 0xfe, 0xd4, 0x09, 0x3c, 0xe3, -0xb4, 0xdc, 0x4f, 0xcb, 0x85, 0xa4, 0x65, 0xa2, -0xd0, 0xd7, 0x59, 0x1f, 0xec, 0xf5, 0xdf, 0xfd, -0x5a, 0xeb, 0x7f, 0x66, 0xad, 0xff, 0xe7, 0xce, -0x87, 0x8a, 0xaf, 0x31, 0x1d, 0x80, 0xb3, 0xf7, -0x63, 0x86, 0x87, 0x03, 0x06, 0x43, 0x14, 0x64, -0x28, 0xa6, 0x86, 0x42, 0x46, 0x10, 0x80, 0x69, -0x18, 0xeb, 0x0f, 0x5b, 0xf3, 0x87, 0x8a, 0xbe, -0x82, 0x29, 0xdc, 0xa2, 0x8a, 0x1a, 0x5b, 0x8f, -0x76, 0xe2, 0x16, 0x5d, 0x4a, 0xb1, 0x75, 0xf0, -0x16, 0x35, 0x26, 0x59, 0xe3, 0x11, 0x35, 0x32, -0xb0, 0xc5, 0x9a, 0x5f, 0xf3, 0x31, 0x1c, 0xc6, -0x4b, 0xa2, 0x91, 0x2e, 0x4f, 0x33, 0xbc, 0x17, -0x0b, 0xea, 0x42, 0x17, 0xda, 0x0f, 0x4f, 0x61, -0x62, 0x0c, 0x22, 0xfa, 0xc8, 0x30, 0x32, 0x9c, -0x15, 0xc5, 0x13, 0x45, 0x3d, 0xdc, 0x01, 0x10, -0x55, 0xbf, 0xec, 0xe9, 0x84, 0x18, 0x04, 0x34, -0x41, 0xae, 0x68, 0x85, 0x38, 0x35, 0x42, 0x68, -0x04, 0x9e, 0x35, 0x8d, 0x43, 0x8c, 0xb5, 0xbe, -0xc6, 0x1d, 0x84, 0xc3, 0x10, 0x8c, 0x96, 0xf6, -0xc6, 0xbe, 0x89, 0x1e, 0x85, 0xe0, 0x51, 0xa1, -0x17, 0xfd, 0x1e, 0x9e, 0x82, 0xa0, 0x26, 0x0c, -0xa0, 0x09, 0xfa, 0x88, 0x18, 0xde, 0x0c, 0x17, -0xcd, 0xce, 0x5f, 0x7d, 0xd5, 0x04, 0x9c, 0x87, -0xe6, 0x0d, 0xa2, 0xcc, 0x2e, 0x14, 0x53, 0xbb, -0x9a, 0xef, 0x28, 0xe9, 0x89, 0x6f, 0x80, 0xd7, -0xa1, 0x59, 0x93, 0x06, 0xd8, 0x09, 0xf8, 0xd2, -0x34, 0xd2, 0x9c, 0xb5, 0x7e, 0x92, 0x39, 0x02, -0x53, 0xd0, 0xb4, 0xba, 0x3c, 0x73, 0xed, 0x08, -0x4c, 0xf1, 0xf7, 0xa9, 0x25, 0x1a, 0x3b, 0x40, -0x46, 0x5a, 0x34, 0x29, 0xc3, 0x5e, 0xb6, 0x8c, -0x71, 0xb0, 0xd6, 0xd7, 0xe4, 0x83, 0x74, 0x91, -0xa8, 0xf8, 0x73, 0x76, 0x81, 0x7a, 0x02, 0x35, -0xab, 0x52, 0x62, 0xcd, 0x59, 0x6b, 0x59, 0x7b, -0xfd, 0x8b, 0x9c, 0x15, 0xd9, 0x93, 0x45, 0x01, -0x63, 0x93, 0xfc, 0x41, 0xf6, 0x9f, 0xa0, 0x3b, -0x19, 0x8c, 0xfc, 0x43, 0x05, 0x7a, 0x4d, 0x3b, -0x6c, 0xed, 0xff, 0xbc, 0x69, 0x5c, 0x20, 0xd9, -0x6f, 0xfe, 0xa4, 0xb8, 0x36, 0x1a, 0x04, 0x58, -0xc4, 0xdd, 0x05, 0x38, 0xce, 0x04, 0x46, 0x05, -0x40, 0x47, 0xad, 0xb0, 0xd8, 0xf1, 0x99, 0x24, -0x67, 0xc5, 0xfc, 0xc9, 0xc8, 0xdf, 0x83, 0x17, -0xf0, 0xe2, 0xa8, 0xff, 0x9f, 0xd1, 0x77, 0x61, -0x5b, 0xc7, 0x62, 0x5d, 0x88, 0xa0, 0x77, 0xe9, -0x88, 0x2e, 0x6c, 0x45, 0xa7, 0xe0, 0x71, 0xd3, -0xf8, 0xca, 0x5e, 0x3f, 0xc2, 0xb7, 0xc1, 0x1f, -0xa1, 0x49, 0x2d, 0x67, 0x1e, 0x82, 0xd8, 0x10, -0x34, 0x91, 0xd5, 0x58, 0x8d, 0x8e, 0x68, 0x52, -0x88, 0x1d, 0x31, 0x8d, 0xa5, 0xec, 0x28, 0xb2, -0x12, 0x49, 0xad, 0xa6, 0xf1, 0x69, 0x51, 0xa5, -0x9b, 0xd9, 0x0c, 0x59, 0x86, 0x44, 0x23, 0xcd, -0x4e, 0xaa, 0xf9, 0xf1, 0x49, 0x17, 0x5b, 0xf1, -0xe1, 0x39, 0x23, 0x3e, 0x29, 0x31, 0xc6, 0xfa, -0xb0, 0x16, 0xa9, 0xd3, 0x24, 0xcc, 0x7a, 0x5d, -0xf1, 0xff, 0xd0, 0xce, 0x9f, 0x54, 0xcd, 0x5e, -0x78, 0x01, 0x02, 0x61, 0x3e, 0xb4, 0x5b, 0x54, -0xee, 0x67, 0x6a, 0x35, 0x41, 0x0d, 0xcb, 0xb0, -0x0d, 0x16, 0x6b, 0xc2, 0x16, 0xf4, 0x3e, 0x79, -0x64, 0x18, 0x17, 0xec, 0xcf, 0x57, 0x81, 0xc7, -0x0c, 0xef, 0xf8, 0x4d, 0x9e, 0x0a, 0x78, 0x00, -0xd7, 0xea, 0x82, 0x1e, 0x5b, 0x01, 0xdb, 0x2c, -0x7f, 0xb3, 0x8e, 0xeb, 0x76, 0x66, 0x6f, 0xe2, -0x7a, 0x68, 0xd0, 0x46, 0xfb, 0x15, 0x54, 0x96, -0x88, 0x47, 0xf4, 0x31, 0xa1, 0x7e, 0x7f, 0x19, -0xce, 0xcf, 0xb7, 0x51, 0x3b, 0x3f, 0xc7, 0xab, -0xc7, 0xe1, 0x0b, 0x68, 0xc1, 0x62, 0x92, 0xbd, -0xa1, 0xf8, 0x44, 0xa4, 0x0e, 0x4b, 0x3a, 0x6a, -0x44, 0x27, 0xa0, 0x19, 0x4b, 0x49, 0x96, 0x3e, -0x32, 0x8c, 0x2f, 0xec, 0xfd, 0x44, 0x98, 0x24, -0x4c, 0x42, 0x33, 0x48, 0xbc, 0x70, 0x5a, 0x9d, -0x54, 0x89, 0x81, 0x59, 0x5d, 0x35, 0x46, 0x88, -0x01, 0x59, 0x63, 0x14, 0xac, 0xf5, 0x79, 0xb9, -0x0f, 0x2e, 0x91, 0xf8, 0x8b, 0xcf, 0x55, 0x2e, -0x0c, 0xbf, 0x0e, 0x75, 0xaa, 0xb4, 0xbb, 0x64, -0x4c, 0xbd, 0x04, 0x34, 0x91, 0xd8, 0x31, 0xc8, -0x1a, 0x43, 0xf6, 0x7e, 0x30, 0xb7, 0x11, 0x5e, -0x84, 0x60, 0x7b, 0x57, 0xc2, 0x53, 0x02, 0x1d, -0x09, 0xaf, 0x4a, 0xf2, 0xff, 0x2c, 0x26, 0x23, -0xaa, 0x90, 0x40, 0x63, 0xe4, 0x51, 0x23, 0x35, -0x74, 0xb0, 0xaa, 0x60, 0x43, 0x91, 0x8f, 0xce, -0x0f, 0xfb, 0xf7, 0x78, 0x7c, 0xb0, 0x1d, 0xbc, -0xe1, 0xb5, 0xe6, 0x34, 0x7b, 0xbe, 0x61, 0xbc, -0x6a, 0xe7, 0x83, 0x52, 0xc5, 0xc1, 0x33, 0x10, -0x50, 0x79, 0x19, 0xf9, 0xc8, 0x31, 0x54, 0x54, -0x41, 0x46, 0xc3, 0xc6, 0x48, 0xd6, 0xf0, 0x53, -0x63, 0x88, 0xb1, 0xf2, 0x61, 0x6b, 0x59, 0xd4, -0x70, 0x4a, 0xc4, 0x82, 0x1f, 0x52, 0x50, 0x47, -0xbc, 0x43, 0xb6, 0x9b, 0xb6, 0xf1, 0x26, 0x6b, -0xe5, 0x67, 0x6f, 0x11, 0x75, 0xaa, 0xa5, 0x7d, -0xc9, 0x1e, 0xf6, 0x53, 0x62, 0xfc, 0x4a, 0x95, -0xda, 0xd9, 0xf7, 0x2d, 0x37, 0x37, 0x12, 0xa3, -0x91, 0x1a, 0xe7, 0x8a, 0xad, 0x7c, 0xa8, 0x21, -0xf3, 0xdf, 0x81, 0x55, 0x43, 0x62, 0x26, 0x5e, -0xcf, 0xbc, 0x41, 0x13, 0x2f, 0x5d, 0x72, 0x11, -0xf2, 0xe3, 0xf3, 0xaa, 0x5d, 0x1f, 0x1a, 0x6a, -0x74, 0x18, 0x84, 0xa0, 0x1c, 0xe9, 0x44, 0xb5, -0x6a, 0x17, 0x17, 0x04, 0x81, 0xee, 0x87, 0x8c, -0x4c, 0x33, 0xde, 0xe4, 0xac, 0xf8, 0x44, 0xa0, -0x93, 0x38, 0x15, 0x54, 0xf9, 0x10, 0xf1, 0xb7, -0x03, 0x7c, 0xea, 0x5a, 0xc3, 0x4d, 0x26, 0xa0, -0xb2, 0x0e, 0xc7, 0x73, 0x9f, 0x57, 0x2f, 0xd7, -0x07, 0x2f, 0x32, 0xc1, 0x28, 0xbf, 0x47, 0x09, -0x90, 0x78, 0x92, 0xe8, 0x3d, 0x5c, 0x28, 0x9e, -0x76, 0x3e, 0x24, 0xab, 0xc7, 0xc4, 0x77, 0xb8, -0xa6, 0x4d, 0x81, 0x44, 0x69, 0xb1, 0x77, 0xbb, -0xde, 0xac, 0xae, 0x4b, 0xa0, 0xb3, 0xf0, 0xef, -0x79, 0xfb, 0x1f, 0xb7, 0xeb, 0x4f, 0x8a, 0xe9, -0x83, 0x1b, 0xe8, 0xe0, 0x23, 0xc2, 0x39, 0xf5, -0x52, 0xc2, 0x78, 0xfa, 0x7b, 0x97, 0xbf, 0x5f, -0xd8, 0xf5, 0x87, 0x97, 0x8d, 0x7c, 0x93, 0x45, -0xb4, 0xa6, 0x16, 0xa5, 0xd4, 0xe6, 0x52, 0xa9, -0x93, 0x3d, 0xed, 0x8a, 0xff, 0x09, 0xbb, 0xfe, -0xf8, 0x8b, 0xfc, 0xf0, 0x12, 0x2c, 0xe9, 0xe7, -0x75, 0xf4, 0x2d, 0xfc, 0xe0, 0xea, 0x25, 0x0f, -0x09, 0xfb, 0xd1, 0x97, 0xa1, 0x97, 0x20, 0x88, -0xe7, 0x26, 0xd1, 0x38, 0x50, 0x43, 0x48, 0x92, -0xfc, 0xb6, 0xf2, 0xc1, 0x6f, 0xd6, 0x9f, 0x49, -0x8f, 0x0f, 0x49, 0x4a, 0xbc, 0x8b, 0x9c, 0x8e, -0x06, 0xf4, 0x86, 0xef, 0x59, 0x66, 0xfa, 0x79, -0x39, 0x61, 0xd7, 0x1f, 0x2c, 0xdf, 0x6a, 0x1c, -0x52, 0xcf, 0x16, 0x6f, 0x0f, 0x6c, 0x53, 0x17, -0x63, 0xd6, 0x71, 0x6c, 0x6d, 0x63, 0xdc, 0x5e, -0xbf, 0xab, 0xeb, 0x94, 0xfc, 0x39, 0x5e, 0xa5, -0x07, 0x1b, 0x84, 0x39, 0xf0, 0x1a, 0x31, 0xa4, -0xf5, 0xe4, 0x74, 0xd0, 0x11, 0x61, 0x2b, 0x7b, -0xca, 0x30, 0xa4, 0xad, 0xec, 0x87, 0x76, 0xfd, -0xe1, 0xab, 0x8d, 0x7a, 0xa2, 0x95, 0x0d, 0x54, -0x6e, 0xa4, 0x06, 0x76, 0x96, 0x11, 0xdb, 0x18, -0xb2, 0xeb, 0x0f, 0x14, 0xfd, 0x92, 0x36, 0xa9, -0x64, 0xf9, 0x49, 0x76, 0xbe, 0xfc, 0x5a, 0x82, -0x11, 0xdb, 0xde, 0x59, 0xf3, 0x99, 0x3a, 0x95, -0x98, 0xde, 0xbf, 0x34, 0xbb, 0xfe, 0xf4, 0xd7, -0xec, 0x55, 0xc9, 0x26, 0x3b, 0xcb, 0x6e, 0x66, -0x6f, 0xc5, 0xdb, 0xa0, 0x76, 0x8f, 0xa7, 0x1d, -0xbd, 0x9d, 0xbf, 0x7f, 0xf6, 0x49, 0xfb, 0xf3, -0x05, 0xbc, 0xd7, 0xf4, 0x57, 0x46, 0xff, 0xe8, -0x7b, 0x90, 0xaf, 0x6d, 0x2d, 0x6d, 0x7f, 0xf5, -0x6d, 0xee, 0x05, 0xf8, 0xd7, 0x69, 0xfe, 0x6a, -0x76, 0xfd, 0x51, 0xcc, 0xfa, 0x93, 0xb9, 0x49, -0x42, 0x6d, 0xc5, 0x31, 0x55, 0xc1, 0xc2, 0x7c, -0x78, 0x55, 0xcd, 0xaf, 0xe7, 0x5d, 0xf6, 0x79, -0xef, 0xaf, 0x9e, 0xe0, 0x89, 0x53, 0x99, 0xf2, -0xe7, 0xd8, 0xdb, 0xe1, 0x75, 0xed, 0x10, 0x33, -0xef, 0x08, 0xf9, 0x58, 0xbf, 0x84, 0x7b, 0xa7, -0xd7, 0x4f, 0x7b, 0x3f, 0x98, 0x31, 0xe2, 0xd3, -0xb6, 0xae, 0xaa, 0x92, 0x3c, 0x8d, 0x34, 0x43, -0xf9, 0x00, 0xc9, 0x87, 0xfc, 0xf8, 0xe4, 0xea, -0x61, 0xad, 0x6c, 0xf4, 0x3b, 0x4d, 0xcc, 0xb0, -0x7f, 0x87, 0xdf, 0xc0, 0x12, 0xf4, 0xa4, 0x49, -0x37, 0xcf, 0xaf, 0xe7, 0x5a, 0xab, 0xb5, 0x9f, -0x7d, 0xdc, 0x66, 0xf8, 0x29, 0x04, 0xb7, 0xf6, -0x1f, 0x79, 0xe9, 0x71, 0xe8, 0xd7, 0x03, 0x0a, -0x3f, 0x80, 0x7e, 0x07, 0x87, 0xa7, 0xf7, 0x5f, -0xa4, 0xdb, 0xf5, 0x01, 0x93, 0x7e, 0x47, 0xba, -0xb3, 0xce, 0xef, 0x42, 0x3e, 0xb9, 0x5b, 0x09, -0x2a, 0xa5, 0x89, 0x8a, 0x33, 0x8a, 0x6b, 0xbe, -0x9d, 0x0f, 0x7c, 0x95, 0x68, 0x04, 0x81, 0x07, -0xd4, 0x03, 0xfb, 0xc8, 0x69, 0x2d, 0x95, 0x49, -0xf4, 0xf2, 0xe3, 0x93, 0xab, 0x3f, 0x50, 0xb6, -0x99, 0xf6, 0x77, 0x4d, 0xc4, 0x95, 0x3e, 0x44, -0xda, 0x0a, 0x94, 0x25, 0x8c, 0xf8, 0x64, 0xfd, -0x3d, 0x6c, 0x1a, 0x9a, 0x5d, 0x7f, 0xf6, 0x15, -0x5d, 0x86, 0xdf, 0x12, 0xa7, 0x96, 0x68, 0xc4, -0xbb, 0xcb, 0xd0, 0x02, 0x4f, 0x17, 0xf2, 0xf7, -0x03, 0xbb, 0xfe, 0x68, 0x45, 0xd9, 0x24, 0xd1, -0x2b, 0x9b, 0xe1, 0x32, 0x5e, 0x59, 0xdb, 0x93, -0x62, 0x2f, 0xc0, 0x6f, 0x67, 0xe4, 0x1f, 0x2c, -0x53, 0xc8, 0x69, 0x4c, 0x76, 0x77, 0xb1, 0x01, -0xf8, 0x00, 0x7b, 0xc1, 0xd3, 0x85, 0xf4, 0x64, -0x77, 0x1e, 0xff, 0xe8, 0xb9, 0xfa, 0x5f, 0xd4, -0x96, 0x75, 0xaa, 0xb8, 0x8d, 0x56, 0x27, 0x95, -0x38, 0x3e, 0xec, 0xea, 0x47, 0x43, 0x39, 0xfe, -0xa9, 0xa6, 0xfc, 0xb3, 0x08, 0x93, 0xa0, 0x05, -0xe0, 0x09, 0x6d, 0xd1, 0x06, 0x4f, 0x4f, 0xc5, -0x39, 0xa5, 0x3b, 0x2f, 0x9e, 0x39, 0xfe, 0x81, -0xaa, 0x00, 0x8d, 0x46, 0x72, 0xe7, 0x13, 0xc2, -0x66, 0xc8, 0x68, 0x4d, 0x21, 0xbe, 0x8b, 0xfd, -0x9d, 0xab, 0xff, 0x6a, 0x76, 0xfd, 0x39, 0x0d, -0x46, 0x7f, 0xdf, 0x25, 0xe9, 0xec, 0x11, 0xf8, -0x13, 0xac, 0x04, 0x49, 0xab, 0x74, 0xc7, 0x67, -0xd2, 0xc9, 0x3f, 0xf2, 0x7b, 0xd0, 0x3c, 0x22, -0xfa, 0x0e, 0x4c, 0xa0, 0x14, 0x5e, 0xa1, 0x92, -0xfa, 0x73, 0x16, 0xd6, 0x9a, 0xcb, 0x6e, 0xb6, -0xd6, 0xcf, 0xd8, 0xf5, 0x27, 0xd5, 0x6a, 0xf0, -0x4f, 0x82, 0x1f, 0x24, 0xbb, 0x25, 0xfd, 0x48, -0x2d, 0xc7, 0x68, 0x8c, 0x99, 0xb6, 0xff, 0x72, -0x27, 0xff, 0x9c, 0x31, 0xe3, 0x93, 0xf6, 0x28, -0xe1, 0x11, 0x02, 0xa8, 0x3e, 0x20, 0xf5, 0x59, -0x97, 0x69, 0x7c, 0x3c, 0x05, 0xf9, 0x67, 0x03, -0x33, 0x9f, 0x36, 0xfd, 0xa4, 0x27, 0x52, 0x7c, -0x4a, 0x2e, 0xc2, 0xb5, 0x8a, 0xb0, 0x9e, 0xf0, -0xcf, 0x34, 0x1e, 0xf0, 0x6c, 0x45, 0x27, 0x1d, -0xfc, 0x43, 0xf3, 0xad, 0x29, 0x5d, 0xce, 0x6d, -0x9b, 0x80, 0x30, 0x54, 0x69, 0x52, 0x05, 0x29, -0xb3, 0x71, 0x72, 0x22, 0xca, 0x43, 0x6c, 0x9b, -0x05, 0x42, 0xa3, 0x76, 0xba, 0xa9, 0xf3, 0x68, -0x7c, 0x56, 0xa5, 0x17, 0xff, 0x9a, 0x44, 0xe3, -0x22, 0x01, 0x83, 0x72, 0x92, 0x3f, 0xea, 0x94, -0x3c, 0x13, 0xff, 0xf4, 0x17, 0x19, 0x41, 0x96, -0x49, 0x58, 0x48, 0xfc, 0xa1, 0x99, 0x21, 0xd1, -0x38, 0x33, 0x1b, 0xff, 0x5c, 0x65, 0xd4, 0x13, -0x2c, 0x00, 0x7b, 0x2b, 0xf7, 0x3c, 0xda, 0x07, -0x82, 0x4a, 0x76, 0xfb, 0xf8, 0x8c, 0xfc, 0xa3, -0x99, 0xfc, 0xb3, 0x81, 0x60, 0xde, 0x7c, 0xf8, -0x85, 0xb6, 0xf8, 0xb6, 0xb9, 0x5b, 0xd1, 0x67, -0x2e, 0xfe, 0xc9, 0xd8, 0xe7, 0x3d, 0x52, 0x65, -0x04, 0x2d, 0xd3, 0x7d, 0x0d, 0x6a, 0xe3, 0x9f, -0x55, 0x95, 0xb4, 0x50, 0x1f, 0x7b, 0x13, 0x0e, -0xcc, 0xc2, 0x3f, 0xfd, 0x14, 0x72, 0x12, 0xd2, -0x41, 0xd6, 0xcf, 0x7f, 0x06, 0xf7, 0xc5, 0x05, -0x1d, 0x5d, 0x52, 0xf2, 0xf8, 0x07, 0x39, 0xf8, -0x07, 0x8c, 0xa6, 0x23, 0xb3, 0x45, 0xb4, 0xfb, -0xdc, 0x64, 0xb6, 0xa1, 0xce, 0xd9, 0xf8, 0xc7, -0x68, 0x6a, 0x43, 0x65, 0x03, 0x71, 0x1f, 0x73, -0x09, 0xd7, 0x85, 0xa5, 0xc4, 0xed, 0xb4, 0x8d, -0xce, 0xcc, 0x3f, 0x46, 0x93, 0x6d, 0x17, 0xf6, -0xee, 0xf0, 0x95, 0xbe, 0xb8, 0x9e, 0xf0, 0x4f, -0xc2, 0x6b, 0xb6, 0x5d, 0xc9, 0xd1, 0x7f, 0x73, -0xfc, 0x53, 0x93, 0xe5, 0x1f, 0x61, 0x37, 0xda, -0x28, 0xbf, 0x08, 0xfb, 0x57, 0xcf, 0x4d, 0xa0, -0x3e, 0x63, 0xda, 0xdc, 0x82, 0xfc, 0xc3, 0x03, -0x97, 0x6d, 0xfa, 0x75, 0x45, 0xc4, 0x50, 0xda, -0xe7, 0xca, 0xe8, 0x18, 0x47, 0x47, 0x3c, 0x0e, -0x1e, 0xc8, 0xd5, 0x9f, 0x41, 0x3e, 0x6a, 0x39, -0x15, 0x85, 0x41, 0xa6, 0x02, 0x76, 0x62, 0xd6, -0x24, 0x40, 0xc1, 0xe1, 0xef, 0xc7, 0xac, 0xb5, -0x9f, 0xde, 0x79, 0x59, 0xa7, 0xf6, 0x10, 0xef, -0xfe, 0x44, 0x78, 0x66, 0x67, 0xfa, 0x6f, 0xde, -0xaf, 0xc9, 0xef, 0xef, 0xe7, 0x4a, 0xac, 0x78, -0xf6, 0x56, 0x1b, 0xbc, 0xa4, 0x8a, 0xe9, 0x6d, -0x63, 0xf0, 0x29, 0x1c, 0x6a, 0xaf, 0x19, 0x60, -0x17, 0xb8, 0x78, 0xe0, 0x9c, 0x9d, 0x3f, 0x0d, -0x72, 0x94, 0xa3, 0x90, 0xe3, 0xef, 0x44, 0x7a, -0x62, 0x12, 0xbc, 0x50, 0x86, 0x11, 0x2e, 0xc0, -0x3f, 0xb9, 0xb7, 0xd8, 0x56, 0xe2, 0x9d, 0xa8, -0xf2, 0x35, 0x68, 0x58, 0x79, 0x86, 0xe9, 0x57, -0xf9, 0x04, 0xe2, 0x18, 0x07, 0xef, 0x65, 0xfd, -0xcd, 0xf1, 0x98, 0x11, 0x3d, 0x0d, 0x76, 0x91, -0xe8, 0x3d, 0xc1, 0xfb, 0xd5, 0xed, 0x89, 0x70, -0x9f, 0xea, 0x8a, 0x67, 0x8e, 0x7f, 0x38, 0xca, -0xb7, 0xcd, 0x61, 0x6e, 0x2f, 0x79, 0xfa, 0x4c, -0xc5, 0xbf, 0xac, 0xe7, 0xe7, 0xd8, 0xfb, 0x5f, -0x53, 0x80, 0x7f, 0xfa, 0xc1, 0x98, 0xbf, 0x3a, -0xeb, 0xdd, 0xdd, 0x11, 0xe9, 0x51, 0xe2, 0x5d, -0xbe, 0xbf, 0x1f, 0xda, 0xf5, 0xc7, 0x0f, 0x26, -0xff, 0x48, 0x78, 0x8d, 0x22, 0xa6, 0xda, 0x56, -0x80, 0xd4, 0xb9, 0x46, 0x87, 0x14, 0x9a, 0x91, -0x7f, 0x38, 0xca, 0x3f, 0x8b, 0x7b, 0x05, 0x7d, -0x87, 0xbf, 0xf8, 0xc1, 0xa3, 0x5e, 0x4a, 0x3b, -0xe3, 0xf0, 0x2e, 0x49, 0x63, 0x21, 0xc7, 0x3f, -0xec, 0x8e, 0x1c, 0xff, 0xfc, 0x97, 0x51, 0x7f, -0x06, 0x05, 0x2f, 0x12, 0x21, 0xae, 0xb6, 0x1e, -0xa5, 0xc7, 0x84, 0xbc, 0x2b, 0x05, 0xb4, 0x52, -0x67, 0x7d, 0xb6, 0xeb, 0x4f, 0x2d, 0x73, 0x8d, -0x79, 0x7e, 0x37, 0xa1, 0xf9, 0x91, 0x6d, 0x7c, -0x6d, 0x6a, 0xee, 0x16, 0x74, 0xaa, 0xe3, 0x27, -0x70, 0xdd, 0xb4, 0xf3, 0x9b, 0xcc, 0xad, 0xcf, -0xcf, 0x97, 0x3f, 0xef, 0x58, 0xb5, 0x4f, 0xf0, -0x7b, 0x9b, 0xf1, 0x8d, 0x78, 0xf9, 0x05, 0x89, -0x62, 0xcf, 0x6f, 0xc8, 0xb1, 0x95, 0x4c, 0xfe, -0x99, 0x97, 0xc7, 0x3f, 0x65, 0x26, 0xff, 0x90, -0xd3, 0x37, 0x41, 0x4e, 0xdf, 0x2f, 0x53, 0xd2, -0xc0, 0x9a, 0x8f, 0xe4, 0x99, 0xf9, 0x47, 0x35, -0xfb, 0x57, 0xb2, 0x2c, 0xc5, 0xde, 0x03, 0xaf, -0xe2, 0x65, 0xfa, 0xba, 0x49, 0x76, 0x4a, 0x99, -0x72, 0xf6, 0xaf, 0x75, 0x93, 0x95, 0xe9, 0x1c, -0xff, 0x5c, 0x65, 0xf0, 0x0f, 0xe6, 0x55, 0xd4, -0xa4, 0xfe, 0xaf, 0x72, 0xdd, 0x90, 0x44, 0xb6, -0xad, 0xe6, 0xf3, 0x5b, 0x8e, 0x37, 0x12, 0x60, -0xd4, 0xab, 0x4e, 0x7e, 0x0b, 0xba, 0x06, 0x1e, -0xe6, 0x6e, 0x33, 0xa6, 0x29, 0xf9, 0xf3, 0x87, -0xed, 0xfa, 0x13, 0xad, 0x1a, 0xe1, 0x49, 0xd0, -0x74, 0x1e, 0x76, 0x04, 0x60, 0xb7, 0xb8, 0x28, -0x13, 0x5b, 0x8e, 0xde, 0x72, 0xf5, 0xf7, 0x93, -0x76, 0x7e, 0xfa, 0x0d, 0xde, 0x6b, 0x92, 0xc5, -0x27, 0xd9, 0x26, 0xc2, 0x3f, 0x3f, 0xba, 0x28, -0xbc, 0xcc, 0x4e, 0xa9, 0xf9, 0xfe, 0x9e, 0x70, -0xec, 0xc7, 0x18, 0xdc, 0xf3, 0xa0, 0xc2, 0x1e, -0x64, 0xbe, 0xc4, 0xd3, 0xa7, 0xd9, 0xc6, 0x98, -0x5d, 0x1f, 0x76, 0xc9, 0x97, 0x19, 0x52, 0xb4, -0xef, 0x12, 0xf5, 0xca, 0x26, 0xfe, 0x14, 0xb3, -0x4c, 0xbb, 0x26, 0x53, 0x69, 0x96, 0xf1, 0x32, -0x47, 0x3d, 0xd7, 0xed, 0xfd, 0x1c, 0xed, 0xdc, -0x4c, 0x9b, 0x54, 0x9a, 0xef, 0x47, 0x07, 0x8b, -0x63, 0x8c, 0x97, 0x74, 0x2b, 0x30, 0xdb, 0x96, -0xe4, 0x78, 0x7f, 0x3f, 0xad, 0x5a, 0xeb, 0x13, -0xfe, 0x91, 0xc9, 0x53, 0xcc, 0xf7, 0x17, 0x07, -0x60, 0x87, 0xe2, 0x3d, 0xca, 0x0f, 0x78, 0x27, -0xdc, 0xbc, 0x94, 0xab, 0x3f, 0x1c, 0xed, 0x47, -0x41, 0x1c, 0x81, 0xf2, 0x1e, 0x88, 0x81, 0xa2, -0xad, 0x0d, 0x15, 0x9b, 0x61, 0x31, 0xfa, 0xdd, -0x81, 0x7c, 0xfe, 0xc1, 0x22, 0xed, 0xa7, 0xcd, -0x58, 0x1c, 0x20, 0xbc, 0xb1, 0x83, 0x59, 0x76, -0xf4, 0xe4, 0x00, 0xd9, 0x3f, 0x75, 0x53, 0x70, -0xf8, 0x3b, 0x6e, 0xd7, 0x9f, 0xe4, 0xbc, 0xcb, -0x32, 0xe9, 0x5f, 0x5a, 0x99, 0x4a, 0xbc, 0x9b, -0x80, 0x5f, 0x69, 0xdf, 0x73, 0xb8, 0x79, 0x19, -0x3e, 0xc9, 0xfa, 0xcb, 0x5a, 0xf1, 0xd4, 0xb2, -0xfc, 0x2c, 0x9d, 0x61, 0xeb, 0x60, 0x18, 0xaf, -0xc4, 0xa2, 0x86, 0x1a, 0xe1, 0x93, 0x19, 0xf9, -0x47, 0x33, 0xf8, 0x27, 0x98, 0x14, 0x0e, 0x22, -0x45, 0xee, 0xc2, 0xde, 0x24, 0xdf, 0x8b, 0x9e, -0x86, 0x7c, 0xfe, 0xc9, 0xe9, 0x3f, 0x29, 0x6e, -0x84, 0x7b, 0x16, 0x44, 0x10, 0xfa, 0xc2, 0x1b, -0xa1, 0x0b, 0x6d, 0xec, 0x28, 0x0d, 0x55, 0xf0, -0xae, 0x7e, 0x74, 0x21, 0x8f, 0x7f, 0x8c, 0x97, -0x94, 0x3b, 0xe9, 0xfa, 0x89, 0xeb, 0xe8, 0xfa, -0x4f, 0xcd, 0xc8, 0x3f, 0x6a, 0xb5, 0x11, 0x84, -0xb0, 0x74, 0x2d, 0x0a, 0xc7, 0xb4, 0xd4, 0x8a, -0x8e, 0xb2, 0x9e, 0xf8, 0xb5, 0xca, 0xf9, 0x2b, -0xe8, 0x3f, 0x2d, 0x37, 0x4a, 0xe3, 0x95, 0x83, -0x84, 0x0f, 0xef, 0xd1, 0xca, 0x35, 0xf6, 0xa2, -0x41, 0x8c, 0xce, 0xfe, 0x3e, 0xe1, 0xd2, 0x7f, -0x48, 0x91, 0xe9, 0x83, 0x94, 0x6c, 0x7c, 0x10, -0x63, 0xf8, 0x8a, 0xfa, 0xcf, 0x6d, 0x42, 0x27, -0xe1, 0xb7, 0x6e, 0xec, 0x1d, 0x27, 0x85, 0xf7, -0x98, 0x2b, 0x1f, 0x72, 0xfc, 0x33, 0x6e, 0xf1, -0xe1, 0xf5, 0x28, 0x06, 0xb1, 0xa4, 0xff, 0x03, -0xbe, 0xd4, 0x3b, 0xab, 0xfe, 0x93, 0xe5, 0x1f, -0x61, 0x3c, 0xdc, 0x08, 0x0f, 0x24, 0xf6, 0x25, -0xf9, 0x4d, 0xde, 0xd1, 0x9c, 0xfe, 0x93, 0x35, -0x2e, 0x4f, 0xe3, 0x1f, 0x02, 0x39, 0x20, 0xc9, -0x6c, 0xa7, 0x77, 0x48, 0x6e, 0xd0, 0x02, 0x4a, -0xbe, 0xfe, 0x53, 0x12, 0x72, 0xea, 0x3f, 0x06, -0xff, 0xb4, 0x80, 0xd4, 0x5e, 0x79, 0x12, 0xbe, -0x92, 0xbf, 0xd5, 0x29, 0xfd, 0xa1, 0x00, 0x3f, -0xbb, 0xf8, 0x27, 0x42, 0x82, 0xa0, 0xc0, 0x93, -0x50, 0xa7, 0xf5, 0x60, 0xd2, 0x94, 0xf2, 0xe2, -0xbf, 0xc6, 0xc5, 0x3f, 0x43, 0xc2, 0x16, 0x4f, -0x0d, 0x3c, 0x00, 0xfb, 0x34, 0x3e, 0x8a, 0x12, -0x6e, 0xfd, 0xc7, 0x8e, 0x3f, 0x36, 0xf9, 0x27, -0x2a, 0xac, 0x8f, 0xcd, 0xe1, 0x7f, 0x8e, 0x95, -0x8f, 0x78, 0x3f, 0xba, 0x5b, 0x7e, 0x3c, 0x5f, -0xff, 0xb1, 0xe3, 0x9f, 0xe5, 0x9f, 0xbf, 0x16, -0xe4, 0x0a, 0x0f, 0xc4, 0x38, 0x25, 0xed, 0xaf, -0x8f, 0x1d, 0x53, 0x66, 0xd3, 0x7f, 0xfa, 0x4d, -0xc8, 0x89, 0xb2, 0x8d, 0xf2, 0xc7, 0x5b, 0xea, -0x70, 0x60, 0x4c, 0xf8, 0x4f, 0xfc, 0xe1, 0xcc, -0xfa, 0x0f, 0xd8, 0x4d, 0xe7, 0x74, 0x78, 0x52, -0x6d, 0xae, 0x20, 0xc6, 0x3e, 0xee, 0x8a, 0xfc, -0xa3, 0x49, 0x7b, 0xe3, 0x0b, 0xe1, 0x78, 0xc7, -0x40, 0xab, 0xf8, 0x0d, 0x02, 0xb9, 0x57, 0xd4, -0x7f, 0x56, 0x0b, 0xbd, 0xe1, 0x05, 0xd0, 0xa1, -0x79, 0x27, 0x3d, 0x89, 0x8a, 0x6f, 0x1a, 0xfa, -0x4f, 0xf9, 0x6c, 0xfc, 0x43, 0x06, 0x3d, 0x9c, -0xba, 0xbd, 0xd6, 0x4b, 0xfa, 0xbb, 0xa7, 0x0f, -0xe7, 0xe9, 0x15, 0x15, 0x0e, 0xfe, 0xe1, 0x0c, -0xfe, 0x89, 0x0a, 0x35, 0xa8, 0x08, 0x3a, 0x40, -0x21, 0xd8, 0x53, 0xde, 0x09, 0x33, 0xf3, 0x4f, -0x43, 0x99, 0xcd, 0x3f, 0xa4, 0xa4, 0x33, 0x75, -0x54, 0x08, 0x4a, 0x4e, 0xd7, 0x1f, 0x4a, 0x30, -0xfb, 0x26, 0x63, 0xeb, 0x3f, 0xf3, 0xb2, 0xfe, -0xde, 0xc2, 0x5e, 0x44, 0xcf, 0x43, 0x73, 0xbb, -0xf4, 0xb6, 0x70, 0x8b, 0xe1, 0x66, 0xb9, 0x93, -0x67, 0xb8, 0x1c, 0x6f, 0x18, 0xfc, 0xa3, 0x49, -0xe9, 0xb8, 0x0f, 0x8e, 0x41, 0x5d, 0x44, 0x4c, -0xb3, 0xf5, 0x6e, 0xfd, 0xc7, 0xc1, 0x3f, 0x59, -0xc8, 0x49, 0x22, 0x1e, 0x4e, 0x92, 0x54, 0xe3, -0xef, 0x27, 0xdd, 0x76, 0x66, 0xfe, 0x89, 0x14, -0xd9, 0x4e, 0xb5, 0xd6, 0x6e, 0x47, 0x4a, 0xbb, -0x47, 0x0e, 0x73, 0x90, 0xcf, 0x3f, 0xa3, 0x39, -0xfe, 0xa9, 0xee, 0xb3, 0x82, 0xdc, 0xba, 0xfa, -0xa7, 0xb2, 0x57, 0xf5, 0x3c, 0x8c, 0xfe, 0x7b, -0x76, 0xfd, 0x87, 0x6e, 0xf2, 0x87, 0x52, 0x42, -0xf8, 0x01, 0x3a, 0x7e, 0xa6, 0x4e, 0x5d, 0x94, -0x60, 0x1d, 0x9f, 0xef, 0x8b, 0xf9, 0xfc, 0x33, -0xce, 0xf4, 0x71, 0x97, 0xe8, 0x79, 0xf9, 0x06, -0x7b, 0x10, 0x2e, 0xc5, 0x8e, 0xa8, 0x65, 0x35, -0x39, 0x37, 0x0b, 0xe8, 0x3f, 0x7e, 0xd9, 0xe2, -0x9f, 0x78, 0x2d, 0x9c, 0xe4, 0xe7, 0x90, 0xf8, -0xb3, 0x8a, 0x72, 0x45, 0xfd, 0x67, 0x0f, 0xc1, -0xf8, 0x45, 0xe4, 0x7c, 0x79, 0x71, 0x38, 0x59, -0xb9, 0xd5, 0x92, 0x7d, 0x0a, 0xe9, 0x3f, 0xd9, -0xf7, 0x2f, 0x81, 0x41, 0x25, 0xc3, 0x0f, 0x81, -0x6f, 0x12, 0x42, 0xc5, 0xa5, 0xae, 0xfa, 0x93, -0xd3, 0x7f, 0x92, 0x26, 0xff, 0xa8, 0x64, 0xf0, -0x1a, 0xe6, 0x27, 0xbc, 0x82, 0x3c, 0xa1, 0xe2, -0x5b, 0x99, 0x99, 0xf5, 0x9f, 0x7e, 0x7e, 0x3e, -0x81, 0x1c, 0x42, 0x3b, 0x11, 0x61, 0x0e, 0xfc, -0x1a, 0x2f, 0xf7, 0x8a, 0xeb, 0xd9, 0x0a, 0x4b, -0xf6, 0x29, 0xa4, 0xff, 0xcc, 0x33, 0xea, 0xad, -0x4a, 0xaa, 0xc7, 0xd9, 0xe2, 0xa7, 0x4c, 0x63, -0x0c, 0xde, 0x9b, 0x45, 0xff, 0xa1, 0x4d, 0x6a, -0x55, 0x5f, 0xf9, 0xf8, 0x9a, 0x6f, 0xc1, 0xb1, -0x7d, 0xcb, 0xa2, 0x81, 0x49, 0xb6, 0x19, 0xa6, -0xf2, 0xfa, 0x97, 0xe6, 0xe4, 0x1f, 0xba, 0xc9, -0x39, 0xfc, 0x86, 0xf0, 0x55, 0xf8, 0x7e, 0xe5, -0x3a, 0xd5, 0x00, 0x9b, 0x99, 0xf9, 0x07, 0x4c, -0xfe, 0x39, 0xfa, 0x5d, 0x0d, 0xd5, 0x54, 0xdd, -0xdf, 0x74, 0x1b, 0xe6, 0x6f, 0x41, 0x55, 0xae, -0xf9, 0x0e, 0xfd, 0xc7, 0xac, 0x3f, 0x54, 0x6f, -0xf4, 0x40, 0x07, 0xf6, 0x03, 0xdf, 0x40, 0x0e, -0x5a, 0x7e, 0x3c, 0x53, 0x0e, 0xfd, 0xc7, 0xec, -0x2f, 0xe4, 0x74, 0x5f, 0xef, 0x3d, 0x9e, 0xa8, -0x6b, 0x0f, 0x0c, 0x74, 0xd7, 0xba, 0x78, 0xe6, -0x7c, 0x4e, 0xff, 0x31, 0xf9, 0x07, 0x49, 0x49, -0xe1, 0x03, 0xb8, 0xa4, 0x12, 0x83, 0xa6, 0x8d, -0x5b, 0xff, 0xb1, 0xd6, 0x67, 0xe4, 0xcb, 0xa6, -0x9e, 0xaf, 0xb1, 0x17, 0x94, 0x11, 0xa6, 0x1e, -0x44, 0x99, 0x0d, 0x29, 0x33, 0xeb, 0x3f, 0x18, -0x0c, 0xfe, 0x89, 0xde, 0xd4, 0xf7, 0x4a, 0x12, -0x25, 0x87, 0xbc, 0xbc, 0x3f, 0x81, 0x16, 0x16, -0xe0, 0x19, 0x07, 0xff, 0x30, 0x74, 0x3e, 0x19, -0x4c, 0xe1, 0xed, 0x38, 0x78, 0x13, 0xff, 0x4c, -0x85, 0xb7, 0xf6, 0x4a, 0xfc, 0x13, 0x80, 0x52, -0x85, 0x04, 0xad, 0x1f, 0xfc, 0x54, 0x88, 0xe6, -0xae, 0xa0, 0xff, 0x18, 0xf9, 0x80, 0x49, 0xb7, -0x4a, 0x31, 0xcd, 0x10, 0xa0, 0xe7, 0x2b, 0xdf, -0xdf, 0x9c, 0xfe, 0x43, 0xf8, 0xc7, 0xf0, 0xb7, -0x2c, 0xca, 0x1e, 0x21, 0xfd, 0xfd, 0x05, 0x58, -0x92, 0x26, 0xfd, 0xdd, 0x75, 0xbf, 0x83, 0x6c, -0xde, 0xb8, 0xea, 0x2b, 0x94, 0xbd, 0xed, 0xda, -0x0d, 0x13, 0x78, 0x99, 0xd2, 0x33, 0xc2, 0x36, -0xe1, 0x4f, 0xf0, 0xaa, 0x94, 0x78, 0x31, 0x97, -0x48, 0x19, 0xbb, 0x3e, 0x60, 0xf8, 0xd8, 0xa2, -0x9d, 0x0d, 0xd0, 0x85, 0x57, 0x28, 0x04, 0xdb, -0x5a, 0x54, 0x32, 0x92, 0x21, 0x85, 0x28, 0x68, -0xeb, 0x3f, 0xf6, 0x79, 0xe4, 0x8b, 0x46, 0x20, -0x0e, 0x7e, 0xea, 0x14, 0x86, 0x43, 0xb0, 0x08, -0x78, 0x44, 0x5e, 0x34, 0x08, 0xff, 0xa4, 0xf9, -0x43, 0x48, 0xcc, 0xf9, 0x6b, 0xc5, 0x9f, 0xf2, -0x4f, 0x56, 0x2d, 0xd9, 0xc0, 0x3f, 0x8a, 0xef, -0xf4, 0xee, 0x48, 0x90, 0x68, 0xd1, 0x11, 0xff, -0x2e, 0x14, 0x28, 0xc0, 0x3f, 0xa4, 0xff, 0x66, -0xd5, 0x86, 0x03, 0x90, 0xc1, 0x0d, 0xb5, 0xe2, -0xcf, 0x4a, 0x03, 0x70, 0x1e, 0xdd, 0xa3, 0x89, -0x8f, 0x0a, 0x01, 0x37, 0xff, 0xe8, 0x26, 0xff, -0xd0, 0x20, 0x64, 0x48, 0x2a, 0xad, 0x84, 0x5c, -0x58, 0x26, 0x0b, 0xea, 0x3f, 0x70, 0xd0, 0x3a, -0x7d, 0xfb, 0xd4, 0x13, 0x77, 0xd5, 0x55, 0x49, -0x7d, 0xac, 0xb9, 0xac, 0x98, 0x10, 0x82, 0xd6, -0x3f, 0xed, 0xd0, 0x7f, 0x8a, 0x44, 0x35, 0xbb, -0x49, 0x0d, 0x76, 0x84, 0xe7, 0x28, 0x6b, 0x07, -0xd0, 0xcf, 0xf0, 0x61, 0x58, 0x32, 0x5a, 0x13, -0xf2, 0x04, 0x2c, 0xd7, 0x72, 0xfc, 0xa3, 0x17, -0x7d, 0xc7, 0x0a, 0x42, 0x4c, 0xc1, 0x9a, 0x2f, -0xba, 0x36, 0x89, 0xa4, 0xc0, 0x43, 0x4c, 0x60, -0x92, 0x24, 0x86, 0x88, 0xe2, 0xf9, 0xfc, 0x13, -0x35, 0xf9, 0x87, 0x36, 0xfd, 0x51, 0xb5, 0x13, -0x2f, 0x20, 0x86, 0xd7, 0xbc, 0x21, 0xf2, 0xff, -0x3d, 0x7a, 0xcc, 0x12, 0x46, 0x1c, 0xfa, 0x0f, -0x88, 0x16, 0xed, 0x60, 0xd0, 0xd4, 0xfa, 0x56, -0xa9, 0x9e, 0x35, 0x47, 0xf8, 0x5d, 0x82, 0x08, -0xaf, 0x64, 0xf5, 0x9f, 0x69, 0xfc, 0x73, 0x5f, -0x36, 0x3e, 0x1e, 0xaa, 0xff, 0xec, 0xb4, 0xe3, -0xf3, 0x3f, 0xec, 0xad, 0x33, 0xf2, 0x8f, 0x01, -0xe1, 0x48, 0x67, 0x56, 0xa8, 0x3b, 0x07, 0xd8, -0x8f, 0x92, 0xaf, 0x13, 0x02, 0x37, 0x88, 0x7d, -0x26, 0xfd, 0x87, 0x16, 0x8d, 0x93, 0x70, 0x3f, -0xaa, 0x55, 0x89, 0xf1, 0x7f, 0x98, 0xf0, 0x8f, -0xee, 0x2c, 0x44, 0x2e, 0xfd, 0xc7, 0xa4, 0x9d, -0xa7, 0xf1, 0x82, 0x28, 0x31, 0xde, 0x34, 0xdc, -0x24, 0x85, 0xc5, 0x0e, 0x85, 0x4b, 0xff, 0x31, -0x8a, 0xb6, 0x12, 0x8b, 0x24, 0xff, 0x20, 0xac, -0x40, 0x23, 0x46, 0x18, 0xf9, 0x7a, 0x8f, 0x38, -0x0b, 0xff, 0x24, 0xd9, 0x4b, 0xf8, 0x5c, 0x74, -0xe5, 0x11, 0xe9, 0x1c, 0xc1, 0x9e, 0x13, 0xd0, -0x84, 0xc5, 0x71, 0xc1, 0x5f, 0x88, 0x7f, 0xf2, -0x6e, 0x1f, 0x76, 0x62, 0xf6, 0xa8, 0xd1, 0xa1, -0x96, 0x74, 0xc4, 0x67, 0xe6, 0x1f, 0xda, 0xd4, -0xce, 0xc2, 0xf1, 0x64, 0x5d, 0x54, 0x4a, 0x20, -0x1f, 0x7c, 0x00, 0xcd, 0xad, 0x62, 0x15, 0xbb, -0x10, 0xcf, 0xc4, 0x3f, 0xb4, 0xc9, 0x0e, 0x2b, -0x4f, 0x84, 0x57, 0xb4, 0x0a, 0xb4, 0xfe, 0x6c, -0x27, 0x15, 0x86, 0x4f, 0x78, 0x17, 0xce, 0xc6, -0x3f, 0x59, 0xbd, 0x91, 0x74, 0xf3, 0x3e, 0xfc, -0x04, 0x15, 0x5a, 0xe9, 0x3f, 0xe4, 0xd6, 0x7f, -0xb8, 0x5c, 0xf7, 0x17, 0x0f, 0x80, 0x4f, 0x15, -0xaa, 0x2a, 0x44, 0x02, 0x42, 0xa4, 0x62, 0x57, -0x79, 0xb8, 0x42, 0xfc, 0xb3, 0x29, 0xe7, 0xaf, -0x79, 0xff, 0x45, 0xf8, 0x67, 0x9c, 0x84, 0x25, -0x40, 0x1a, 0x71, 0x81, 0xfb, 0xaf, 0xbf, 0xb0, -0xfd, 0x7d, 0xdb, 0xd0, 0x7f, 0xa4, 0x34, 0x71, -0xfc, 0x92, 0x01, 0x42, 0x0e, 0xfe, 0x71, 0xdc, -0x7f, 0x5d, 0x84, 0x77, 0xac, 0xf9, 0x6f, 0xc0, -0xd5, 0x86, 0x81, 0x8f, 0x43, 0x4b, 0x54, 0x7a, -0x9f, 0xad, 0x47, 0xc7, 0x0b, 0xf0, 0x0f, 0xd7, -0x65, 0x42, 0xce, 0xb8, 0xc1, 0x3f, 0x42, 0x0c, -0xe9, 0xc8, 0x18, 0xe1, 0x91, 0x02, 0x5d, 0xf9, -0xfc, 0xc3, 0x13, 0xfe, 0xd9, 0x65, 0xd1, 0xce, -0x76, 0xc6, 0xa7, 0xce, 0x95, 0x63, 0xc7, 0xa8, -0xbf, 0xed, 0x42, 0x15, 0x29, 0xbc, 0x1d, 0x2e, -0xfd, 0x87, 0xf0, 0xcf, 0x76, 0x8b, 0x76, 0x1e, -0x01, 0xef, 0x8d, 0xc2, 0xc3, 0x46, 0x60, 0x83, -0x74, 0x9a, 0xcf, 0x7a, 0xe4, 0xe4, 0x9f, 0x61, -0x6b, 0xff, 0xc7, 0xe0, 0x68, 0x64, 0x85, 0x89, -0x31, 0xc6, 0xb6, 0x1f, 0x16, 0x7c, 0x70, 0xdc, -0xa5, 0xff, 0x30, 0x7d, 0x0e, 0xda, 0xe9, 0xa5, -0xf7, 0x65, 0xec, 0x70, 0x76, 0x44, 0x28, 0xa4, -0xff, 0xc8, 0x36, 0x6d, 0x9e, 0x96, 0x53, 0xd0, -0x08, 0x7f, 0x49, 0xef, 0x97, 0x53, 0xc6, 0x8d, -0x64, 0x2e, 0xfe, 0x4e, 0xfe, 0x69, 0x50, 0xb2, -0x90, 0x33, 0xc9, 0x3d, 0xa8, 0x53, 0xfd, 0xc7, -0xd3, 0x80, 0x76, 0xc0, 0x92, 0x1e, 0x0f, 0x25, -0xc6, 0x0f, 0xdd, 0xfc, 0xf3, 0x57, 0x4a, 0xf6, -0x50, 0xbc, 0x11, 0x8d, 0x0f, 0x19, 0x85, 0x5a, -0xa4, 0xdf, 0x4f, 0xd0, 0xc9, 0x5f, 0x13, 0x67, -0xe4, 0x1f, 0x7a, 0x48, 0xd3, 0x68, 0x27, 0x57, -0xab, 0x91, 0xd3, 0x57, 0x45, 0xde, 0x5f, 0xc8, -0xfc, 0x1f, 0xa3, 0x79, 0x96, 0x90, 0x9b, 0xcf, -0x3f, 0x06, 0xe4, 0x8c, 0xc2, 0x6b, 0xf8, 0x86, -0xa8, 0x70, 0x89, 0x9d, 0x0f, 0xaf, 0x75, 0xac, -0x4a, 0x06, 0xd6, 0x0b, 0xf3, 0x0b, 0xf1, 0x4f, -0x7f, 0xae, 0x89, 0xff, 0x91, 0x23, 0xc6, 0x33, -0x66, 0x7f, 0xc7, 0x65, 0x7b, 0x0a, 0xf2, 0x4f, -0xf5, 0x17, 0xc6, 0xb7, 0x35, 0xc8, 0xb2, 0x17, -0xc8, 0x6b, 0xfb, 0x52, 0xbd, 0x6d, 0x2b, 0x6d, -0x5b, 0xf4, 0xfe, 0xeb, 0xfd, 0x5c, 0xff, 0x72, -0xf2, 0x4f, 0xaf, 0xfa, 0x1b, 0xb2, 0xc9, 0x72, -0xb2, 0x7f, 0x52, 0x76, 0x96, 0x6b, 0x9e, 0x2d, -0x16, 0xcf, 0xdc, 0x1c, 0xab, 0x2a, 0xc4, 0x3f, -0xbd, 0xd9, 0xb7, 0xb3, 0x8a, 0x0c, 0x3c, 0x2e, -0xd7, 0x86, 0xf9, 0x0c, 0x2d, 0x53, 0xdc, 0x62, -0x5c, 0xba, 0x35, 0x57, 0xaf, 0x9c, 0xfc, 0x93, -0x82, 0x87, 0x4c, 0x35, 0xe3, 0x28, 0xc4, 0xa3, -0xbe, 0x34, 0x09, 0x63, 0xb6, 0xbf, 0xd7, 0xe7, -0x1a, 0xbd, 0x83, 0x7f, 0x8a, 0xfa, 0xad, 0x26, -0xa2, 0xc3, 0x7e, 0xb5, 0x4e, 0x17, 0x3f, 0x5b, -0x9b, 0x2d, 0x9b, 0x83, 0xb9, 0xfe, 0xe5, 0xb8, -0xff, 0x22, 0xb5, 0xc3, 0x1c, 0xbc, 0xf6, 0xb4, -0xf2, 0xa5, 0xfa, 0x1f, 0x61, 0x69, 0x20, 0x3e, -0x9e, 0x1d, 0x89, 0x17, 0xe2, 0x1f, 0x92, 0x22, -0x9f, 0x58, 0xfd, 0xee, 0x2d, 0x58, 0x16, 0x25, -0x46, 0x3d, 0x2d, 0xe3, 0x03, 0x65, 0xed, 0x6c, -0x33, 0x9e, 0x82, 0xab, 0xa7, 0xf3, 0x4f, 0x07, -0xf7, 0xed, 0x70, 0xb6, 0x49, 0xbd, 0xc2, 0x75, -0x6b, 0xde, 0x8d, 0x02, 0xbd, 0x38, 0x36, 0x14, -0x89, 0x44, 0xae, 0xff, 0xea, 0x0e, 0xfd, 0x47, -0x51, 0xb2, 0xea, 0xc4, 0x19, 0xa5, 0x7b, 0xbb, -0x97, 0x1a, 0x4f, 0xd3, 0x69, 0x6a, 0x76, 0xfe, -0xc2, 0x7c, 0xfe, 0x01, 0x43, 0xfd, 0x98, 0x1b, -0x22, 0x41, 0xa3, 0xef, 0x5f, 0xa4, 0x3f, 0x76, -0x19, 0xc4, 0x28, 0xc8, 0xdf, 0xe6, 0x0a, 0xf0, -0x8f, 0x18, 0x95, 0xcf, 0x5b, 0x4e, 0xbd, 0x0e, -0x87, 0xd4, 0x75, 0x99, 0x35, 0x49, 0xea, 0x26, -0x94, 0x6d, 0x31, 0xfa, 0xcb, 0x8a, 0x3c, 0xfe, -0xf9, 0x4e, 0xc2, 0x52, 0x33, 0xd2, 0x9e, 0xcf, -0x09, 0x9a, 0x10, 0x63, 0x8b, 0x9b, 0x7f, 0xdc, -0xf7, 0x5f, 0x93, 0xec, 0xbd, 0x70, 0x39, 0xb6, -0x4c, 0x27, 0xa0, 0x78, 0xaf, 0x8b, 0x9f, 0xf3, -0xef, 0xbf, 0x82, 0xa7, 0x09, 0xe4, 0x04, 0x61, -0x10, 0x7b, 0xe9, 0xf7, 0x7f, 0x6c, 0xec, 0xc9, -0xdd, 0x7f, 0x39, 0xea, 0x8f, 0xdd, 0x8f, 0xda, -0x60, 0x10, 0x91, 0xf3, 0x05, 0xa8, 0xad, 0x00, -0xef, 0xe5, 0xe9, 0x3f, 0x24, 0x68, 0xc5, 0x01, -0x18, 0x1c, 0x5e, 0xa4, 0x91, 0xf5, 0x03, 0x2e, -0xfe, 0x74, 0xdc, 0x7f, 0x55, 0x67, 0x3f, 0xf4, -0xd0, 0xd5, 0x9b, 0xe5, 0x0c, 0x6e, 0xd4, 0xa4, -0xbe, 0x92, 0xcd, 0xd3, 0xf9, 0x50, 0x28, 0x70, -0xff, 0x65, 0x44, 0x83, 0xa0, 0xf1, 0x0b, 0x9a, -0x84, 0x4b, 0x2e, 0xcf, 0x7e, 0xff, 0x45, 0x16, -0x69, 0xa4, 0xc7, 0x70, 0x02, 0xc6, 0x55, 0x62, -0x3c, 0x97, 0x4b, 0x4b, 0x3b, 0xdf, 0x1c, 0xfc, -0xc3, 0x99, 0xbb, 0x5d, 0xfb, 0x32, 0x9a, 0xa8, -0x1a, 0xd4, 0x48, 0x3e, 0xcc, 0x29, 0xb0, 0x7f, -0x27, 0xff, 0xd0, 0x68, 0x90, 0xb0, 0x34, 0x91, -0x68, 0x24, 0x65, 0x5e, 0x13, 0x50, 0xb6, 0xec, -0x14, 0xbe, 0xff, 0x72, 0xf0, 0xcf, 0x29, 0xe6, -0xf9, 0x74, 0xad, 0xde, 0x1d, 0xc9, 0x61, 0x80, -0xad, 0x87, 0x9c, 0xcc, 0xd3, 0x7f, 0x1a, 0x4c, -0xb5, 0x47, 0xa7, 0x86, 0x8f, 0x15, 0xf3, 0xbe, -0xff, 0x53, 0x40, 0xff, 0xd1, 0x0c, 0xec, 0xf9, -0x94, 0x46, 0xe3, 0x34, 0xeb, 0x8e, 0x4f, 0x41, -0xfe, 0x99, 0x80, 0x0c, 0xcd, 0x46, 0xcc, 0xba, -0xe3, 0x53, 0x90, 0x7f, 0xe8, 0xdb, 0x13, 0xfd, -0xfe, 0x0f, 0xda, 0xeb, 0x7a, 0x9f, 0x2a, 0xc4, -0x3f, 0xc5, 0xa7, 0xe0, 0x17, 0xda, 0x02, 0xdd, -0x53, 0x53, 0xc0, 0xdf, 0x82, 0xfc, 0x33, 0xc2, -0x3f, 0x8b, 0x15, 0x4d, 0x08, 0xc4, 0x7a, 0x5c, -0xf9, 0x56, 0x90, 0x7f, 0xc6, 0xe1, 0x33, 0x7c, -0x37, 0x2e, 0x1f, 0x43, 0xfe, 0xdc, 0xc8, 0xcc, -0xfa, 0x4f, 0xa7, 0xf5, 0xf6, 0xdd, 0xc1, 0xba, -0xbf, 0x0f, 0xe3, 0xe6, 0x1f, 0xa6, 0x97, 0xf6, -0x3b, 0x8d, 0xf4, 0x47, 0xf9, 0xfa, 0xd9, 0xf5, -0x9f, 0xac, 0xc8, 0xb0, 0xcb, 0x50, 0x1b, 0xbc, -0x6a, 0xb7, 0x03, 0x63, 0x0a, 0xe9, 0x3f, 0x9c, -0xf9, 0xb4, 0xd4, 0x78, 0xca, 0x2f, 0xa4, 0x7f, -0xd1, 0xc7, 0xcc, 0xfc, 0xfd, 0x1f, 0x3e, 0xfb, -0xfd, 0x1f, 0x52, 0x7f, 0xa8, 0xfa, 0x01, 0xaa, -0x50, 0xe3, 0x71, 0xeb, 0x21, 0x0e, 0xfe, 0x29, -0x35, 0xf5, 0x9f, 0x32, 0xd3, 0xbb, 0x15, 0xcc, -0x4e, 0x2c, 0x28, 0x2e, 0x7f, 0x3f, 0xce, 0xf1, -0x4f, 0xb5, 0x43, 0xcd, 0x78, 0x99, 0x18, 0x3b, -0xdf, 0x2e, 0xa0, 0x6f, 0x38, 0xf9, 0x27, 0xcb, -0x03, 0x69, 0x96, 0xde, 0x7f, 0x11, 0x63, 0x34, -0xee, 0x73, 0xeb, 0x45, 0x6e, 0xfd, 0xc7, 0x50, -0x7b, 0x48, 0xe9, 0x11, 0x3a, 0x67, 0xd5, 0x7f, -0x80, 0x1b, 0x76, 0x79, 0xd7, 0x5a, 0x40, 0xef, -0x2a, 0xa0, 0xff, 0x64, 0xa3, 0xb7, 0x7b, 0xd6, -0xef, 0xff, 0xec, 0xaf, 0xea, 0x9b, 0xee, 0xdd, -0xba, 0x3d, 0xdd, 0x1b, 0x0d, 0xd9, 0xc7, 0xb1, -0x7f, 0xe4, 0xba, 0xff, 0xca, 0xce, 0xef, 0x27, -0x86, 0xcc, 0xf6, 0xb9, 0xe2, 0x53, 0x90, 0x7f, -0x68, 0xb4, 0x1b, 0x41, 0x8a, 0xb3, 0x49, 0x57, -0xfc, 0xf3, 0xef, 0xbf, 0x48, 0xb7, 0xd2, 0x09, -0x84, 0x3c, 0xa6, 0x12, 0xfe, 0x19, 0x47, 0xfe, -0x2b, 0xeb, 0x3f, 0x9a, 0xf0, 0xff, 0xec, 0x5d, -0x6f, 0x70, 0x1c, 0x45, 0x76, 0xef, 0x9d, 0x1d, -0xcb, 0x63, 0x69, 0xa5, 0x1d, 0xdb, 0x12, 0x25, -0x62, 0xe3, 0x5b, 0xaf, 0x05, 0xa7, 0xa3, 0xd6, -0x6b, 0x59, 0x0a, 0x3e, 0xfe, 0x08, 0x69, 0x2c, -0xa8, 0x94, 0x8c, 0x55, 0xe5, 0x2d, 0xc2, 0x07, -0x92, 0xa2, 0xa8, 0x2d, 0xca, 0x1f, 0x9c, 0x2a, -0x1d, 0x51, 0x25, 0xf9, 0xe0, 0xba, 0x23, 0x66, -0x2c, 0x0b, 0x22, 0x63, 0x5d, 0xd0, 0x01, 0x97, -0x38, 0x09, 0xa1, 0xd6, 0x2e, 0x7f, 0x30, 0x57, -0xae, 0x8a, 0x64, 0x63, 0x63, 0xd9, 0x17, 0xdd, -0x58, 0x08, 0x4e, 0x18, 0x63, 0x94, 0x40, 0x11, -0x03, 0x2e, 0x6e, 0x21, 0x22, 0x27, 0x40, 0xe7, -0x08, 0x63, 0x1b, 0xdb, 0xc8, 0x76, 0xba, 0x7b, -0xa6, 0xbb, 0x5f, 0xcf, 0xf4, 0xec, 0x8e, 0x8f, -0x4a, 0x8a, 0xaa, 0xa0, 0x4f, 0xaf, 0x76, 0xbb, -0xd6, 0xd3, 0xcf, 0x33, 0xef, 0xfd, 0xe6, 0xf7, -0x7e, 0xef, 0x75, 0x0a, 0x3f, 0x1d, 0x43, 0x0e, -0x0e, 0x44, 0x4b, 0xb5, 0xe0, 0xf3, 0x72, 0xdc, -0x5f, 0xff, 0x72, 0xfe, 0x89, 0x3c, 0xad, 0x3f, -0x77, 0xf0, 0xf3, 0xeb, 0x28, 0xf8, 0x93, 0x69, -0x58, 0xff, 0x72, 0x41, 0x4e, 0x67, 0xfc, 0x43, -0xfd, 0xbc, 0x7d, 0x07, 0x36, 0x16, 0xbf, 0x60, -0x96, 0xe5, 0x7f, 0xdc, 0xfa, 0xd7, 0x8d, 0x31, -0x6c, 0x20, 0x95, 0xfe, 0x47, 0x63, 0xfe, 0xb1, -0xe6, 0x5d, 0xb5, 0x68, 0x92, 0xda, 0x14, 0x6b, -0xb3, 0xae, 0xd8, 0x3f, 0x9c, 0x4a, 0x9e, 0x52, -0xf0, 0x3f, 0x93, 0xb5, 0x3e, 0xfe, 0x87, 0x5c, -0xe4, 0x52, 0x74, 0x90, 0xc4, 0x9f, 0xfc, 0xb6, -0x87, 0x4a, 0xd4, 0xbf, 0x6c, 0xf4, 0xbc, 0x49, -0x3f, 0xb4, 0xb4, 0xa5, 0xb1, 0x83, 0xe8, 0x66, -0x67, 0xc9, 0x03, 0x8a, 0x78, 0x25, 0xd5, 0xbf, -0x3c, 0x7f, 0x56, 0x24, 0xd0, 0xb0, 0x91, 0x72, -0x96, 0xd4, 0x0b, 0x37, 0x72, 0xe3, 0x3d, 0x5f, -0xfd, 0x8b, 0xee, 0x37, 0x83, 0x2e, 0xd9, 0x38, -0x7e, 0xf6, 0xc5, 0xf7, 0x05, 0xf4, 0x2d, 0xc7, -0x01, 0x1f, 0xee, 0x39, 0x61, 0x0f, 0xfe, 0xf6, -0x52, 0x0e, 0x1b, 0x83, 0x55, 0xdd, 0x01, 0xff, -0x4c, 0xf9, 0xf9, 0x1f, 0x22, 0xe3, 0x9c, 0x23, -0xef, 0x23, 0xc4, 0x9f, 0xad, 0x81, 0x78, 0x2e, -0xf0, 0xd2, 0x31, 0xbd, 0xdb, 0x4d, 0x52, 0x7b, -0x7a, 0x67, 0xf4, 0x11, 0x1b, 0x27, 0xb2, 0x81, -0xa7, 0x82, 0xf9, 0x0b, 0xd4, 0xbf, 0xbc, 0x7c, -0x87, 0x6f, 0xaa, 0x19, 0x34, 0xd2, 0x8f, 0x8d, -0xbd, 0x8a, 0x7c, 0x17, 0xe0, 0x7f, 0xdc, 0xfb, -0x0d, 0x1b, 0xc7, 0x28, 0xde, 0x2e, 0xc1, 0xff, -0x18, 0x5e, 0x36, 0x19, 0x24, 0xfb, 0xd5, 0xa8, -0x91, 0x09, 0xd4, 0x43, 0x8b, 0x7e, 0xfe, 0xc7, -0x49, 0x16, 0xe3, 0x73, 0xc6, 0x79, 0xb6, 0xf1, -0x48, 0xf8, 0xe7, 0x2a, 0xc2, 0xf7, 0x4f, 0x11, -0x7f, 0xcb, 0xef, 0x9f, 0xb9, 0xd4, 0x5b, 0x21, -0xf5, 0x2f, 0x02, 0x72, 0x66, 0xec, 0x11, 0x82, -0x7f, 0xae, 0x70, 0xfc, 0xb3, 0xe8, 0x4d, 0xed, -0x0d, 0xaf, 0xfe, 0x55, 0xc1, 0xeb, 0x5f, 0xf3, -0xba, 0x0c, 0xb6, 0x3b, 0xfc, 0xa2, 0xd1, 0xe0, -0xc0, 0xfd, 0x8e, 0xef, 0x7e, 0x36, 0xa4, 0xfe, -0xe5, 0x7a, 0x0f, 0xff, 0xbe, 0x43, 0x85, 0x40, -0xde, 0x27, 0x53, 0x69, 0x0f, 0x9a, 0xce, 0x0a, -0x7c, 0x52, 0x07, 0xf3, 0xaf, 0x4d, 0xd1, 0x60, -0x26, 0xc6, 0xdc, 0x62, 0x7d, 0x10, 0x52, 0xff, -0x92, 0xbc, 0xc1, 0x8d, 0x0b, 0x5a, 0x98, 0xfe, -0xd9, 0xa9, 0xe1, 0xde, 0x6e, 0xda, 0x26, 0xf2, -0x7b, 0xca, 0x83, 0xee, 0x5f, 0x48, 0xf5, 0xaf, -0xcf, 0xf9, 0xff, 0xbe, 0x99, 0x75, 0x76, 0xcc, -0x8a, 0xeb, 0x3f, 0xc3, 0xf8, 0x9f, 0x0b, 0x81, -0xfa, 0x97, 0x8b, 0x76, 0x2c, 0xec, 0x8d, 0xdb, -0x84, 0x7f, 0x3e, 0x61, 0xfc, 0xcf, 0x2c, 0xcf, -0x77, 0xa4, 0xfe, 0x25, 0x57, 0x7f, 0x00, 0x0d, -0xf2, 0x2e, 0xe3, 0x7f, 0xe6, 0xb8, 0xfe, 0x73, -0x9d, 0x91, 0xb0, 0xbe, 0x74, 0xd5, 0x3e, 0x04, -0xed, 0x2c, 0x25, 0x68, 0x87, 0xe1, 0x9f, 0x7b, -0xc6, 0x53, 0x9c, 0xff, 0x61, 0xeb, 0xad, 0x1b, -0x81, 0x7f, 0x08, 0x90, 0x7e, 0xfa, 0xfc, 0x0e, -0xee, 0x1f, 0x4e, 0x24, 0x4e, 0xf2, 0xf8, 0xf0, -0x0b, 0x88, 0x7f, 0x2e, 0xa3, 0xe6, 0x63, 0xc9, -0xfd, 0xf1, 0x19, 0x71, 0x7f, 0x7a, 0xfe, 0x19, -0x13, 0xf8, 0xe7, 0x67, 0x52, 0xb4, 0x3c, 0x28, -0x85, 0x91, 0xd3, 0xf8, 0x55, 0xeb, 0x0e, 0x8a, -0x7f, 0x38, 0xbe, 0xb2, 0xad, 0x17, 0x0c, 0x80, -0x76, 0x96, 0x17, 0xab, 0x7e, 0x5c, 0xc1, 0x61, -0xcf, 0x49, 0xcd, 0xdb, 0xef, 0x84, 0x0a, 0xff, -0xcc, 0xa0, 0x03, 0x76, 0x83, 0x78, 0xac, 0x76, -0x60, 0x23, 0xed, 0x51, 0x91, 0xef, 0x23, 0x35, -0xfe, 0x31, 0x9b, 0x25, 0xd8, 0x73, 0x09, 0x1d, -0x67, 0xf8, 0x87, 0x5d, 0x3f, 0xa8, 0x7f, 0x61, -0x23, 0x27, 0xa7, 0x21, 0x22, 0x84, 0xbe, 0xd3, -0xc5, 0x3f, 0xec, 0xfa, 0x01, 0xff, 0x43, 0x68, -0x81, 0x66, 0x2b, 0xf9, 0x07, 0xb4, 0x3e, 0x02, -0x89, 0x02, 0x82, 0x7f, 0xd8, 0xf5, 0x03, 0xfe, -0x67, 0x0a, 0x6d, 0x37, 0x88, 0xfe, 0xb9, 0x43, -0xe0, 0x9f, 0xd4, 0xf6, 0x12, 0xfc, 0xcf, 0x14, -0xe5, 0x7f, 0xd6, 0x03, 0xbc, 0x34, 0x6e, 0x7a, -0xeb, 0x4f, 0xf2, 0xfb, 0x0d, 0x09, 0xfe, 0xe7, -0x55, 0xfc, 0x72, 0x48, 0xf5, 0xcf, 0xe2, 0x13, -0xcd, 0xe3, 0x43, 0x8e, 0xcf, 0x63, 0xcb, 0x41, -0xfd, 0x8b, 0xf3, 0x3f, 0x04, 0xff, 0xac, 0x61, -0x9f, 0xf8, 0xf8, 0x9f, 0x53, 0x37, 0x89, 0xfd, -0x6a, 0xe7, 0xd1, 0x28, 0xc6, 0x03, 0x22, 0xad, -0x9f, 0xf7, 0x8c, 0xc5, 0xfe, 0xfa, 0x97, 0xa7, -0x8e, 0x3e, 0x4f, 0xd4, 0xd1, 0x93, 0xdb, 0xf8, -0x27, 0xef, 0xa2, 0x00, 0xff, 0xb3, 0xd9, 0x2c, -0xea, 0x00, 0xed, 0xec, 0x26, 0xf8, 0x87, 0xc3, -0x9e, 0xff, 0xb4, 0x19, 0xff, 0xc3, 0xe3, 0x8f, -0x01, 0xea, 0x5f, 0xa9, 0x11, 0xbb, 0x51, 0x02, -0x42, 0xaf, 0xa6, 0xb6, 0x32, 0xfd, 0x33, 0xf3, -0xbf, 0x84, 0x7f, 0x8e, 0x12, 0x3e, 0x8d, 0x18, -0x77, 0xb8, 0x08, 0x93, 0xfb, 0xf3, 0x35, 0xbe, -0xbe, 0x50, 0x07, 0xae, 0x9f, 0xa8, 0xbb, 0xe7, -0x03, 0x18, 0xf3, 0x5b, 0x27, 0xc0, 0xff, 0x4c, -0x4b, 0xfc, 0x8f, 0xc3, 0x8c, 0x98, 0xe7, 0x31, -0xef, 0xab, 0xb3, 0x21, 0xf8, 0xc7, 0x6e, 0x8e, -0x6d, 0x80, 0xf7, 0x9b, 0xed, 0xf9, 0x7f, 0xcc, -0x57, 0xff, 0xf2, 0xd0, 0xce, 0x21, 0xb4, 0xdb, -0x05, 0x42, 0xde, 0x27, 0x97, 0xd0, 0x53, 0xa1, -0xf8, 0xa7, 0xc9, 0x3c, 0xa1, 0xef, 0x27, 0xef, -0x0b, 0xb7, 0xf7, 0xf2, 0x27, 0xe8, 0x24, 0x6b, -0x54, 0x79, 0x43, 0xc5, 0xff, 0x9c, 0xb6, 0x47, -0x0d, 0x82, 0x1f, 0x7a, 0xc9, 0xf3, 0x5b, 0x4d, -0x19, 0xa1, 0x94, 0x57, 0xc8, 0x2e, 0xf2, 0xf8, -0xb0, 0xb7, 0x7f, 0x19, 0x43, 0x3b, 0xbf, 0xb1, -0x2f, 0xd8, 0xab, 0x89, 0xfe, 0x99, 0xcb, 0x7e, -0x3e, 0xb4, 0x7e, 0xed, 0x7e, 0xf5, 0x71, 0x50, -0xff, 0xe3, 0xc6, 0x93, 0x36, 0xe7, 0xe9, 0x02, -0x12, 0x69, 0x4e, 0x63, 0xf8, 0x47, 0xbc, 0xff, -0x32, 0xfc, 0x83, 0xf3, 0x97, 0x79, 0xce, 0x6e, -0x29, 0x56, 0xfd, 0x49, 0x95, 0x9b, 0xbf, 0xde, -0xba, 0xb8, 0xe2, 0x02, 0x6b, 0xe4, 0x11, 0xfc, -0x8c, 0xa7, 0xff, 0x71, 0xa3, 0xcd, 0x41, 0x13, -0x5f, 0x7f, 0x2e, 0xce, 0x77, 0x74, 0xca, 0xf2, -0xae, 0xff, 0xb3, 0x0a, 0xb6, 0x1e, 0x39, 0x4b, -0x0d, 0xbe, 0xfe, 0x97, 0x68, 0x17, 0x5e, 0x2f, -0xf0, 0xde, 0xbb, 0xac, 0x70, 0x1f, 0xa8, 0x7f, -0xb9, 0x61, 0x67, 0x88, 0xf8, 0xd3, 0x04, 0xf9, -0x9d, 0xc5, 0x73, 0x11, 0xaf, 0xf6, 0xd6, 0xf1, -0xfd, 0xce, 0xa1, 0xb3, 0x6e, 0xff, 0x08, 0xcf, -0x2f, 0x6f, 0xb2, 0xf8, 0xf9, 0x99, 0xbf, 0xfe, -0xe5, 0xf9, 0x27, 0x35, 0x4a, 0xd6, 0x0b, 0xff, -0x30, 0x61, 0x86, 0x54, 0xff, 0x32, 0x78, 0x3c, -0xbf, 0x8a, 0x7e, 0xe8, 0x24, 0x1d, 0x28, 0xf3, -0x78, 0xcb, 0x35, 0x26, 0x00, 0xff, 0xd3, 0x2d, -0xf2, 0xef, 0x11, 0xfb, 0x56, 0x67, 0xc7, 0x40, -0x2f, 0xd7, 0xff, 0x14, 0xd1, 0x8e, 0x79, 0xf4, -0xab, 0x69, 0xa8, 0xff, 0x81, 0xeb, 0x6f, 0x71, -0x76, 0xf4, 0x6b, 0x33, 0x31, 0x96, 0xaf, 0xcd, -0x1d, 0xa1, 0xf8, 0x87, 0xf8, 0xe7, 0x08, 0x89, -0xc6, 0x68, 0x11, 0xd7, 0xff, 0x4c, 0x33, 0xff, -0x8c, 0xf1, 0xf8, 0x83, 0x7e, 0x0a, 0xd0, 0xdd, -0x11, 0x74, 0x83, 0xf3, 0x34, 0xdb, 0x6f, 0xd5, -0x10, 0xce, 0x47, 0xc4, 0x3f, 0x1b, 0x86, 0x16, -0x3b, 0x42, 0xff, 0x53, 0x0d, 0xd2, 0x3a, 0xed, -0xdf, 0x71, 0x54, 0xf8, 0x67, 0x2b, 0xf3, 0x27, -0xc7, 0x3f, 0x13, 0xf1, 0xab, 0xfa, 0xb5, 0x86, -0x16, 0x09, 0x36, 0x87, 0xf3, 0x3f, 0x84, 0xf6, -0x39, 0x83, 0x0e, 0x4f, 0xa6, 0x25, 0xda, 0x27, -0x9c, 0xff, 0xb1, 0xaa, 0x1a, 0xb5, 0x13, 0xd8, -0x2d, 0x29, 0x09, 0xe6, 0x85, 0xf3, 0x3f, 0x39, -0x82, 0xaf, 0xf0, 0x6b, 0x6c, 0x5a, 0x82, 0x91, -0xe1, 0xfa, 0x9f, 0x9e, 0x64, 0x3f, 0x71, 0x4b, -0x47, 0xb3, 0x04, 0x0b, 0x39, 0x7e, 0x0e, 0xd4, -0xbf, 0x72, 0x14, 0x16, 0xce, 0x99, 0xbf, 0x52, -0x03, 0x21, 0x3f, 0xff, 0x83, 0x83, 0x12, 0xfe, -0x7d, 0xfd, 0x27, 0x56, 0x88, 0xde, 0x0c, 0xd6, -0xbf, 0x32, 0x2e, 0xfb, 0xb7, 0x13, 0xdf, 0xa8, -0xc3, 0xbe, 0xcb, 0x0e, 0xe5, 0x7f, 0x48, 0x5b, -0x9c, 0xc2, 0x2d, 0xa5, 0xf8, 0x9f, 0x07, 0x31, -0x1e, 0x38, 0xe8, 0xa3, 0x41, 0x42, 0xf9, 0x1f, -0x0c, 0x72, 0x4c, 0x82, 0x7f, 0xac, 0xd6, 0x09, -0x48, 0xfb, 0x84, 0xf3, 0x3f, 0xc8, 0x85, 0xcd, -0x66, 0x08, 0x50, 0x0c, 0xf0, 0x3f, 0xc5, 0xc4, -0xa0, 0xc2, 0x2d, 0x25, 0xf8, 0x1f, 0x23, 0x47, -0xe2, 0x8f, 0xef, 0x35, 0x2a, 0x94, 0xff, 0x59, -0x55, 0x34, 0x1e, 0xec, 0x08, 0x6e, 0x33, 0x9c, -0xff, 0xb9, 0xdf, 0xb8, 0x01, 0x7b, 0x6f, 0xd8, -0x0e, 0xf1, 0xa7, 0x9f, 0xff, 0x69, 0x2f, 0x24, -0x66, 0x30, 0xec, 0xb9, 0x9a, 0xc8, 0xda, 0x4f, -0x03, 0xfc, 0x43, 0x8c, 0xac, 0x92, 0xff, 0xd1, -0xff, 0xc5, 0xa5, 0x7d, 0x6a, 0x64, 0xfc, 0x53, -0xa2, 0xfe, 0xf5, 0x0c, 0x4e, 0x73, 0x5f, 0xe8, -0xcd, 0x6b, 0xe1, 0x6b, 0x7e, 0xb8, 0xfe, 0x87, -0xb1, 0x0d, 0xbb, 0x25, 0xda, 0xa1, 0xa4, 0xfe, -0xa7, 0xd4, 0x7a, 0x75, 0xfd, 0x0b, 0x0d, 0xc7, -0x82, 0xfd, 0x5f, 0xe1, 0xfa, 0x1f, 0xb2, 0xbb, -0x66, 0xf5, 0x7e, 0x41, 0xfd, 0x8b, 0xe2, 0x9f, -0xbb, 0x29, 0x9f, 0xa3, 0x5f, 0xb3, 0xe4, 0x6d, -0x2a, 0xf9, 0x1f, 0xd2, 0xff, 0xd5, 0xb6, 0x36, -0x81, 0xd7, 0x9b, 0x97, 0x8c, 0x66, 0xf5, 0xfa, -0xa0, 0xfe, 0xc7, 0x20, 0x32, 0x6c, 0x8a, 0x7f, -0xd4, 0xfd, 0x5f, 0x72, 0xfd, 0x2b, 0x4b, 0x64, -0x06, 0x64, 0x77, 0xa1, 0xfb, 0xf5, 0xf1, 0x3f, -0x1d, 0x8d, 0xae, 0x8c, 0x3c, 0xbd, 0x56, 0xed, -0x4f, 0x49, 0xff, 0x83, 0xaf, 0x3f, 0x97, 0x78, -0x8e, 0xc0, 0x36, 0x2b, 0xe4, 0xfa, 0x03, 0xf5, -0xaf, 0x75, 0xee, 0xfd, 0x50, 0x08, 0xf1, 0x4f, -0x80, 0xff, 0x31, 0x5d, 0x6f, 0x5b, 0x21, 0xfe, -0xf7, 0xeb, 0x7f, 0x32, 0x6e, 0x91, 0xf2, 0x08, -0xc1, 0x3f, 0x80, 0xf6, 0x29, 0xc5, 0xff, 0xb8, -0x34, 0x45, 0xea, 0x98, 0xf2, 0x79, 0x51, 0xe1, -0x1f, 0x0c, 0x7b, 0x0e, 0xa0, 0xe5, 0x4e, 0x99, -0xfe, 0x2f, 0x5e, 0xff, 0xc2, 0xb0, 0xc7, 0xf8, -0x8a, 0xe0, 0x1f, 0x40, 0xfb, 0x94, 0xe2, 0x7f, -0x4a, 0xc6, 0x13, 0xbf, 0xfe, 0xa7, 0x7d, 0x2a, -0x79, 0x4a, 0xdb, 0x62, 0xfd, 0x6a, 0xf0, 0x80, -0x3a, 0x7f, 0x05, 0xf4, 0x3f, 0x04, 0xf6, 0x3c, -0x84, 0x5e, 0x6e, 0x5a, 0xad, 0x8e, 0x3f, 0xb2, -0xfe, 0x87, 0x14, 0xf5, 0x96, 0x4c, 0x6a, 0x18, -0x08, 0x69, 0x37, 0xb3, 0x65, 0xb2, 0xde, 0x3b, -0x80, 0x7f, 0xce, 0x2e, 0xa9, 0xad, 0xe8, 0xd2, -0x0f, 0x0c, 0x86, 0xe4, 0x3b, 0x59, 0xff, 0xf3, -0x39, 0x6a, 0x1b, 0x4b, 0xd6, 0x12, 0xd8, 0x63, -0x91, 0xf7, 0x77, 0x6d, 0xc6, 0xad, 0x38, 0xa8, -0xfb, 0xbf, 0x20, 0xfe, 0xf9, 0x3a, 0x15, 0xe2, -0x9f, 0x80, 0xfe, 0x87, 0xe8, 0xeb, 0x5a, 0x71, -0xb4, 0x6f, 0x51, 0xc7, 0x73, 0x27, 0x88, 0x7f, -0x06, 0x35, 0x92, 0x88, 0x49, 0xfe, 0xed, 0x50, -0xe8, 0x99, 0x03, 0xf8, 0xa7, 0xd2, 0xad, 0x76, -0x85, 0xe4, 0x6b, 0x05, 0xfe, 0x31, 0x29, 0xcd, -0x58, 0x0c, 0xc3, 0x03, 0xdc, 0xfd, 0xae, 0xfe, -0xc7, 0xa9, 0x19, 0xa4, 0xb0, 0xd0, 0x9f, 0xdf, -0xc3, 0xf4, 0x3f, 0x4e, 0x32, 0xa7, 0xd8, 0x66, -0x39, 0xfe, 0xe7, 0x1a, 0xe1, 0x7f, 0x88, 0x0c, -0x86, 0xf7, 0x7f, 0x05, 0xf8, 0x1f, 0xdb, 0x0c, -0xa0, 0x9d, 0x8e, 0x6b, 0x96, 0xab, 0x08, 0x4a, -0xcf, 0xd8, 0xa4, 0x11, 0xbe, 0x26, 0xa4, 0xfe, -0xc5, 0x8d, 0x81, 0xd8, 0xb3, 0x8c, 0x11, 0xda, -0x16, 0x82, 0x7f, 0x7c, 0x6e, 0xac, 0xf2, 0x0c, -0x93, 0x94, 0x1a, 0x2b, 0x15, 0xf8, 0x87, 0x79, -0x63, 0x8d, 0x6b, 0x30, 0xbd, 0x9c, 0xf9, 0x46, -0x09, 0xfd, 0x0f, 0xf1, 0xc6, 0xf7, 0x22, 0xe2, -0x1f, 0xc9, 0xdb, 0x99, 0xd4, 0x07, 0x5a, 0x19, -0xfc, 0x03, 0xae, 0x7f, 0x3f, 0x7e, 0x5f, 0x88, -0x80, 0x7f, 0x80, 0x7f, 0x12, 0xe8, 0x59, 0xce, -0x60, 0x94, 0xaa, 0x7f, 0xa1, 0x97, 0xfb, 0x56, -0x7e, 0x8c, 0x8d, 0x65, 0x56, 0x04, 0xfc, 0x83, -0xd1, 0x8e, 0xfe, 0xa5, 0xd6, 0x3a, 0x9e, 0x6c, -0x5a, 0x91, 0xb0, 0xde, 0x2e, 0x5b, 0xff, 0x12, -0xde, 0xe8, 0x89, 0x5f, 0xb9, 0xf7, 0x1a, 0x5a, -0x15, 0xa5, 0xfe, 0x75, 0x14, 0x6d, 0xc1, 0x68, -0x5c, 0xd0, 0x3e, 0x65, 0xeb, 0x5f, 0x31, 0xda, -0x6d, 0xfa, 0xd3, 0x12, 0xfd, 0xef, 0x92, 0xfe, -0xe7, 0xe5, 0xde, 0x95, 0xc5, 0x1d, 0x9b, 0x6f, -0xf9, 0xd0, 0xfe, 0x9b, 0xbe, 0xf2, 0xf5, 0x2f, -0xaf, 0xad, 0x60, 0x09, 0xbe, 0xdf, 0xfc, 0xf3, -0x16, 0x6e, 0x09, 0xa9, 0x7f, 0x31, 0xa3, 0x54, -0xff, 0xbb, 0xc4, 0xff, 0xc4, 0x68, 0x21, 0x2c, -0x58, 0x8f, 0x50, 0xea, 0x7f, 0xa6, 0x5c, 0x19, -0x0c, 0x11, 0x8a, 0xbc, 0x1e, 0x11, 0xff, 0xc4, -0x68, 0xff, 0xf5, 0x27, 0xc6, 0x7b, 0x51, 0xf1, -0xcf, 0xa3, 0x6e, 0xe1, 0x6c, 0x7b, 0x44, 0xfc, -0xe3, 0x1a, 0x27, 0x98, 0x42, 0xe6, 0xd5, 0x70, -0xfc, 0xc3, 0xbb, 0xbd, 0x28, 0xff, 0xe0, 0xef, -0x3f, 0xf2, 0xe3, 0x1f, 0x79, 0x77, 0x9f, 0x94, -0xc1, 0x3f, 0xe0, 0x5b, 0xaa, 0x17, 0x3a, 0x57, -0x78, 0x1d, 0x5f, 0x76, 0x35, 0xc4, 0x3f, 0xba, -0x1f, 0xff, 0xb8, 0x68, 0x27, 0x46, 0x8d, 0x8f, -0xd0, 0x29, 0xf7, 0x93, 0x8f, 0x6d, 0xf7, 0xab, -0xd8, 0xdf, 0x4a, 0xf8, 0x87, 0xed, 0x77, 0x01, -0x35, 0x9a, 0xd2, 0xe3, 0x68, 0x6b, 0x2c, 0x63, -0x2d, 0x30, 0x49, 0x47, 0x58, 0x78, 0xfd, 0xab, -0xc2, 0xf3, 0xa7, 0x2b, 0x04, 0x92, 0xfd, 0xf9, -0x24, 0x8f, 0x0f, 0x80, 0xff, 0x99, 0xd2, 0x2f, -0x69, 0x9e, 0x9e, 0xe7, 0x75, 0xb4, 0x45, 0xba, -0xfe, 0x69, 0xe4, 0xc3, 0x3f, 0x6c, 0xbf, 0xcb, -0x98, 0xb1, 0xa5, 0x7c, 0xfd, 0xab, 0xe0, 0x0d, -0x22, 0x10, 0xb4, 0x8f, 0xc0, 0x3f, 0xfc, 0xfe, -0x97, 0xf8, 0x9f, 0x23, 0x5a, 0xb6, 0x70, 0x1f, -0xe9, 0x67, 0x7c, 0xaa, 0x3c, 0xfe, 0x69, 0x72, -0xcb, 0x5e, 0xe3, 0x37, 0x36, 0xf5, 0x72, 0x9a, -0x42, 0xd4, 0xbf, 0x74, 0x15, 0xff, 0x43, 0x8c, -0x62, 0x55, 0x8e, 0xd2, 0xb6, 0x65, 0xf1, 0xcf, -0xe6, 0xf8, 0x0b, 0xd4, 0xa8, 0xde, 0x14, 0x3f, -0x89, 0x7e, 0x5d, 0x1e, 0xff, 0xd0, 0xe8, 0xa1, -0xb5, 0x3a, 0x35, 0x80, 0xdf, 0xb8, 0x1a, 0x8a, -0x7f, 0x00, 0xda, 0x39, 0xb5, 0xf8, 0x02, 0x7a, -0xbc, 0x3c, 0xfe, 0xa1, 0x57, 0xbb, 0xf0, 0x47, -0x13, 0x55, 0x0f, 0x78, 0xfd, 0xef, 0x0b, 0xc8, -0x27, 0xbf, 0x75, 0xbf, 0xfa, 0x5c, 0xc2, 0x3f, -0x12, 0x3a, 0x5a, 0x92, 0x0f, 0xf6, 0xcb, 0x87, -0xf1, 0x3f, 0xd4, 0x40, 0x5e, 0x7f, 0xf7, 0x02, -0xd0, 0xdf, 0x14, 0xd0, 0x3f, 0x83, 0x68, 0x09, -0xf6, 0x3b, 0x57, 0x0e, 0xff, 0x10, 0xa3, 0x6f, -0x3e, 0xf8, 0xe4, 0x73, 0x35, 0xfe, 0xb9, 0x8b, -0x47, 0xef, 0x7c, 0xd2, 0x89, 0x9f, 0x67, 0x61, -0xfc, 0xb1, 0x12, 0xf8, 0xc7, 0xcb, 0x56, 0x56, -0xcd, 0x80, 0x36, 0x65, 0x97, 0xc3, 0x3f, 0xb7, -0x12, 0xbd, 0x0a, 0xfd, 0x76, 0xa2, 0x6a, 0x27, -0xfe, 0xdf, 0x8f, 0x80, 0x7f, 0x3c, 0xff, 0x58, -0x95, 0xe6, 0xa2, 0x89, 0x32, 0xf8, 0xe7, 0xa8, -0x84, 0x06, 0x6d, 0xa1, 0xf7, 0xee, 0x2e, 0x81, -0x7f, 0xbc, 0xfd, 0x5a, 0x35, 0x4e, 0x2c, 0xd8, -0xbf, 0x03, 0xf0, 0x4f, 0x9d, 0x54, 0xff, 0xba, -0xab, 0x73, 0x40, 0xc9, 0xff, 0xc4, 0xb8, 0xff, -0x21, 0xfe, 0x39, 0x6c, 0xa7, 0xbb, 0x8c, 0x28, -0xfc, 0x4f, 0xa3, 0xbb, 0xbb, 0xfd, 0xe8, 0xd6, -0x8e, 0x46, 0x35, 0xde, 0xe3, 0xfa, 0xe7, 0x79, -0x00, 0xff, 0x1c, 0x46, 0xe9, 0xbc, 0x51, 0x86, -0xff, 0x81, 0xf9, 0xf7, 0x52, 0xae, 0x31, 0x9f, -0x50, 0xe1, 0xc3, 0x30, 0xfc, 0x63, 0xb7, 0xa3, -0x72, 0xf8, 0x07, 0x81, 0xfb, 0xf3, 0xe2, 0xbd, -0x6d, 0x56, 0x02, 0xe2, 0x2b, 0x05, 0xfe, 0xa9, -0x03, 0xf8, 0x67, 0xc8, 0xc9, 0x76, 0x36, 0x46, -0xe4, 0x7f, 0x28, 0x5f, 0xea, 0x36, 0x0e, 0x9c, -0x60, 0xf8, 0xa7, 0x8c, 0xfe, 0x07, 0x1d, 0x1a, -0x5b, 0xb9, 0xa9, 0x33, 0x22, 0xff, 0x43, 0xd0, -0xce, 0x6c, 0x67, 0x9b, 0x95, 0x21, 0xc6, 0xdb, -0xee, 0x20, 0x20, 0x15, 0xfe, 0xa9, 0x16, 0xfe, -0x21, 0xc4, 0x69, 0x67, 0x34, 0xfe, 0xc7, 0xf3, -0x3f, 0x8e, 0xde, 0x88, 0xb9, 0xa5, 0xa6, 0x3c, -0xfe, 0x79, 0x09, 0xad, 0x44, 0x46, 0x14, 0xfe, -0xc7, 0xdb, 0xdd, 0x41, 0x7b, 0x55, 0xde, 0x88, -0xc4, 0xff, 0x78, 0xfe, 0xec, 0xc8, 0x9e, 0x33, -0xa2, 0xf0, 0x3f, 0x1e, 0xda, 0xb9, 0x5a, 0x68, -0x1f, 0xcc, 0xf8, 0xf8, 0x9f, 0x10, 0xfc, 0xe3, -0x96, 0x21, 0x3a, 0xda, 0xb4, 0x0d, 0x11, 0xf9, -0x1f, 0x9a, 0xdd, 0x1a, 0xb1, 0xff, 0xaf, 0x87, -0xff, 0x69, 0xa0, 0x32, 0xe6, 0xeb, 0xe0, 0x7f, -0xb2, 0x9d, 0xca, 0xf5, 0xa1, 0xfc, 0x4f, 0x26, -0xd7, 0x78, 0x5d, 0xfc, 0x4f, 0x1b, 0x1a, 0x88, -0xc2, 0xff, 0x78, 0xbb, 0xbb, 0x12, 0xbb, 0x3b, -0x17, 0x81, 0xff, 0x11, 0xeb, 0x51, 0x7b, 0xce, -0x88, 0xc6, 0xff, 0x54, 0x11, 0x3c, 0x30, 0x4d, -0x1a, 0xe1, 0xcb, 0xf3, 0x3f, 0xee, 0xa6, 0x3a, -0x88, 0x91, 0xcd, 0x19, 0x91, 0xf8, 0x1f, 0xe2, -0xb4, 0x3d, 0xb1, 0x17, 0x53, 0xd9, 0x0e, 0xb5, -0x3f, 0xfd, 0xfd, 0x5f, 0xee, 0xd5, 0x8e, 0xac, -0x6b, 0xcd, 0x25, 0x22, 0xf1, 0x3f, 0xde, 0xb7, -0xbd, 0x6d, 0x7f, 0x11, 0x8d, 0xff, 0xf1, 0xbc, -0x6d, 0xb5, 0x99, 0x35, 0x51, 0xf8, 0x9f, 0xac, -0xbd, 0x83, 0xa0, 0x9d, 0x51, 0xb4, 0xaa, 0xdf, -0x88, 0xc8, 0xff, 0x90, 0xa7, 0x63, 0xd8, 0xc8, -0xe4, 0x2a, 0x55, 0xcf, 0x8b, 0x52, 0xff, 0x7c, -0x1a, 0x1d, 0xd4, 0x57, 0x3a, 0xca, 0xe7, 0x57, -0x89, 0x7f, 0x3e, 0x44, 0xe7, 0xed, 0xd6, 0x7c, -0x4d, 0x44, 0xfe, 0x87, 0xc6, 0x13, 0x9d, 0xf6, -0x7f, 0x95, 0xe4, 0x7f, 0x40, 0xfe, 0xd2, 0x5b, -0x9f, 0x59, 0x9d, 0xe2, 0xf9, 0xab, 0x3a, 0x14, -0xff, 0x7c, 0xc5, 0xaf, 0x3f, 0x77, 0x9b, 0xa1, -0xba, 0x7e, 0x14, 0xe8, 0xff, 0xf2, 0xd6, 0xc7, -0xbf, 0xaf, 0x8e, 0x57, 0x70, 0xfe, 0x0f, 0x05, -0x39, 0x2e, 0x8d, 0x36, 0x6c, 0x35, 0x20, 0x65, -0xbe, 0x83, 0xfa, 0xe7, 0x7d, 0xb4, 0x48, 0xe1, -0x76, 0x73, 0x9f, 0xba, 0xa5, 0x4f, 0x99, 0xbf, -0x42, 0xf0, 0x0f, 0xbe, 0x5b, 0x86, 0xca, 0xf1, -0x3f, 0xc8, 0x0d, 0xda, 0x35, 0xb3, 0x54, 0xff, -0xd3, 0x62, 0x27, 0xca, 0xf0, 0x3f, 0xb5, 0x02, -0xff, 0xe8, 0xc3, 0x63, 0x8d, 0x7b, 0xfd, 0xf9, -0xeb, 0x16, 0x35, 0xff, 0xe3, 0x7e, 0x6b, 0x3f, -0x52, 0xec, 0x57, 0xf2, 0x45, 0x12, 0xfe, 0xe1, -0xd9, 0x6d, 0x44, 0xbf, 0xd5, 0xf1, 0xc7, 0xe7, -0x06, 0x35, 0xff, 0xe3, 0xed, 0xb7, 0xd9, 0xc9, -0x94, 0xe1, 0x7f, 0x40, 0xfd, 0x4b, 0x3f, 0x7f, -0x1d, 0xfc, 0xcf, 0x29, 0x57, 0xf6, 0x9c, 0x4a, -0x74, 0xc6, 0xdb, 0xcc, 0x08, 0xf8, 0x67, 0x67, -0x3c, 0x8b, 0x8e, 0xf6, 0x66, 0x53, 0x95, 0x7b, -0xa3, 0xe9, 0x9f, 0x07, 0xb5, 0x2e, 0x7c, 0x63, -0x64, 0x71, 0x42, 0x50, 0xe8, 0xeb, 0xe4, 0xfe, -0x2f, 0x8f, 0x7f, 0xa3, 0x8e, 0x6d, 0xaa, 0x7c, -0x4e, 0x0b, 0x30, 0x42, 0x1d, 0x0a, 0xfe, 0xc7, -0x8c, 0x93, 0x41, 0x49, 0xad, 0xa9, 0x2e, 0x57, -0x3f, 0xb6, 0x45, 0x9a, 0x0f, 0xa0, 0xc0, 0x3f, -0x9e, 0x2c, 0x0a, 0x25, 0x8b, 0x02, 0x06, 0x87, -0xf0, 0x3f, 0x1f, 0xb8, 0x7c, 0x2c, 0x7d, 0x30, -0x73, 0x4a, 0x7d, 0x6f, 0x38, 0xff, 0x63, 0x55, -0xa5, 0x62, 0xdd, 0x62, 0x7e, 0x42, 0xa9, 0xfa, -0x17, 0x75, 0x8b, 0x8d, 0xdf, 0x17, 0x82, 0x7a, -0xb0, 0x90, 0xfa, 0x17, 0x6d, 0x84, 0x9f, 0xa9, -0xa0, 0x13, 0x11, 0xc9, 0xd8, 0x9f, 0x50, 0xfc, -0x93, 0x21, 0xfe, 0xc1, 0xbf, 0xaf, 0x3d, 0x86, -0x36, 0x98, 0x71, 0x57, 0x11, 0x14, 0x82, 0x7f, -0x6e, 0x82, 0xfe, 0x89, 0x3d, 0x6e, 0x27, 0xff, -0x2d, 0x1a, 0xfe, 0xf1, 0xf8, 0x6a, 0x3b, 0xd9, -0x5f, 0x5a, 0xff, 0x1c, 0x63, 0xfc, 0x33, 0x89, -0x1e, 0xda, 0x4a, 0xbb, 0x2a, 0xaf, 0xd0, 0x4f, -0x02, 0xfc, 0x63, 0xbe, 0x20, 0xed, 0x97, 0xcc, -0x3b, 0x8a, 0xaa, 0x7f, 0xc6, 0x46, 0xf7, 0x44, -0x55, 0xab, 0xc2, 0x9f, 0xa1, 0xfc, 0x4f, 0xbb, -0x9d, 0x2c, 0xee, 0x88, 0xa4, 0x7f, 0x16, 0xb2, -0xe7, 0x6d, 0x45, 0xb4, 0x39, 0x32, 0xff, 0x63, -0x25, 0x77, 0x5e, 0x4f, 0xfd, 0x8b, 0x14, 0x52, -0xaf, 0x0b, 0xff, 0x84, 0xcc, 0xeb, 0x2b, 0xc9, -0xff, 0x94, 0xc4, 0x3f, 0xf3, 0xf2, 0x81, 0x6c, -0x5b, 0x12, 0xff, 0x30, 0x3c, 0x30, 0x19, 0xf7, -0x1a, 0xdb, 0x73, 0x51, 0xf1, 0x0f, 0x95, 0x3d, -0xaf, 0xdd, 0x30, 0x49, 0x85, 0x34, 0xe5, 0xf1, -0x8f, 0x96, 0xa2, 0x46, 0x0d, 0x33, 0x28, 0xfe, -0x99, 0x0e, 0xc5, 0x3f, 0x83, 0x9e, 0xec, 0x59, -0x18, 0xe5, 0xf0, 0x8f, 0xfb, 0x1f, 0x51, 0x29, -0xe9, 0xcf, 0x5f, 0xa4, 0x46, 0x87, 0x02, 0xff, -0xd4, 0xbb, 0x97, 0x9d, 0xab, 0xfa, 0x3b, 0xc5, -0xf5, 0x2b, 0xf0, 0xcf, 0xf3, 0xae, 0xec, 0xb9, -0x93, 0x16, 0xc2, 0x22, 0xeb, 0x9f, 0x43, 0x8c, -0x20, 0xfe, 0xf1, 0xd0, 0x4e, 0x0d, 0x19, 0xd4, -0x13, 0x19, 0xff, 0x50, 0x03, 0xe8, 0x7f, 0x4a, -0xe1, 0x9f, 0xcd, 0xec, 0x69, 0xdd, 0x18, 0x0d, -0xff, 0xf4, 0x28, 0x60, 0x4f, 0x59, 0xfe, 0x87, -0xf1, 0xf9, 0x65, 0xeb, 0x5f, 0x24, 0x49, 0xb5, -0xb1, 0x44, 0xa6, 0xa8, 0x7f, 0xe9, 0x10, 0xff, -0x78, 0x43, 0x0e, 0x1f, 0x22, 0x6d, 0x5c, 0x44, -0xd8, 0x5c, 0xba, 0xfe, 0xe5, 0xed, 0x77, 0x56, -0x11, 0xa6, 0x4a, 0xf1, 0x3f, 0xb7, 0xbb, 0x6d, -0x3e, 0xef, 0xa8, 0xeb, 0x5f, 0x3c, 0x3e, 0x70, -0xfe, 0xe7, 0x30, 0x93, 0x95, 0x16, 0x14, 0xfa, -0x8d, 0xcf, 0x83, 0xfa, 0x67, 0xee, 0x8d, 0xbd, -0x8b, 0x5d, 0x63, 0xbe, 0xfb, 0x49, 0x56, 0x5d, -0xff, 0x9a, 0xef, 0x45, 0xef, 0x31, 0x22, 0x0c, -0x96, 0xe3, 0xf9, 0x86, 0xd9, 0x15, 0x8e, 0xe5, -0xe7, 0x7f, 0xd6, 0xf1, 0x6c, 0x55, 0xe8, 0x8d, -0x52, 0xff, 0xa2, 0xdf, 0xd2, 0x46, 0xb0, 0xc1, -0x8a, 0x19, 0x23, 0xb0, 0x5e, 0x67, 0xf7, 0x03, -0xe3, 0x7f, 0xc4, 0x74, 0x29, 0x44, 0x0c, 0xbd, -0x5c, 0xfd, 0x0b, 0xb2, 0x5b, 0x91, 0xf0, 0x4f, -0x8f, 0xaa, 0xfe, 0x15, 0x2b, 0x51, 0xff, 0x9a, -0xbf, 0x05, 0xcd, 0x99, 0x2d, 0x4d, 0x89, 0x88, -0xfa, 0x1f, 0xca, 0xff, 0x58, 0x69, 0x5b, 0xc9, -0xff, 0xcc, 0x72, 0xff, 0x37, 0xc2, 0xfa, 0xd7, -0x90, 0x99, 0x36, 0x94, 0xef, 0xe3, 0xa1, 0xfa, -0xe7, 0xdd, 0x05, 0x54, 0x9a, 0xff, 0x41, 0x74, -0xfe, 0xb0, 0x87, 0x2e, 0x46, 0xec, 0xa6, 0x66, -0x5d, 0xe9, 0x1f, 0x7e, 0xfd, 0xbb, 0x4c, 0xc0, -0xff, 0xe0, 0xf8, 0x6c, 0xaf, 0x52, 0xe2, 0x43, -0x90, 0x7f, 0xc5, 0xf3, 0xa8, 0x5f, 0x4a, 0xdc, -0x99, 0x52, 0xe2, 0x73, 0xa1, 0x7f, 0x66, 0xfd, -0x5f, 0x2e, 0x7f, 0x95, 0x48, 0xf7, 0x29, 0xf9, -0x2b, 0xa1, 0x7f, 0x76, 0x20, 0x1f, 0x78, 0xc4, -0x4e, 0x2d, 0x54, 0xbe, 0x7f, 0xcd, 0xf2, 0xdb, -0x21, 0x8f, 0x20, 0xff, 0x63, 0xaf, 0x28, 0x54, -0xaa, 0xf8, 0x90, 0x39, 0xbe, 0x5e, 0xe2, 0x7f, -0xce, 0xa2, 0xc3, 0x7a, 0x8d, 0x52, 0xff, 0x53, -0xc1, 0xd6, 0x5b, 0x4b, 0x21, 0x3f, 0x66, 0xfe, -0xeb, 0x13, 0xd5, 0x5f, 0x28, 0xf1, 0x0f, 0xdb, -0xaf, 0x01, 0xf9, 0x9f, 0xaf, 0xed, 0x66, 0xa4, -0x8e, 0x57, 0x42, 0xff, 0x09, 0xf9, 0x1f, 0xda, -0x7f, 0x51, 0x9a, 0xff, 0x41, 0x90, 0xff, 0x39, -0xd0, 0xbf, 0xbc, 0x49, 0xa9, 0xff, 0x81, 0xfa, -0x67, 0x10, 0xcf, 0xf7, 0x5b, 0xe9, 0x07, 0x95, -0xf1, 0xe7, 0x7d, 0x81, 0x7f, 0x74, 0x86, 0x7f, -0x70, 0xd0, 0xbe, 0x8a, 0xbe, 0x1c, 0x4a, 0x2a, -0xf9, 0x1f, 0xf1, 0xfb, 0x52, 0x3e, 0xea, 0x0c, -0xc9, 0x47, 0x42, 0x4f, 0xeb, 0xce, 0x7f, 0x16, -0x7a, 0xd7, 0xdc, 0x09, 0x25, 0xff, 0xc3, 0xd7, -0xdb, 0xba, 0xc8, 0xb6, 0xe6, 0x88, 0x1d, 0xc6, -0xff, 0xb0, 0xf0, 0xc3, 0xfb, 0xbf, 0xf8, 0x74, -0xbe, 0xfe, 0x32, 0xfc, 0x4f, 0x2d, 0xc4, 0x3f, -0x56, 0x26, 0x8c, 0x0f, 0x61, 0xbf, 0xcf, 0xfa, -0xbf, 0xe8, 0xee, 0x2e, 0xa3, 0x65, 0xa4, 0xed, -0x3d, 0xb8, 0x5f, 0xd1, 0xff, 0x75, 0x18, 0xf2, -0x21, 0xd7, 0xac, 0x76, 0xeb, 0x69, 0xd5, 0x7e, -0xcf, 0xf0, 0xf8, 0x73, 0x7b, 0x1d, 0xf0, 0xcf, -0x5f, 0x1b, 0x2d, 0x6a, 0x3d, 0xcc, 0x19, 0xfe, -0xfc, 0xd6, 0x23, 0xa0, 0x7f, 0xbe, 0x88, 0xd2, -0xc6, 0x12, 0x15, 0xff, 0x23, 0xf4, 0xc9, 0x96, -0xde, 0x07, 0x76, 0x67, 0x14, 0x3a, 0x94, 0x78, -0xef, 0xdf, 0x63, 0x6c, 0x7d, 0xbd, 0xbe, 0x07, -0xa2, 0x9d, 0x74, 0x88, 0x9e, 0x8a, 0x3f, 0xef, -0xde, 0xfc, 0x43, 0x8f, 0xff, 0x19, 0x6c, 0xc6, -0xdf, 0xaa, 0xf8, 0x1f, 0x7e, 0x3d, 0xd3, 0x52, -0xff, 0x97, 0xdd, 0xd6, 0xa3, 0xdc, 0xef, 0x65, -0x81, 0x67, 0x10, 0xb8, 0xdf, 0xa6, 0xad, 0x66, -0xc4, 0xfd, 0x5f, 0xad, 0xc4, 0x3f, 0x86, 0x0e, -0xf0, 0xcf, 0xe8, 0xe4, 0x8a, 0x5d, 0x4a, 0xfe, -0x67, 0x8c, 0x3f, 0x5d, 0xc6, 0xcf, 0xc1, 0xf3, -0x32, 0x82, 0x52, 0x5b, 0x79, 0x7c, 0x86, 0x81, -0x28, 0xd8, 0xff, 0x45, 0x9f, 0xd6, 0x43, 0xc6, -0xf2, 0x47, 0x42, 0xf8, 0x10, 0x76, 0xbf, 0x35, -0xd6, 0x73, 0xfd, 0xf3, 0x87, 0xfa, 0xdc, 0x93, -0x2d, 0x1f, 0x25, 0x18, 0xec, 0xa9, 0x06, 0xf8, -0xe7, 0x38, 0x8f, 0x3f, 0x92, 0xfe, 0xf9, 0x22, -0x1a, 0x2d, 0xc7, 0xff, 0xe4, 0xf5, 0x51, 0x91, -0xad, 0xe6, 0xec, 0x96, 0x86, 0xe4, 0x25, 0x45, -0xfe, 0x9a, 0x14, 0x7a, 0x63, 0x04, 0xf4, 0xcf, -0x2f, 0xd5, 0x2f, 0xef, 0x52, 0xc5, 0x9f, 0x45, -0x9f, 0x89, 0xe7, 0x51, 0xf0, 0x3f, 0xcf, 0xa3, -0xe7, 0xd0, 0x72, 0x6b, 0x7d, 0x4f, 0x45, 0x70, -0xbf, 0xaf, 0x59, 0xfc, 0x7e, 0xab, 0x75, 0xdf, -0xee, 0xe3, 0x34, 0xdf, 0x39, 0xa9, 0x9e, 0x1d, -0xaa, 0xf8, 0x33, 0x09, 0xf0, 0xaa, 0xbb, 0xdf, -0xef, 0x0d, 0xc5, 0xf6, 0xa1, 0x23, 0x83, 0xcd, -0x7f, 0x15, 0x57, 0xed, 0xf7, 0xa4, 0xa8, 0xb7, -0x2e, 0x84, 0xdd, 0x5e, 0xd6, 0xe8, 0x03, 0x4a, -0xff, 0x4c, 0xeb, 0x02, 0xff, 0x80, 0x78, 0xfe, -0x35, 0x35, 0xb4, 0xe0, 0xfb, 0xfe, 0x34, 0xe7, -0x7f, 0x8e, 0x49, 0xf5, 0x2f, 0x27, 0xdb, 0xa3, -0xd2, 0xf3, 0xa4, 0x8b, 0xc1, 0xfe, 0x2f, 0xfa, -0x6d, 0x7f, 0x76, 0x16, 0x1b, 0xdd, 0x0a, 0xfe, -0x87, 0xdd, 0x3f, 0x86, 0xe9, 0xab, 0x7f, 0xa9, -0xe2, 0x73, 0x87, 0xb8, 0x3f, 0x51, 0xbd, 0xdc, -0xdd, 0x66, 0xc1, 0xb2, 0x97, 0xe0, 0xbb, 0x2a, -0xb8, 0xfe, 0xb9, 0xce, 0x57, 0xff, 0x52, 0xf3, -0x3f, 0x7f, 0x14, 0xa2, 0xff, 0x69, 0x77, 0x12, -0xeb, 0x14, 0xfd, 0x83, 0x00, 0xff, 0xd4, 0x4b, -0x68, 0x67, 0xd5, 0x69, 0xa3, 0x77, 0x51, 0x90, -0xff, 0x11, 0xf8, 0x47, 0xd6, 0xff, 0xe8, 0xdd, -0xaf, 0x18, 0x2a, 0x7e, 0x03, 0x9c, 0x7f, 0x01, -0xeb, 0x5f, 0x47, 0xb5, 0x47, 0x1d, 0xa3, 0x74, -0xff, 0xbb, 0x4f, 0xff, 0xd3, 0x96, 0xef, 0x1a, -0xb8, 0x27, 0xc8, 0x3f, 0x8c, 0xf3, 0xeb, 0xf7, -0xf5, 0x7f, 0xb5, 0x6d, 0x54, 0xeb, 0xc3, 0x95, -0xf8, 0x07, 0x1b, 0xad, 0x6b, 0xbb, 0xfa, 0xe2, -0x99, 0x80, 0xbe, 0xe5, 0x5c, 0x38, 0xff, 0x63, -0xd8, 0xf1, 0x47, 0x6d, 0xff, 0xfc, 0xea, 0xb3, -0x00, 0xff, 0x74, 0x49, 0x78, 0x18, 0xaf, 0xd7, -0x6a, 0x02, 0xe7, 0x83, 0x00, 0xfc, 0xe3, 0x9e, -0x7f, 0xc1, 0xb3, 0x7f, 0xde, 0x38, 0xa5, 0x3d, -0x1c, 0x98, 0x87, 0x0c, 0xf1, 0x4f, 0x97, 0xcb, -0xff, 0x50, 0xb4, 0x63, 0xb6, 0x5a, 0x89, 0x86, -0x78, 0x42, 0x7b, 0x05, 0xc9, 0x42, 0x68, 0x80, -0x7f, 0xea, 0xa0, 0x7f, 0xf4, 0xf6, 0x8d, 0xd8, -0x38, 0x5d, 0x0a, 0xff, 0xd4, 0xc9, 0x6a, 0xbd, -0x89, 0x84, 0x8a, 0xff, 0x19, 0x0b, 0xeb, 0x7f, -0xcf, 0x8c, 0x19, 0x4e, 0xfc, 0xa1, 0x20, 0xfe, -0xe1, 0xcf, 0x7b, 0x0a, 0xe2, 0x1f, 0x7a, 0x10, -0x46, 0xa7, 0xf6, 0x70, 0x09, 0xfc, 0xb3, 0x89, -0xf3, 0x3f, 0x1d, 0xd4, 0x28, 0xf6, 0xdf, 0xa6, -0x98, 0xb7, 0xf0, 0xbe, 0x82, 0xff, 0x99, 0x4f, -0xd1, 0xce, 0xde, 0xcc, 0x74, 0x7c, 0x53, 0x29, -0xfc, 0x13, 0x0b, 0x64, 0x7f, 0x3a, 0xf6, 0x27, -0x2b, 0xe3, 0x1f, 0x91, 0x8f, 0x24, 0xfc, 0x43, -0x0e, 0xc2, 0x60, 0x69, 0x0e, 0x02, 0x83, 0x90, -0xfe, 0xaf, 0x11, 0x04, 0xf0, 0xcf, 0x32, 0x91, -0x7f, 0xd3, 0x45, 0xfe, 0xff, 0x7b, 0xbb, 0x9f, -0xff, 0x31, 0xa8, 0x70, 0x25, 0x16, 0x86, 0x7f, -0x1a, 0x6b, 0x65, 0xfe, 0x27, 0x67, 0xd4, 0x7a, -0x30, 0xa0, 0x52, 0x8d, 0x7f, 0x60, 0xfd, 0xeb, -0x30, 0x36, 0x78, 0xfe, 0x95, 0xe6, 0x3f, 0xcf, -0x67, 0xeb, 0x77, 0xfa, 0xf4, 0x3c, 0xb9, 0xe4, -0xec, 0x3d, 0x0a, 0x3c, 0x13, 0x57, 0xf6, 0x7f, -0x61, 0x63, 0x23, 0xf6, 0x4f, 0xf0, 0xfc, 0x8b, -0x33, 0xe0, 0xfc, 0x0b, 0xd0, 0xed, 0x8e, 0xdd, -0xfe, 0x87, 0x9e, 0x10, 0xda, 0x8f, 0x7f, 0xd8, -0xff, 0x6f, 0xa7, 0x84, 0x7f, 0x50, 0xa6, 0xd3, -0x58, 0xd4, 0x1b, 0xc4, 0x3f, 0x6f, 0x73, 0x7e, -0xbb, 0x1e, 0xf9, 0xfd, 0xb9, 0xd3, 0x9d, 0xa7, -0xbd, 0x36, 0x04, 0xff, 0xc8, 0xfd, 0x5f, 0x5b, -0xac, 0x06, 0x25, 0xfe, 0x89, 0xb1, 0xf5, 0x13, -0xa2, 0xfe, 0xb5, 0x91, 0x8c, 0x81, 0xb2, 0xde, -0x1a, 0x54, 0xf4, 0xbf, 0x5f, 0x06, 0xf7, 0x8f, -0xc4, 0xff, 0xb4, 0xc6, 0x36, 0xf4, 0x45, 0xe7, -0x7f, 0x3e, 0x83, 0xb0, 0x27, 0xa9, 0xc4, 0x3f, -0x80, 0xff, 0x71, 0x0d, 0x3e, 0x8f, 0x57, 0x7a, -0x1f, 0x17, 0xe7, 0x5f, 0x2c, 0x04, 0xf8, 0xc7, -0x9b, 0xf6, 0xf3, 0x0e, 0xed, 0xff, 0xaa, 0x04, -0xcf, 0xef, 0x84, 0x38, 0xff, 0x02, 0xd6, 0xbf, -0x5e, 0xf6, 0xda, 0xbe, 0xc4, 0xf9, 0x17, 0x2f, -0x07, 0xf0, 0x0f, 0x8e, 0xff, 0x3f, 0x11, 0xef, -0xfb, 0x38, 0xfb, 0x1c, 0x8a, 0x07, 0xe7, 0xfb, -0xc1, 0xfa, 0xd7, 0xa8, 0x94, 0xad, 0x26, 0xde, -0xba, 0xb2, 0x2d, 0x98, 0xbf, 0x4e, 0x09, 0xfc, -0x63, 0xc2, 0xf8, 0xa3, 0x53, 0xa3, 0xd6, 0x13, -0x22, 0x8a, 0xeb, 0xff, 0x98, 0xaf, 0xf7, 0xeb, -0x7f, 0xc6, 0xab, 0x7a, 0x5e, 0x0b, 0xc6, 0xab, -0xd7, 0x6c, 0xb6, 0x3e, 0x55, 0x2b, 0x55, 0x37, -0xb2, 0x84, 0x08, 0xba, 0xb7, 0x04, 0xfe, 0xf1, -0xe9, 0x7f, 0x68, 0x74, 0x0d, 0xe6, 0xf7, 0x89, -0x12, 0xfc, 0xcf, 0x50, 0x7c, 0x9f, 0xff, 0x93, -0x7b, 0x04, 0xfe, 0x59, 0x6e, 0xfa, 0xb2, 0x5b, -0x62, 0x76, 0x5b, 0x9b, 0x15, 0xe8, 0x7f, 0x97, -0xce, 0xbf, 0x80, 0xf9, 0xeb, 0x58, 0xe5, 0x90, -0x57, 0x7f, 0x49, 0xaa, 0xf1, 0x8f, 0x2f, 0xdf, -0x91, 0x44, 0xa6, 0xea, 0x7f, 0xe7, 0xf8, 0xa7, -0x36, 0x90, 0xfd, 0x2b, 0x06, 0x02, 0x78, 0x3b, -0x84, 0xff, 0x21, 0x6c, 0x98, 0x37, 0xf6, 0x47, -0x9e, 0xff, 0x5c, 0xac, 0xe0, 0xfc, 0x8f, 0x0f, -0xff, 0xb8, 0x85, 0xbf, 0x40, 0x7e, 0xff, 0x7e, -0x0f, 0xff, 0x07, 0xb4, 0x3e, 0xb4, 0x0b, 0x35, -0x92, 0xf0, 0x17, 0x6e, 0x20, 0xf8, 0xa7, 0x23, -0x7c, 0x75, 0x16, 0x32, 0x4b, 0x19, 0xf0, 0xaf, -0x0f, 0x2d, 0x47, 0x86, 0xa5, 0x99, 0xa5, 0x8c, -0x6f, 0xf2, 0xfb, 0xe4, 0x58, 0x33, 0x83, 0x9d, -0x6f, 0x16, 0x62, 0x80, 0xbf, 0xd2, 0x0b, 0x5d, -0xe3, 0x9b, 0xfc, 0xfe, 0xf5, 0xfe, 0x7d, 0xcb, -0xfc, 0x6f, 0x92, 0xb3, 0xfc, 0x4e, 0xa0, 0xbf, -0x44, 0x4b, 0x9d, 0x12, 0x86, 0xfe, 0x7b, 0xff, -0xfe, 0xff, 0xb2, 0xff, 0x75, 0xd3, 0x8e, 0xe0, -0xf3, 0x18, 0x8f, 0x3f, 0xd7, 0xfb, 0xd7, 0xda, -0x1a, 0x65, 0x55, 0x32, 0xf9, 0x7b, 0xfe, 0xfc, -0xff, 0xc1, 0x5f, 0xfb, 0xb5, 0x6b, 0xd7, 0x9c, -0x32, 0xc6, 0xff, 0xe7, 0xf5, 0xdf, 0xb2, 0xe7, -0xf1, 0xbb, 0x78, 0xf8, 0x5d, 0x3c, 0xfc, 0x06, -0xfe, 0xff, 0x2e, 0x1e, 0x96, 0xfb, 0xfb, 0xb6, -0xc5, 0x9f, 0x6f, 0xd7, 0x7a, 0xc8, 0x8f, 0xc5, -0xae, 0xd9, 0x2d, 0xbb, 0x12, 0x17, 0x5d, 0xe1, -0x74, 0x84, 0xfa, 0xe0, 0x82, 0xa3, 0xf6, 0xee, -0x62, 0xf5, 0x90, 0x76, 0xb5, 0x14, 0x3f, 0x86, -0x06, 0x12, 0x07, 0x62, 0x19, 0xd6, 0x76, 0x9a, -0xf6, 0xf4, 0x60, 0xb1, 0x50, 0x7e, 0xac, 0x4e, -0x62, 0x23, 0xd3, 0xce, 0x02, 0x05, 0x3f, 0x09, -0xf4, 0x51, 0xb1, 0x5a, 0xf0, 0x76, 0x70, 0x20, -0xd6, 0xf4, 0x8e, 0xb2, 0x7e, 0xb7, 0x35, 0x96, -0xf2, 0xd6, 0xef, 0x42, 0x90, 0xff, 0xa9, 0x6c, -0xcf, 0x7b, 0xb0, 0xf9, 0xf1, 0x32, 0xfc, 0x58, -0x0d, 0x7d, 0x0d, 0x89, 0xb5, 0x4d, 0x56, 0xe3, -0x9f, 0x75, 0xfc, 0xbf, 0x7f, 0x4e, 0x5d, 0x1f, -0x3c, 0x6a, 0x65, 0x7b, 0xb1, 0x31, 0x17, 0x4d, -0x1f, 0x4e, 0x8c, 0x6e, 0x84, 0x8d, 0x37, 0x4b, -0xd5, 0x07, 0xa5, 0xfe, 0x38, 0xfb, 0x47, 0x96, -0xb2, 0x5e, 0x26, 0xd5, 0x07, 0xd9, 0x7c, 0xa4, -0x01, 0xc2, 0x86, 0x4d, 0x56, 0xc3, 0xfa, 0xa0, -0x7e, 0x20, 0xd6, 0xea, 0x6c, 0x68, 0x5a, 0x0c, -0xf8, 0x31, 0x5f, 0x7f, 0x1c, 0xd5, 0x87, 0x07, -0xe6, 0xc9, 0x0b, 0x7e, 0x8c, 0xf0, 0xdb, 0x1f, -0xa0, 0x35, 0x4e, 0xb5, 0xeb, 0x8d, 0xdb, 0x89, -0x3e, 0xff, 0x77, 0x29, 0x3f, 0x7f, 0x08, 0xf8, -0x31, 0xe9, 0xfd, 0x14, 0xdd, 0x86, 0xdf, 0x77, -0xb4, 0x13, 0x76, 0xf8, 0xf9, 0x68, 0x48, 0xe6, -0xc7, 0x56, 0x2c, 0xa7, 0xfa, 0x70, 0x3f, 0x1f, -0x08, 0xeb, 0x83, 0xd2, 0xfb, 0x69, 0x43, 0x02, -0xb6, 0xa5, 0x84, 0xf0, 0x63, 0xef, 0xa3, 0x35, -0x76, 0xb5, 0xcb, 0x86, 0xdd, 0x55, 0x18, 0x28, -0xd0, 0xf9, 0xd8, 0x84, 0x16, 0x8b, 0xa9, 0xf8, -0x31, 0xa9, 0x3f, 0xce, 0x0a, 0xab, 0x0f, 0x02, -0x7e, 0x03, 0xb0, 0x25, 0x77, 0x14, 0xbc, 0xfe, -0xf1, 0xed, 0x01, 0x7d, 0x14, 0x5b, 0xcf, 0xe7, -0x43, 0x0e, 0x6a, 0x53, 0xfa, 0x70, 0x7f, 0x7a, -0x23, 0x65, 0xb7, 0x5e, 0x2c, 0x3b, 0x1f, 0x12, -0xcc, 0x07, 0x48, 0x4f, 0xd9, 0xfe, 0xf5, 0x82, -0x1f, 0x23, 0xe9, 0x54, 0x3e, 0x0d, 0xb6, 0x36, -0x3d, 0x8e, 0x9f, 0x0a, 0x5f, 0x7d, 0x90, 0xcf, -0x27, 0xd9, 0x6c, 0xe4, 0xe1, 0xee, 0x9a, 0xc9, -0x69, 0x20, 0x44, 0x86, 0x14, 0x3a, 0x1f, 0x12, -0xea, 0xc3, 0xbf, 0x70, 0xe7, 0x5d, 0x07, 0xfb, -0xe3, 0xce, 0x48, 0xf3, 0x91, 0xde, 0x13, 0xfa, -0xf0, 0xbb, 0xac, 0xe4, 0xcf, 0xe2, 0xe7, 0x52, -0xfe, 0xfe, 0xc1, 0x33, 0xd2, 0x7c, 0x6c, 0xc0, -0x86, 0xa5, 0xed, 0xf5, 0x76, 0x7c, 0x97, 0xd6, -0x1f, 0xca, 0x8f, 0x59, 0xf3, 0xc6, 0x7d, 0xfb, -0x5d, 0xd4, 0x31, 0xce, 0xc6, 0x62, 0x83, 0xf3, -0x61, 0x99, 0xff, 0x77, 0xca, 0xf3, 0x21, 0xe9, -0xf9, 0x74, 0x7b, 0xd0, 0x82, 0xf0, 0xfa, 0x60, -0x1d, 0xb8, 0xfe, 0x2f, 0xd0, 0x9d, 0x54, 0x0f, -0xaf, 0xaf, 0xd3, 0xe4, 0x7e, 0x37, 0x50, 0x1f, -0x8c, 0xed, 0x91, 0x4e, 0x8f, 0xfd, 0xb3, 0xa4, -0x98, 0x8f, 0xcd, 0xd7, 0xcf, 0x07, 0xf5, 0x41, -0xa9, 0x3f, 0x2e, 0x45, 0x8d, 0xe0, 0x7c, 0x4e, -0xc8, 0x8f, 0xed, 0x05, 0xf5, 0xc1, 0x42, 0xd6, -0x5e, 0x5f, 0xd0, 0xee, 0x4a, 0x85, 0xd7, 0x07, -0x1b, 0xfb, 0xb8, 0x5e, 0x37, 0x41, 0xe6, 0xb3, -0xe5, 0xb1, 0x91, 0xb4, 0x79, 0x47, 0x4f, 0x80, -0x1f, 0x5b, 0x8e, 0x64, 0x99, 0x50, 0x2e, 0xfe, -0x63, 0x85, 0x70, 0x48, 0xf0, 0x63, 0x8d, 0x62, -0x3e, 0xd2, 0x0b, 0x3a, 0x19, 0x8b, 0x34, 0xff, -0xe2, 0xb6, 0x1b, 0x02, 0xfa, 0x28, 0xc0, 0x8f, -0x2d, 0x05, 0xf1, 0xfc, 0x32, 0xf1, 0xc6, 0xf0, -0xfa, 0x52, 0xf5, 0x41, 0x0b, 0xd6, 0x77, 0xce, -0xdb, 0xab, 0xf3, 0x03, 0x17, 0xef, 0x29, 0xc9, -0x8f, 0x49, 0xf3, 0x91, 0x2c, 0x1a, 0x7f, 0x4c, -0x7c, 0xd9, 0x77, 0xb8, 0x9f, 0x7c, 0xc5, 0xf4, -0x51, 0xfc, 0x79, 0xb4, 0x25, 0x3d, 0xc3, 0xcd, -0xe3, 0x0b, 0x7a, 0x14, 0xe7, 0x83, 0x8c, 0xf3, -0xfa, 0x20, 0x99, 0x0f, 0xd9, 0xc2, 0xa2, 0xcd, -0x6a, 0xb4, 0xb1, 0x07, 0xc7, 0x1f, 0x84, 0xfc, -0xfe, 0x04, 0xf5, 0x41, 0x2f, 0x7f, 0x55, 0x91, -0x63, 0xc8, 0x2e, 0xa3, 0x35, 0xf9, 0xea, 0xd9, -0x2a, 0xc3, 0xbf, 0x5f, 0x0d, 0xce, 0x87, 0x14, -0xfe, 0x21, 0x07, 0xcb, 0x76, 0x61, 0xe3, 0x53, -0xb1, 0x9e, 0x29, 0x88, 0x02, 0xf5, 0xc1, 0x9a, -0x59, 0x7a, 0x1e, 0x68, 0xcb, 0xbd, 0xd5, 0xee, -0xa0, 0x6c, 0x39, 0x9e, 0x4f, 0x81, 0xfa, 0x20, -0xc8, 0x5f, 0xc3, 0x76, 0xca, 0x32, 0x86, 0xb4, -0x4f, 0x03, 0xe7, 0x73, 0x85, 0xf1, 0x63, 0x5b, -0x1f, 0x71, 0x6e, 0x1c, 0xd2, 0x7e, 0x87, 0xfc, -0xf5, 0x20, 0xc0, 0x8f, 0x41, 0x3d, 0xcc, 0x01, -0xed, 0x11, 0x6b, 0x27, 0x19, 0x94, 0xed, 0x8b, -0xcf, 0xb0, 0x3e, 0xe8, 0xd7, 0x87, 0x57, 0xf7, -0xe0, 0xc7, 0xc4, 0x9f, 0x5f, 0x8a, 0x1c, 0x72, -0x4b, 0xfd, 0x71, 0xf4, 0x7c, 0xc6, 0xd9, 0xe0, -0xf9, 0x56, 0xf3, 0x45, 0x7d, 0x70, 0x0c, 0xde, -0x3f, 0x5f, 0xd9, 0xed, 0x4e, 0xa6, 0x93, 0xd6, -0x07, 0x6f, 0x7b, 0x5d, 0xc2, 0x3f, 0xfc, 0x3c, -0x91, 0x31, 0x43, 0x56, 0x43, 0xf5, 0x54, 0xf7, -0x57, 0x66, 0x0a, 0x47, 0xed, 0x15, 0xb3, 0x6a, -0xfc, 0x33, 0x81, 0xa4, 0x7c, 0xd4, 0x78, 0x2f, -0xa9, 0x0f, 0xe2, 0xe7, 0xab, 0x61, 0x32, 0x44, -0x1f, 0xa5, 0xb3, 0xfa, 0x20, 0x39, 0x66, 0x4e, -0xcb, 0x76, 0x78, 0xf5, 0xc1, 0x74, 0x48, 0x7d, -0x70, 0xa1, 0xa4, 0xcf, 0x41, 0xad, 0xa6, 0x31, -0x20, 0xc6, 0x86, 0x2b, 0xf4, 0x51, 0x85, 0x85, -0xfc, 0xfc, 0x0b, 0x5a, 0x1f, 0x84, 0xf3, 0xa3, -0xb4, 0x92, 0xf5, 0x41, 0x6d, 0x46, 0x27, 0xf3, -0x19, 0xa8, 0xfe, 0xfc, 0x0d, 0xa3, 0xed, 0x15, -0x08, 0xb4, 0xe4, 0xf9, 0x90, 0xa0, 0x5f, 0x20, -0x3d, 0x61, 0x2c, 0xc0, 0xd7, 0xbf, 0xa2, 0x73, -0xd5, 0xa9, 0x6a, 0xa5, 0x3e, 0xaa, 0x28, 0xdd, -0x0f, 0xa8, 0xc1, 0xe9, 0x6c, 0xc4, 0xc6, 0x62, -0x27, 0x83, 0x81, 0xe2, 0xa2, 0xae, 0x20, 0xfe, -0x99, 0x35, 0x21, 0xfe, 0xe9, 0xdf, 0x95, 0x37, -0xa6, 0x9f, 0x74, 0xeb, 0x65, 0x0b, 0x94, 0xf8, -0x67, 0x53, 0xbd, 0xa7, 0x8f, 0x5a, 0x8d, 0x61, -0xcf, 0x01, 0xb3, 0xc9, 0xca, 0x34, 0xe0, 0xcb, -0x26, 0xfd, 0x71, 0x09, 0x01, 0x84, 0x34, 0x70, -0x3e, 0x6c, 0xad, 0x8c, 0x7f, 0x2c, 0x7a, 0x90, -0xee, 0x7f, 0xa3, 0xf6, 0x71, 0x09, 0xff, 0xcc, -0x63, 0xfb, 0x35, 0x74, 0x89, 0x9d, 0x7e, 0xcc, -0x62, 0x83, 0x92, 0x26, 0x13, 0x4a, 0xfc, 0x73, -0xc2, 0xf0, 0xf5, 0xdb, 0x26, 0xac, 0x38, 0xf9, -0x24, 0x73, 0xc2, 0xe8, 0xe9, 0x60, 0xf1, 0x24, -0xbe, 0x1f, 0xd6, 0x07, 0x4d, 0x88, 0xee, 0x66, -0xd7, 0x6d, 0x4e, 0x53, 0x63, 0xca, 0x50, 0xe2, -0x9f, 0x2e, 0x5d, 0xee, 0x3e, 0x98, 0x6c, 0x6c, -0xd5, 0xf6, 0xd1, 0x4f, 0x0c, 0x35, 0xfe, 0xd1, -0x65, 0x7d, 0x78, 0xa1, 0xfa, 0x23, 0x6a, 0xb4, -0xda, 0x99, 0x08, 0xfa, 0x28, 0x72, 0x50, 0xd1, -0x56, 0x05, 0x10, 0x7a, 0x46, 0x5d, 0x1f, 0xfc, -0x14, 0xb5, 0x6e, 0xca, 0xfc, 0x43, 0xdc, 0x1d, -0x0b, 0x59, 0x13, 0xa9, 0x3e, 0x98, 0x33, 0x76, -0x6a, 0x53, 0xc6, 0x76, 0x74, 0xe7, 0xfd, 0x86, -0x84, 0x7f, 0xd8, 0x1f, 0xab, 0x0f, 0xba, 0xf3, -0xb1, 0x2d, 0xbc, 0x9e, 0x0e, 0x8a, 0x5c, 0x4b, -0x85, 0xcd, 0x0a, 0xfc, 0x93, 0x82, 0xf5, 0x41, -0x32, 0x16, 0xc0, 0x20, 0x63, 0x01, 0xb6, 0x22, -0x7a, 0x50, 0x91, 0xa2, 0x3e, 0xb8, 0xf9, 0x26, -0xb6, 0x29, 0xaa, 0xbe, 0x5e, 0x46, 0xfb, 0xd3, -0xe9, 0x7c, 0x00, 0xd8, 0xa8, 0x75, 0x66, 0xbe, -0x52, 0x1f, 0x75, 0xc9, 0x1d, 0x44, 0x46, 0xc7, -0x1e, 0xc2, 0x46, 0xb9, 0xc5, 0x50, 0x1f, 0x45, -0x3e, 0x5c, 0xe3, 0x76, 0xd3, 0xe3, 0xf8, 0xfc, -0x48, 0x82, 0x08, 0xcb, 0xdf, 0x44, 0xed, 0xf7, -0x25, 0x94, 0xf8, 0xa7, 0x1e, 0x81, 0xfe, 0xb8, -0x8b, 0x68, 0x8d, 0x99, 0x29, 0x68, 0x45, 0x32, -0x16, 0xd2, 0x34, 0xd4, 0xf5, 0x41, 0x24, 0xd5, -0x07, 0x53, 0x79, 0x7c, 0x1b, 0x8c, 0xd3, 0xb1, -0x90, 0x86, 0x1a, 0xff, 0xd4, 0x8a, 0xfe, 0x38, -0x0c, 0x3b, 0x2b, 0xf2, 0xd8, 0x9f, 0xe3, 0xda, -0x76, 0x24, 0x0b, 0xd5, 0x64, 0x7d, 0xd4, 0x08, -0xbd, 0x48, 0xfa, 0x6d, 0xb3, 0xd5, 0xba, 0xd3, -0xfb, 0xff, 0xcd, 0x28, 0xf1, 0xcf, 0x84, 0xbf, -0x5e, 0x5c, 0xf3, 0x8f, 0x9e, 0x11, 0x5e, 0x1f, -0x9c, 0x66, 0xf8, 0x67, 0x1a, 0xe3, 0x9f, 0x95, -0xb4, 0x3e, 0x68, 0xb4, 0x19, 0x19, 0x25, 0xfe, -0x91, 0xf4, 0x51, 0x87, 0x9c, 0x55, 0xcf, 0x19, -0x64, 0x3e, 0xe4, 0x68, 0x6a, 0xd5, 0xa0, 0xa1, -0xd6, 0x47, 0xe9, 0x72, 0xf5, 0xbc, 0x68, 0x34, -0x3d, 0x89, 0x0d, 0x87, 0x18, 0xde, 0x8b, 0xc3, -0xfa, 0xa6, 0xb4, 0xc0, 0x3f, 0xc8, 0x04, 0xd5, -0xb1, 0x83, 0xd6, 0xca, 0x31, 0x23, 0x97, 0x3a, -0x6d, 0x1f, 0x44, 0x2b, 0x7b, 0x81, 0x50, 0x6a, -0x91, 0xc0, 0x3f, 0xc6, 0xce, 0x87, 0x05, 0xda, -0xf9, 0x2f, 0x57, 0x16, 0xf5, 0x1b, 0xe7, 0x82, -0xdd, 0x5a, 0x4c, 0xa8, 0xf1, 0x4f, 0xdd, 0x3e, -0x31, 0x5d, 0xf6, 0x22, 0x89, 0x4e, 0x83, 0xd4, -0x58, 0x63, 0x87, 0xe8, 0xa3, 0xfa, 0x46, 0x4d, -0x6f, 0x9a, 0x0d, 0xed, 0x6f, 0x2a, 0x24, 0x26, -0x68, 0xda, 0x6a, 0x29, 0xe8, 0x6e, 0xfe, 0xba, -0x8b, 0xe2, 0x1f, 0x51, 0x8f, 0xf3, 0xc5, 0x1f, -0xbb, 0x3a, 0x47, 0x81, 0xcd, 0x0f, 0x4c, 0x03, -0x54, 0x0c, 0x85, 0x3e, 0xca, 0x5f, 0x1f, 0x1c, -0x34, 0xf2, 0x9a, 0x3b, 0xd8, 0x7f, 0x81, 0xb2, -0x3e, 0x68, 0xf9, 0xe2, 0x8f, 0xdd, 0x48, 0x07, -0xb5, 0xa1, 0x46, 0xf4, 0x83, 0x10, 0x7d, 0x14, -0x17, 0x75, 0xd3, 0xfc, 0xe5, 0x18, 0x36, 0x0e, -0xb3, 0x97, 0xf1, 0x8d, 0xe4, 0xbd, 0x51, 0x52, -0xe9, 0xc5, 0x84, 0xe8, 0x47, 0x58, 0x08, 0xfb, -0x07, 0xc9, 0xc1, 0x9d, 0x7d, 0x54, 0x28, 0x85, -0xe3, 0xc9, 0x50, 0x4c, 0xd4, 0x07, 0xf9, 0xfd, -0xbf, 0x9c, 0xe2, 0x1f, 0x6f, 0x3e, 0x00, 0x99, -0x97, 0x98, 0x20, 0xf9, 0xee, 0xa4, 0xdd, 0x96, -0x8f, 0x50, 0x1f, 0x24, 0xe7, 0xb9, 0x37, 0x3e, -0x85, 0x8d, 0x5f, 0xe4, 0xb3, 0x79, 0x50, 0x1f, -0x5c, 0x04, 0xf1, 0x4f, 0xb7, 0x09, 0xdf, 0xee, -0x0b, 0xf7, 0xf5, 0x6b, 0x03, 0xa8, 0x3f, 0x95, -0xed, 0x8f, 0xa4, 0x8f, 0xca, 0xa6, 0xfa, 0x51, -0xc5, 0x09, 0xf2, 0xfe, 0x85, 0xfe, 0x54, 0x5d, -0x1f, 0x84, 0xfa, 0x28, 0x52, 0x1f, 0xac, 0x20, -0xfe, 0x99, 0x08, 0xaf, 0x0f, 0xfe, 0x5c, 0xaa, -0x06, 0xde, 0xed, 0x54, 0x93, 0xfd, 0x9e, 0xf7, -0x09, 0xa5, 0x44, 0x7d, 0xd0, 0x79, 0x42, 0xd6, -0x47, 0xa5, 0xca, 0xcc, 0x87, 0x1c, 0x93, 0xf5, -0x51, 0xd9, 0x14, 0x19, 0xe4, 0x18, 0xe4, 0x7f, -0xf8, 0x7c, 0xda, 0xe3, 0x68, 0xc0, 0x84, 0xf7, -0x03, 0x52, 0xea, 0x75, 0x05, 0xfe, 0x29, 0x72, -0xfc, 0xe3, 0x7a, 0x0f, 0xa9, 0xe7, 0x43, 0xf2, -0xfc, 0xb8, 0xd6, 0xa7, 0x8f, 0xba, 0x41, 0xa9, -0x97, 0x0b, 0x9f, 0x8f, 0x6d, 0xab, 0xf5, 0x63, -0xa1, 0xf3, 0x91, 0x72, 0xca, 0xdf, 0x0f, 0xc3, -0x3f, 0x66, 0xc8, 0x7c, 0x48, 0x81, 0x7f, 0x26, -0xa4, 0xf8, 0x63, 0xca, 0x6e, 0x01, 0xfd, 0x71, -0xec, 0x7e, 0x9b, 0x95, 0xf4, 0x51, 0x4f, 0xc8, -0x34, 0x88, 0xc0, 0x3f, 0x7c, 0x3e, 0x76, 0xa7, -0xd1, 0x65, 0x09, 0x35, 0x78, 0xaa, 0xd5, 0x56, -0xce, 0x87, 0x7c, 0x5f, 0xcc, 0xc7, 0xae, 0xfb, -0xa5, 0x59, 0xde, 0x3f, 0x62, 0x3e, 0x76, 0x23, -0xc4, 0x3f, 0x5f, 0xda, 0x4d, 0x84, 0xff, 0x39, -0x13, 0xc0, 0xe7, 0x80, 0xff, 0xa9, 0x0f, 0xf2, -0x3f, 0x73, 0xe8, 0x3f, 0xfc, 0xfc, 0x8f, 0xd0, -0x3f, 0xf8, 0xf8, 0x9f, 0x7c, 0x19, 0xfe, 0x67, -0x93, 0x1c, 0x7f, 0x1a, 0x66, 0x29, 0xff, 0xe3, -0x9f, 0xb7, 0x20, 0xfa, 0xd7, 0xa6, 0xeb, 0x24, -0x35, 0x78, 0xcb, 0x9e, 0x84, 0xe0, 0x7f, 0x60, -0x7f, 0x1c, 0xbb, 0xfe, 0xce, 0x98, 0x8c, 0x7f, -0xf4, 0x10, 0x7d, 0x38, 0xbb, 0x7e, 0xbf, 0x3e, -0x5c, 0xad, 0x7f, 0x0e, 0xc3, 0x3f, 0x76, 0x56, -0xad, 0x4f, 0x16, 0xfc, 0x4f, 0x40, 0x1f, 0xa5, -0x34, 0x4e, 0xaa, 0xf1, 0xcf, 0xb0, 0x2d, 0x8f, -0x45, 0xe2, 0x78, 0x40, 0xcc, 0xc7, 0xde, 0xec, -0x9f, 0x0f, 0x10, 0xb5, 0x3f, 0x8e, 0xd0, 0x20, -0xb4, 0x3f, 0x4e, 0xb1, 0xdf, 0x15, 0xca, 0xf9, -0xd8, 0x04, 0xff, 0x78, 0x86, 0x9f, 0xff, 0x01, -0xfd, 0x71, 0xf5, 0x41, 0x35, 0x78, 0x91, 0xcd, -0x47, 0x12, 0xf3, 0x01, 0x2a, 0x42, 0xf0, 0x8f, -0x6b, 0x14, 0x4a, 0xf0, 0x3f, 0xfa, 0x1e, 0xbf, -0xf7, 0xd2, 0xe3, 0x81, 0xf9, 0x48, 0xd2, 0x7c, -0x6c, 0x43, 0xe8, 0xc3, 0xf9, 0xf5, 0xfb, 0xf9, -0x1f, 0xbe, 0x5f, 0xa2, 0x8f, 0x1a, 0x41, 0x21, -0xb7, 0x01, 0xe7, 0x7f, 0xce, 0x82, 0xfb, 0x07, -0xf0, 0x3f, 0xd3, 0x7c, 0x50, 0xa4, 0xcf, 0xff, -0x21, 0xf3, 0xb1, 0x47, 0x7d, 0xb4, 0x0f, 0x33, -0xee, 0x07, 0xfd, 0x71, 0x22, 0xfe, 0x0c, 0xa0, -0x5d, 0x34, 0xfe, 0x54, 0xb8, 0x13, 0x5d, 0x3c, -0xbd, 0x4a, 0xb7, 0x23, 0xe9, 0xc3, 0x6d, 0x88, -0x7f, 0x5e, 0xa2, 0x46, 0xfa, 0xb4, 0xfd, 0xf7, -0xbe, 0xe7, 0x57, 0xf4, 0x43, 0xf5, 0xf7, 0x3f, -0xcc, 0xf9, 0x1f, 0xf4, 0x09, 0x1b, 0x94, 0xed, -0xe7, 0x7f, 0xc0, 0x7c, 0xec, 0x3a, 0x39, 0xbf, -0x93, 0x6c, 0x0e, 0xe2, 0xed, 0x07, 0xac, 0xdf, -0x84, 0xc7, 0x07, 0xa8, 0x0f, 0xbf, 0x32, 0xd8, -0x5e, 0xac, 0xb9, 0x18, 0xbf, 0x06, 0xf3, 0xd7, -0xaa, 0xa9, 0xe4, 0x25, 0x38, 0x1f, 0xdb, 0x00, -0xfc, 0xcf, 0x21, 0xb4, 0xf2, 0x35, 0x02, 0x7b, -0x82, 0xe7, 0x83, 0x88, 0xf9, 0xd8, 0x82, 0xff, -0x79, 0x1e, 0xc3, 0xa4, 0x3f, 0x97, 0x64, 0x60, -0xae, 0xb1, 0xbe, 0x27, 0x0d, 0xe7, 0x03, 0x80, -0xf8, 0x33, 0xec, 0x7b, 0xed, 0x02, 0xfd, 0x71, -0xfc, 0x7a, 0x44, 0xfe, 0xda, 0x47, 0xf6, 0x5b, -0xac, 0x01, 0x63, 0x91, 0x54, 0xf3, 0x01, 0x62, -0x92, 0x7e, 0x3e, 0xa4, 0x5f, 0xac, 0xe8, 0xc3, -0x3f, 0x5e, 0xf4, 0x9e, 0x0b, 0x9b, 0x0f, 0x29, -0xe6, 0x63, 0xef, 0x42, 0x0c, 0xff, 0xe0, 0xeb, -0x19, 0xb2, 0x6e, 0x55, 0xe7, 0xaf, 0x90, 0xf9, -0xd8, 0x23, 0x46, 0xd9, 0xf9, 0x90, 0x95, 0x3a, -0xe8, 0x8f, 0xdb, 0xef, 0xa3, 0xc5, 0x04, 0xfe, -0x11, 0xf3, 0xb1, 0x6f, 0xea, 0x86, 0xfb, 0xa5, -0xf3, 0x21, 0x83, 0xfe, 0x71, 0x56, 0x70, 0xfc, -0xf3, 0xcf, 0x7c, 0x53, 0xe4, 0x7c, 0xd8, 0xbb, -0x95, 0xfb, 0xfd, 0x63, 0xf1, 0x3c, 0xfe, 0x0f, -0x7b, 0xd7, 0x1e, 0x1c, 0xc5, 0x71, 0xe6, 0x7b, -0x1e, 0x2b, 0x8d, 0xb4, 0x2b, 0x34, 0x7a, 0x2c, -0xac, 0x1d, 0x20, 0xa3, 0x07, 0xa0, 0x73, 0x84, -0x58, 0x0b, 0xbf, 0x72, 0x70, 0x30, 0x5a, 0x01, -0x11, 0x8f, 0x98, 0x8d, 0xc1, 0xa0, 0xa4, 0x54, -0x57, 0x63, 0x17, 0x55, 0xf1, 0x1f, 0x9c, 0x4b, -0x38, 0x57, 0x17, 0xe7, 0x1e, 0x76, 0xaf, 0x1e, -0x80, 0x2d, 0xe7, 0xbc, 0xc1, 0x9c, 0xad, 0x3b, -0x53, 0x75, 0x22, 0x21, 0x39, 0xd7, 0x95, 0xcf, -0x07, 0xc4, 0x0f, 0xce, 0x76, 0xd9, 0x23, 0x59, -0x38, 0x32, 0xa7, 0xc3, 0x9c, 0x8f, 0x72, 0x11, -0x9b, 0x32, 0xb2, 0x8b, 0x4a, 0x54, 0x65, 0xfb, -0xac, 0xe3, 0xc8, 0x19, 0x12, 0x1b, 0xae, 0x7b, -0x5e, 0xdd, 0x33, 0xd3, 0xbd, 0x3b, 0x6b, 0xec, -0x4b, 0x72, 0xf6, 0xfe, 0xf5, 0x63, 0xb6, 0x19, -0x75, 0x7f, 0xdb, 0xf3, 0xf5, 0x6f, 0xbe, 0xa7, -0x59, 0x15, 0x66, 0x3b, 0x05, 0xf3, 0xe3, 0xc0, -0x13, 0x72, 0x90, 0xed, 0x14, 0xac, 0x8f, 0x24, -0x4f, 0x86, 0xac, 0x7f, 0x36, 0x78, 0xd4, 0xc7, -0xf7, 0x98, 0xf9, 0x71, 0x5c, 0xe0, 0xeb, 0x8f, -0xa6, 0x04, 0xa4, 0xd1, 0xe4, 0x02, 0x52, 0x38, -0xcb, 0xf4, 0xd5, 0x07, 0x78, 0xd1, 0x2f, 0x0d, -0x31, 0xbc, 0x1f, 0x0a, 0xd7, 0x87, 0x0c, 0x83, -0x42, 0xf5, 0x21, 0x83, 0x60, 0xb4, 0x50, 0x7d, -0x48, 0x47, 0x50, 0xc4, 0x22, 0xed, 0xf2, 0x1f, -0xf7, 0xf7, 0x0d, 0xf8, 0xbf, 0x58, 0xe0, 0x4b, -0x9c, 0xfe, 0xb0, 0x7e, 0xda, 0x33, 0xce, 0xa9, -0x0f, 0x99, 0x7c, 0x3e, 0x24, 0x0d, 0xaa, 0xc2, -0x7c, 0xe1, 0xfa, 0x48, 0xb8, 0x2c, 0xc3, 0x2e, -0x96, 0x7c, 0xb8, 0xfd, 0xd1, 0x22, 0xd6, 0xc7, -0xa6, 0x56, 0xb7, 0xde, 0xb2, 0xff, 0x44, 0xa8, -0x0f, 0xc9, 0x78, 0xac, 0x8a, 0xd7, 0x07, 0xe0, -0x00, 0x5e, 0x7d, 0x48, 0x1e, 0x28, 0x54, 0x1f, -0x80, 0xcd, 0x7f, 0xdc, 0xf1, 0xe1, 0xfa, 0x00, -0xa5, 0xd5, 0x47, 0x2a, 0xad, 0x3e, 0x76, 0x84, -0xfa, 0x00, 0x91, 0xf8, 0x0f, 0xc7, 0xff, 0xc5, -0x03, 0x9d, 0xdc, 0xfa, 0x90, 0x14, 0xa0, 0xeb, -0x2b, 0xf2, 0xfa, 0xa3, 0xf1, 0x00, 0xab, 0x3e, -0x92, 0xb3, 0xba, 0x47, 0xd9, 0xeb, 0xf5, 0xe6, -0x13, 0xea, 0x8f, 0x16, 0x00, 0xb3, 0x02, 0xf5, -0x91, 0x82, 0xfd, 0xd1, 0x82, 0xf3, 0x9f, 0x6f, -0xf3, 0x1f, 0x77, 0x7f, 0xfa, 0xfb, 0xa3, 0xf1, -0x00, 0xb1, 0x3f, 0x14, 0xad, 0x0f, 0x70, 0x03, -0xa7, 0x3f, 0x1a, 0x2b, 0x2d, 0x8e, 0xaa, 0x0f, -0xe0, 0x7e, 0xc2, 0xf5, 0x01, 0x02, 0xc0, 0xaa, -0x57, 0x43, 0xea, 0x63, 0x6b, 0x42, 0xd8, 0xdb, -0x15, 0x06, 0x94, 0xff, 0x4b, 0x99, 0x5f, 0xc1, -0x2d, 0x0b, 0x80, 0xc1, 0xf5, 0x08, 0x34, 0x1d, -0xe3, 0xd5, 0x07, 0xb8, 0x87, 0xad, 0x6f, 0x29, -0xff, 0x57, 0x32, 0xca, 0xf9, 0x75, 0x82, 0xd4, -0x47, 0xba, 0x8a, 0xd2, 0x3f, 0xbf, 0xa4, 0x0a, -0xd5, 0x8e, 0xf3, 0xeb, 0x63, 0x17, 0x5f, 0x2f, -0xe5, 0xff, 0x92, 0x29, 0xe9, 0x05, 0xdd, 0xee, -0x93, 0x4e, 0x04, 0x3e, 0x65, 0x7f, 0x6e, 0x09, -0xd5, 0x87, 0x0c, 0x82, 0xd1, 0x8d, 0x07, 0xeb, -0x8e, 0xb1, 0xeb, 0x23, 0xf9, 0xf2, 0xe5, 0x37, -0x52, 0xff, 0x91, 0xd1, 0x1f, 0x2d, 0x44, 0x03, -0xbe, 0x4c, 0xae, 0xd4, 0x11, 0xfb, 0x0f, 0xae, -0x0f, 0xb0, 0x8c, 0x79, 0x7e, 0x49, 0x1c, 0xff, -0xd7, 0x76, 0xf0, 0x68, 0xa1, 0xf3, 0x6e, 0x56, -0xc0, 0xfe, 0x03, 0xc2, 0xd9, 0x61, 0x0c, 0xfe, -0x43, 0xec, 0x3f, 0x4a, 0x38, 0x5a, 0xfe, 0xbd, -0x70, 0x7c, 0xb8, 0xe8, 0xf1, 0x9f, 0x79, 0xbc, -0xf5, 0x7a, 0xe0, 0xc1, 0x19, 0x69, 0xba, 0x9c, -0x97, 0x1f, 0x17, 0xb9, 0x3f, 0x48, 0x54, 0xfe, -0xc3, 0xa8, 0x8f, 0xcd, 0x5a, 0xef, 0x15, 0xf0, -0x9f, 0x08, 0xfc, 0x64, 0x82, 0x57, 0x1f, 0x9b, -0x03, 0x3e, 0x4b, 0xfe, 0x53, 0xa0, 0x3e, 0x24, -0x17, 0xcc, 0x94, 0xc2, 0x7f, 0xf8, 0xf5, 0x21, -0xb9, 0xe0, 0x8d, 0x02, 0xf5, 0xb1, 0x99, 0xf6, -0x1f, 0x9a, 0xff, 0x84, 0xba, 0xf5, 0x7d, 0x9a, -0xfc, 0x67, 0x14, 0x44, 0x59, 0x2f, 0xc5, 0x7f, -0xf6, 0x7e, 0xbe, 0xf9, 0x0f, 0xa7, 0x9f, 0xc5, -0x27, 0xe6, 0x3f, 0x47, 0xfc, 0xfc, 0x67, 0xfe, -0xa7, 0xc2, 0x7f, 0xa8, 0xfa, 0x48, 0xc3, 0x5c, -0xfe, 0x53, 0xfd, 0xa9, 0xf0, 0x1f, 0x10, 0xe4, -0x3f, 0xc5, 0xfa, 0x83, 0xd4, 0x14, 0xe1, 0x3f, -0xc1, 0xfe, 0xb0, 0xc9, 0x28, 0xf3, 0xa7, 0xf8, -0x8f, 0xf0, 0x29, 0xf3, 0x9f, 0xc8, 0xf9, 0x71, -0x9f, 0x90, 0xff, 0xb4, 0xfa, 0xed, 0x3f, 0xfb, -0x69, 0xfe, 0x13, 0x0c, 0xdb, 0x63, 0xf0, 0x1f, -0x5f, 0x7d, 0x48, 0x2e, 0xe0, 0xf2, 0x1f, 0x0e, -0x20, 0xfc, 0xc7, 0xa4, 0xfa, 0xa3, 0x45, 0xe2, -0x3f, 0x91, 0xf4, 0x0f, 0xe1, 0x3f, 0xaa, 0xdb, -0x1f, 0xb6, 0x30, 0xff, 0xf1, 0x7e, 0x2f, 0x23, -0xd2, 0xfb, 0x17, 0xe1, 0x3f, 0x46, 0x98, 0xff, -0x88, 0xe1, 0xf5, 0x1e, 0xf7, 0xe6, 0x33, 0xc0, -0xc8, 0x8f, 0xa3, 0x81, 0x1c, 0xb0, 0xff, 0x98, -0x5c, 0xfe, 0xe3, 0xf3, 0x7f, 0x6d, 0xa3, 0xf9, -0x4f, 0xf1, 0xf3, 0xab, 0x40, 0x7e, 0x5c, 0x18, -0xac, 0x3f, 0x58, 0xcb, 0x8b, 0xff, 0xe1, 0xf2, -0x01, 0x6f, 0x7f, 0xc2, 0x2a, 0x1e, 0xff, 0x89, -0x10, 0xff, 0xc3, 0x03, 0x75, 0xd3, 0x22, 0xc5, -0x7f, 0x14, 0x7b, 0x93, 0x74, 0xd2, 0x81, 0x40, -0xda, 0xd2, 0xf1, 0x04, 0x93, 0xff, 0x8c, 0x0d, -0x33, 0x69, 0x8f, 0xd9, 0x74, 0x42, 0xe1, 0xf9, -0xbf, 0x58, 0xcb, 0xd4, 0xb5, 0x6e, 0xda, 0x30, -0xc8, 0x8a, 0xff, 0xf1, 0x8b, 0xf1, 0x87, 0x3a, -0x5d, 0x68, 0x88, 0xef, 0xff, 0xb2, 0xc1, 0x7f, -0x83, 0x5e, 0x9d, 0x2e, 0xa4, 0xf9, 0xef, 0x45, -0xfb, 0xc3, 0xae, 0xf0, 0xfb, 0x07, 0x8b, 0xf2, -0x9f, 0x76, 0x93, 0x8e, 0x6f, 0x99, 0x09, 0xf9, -0xbf, 0x24, 0xdf, 0xfc, 0x5f, 0x1c, 0x69, 0x7f, -0x9d, 0x9e, 0x3f, 0x5d, 0x1f, 0x89, 0xa9, 0x7f, -0xa0, 0x36, 0x45, 0xcb, 0x87, 0xf4, 0x87, 0xbd, -0x10, 0xa8, 0x0f, 0xe0, 0x82, 0xfd, 0x53, 0x74, -0x3c, 0x8c, 0xcf, 0xff, 0xe5, 0x06, 0xf9, 0xf8, -0x68, 0x4f, 0xda, 0x2e, 0x94, 0xed, 0xd9, 0x7f, -0x28, 0xff, 0x17, 0x53, 0x3e, 0xcb, 0x7c, 0xfe, -0x62, 0xe2, 0xff, 0x0a, 0xc4, 0xff, 0x38, 0xe0, -0x43, 0xd0, 0xde, 0xed, 0xd3, 0x57, 0x5e, 0xfd, -0xcf, 0xc9, 0x14, 0x53, 0xff, 0xc0, 0x86, 0x8c, -0xdf, 0xff, 0xe5, 0xca, 0x33, 0x54, 0x1f, 0x80, -0x34, 0x8a, 0x65, 0xfa, 0xbf, 0xb6, 0xcb, 0xcc, -0xfd, 0x06, 0x1a, 0xcf, 0xfa, 0xf4, 0x0f, 0xcf, -0xff, 0xe5, 0x80, 0x73, 0x80, 0x34, 0x8a, 0xcd, -0x15, 0xf4, 0x7f, 0xb9, 0xe0, 0x85, 0x48, 0xfe, -0x2f, 0x0f, 0xe4, 0xdb, 0x75, 0x2a, 0xbe, 0xa5, -0xbc, 0x40, 0x7d, 0x00, 0x07, 0x88, 0x77, 0xb7, -0x94, 0xe2, 0xff, 0xd2, 0x17, 0xfa, 0x0a, 0x65, -0xf3, 0xfc, 0x5f, 0x04, 0x34, 0x3b, 0x85, 0xb2, -0x25, 0xab, 0x94, 0x74, 0x71, 0xff, 0xd7, 0xd3, -0x76, 0x20, 0x90, 0x13, 0x1a, 0xc4, 0xf6, 0x7f, -0x51, 0x40, 0x5f, 0xe6, 0x2b, 0x94, 0x4d, 0xf9, -0xbf, 0xa8, 0xf1, 0x2a, 0x71, 0x84, 0xc1, 0x95, -0xbd, 0x74, 0xfc, 0x0f, 0xb3, 0x3e, 0xa4, 0xe1, -0xa3, 0x3d, 0x5a, 0x4b, 0x74, 0xff, 0x17, 0x38, -0x14, 0x28, 0x0c, 0xc5, 0x8c, 0xff, 0xf1, 0xff, -0x10, 0xe3, 0x0a, 0xdb, 0xff, 0xc5, 0xe3, 0x6f, -0x86, 0x2f, 0xfe, 0x87, 0xf8, 0xbf, 0x6a, 0xd8, -0xfc, 0x67, 0xf9, 0xed, 0x4b, 0xa8, 0x2b, 0x4c, -0xff, 0x57, 0x80, 0xf6, 0xd0, 0xf1, 0x3f, 0x2c, -0xff, 0x17, 0xa0, 0x68, 0xcf, 0x0b, 0xea, 0x92, -0x7c, 0x0b, 0xbb, 0x3e, 0xa4, 0xa7, 0x7f, 0x74, -0x9f, 0x7e, 0x6e, 0x9d, 0xa1, 0xf5, 0x0f, 0xc7, -0xff, 0x45, 0x80, 0xb2, 0x38, 0xdb, 0xc2, 0xf3, -0x7f, 0x31, 0x69, 0xcf, 0xf2, 0xa9, 0x56, 0xae, -0xff, 0xeb, 0x2f, 0x02, 0xa7, 0xb9, 0xa5, 0x46, -0x74, 0x9f, 0x3e, 0x21, 0xef, 0xbf, 0x7b, 0x5f, -0x08, 0x55, 0x33, 0xbe, 0x04, 0x2e, 0xc1, 0x9f, -0x4e, 0xd1, 0xe7, 0x97, 0x49, 0xf8, 0xa7, 0x9d, -0x7f, 0x31, 0xea, 0x9f, 0xff, 0xd3, 0xa0, 0x69, -0x55, 0x8b, 0x8f, 0xff, 0xb8, 0xe3, 0xd9, 0xf6, -0x9f, 0xa7, 0x41, 0x83, 0x4e, 0x17, 0x86, 0xa2, -0xeb, 0x43, 0xb2, 0xf4, 0xcf, 0x61, 0x2f, 0xf1, -0xc7, 0xbe, 0xf2, 0x0a, 0x55, 0x1f, 0x20, 0xe4, -0xbf, 0x60, 0x9c, 0x2f, 0x1c, 0xff, 0x17, 0xed, -0x28, 0xf4, 0x05, 0x66, 0x70, 0xfc, 0x5f, 0xa4, -0x50, 0x92, 0x89, 0x0b, 0x05, 0x30, 0xfd, 0x5f, -0x4c, 0xfe, 0xf3, 0x2f, 0x46, 0x5b, 0x96, 0x3e, -0xbf, 0x38, 0xfe, 0x2f, 0x0f, 0xa0, 0x6d, 0x66, -0xd2, 0xe3, 0xa9, 0xfa, 0xd8, 0xe1, 0xfa, 0x00, -0x96, 0x7c, 0x5a, 0x75, 0xaa, 0x90, 0x78, 0x86, -0xf2, 0x7f, 0xf1, 0xf8, 0x0f, 0xa0, 0xe5, 0x43, -0xea, 0x43, 0xee, 0x0f, 0xd6, 0x07, 0xb0, 0x03, -0xa1, 0x85, 0x60, 0x3d, 0x28, 0x86, 0xfd, 0xe7, -0x9e, 0xdf, 0x47, 0xfb, 0x4f, 0xb0, 0x3e, 0x12, -0x1b, 0x70, 0xfb, 0xa3, 0xfd, 0x5f, 0xd9, 0x7f, -0xe4, 0x2b, 0xb3, 0xff, 0x14, 0xf7, 0x7f, 0x55, -0x5d, 0x91, 0xfd, 0xa7, 0x50, 0x7f, 0xb4, 0xa2, -0xf6, 0x9f, 0x08, 0xf2, 0xf9, 0x14, 0xfd, 0x5f, -0xd1, 0xfa, 0xc3, 0x7e, 0x6e, 0xed, 0x3f, 0xbf, -0x1d, 0xff, 0x57, 0xe1, 0xfe, 0x68, 0x85, 0xec, -0x3f, 0x7c, 0xff, 0x17, 0x27, 0xfe, 0xe7, 0x4a, -0xfd, 0x5f, 0xd1, 0xfa, 0xc3, 0x46, 0xb6, 0xff, -0x90, 0xfa, 0x48, 0x62, 0x41, 0xfb, 0x8f, 0x67, -0x7f, 0x88, 0x68, 0xff, 0x71, 0xef, 0x7f, 0x85, -0xf5, 0xb1, 0xb9, 0xf6, 0x1f, 0xdd, 0x1b, 0x5f, -0x9a, 0xfd, 0x27, 0xd8, 0x1f, 0x8d, 0x0d, 0x38, -0xfd, 0x41, 0x4a, 0xaf, 0x8f, 0x5d, 0xd4, 0xfe, -0x13, 0xee, 0x8f, 0x16, 0xb1, 0x3f, 0x6c, 0x44, -0xfb, 0x0f, 0x9b, 0xff, 0x04, 0xe3, 0x9d, 0x0a, -0xf5, 0x47, 0x63, 0x01, 0x56, 0x7f, 0x34, 0x91, -0x0a, 0x84, 0x7e, 0x33, 0xa8, 0x3f, 0x0b, 0xf4, -0x47, 0x23, 0xa0, 0x9c, 0xc1, 0x7f, 0x28, 0xff, -0x57, 0x81, 0xc0, 0x06, 0x7e, 0x7f, 0xb4, 0x12, -0xed, 0x3f, 0x9c, 0x78, 0x21, 0x7e, 0x7f, 0x34, -0xdc, 0xbf, 0x32, 0x20, 0x1f, 0x89, 0x5b, 0x1f, -0x29, 0xd8, 0x36, 0x97, 0xc1, 0x7f, 0x22, 0xd9, -0x7f, 0xf8, 0xfd, 0x61, 0x09, 0xd8, 0x96, 0x38, -0x4f, 0x0a, 0x45, 0x06, 0xf9, 0xcf, 0x2c, 0x1f, -0xdb, 0xb9, 0x13, 0x3c, 0xd7, 0x77, 0x27, 0x54, -0x7e, 0x4c, 0x1a, 0x85, 0x14, 0xe3, 0x3f, 0x3f, -0xc2, 0xf9, 0x14, 0xb5, 0x5e, 0xa3, 0x90, 0x4c, -0x61, 0xfe, 0x63, 0xfd, 0x22, 0x3b, 0x5b, 0xf2, -0xa4, 0x51, 0x48, 0x71, 0xfe, 0xd3, 0x06, 0x13, -0x0f, 0xc5, 0xbd, 0x47, 0xa9, 0x28, 0xff, 0x91, -0x57, 0xc2, 0xea, 0xee, 0xf8, 0x5f, 0x96, 0xc0, -0x7f, 0x54, 0xc4, 0x3f, 0x5b, 0xd5, 0xa8, 0xfc, -0x07, 0xbd, 0xad, 0x29, 0x07, 0x2b, 0xed, 0xaf, -0x86, 0xa2, 0xf1, 0x1f, 0x45, 0xad, 0x2c, 0x21, -0xfe, 0x67, 0xc9, 0x54, 0xcb, 0x37, 0x49, 0xe3, -0x8c, 0x53, 0xaa, 0x7b, 0x7f, 0x3e, 0xff, 0x49, -0x1c, 0x8c, 0x27, 0xa2, 0xf3, 0x1f, 0x7f, 0x20, -0x59, 0x14, 0xfe, 0x93, 0xc8, 0xc7, 0x5b, 0x4b, -0xe1, 0x3f, 0x4a, 0xd6, 0x4b, 0xa4, 0x6d, 0x64, -0xf3, 0x9f, 0x94, 0x6f, 0xbd, 0x95, 0xcb, 0xc9, -0x7a, 0x23, 0xf0, 0x9f, 0x93, 0x95, 0xd7, 0x91, -0x78, 0xaa, 0xe2, 0xfc, 0x67, 0xc9, 0xc8, 0xac, -0x69, 0xa9, 0x85, 0xd8, 0x7f, 0xdc, 0xf9, 0x70, -0xf8, 0x8f, 0xb8, 0x02, 0x2c, 0x86, 0xfd, 0xa5, -0xf0, 0x9f, 0x4c, 0x62, 0x6f, 0xbc, 0x39, 0x3a, -0xff, 0x69, 0xc5, 0xf9, 0x47, 0xcd, 0xa5, 0xf0, -0x1f, 0x45, 0x25, 0xe3, 0x8b, 0xf3, 0x1f, 0xf4, -0x7e, 0x57, 0x5f, 0x89, 0xbe, 0x12, 0x23, 0xf3, -0x9f, 0x56, 0x2a, 0x11, 0xbb, 0x38, 0xff, 0xf9, -0x2b, 0xbd, 0xfa, 0x64, 0x49, 0xfc, 0x27, 0x5b, -0x7d, 0x5a, 0x6a, 0x2e, 0x81, 0xff, 0x68, 0xf1, -0xdd, 0xa4, 0x51, 0x48, 0x24, 0xfe, 0x53, 0x2f, -0xca, 0x25, 0xf0, 0x9f, 0xae, 0x38, 0x2d, 0xcf, -0x20, 0xff, 0xe9, 0x78, 0x30, 0x4c, 0x63, 0x86, -0x87, 0x9a, 0x4b, 0xe2, 0x3f, 0x7b, 0x4a, 0xe4, -0x3f, 0x03, 0x44, 0xfe, 0x2c, 0xfe, 0x93, 0x09, -0xd3, 0x9e, 0x96, 0x92, 0xf8, 0xcf, 0x4d, 0xe4, -0x79, 0x89, 0xc4, 0x7f, 0x66, 0xfa, 0xe6, 0xba, -0xa6, 0x95, 0x48, 0xfc, 0xa7, 0x3b, 0x6e, 0x7f, -0xb5, 0xf1, 0xee, 0x4e, 0x1e, 0xff, 0x21, 0xf6, -0x1f, 0x74, 0x0c, 0xd5, 0x97, 0xc8, 0x7f, 0x4e, -0x7b, 0xe7, 0x57, 0x53, 0x24, 0xfe, 0xe3, 0xe8, -0x9f, 0xf1, 0xf8, 0x8e, 0x28, 0xf1, 0x3f, 0x63, -0x48, 0xed, 0xcc, 0x8d, 0xce, 0x7f, 0xd0, 0x41, -0xd0, 0x6e, 0xc9, 0x73, 0x3b, 0x8f, 0xff, 0xf8, -0xf5, 0x27, 0x52, 0xb3, 0x4f, 0x5a, 0xfa, 0xf3, -0x1e, 0x7c, 0xe5, 0xdd, 0x48, 0xfc, 0x87, 0x65, -0xff, 0x61, 0xc5, 0xff, 0x58, 0x1a, 0x7e, 0x2c, -0x91, 0x95, 0x96, 0x83, 0x12, 0xf8, 0x4f, 0x65, -0x9e, 0x14, 0x7e, 0x8c, 0xe2, 0xff, 0x52, 0xe8, -0xf1, 0x7c, 0xfe, 0xe3, 0x81, 0x4a, 0xea, 0xbc, -0xe3, 0xf2, 0x1f, 0x0b, 0xd8, 0x12, 0x4b, 0xf4, -0x92, 0x42, 0xc4, 0x2c, 0xfe, 0xd3, 0xe9, 0x3f, -0xdf, 0xf9, 0xfc, 0x47, 0xbd, 0x0c, 0x6f, 0x8c, -0x1c, 0xff, 0x63, 0x62, 0xfe, 0x03, 0x1a, 0x8b, -0xd9, 0x7f, 0x3c, 0xfb, 0xf3, 0x44, 0xcc, 0x0b, -0xa2, 0x8b, 0x6a, 0xff, 0x11, 0x82, 0xd9, 0xee, -0x04, 0xb8, 0xa9, 0x76, 0xc4, 0xff, 0x65, 0xf1, -0x1f, 0x91, 0xd3, 0x46, 0x87, 0x61, 0xff, 0xe1, -0xf9, 0xbf, 0xa2, 0xe6, 0x7f, 0x15, 0xb3, 0xff, -0x9c, 0x62, 0xef, 0x87, 0x82, 0xf6, 0x9f, 0xe7, -0x8a, 0xbe, 0x2f, 0x50, 0xfe, 0xaf, 0x68, 0xf1, -0x3f, 0x94, 0xff, 0x2b, 0x9a, 0xfd, 0xc7, 0xf3, -0x7f, 0x05, 0xfa, 0xc3, 0x72, 0xec, 0x3f, 0xde, -0xf3, 0x18, 0xcd, 0xfe, 0xc3, 0xad, 0x8f, 0xcd, -0xb3, 0xff, 0x78, 0xfa, 0x0d, 0xfa, 0xed, 0x3f, -0x7f, 0x62, 0x81, 0x8a, 0x42, 0xfd, 0x41, 0x22, -0xf9, 0xdf, 0x41, 0x31, 0xfe, 0xc3, 0xcd, 0xff, -0x8a, 0x68, 0xff, 0x71, 0xe7, 0x1f, 0xd5, 0xfe, -0xe3, 0xce, 0xff, 0xb3, 0xb1, 0xff, 0x1c, 0xf7, -0xf3, 0x1f, 0xbd, 0x98, 0x3d, 0x84, 0xf8, 0xbf, -0x3e, 0x23, 0xfb, 0x8f, 0x3f, 0xff, 0x4b, 0x0f, -0x0c, 0x53, 0xbc, 0x0c, 0xa9, 0xef, 0x7d, 0x42, -0xfb, 0x0f, 0xf1, 0x7f, 0x61, 0xfe, 0xa3, 0x05, -0x96, 0x59, 0x11, 0xea, 0x0f, 0xe2, 0xed, 0x9f, -0xc2, 0xf6, 0x1f, 0x85, 0x95, 0xff, 0x45, 0xec, -0x3f, 0xdc, 0xc4, 0x2e, 0xc2, 0x7f, 0xa6, 0x23, -0xd9, 0x7f, 0xce, 0x95, 0x68, 0xff, 0xe1, 0xe4, -0x7f, 0x7d, 0x36, 0xf6, 0x1f, 0xa5, 0xf8, 0xf3, -0x4b, 0xfc, 0x5f, 0xd1, 0xec, 0x3f, 0xef, 0xd0, -0xfc, 0x47, 0xf9, 0x8d, 0x5a, 0x54, 0x9f, 0x10, -0x7e, 0x12, 0xbb, 0x24, 0x5c, 0xfe, 0xc1, 0xca, -0xa9, 0xf2, 0x22, 0xf6, 0x1f, 0x57, 0x3e, 0xbe, -0xfe, 0xb0, 0x7c, 0xfb, 0x0f, 0xc9, 0xff, 0xf2, -0xf3, 0x9f, 0x05, 0xec, 0xf1, 0x3e, 0xfe, 0xa3, -0x50, 0x61, 0xcf, 0x09, 0x8e, 0xfd, 0x87, 0xca, -0xff, 0x7a, 0x5c, 0x59, 0x49, 0x56, 0xb7, 0x90, -0x63, 0x3f, 0x27, 0xfc, 0x47, 0xbf, 0x72, 0xfe, -0x53, 0x28, 0xff, 0x0b, 0x46, 0xb2, 0xff, 0x14, -0xf3, 0x7f, 0xb9, 0x40, 0x29, 0xce, 0x7f, 0xd6, -0x87, 0xe4, 0xb3, 0x3e, 0xc0, 0x7f, 0x98, 0xfe, -0x41, 0x0c, 0xbc, 0x7c, 0x7f, 0x9a, 0xff, 0x7c, -0xfd, 0xa3, 0x9a, 0x52, 0xed, 0x3f, 0x97, 0xe0, -0xd2, 0xe6, 0xc4, 0x64, 0x79, 0x3b, 0x98, 0x84, -0xd7, 0x6a, 0x55, 0x93, 0xd2, 0xec, 0x22, 0xfe, -0xaf, 0x67, 0x61, 0x23, 0x50, 0xfa, 0x44, 0x6d, -0x64, 0xb7, 0x82, 0x00, 0xc8, 0x2c, 0xb4, 0x68, -0xcf, 0x2c, 0xae, 0xff, 0xeb, 0x59, 0xc1, 0x50, -0x94, 0x5a, 0x51, 0x86, 0x10, 0x34, 0x6a, 0x0a, -0xa8, 0x95, 0x83, 0xfb, 0x21, 0x60, 0xff, 0x79, -0x56, 0x46, 0xb7, 0x55, 0xc5, 0x55, 0x60, 0x37, -0x40, 0x00, 0xa2, 0xd7, 0xae, 0x82, 0xf1, 0xcf, -0xea, 0x6f, 0x40, 0xbb, 0xd1, 0xba, 0x5b, 0x6a, -0x04, 0xaf, 0xc0, 0xc3, 0x30, 0x71, 0xb0, 0xba, -0x25, 0x6c, 0x1f, 0x0b, 0xe4, 0x7f, 0xbd, 0xb8, -0xaa, 0x7a, 0x54, 0x3a, 0xa8, 0x7f, 0xac, 0xae, -0x84, 0xb3, 0x66, 0xe6, 0x5c, 0x08, 0x15, 0x12, -0x0f, 0xda, 0x7f, 0xfe, 0xdc, 0x48, 0x0c, 0x4b, -0x0b, 0xd5, 0x57, 0x60, 0x3b, 0x4c, 0x1c, 0x91, -0x5a, 0x42, 0xf9, 0xdd, 0x7e, 0xfb, 0x0f, 0x62, -0xfb, 0x86, 0x32, 0x8c, 0xa6, 0x7d, 0x1f, 0xd4, -0xa0, 0x72, 0xa4, 0xb6, 0xc5, 0x5f, 0x0f, 0x2a, -0x64, 0xff, 0x39, 0x0c, 0xae, 0x81, 0x8a, 0x26, -0x2a, 0xe0, 0x7e, 0xa0, 0xe1, 0xfe, 0x20, 0xb2, -0x2a, 0x59, 0x62, 0x51, 0x27, 0xdd, 0xd2, 0x01, -0x7e, 0xfb, 0xcf, 0xd3, 0x70, 0xf1, 0x88, 0x72, -0x87, 0xf8, 0x25, 0xb0, 0x13, 0xe7, 0x83, 0x77, -0x89, 0x37, 0x84, 0xf2, 0xc1, 0xfd, 0xfe, 0xaf, -0x73, 0xe0, 0x0f, 0x91, 0x58, 0xca, 0x5b, 0xc1, -0x31, 0x90, 0xd6, 0x13, 0x20, 0x2e, 0xe3, 0xfe, -0x20, 0x05, 0xfc, 0x5f, 0x97, 0x9c, 0xb6, 0x71, -0xc2, 0x25, 0x5c, 0x36, 0xc1, 0x94, 0xfe, 0xa7, -0xb8, 0xff, 0x6b, 0x2a, 0xf1, 0x58, 0x27, 0x12, -0x0b, 0xb4, 0xf2, 0x13, 0x8f, 0x89, 0x41, 0xf9, -0x84, 0xed, 0x3f, 0x2d, 0x46, 0x65, 0x4a, 0xdc, -0x05, 0xf6, 0x63, 0xed, 0x71, 0x0a, 0xec, 0x2a, -0xea, 0xff, 0x52, 0xee, 0x16, 0xe7, 0x83, 0x47, -0xec, 0xb0, 0x9f, 0x37, 0x42, 0xeb, 0x0d, 0xd8, -0x7f, 0xf4, 0x56, 0xb3, 0x0b, 0x67, 0xcf, 0x3d, -0x84, 0x89, 0xf4, 0x57, 0x6b, 0x5f, 0x31, 0x83, -0xfd, 0x56, 0x02, 0xf6, 0x1f, 0x75, 0x45, 0x3e, -0x31, 0x22, 0x29, 0xe0, 0x0d, 0xbd, 0x1d, 0x56, -0x1f, 0x90, 0xde, 0x65, 0xe4, 0xbf, 0xbb, 0xf3, -0x41, 0xfc, 0x47, 0xb5, 0xca, 0xfe, 0x58, 0x65, -0x00, 0x15, 0xab, 0x3f, 0xc8, 0x4c, 0x34, 0xff, -0xd7, 0x2f, 0x20, 0x4e, 0xeb, 0x4e, 0xb0, 0xf9, -0x8f, 0xdf, 0xfe, 0x73, 0x67, 0x36, 0xbe, 0x57, -0xfc, 0x25, 0xb8, 0x4f, 0x6f, 0xd3, 0x2b, 0xf7, -0xd6, 0x15, 0xe7, 0x3f, 0x4b, 0xf4, 0xf8, 0x09, -0xf1, 0x3c, 0xf8, 0x3e, 0x02, 0x0a, 0x06, 0xc5, -0xfc, 0x5f, 0x8b, 0x7b, 0xe3, 0x3d, 0xe2, 0x87, -0x60, 0xd0, 0x5c, 0x9c, 0xad, 0xec, 0x11, 0x4f, -0x16, 0xf5, 0x7f, 0xb5, 0x82, 0x6a, 0xd0, 0x64, -0x22, 0x35, 0xbf, 0x02, 0x87, 0xfd, 0x84, 0xd7, -0x5b, 0x38, 0xfe, 0x39, 0x7c, 0xe2, 0x07, 0xed, -0x3f, 0x2b, 0xf5, 0xc4, 0x49, 0xe9, 0x57, 0xb8, -0xfe, 0x8f, 0x99, 0x38, 0x21, 0x5d, 0xe7, 0x1f, -0xbf, 0x8b, 0x11, 0xff, 0xac, 0xe0, 0x6a, 0x36, -0xea, 0x11, 0xa4, 0x1f, 0xaa, 0xa0, 0x18, 0xea, -0x0f, 0xd2, 0x18, 0xb2, 0xff, 0x64, 0x70, 0xb4, -0x0f, 0x3c, 0x34, 0x4b, 0x43, 0xa0, 0x2f, 0x6c, -0x01, 0x0b, 0xda, 0x7f, 0x5a, 0xed, 0x6a, 0x3f, -0x87, 0x40, 0xa3, 0x5e, 0x91, 0x16, 0xc3, 0x8c, -0x28, 0x9c, 0xff, 0x95, 0xd8, 0x6b, 0x95, 0x79, -0x3c, 0x8c, 0x7f, 0xdf, 0x66, 0x06, 0xff, 0x71, -0xf7, 0xa7, 0x93, 0xff, 0x95, 0x59, 0x52, 0x90, -0xff, 0x30, 0xe2, 0x9f, 0x07, 0xe2, 0x0d, 0xe8, -0xd8, 0x64, 0xd7, 0x3f, 0xec, 0x0c, 0xe6, 0x7f, -0x2d, 0xf9, 0x61, 0x7c, 0x4a, 0xbc, 0x09, 0xfc, -0x35, 0x68, 0x43, 0x40, 0xba, 0x3b, 0xd0, 0x31, -0x96, 0x19, 0xff, 0x7c, 0x5d, 0x5f, 0x02, 0xf4, -0x83, 0xb6, 0xa9, 0xf5, 0xe9, 0x5a, 0xa5, 0x00, -0xff, 0x71, 0xf2, 0xbf, 0x74, 0xdc, 0xa6, 0xb9, -0x66, 0xd0, 0x36, 0x9b, 0x74, 0x17, 0xce, 0xff, -0x42, 0x24, 0x67, 0xf1, 0x48, 0xf5, 0xb4, 0xd4, -0x0e, 0x5e, 0xc6, 0x6c, 0x67, 0x5a, 0xba, 0xba, -0x78, 0xfc, 0x33, 0x5e, 0xdd, 0x7b, 0xb8, 0xed, -0xb2, 0x89, 0xc0, 0x74, 0x01, 0xff, 0x17, 0xce, -0xff, 0x3a, 0x43, 0x9f, 0x56, 0xb3, 0x2e, 0x48, -0xbf, 0x0e, 0x9d, 0x5f, 0xa1, 0xfc, 0xaf, 0x71, -0xdc, 0x9f, 0x5a, 0x7f, 0x0a, 0x2c, 0x19, 0x55, -0xb2, 0x48, 0xff, 0x78, 0xf3, 0xf7, 0xea, 0x1f, -0xba, 0xf7, 0xc7, 0xfc, 0xc7, 0xf1, 0x76, 0x9d, -0xc0, 0xf9, 0xf2, 0x66, 0xa5, 0x21, 0xfe, 0xbc, -0x50, 0xfc, 0xb3, 0x9b, 0xff, 0xa5, 0x22, 0xe9, -0x1d, 0xc4, 0x66, 0x10, 0x80, 0xa4, 0x41, 0xe4, -0x69, 0x37, 0x42, 0x3d, 0xe5, 0xcb, 0xff, 0x7a, -0x93, 0xf8, 0xbf, 0xac, 0x42, 0xbb, 0xef, 0x42, -0x7e, 0xfc, 0xb3, 0x63, 0xff, 0xd1, 0xed, 0x6f, -0x75, 0xeb, 0x5b, 0x4a, 0x3e, 0x76, 0x46, 0x58, -0xd3, 0xdb, 0x41, 0xfe, 0x03, 0xab, 0xa7, 0x84, -0x19, 0x2c, 0x8d, 0xe9, 0xaa, 0xf3, 0x12, 0x3e, -0xef, 0x96, 0xf8, 0xf4, 0x39, 0x95, 0xff, 0x65, -0xe7, 0xbf, 0x83, 0xf5, 0xb8, 0x4d, 0xed, 0x73, -0x23, 0x56, 0x18, 0xcf, 0x74, 0xd8, 0x9f, 0x65, -0x10, 0xfe, 0xb3, 0x5d, 0xb0, 0x2e, 0x1e, 0xc2, -0xdf, 0x6a, 0x6d, 0x7a, 0x05, 0x73, 0x3c, 0x33, -0xfe, 0x59, 0x45, 0xd2, 0xd0, 0x95, 0xb4, 0x25, -0x9f, 0xed, 0xb6, 0x7c, 0x96, 0x86, 0xec, 0x3f, -0x8a, 0x6b, 0xe4, 0x29, 0x9f, 0xb2, 0x16, 0x5e, -0xe5, 0xae, 0xb7, 0x58, 0xfe, 0x57, 0xe7, 0xf3, -0x76, 0xfd, 0xba, 0x19, 0xe9, 0x42, 0x98, 0xff, -0x90, 0xfc, 0xaf, 0xef, 0x5f, 0x00, 0xaf, 0x82, -0xa5, 0xf4, 0x6e, 0xe9, 0x2c, 0x68, 0xff, 0x41, -0xf2, 0x1f, 0x2a, 0x6e, 0xff, 0xf1, 0x7e, 0xdf, -0x09, 0xf0, 0x80, 0xda, 0x2f, 0x97, 0x60, 0xff, -0x91, 0x9f, 0xa8, 0x1d, 0xd2, 0x16, 0x72, 0xed, -0x3f, 0x62, 0xb0, 0xfe, 0xa1, 0xfc, 0x04, 0x62, -0x23, 0x4f, 0x47, 0xb6, 0xff, 0xe4, 0xc0, 0x93, -0x68, 0x51, 0xcb, 0x3c, 0x69, 0x8c, 0x62, 0xa0, -0xb9, 0xf2, 0x49, 0x85, 0xf9, 0x0f, 0xc0, 0xf7, -0x6f, 0x77, 0xef, 0xc6, 0x30, 0x34, 0x8d, 0xfa, -0xf8, 0xcf, 0x85, 0xfa, 0x85, 0xd9, 0xa1, 0xe1, -0x90, 0xfd, 0x8a, 0x6b, 0xff, 0x31, 0xe5, 0xc5, -0x60, 0xc8, 0xd4, 0x7c, 0xd2, 0x38, 0x5e, 0x20, -0xfe, 0x67, 0x06, 0xcc, 0x17, 0x73, 0x81, 0xe8, -0xdf, 0xb7, 0x34, 0x7e, 0xfe, 0xd7, 0x1d, 0x60, -0x31, 0x18, 0x03, 0x07, 0x5d, 0xb6, 0x73, 0x5d, -0xd0, 0xfe, 0xa3, 0x06, 0xf9, 0x4f, 0xfd, 0xe3, -0xfc, 0xb2, 0x12, 0x44, 0x9e, 0x9e, 0xfe, 0x51, -0xe4, 0x03, 0x89, 0x63, 0x44, 0x3e, 0x45, 0xe3, -0x7f, 0xa6, 0xd5, 0x7d, 0xe8, 0x19, 0xe6, 0xb4, -0x85, 0x65, 0xd6, 0x7f, 0x7e, 0x58, 0xde, 0xd5, -0xb7, 0xbf, 0x84, 0xf8, 0x9f, 0x7f, 0x06, 0x39, -0x5d, 0x2b, 0xb2, 0xdf, 0x08, 0xff, 0x99, 0x90, -0x9f, 0x85, 0xc7, 0xa9, 0x68, 0x67, 0x07, 0x88, -0x7c, 0xfe, 0x33, 0x22, 0x06, 0xdb, 0xc2, 0xbe, -0xad, 0x14, 0xe0, 0x3f, 0xe0, 0x27, 0xc6, 0x28, -0x68, 0xf7, 0x9f, 0xfe, 0x05, 0xf9, 0xcf, 0x02, -0x78, 0xdf, 0x54, 0xa3, 0xd3, 0x1f, 0xd6, 0x39, -0x76, 0x61, 0x01, 0xfe, 0x23, 0x37, 0x8b, 0x43, -0x6a, 0xa0, 0x8d, 0xa9, 0xfe, 0x55, 0x91, 0x5f, -0xff, 0x39, 0x26, 0xe6, 0xf4, 0x91, 0xc8, 0xf1, -0x3f, 0xdd, 0x8a, 0x89, 0xf4, 0x53, 0x3b, 0xc3, -0xdf, 0xc7, 0xb3, 0xff, 0x20, 0x1a, 0x13, 0xb4, -0xe7, 0x84, 0xf9, 0x8f, 0x97, 0x7f, 0x91, 0xaa, -0xfa, 0x55, 0xdf, 0xbf, 0x19, 0x7e, 0xf9, 0x84, -0xfb, 0xa3, 0xbd, 0x4c, 0xd5, 0x3f, 0x9c, 0x80, -0xbb, 0xb5, 0x46, 0xbf, 0xd9, 0x47, 0xe6, 0xc7, -0xff, 0x18, 0x60, 0x10, 0xe6, 0x0c, 0x2d, 0x72, -0xfc, 0xcf, 0x11, 0xc4, 0x67, 0xee, 0xd3, 0x39, -0x6d, 0x61, 0x59, 0xfc, 0x47, 0xfe, 0x31, 0x78, -0x05, 0xd1, 0x1e, 0x6b, 0xb6, 0x11, 0xec, 0x3f, -0x13, 0x60, 0xa0, 0xac, 0x94, 0xf8, 0x1f, 0x05, -0xec, 0x6f, 0x34, 0xc3, 0xf2, 0xe7, 0xc6, 0xff, -0x28, 0x03, 0x5f, 0x45, 0xb4, 0xa7, 0xd1, 0x67, -0xed, 0xb9, 0xa8, 0xf3, 0xed, 0x3f, 0x8a, 0x5c, -0x0d, 0xfa, 0x60, 0xb1, 0xe7, 0x85, 0xf0, 0x1f, -0x01, 0xcc, 0x5d, 0xb8, 0x53, 0x2f, 0xf6, 0xfc, -0x12, 0xff, 0x97, 0x02, 0xaf, 0x46, 0xaf, 0xd5, -0x87, 0x7c, 0x6c, 0xe7, 0xf5, 0x02, 0xf1, 0x3f, -0x2d, 0xf2, 0x01, 0x86, 0x35, 0xc3, 0xbd, 0xa2, -0x86, 0xf9, 0x8f, 0xfc, 0x42, 0xd7, 0x24, 0xf4, -0x9d, 0x5f, 0xd2, 0x1b, 0xe0, 0x83, 0x3e, 0x5e, -0xfc, 0xcf, 0x3f, 0x82, 0xe7, 0xdf, 0xd9, 0x69, -0xbf, 0x76, 0x79, 0xb3, 0x3d, 0xa5, 0xbb, 0xef, -0x5f, 0x72, 0x28, 0xfe, 0x67, 0x04, 0x0c, 0xab, -0x3b, 0x03, 0xfa, 0xea, 0x64, 0x28, 0xf1, 0x8d, -0xd8, 0x7f, 0x70, 0x7f, 0xd8, 0xfe, 0x80, 0x3c, -0xcd, 0x50, 0xbf, 0x4b, 0xe2, 0xff, 0x52, 0xd0, -0xf9, 0x75, 0x6c, 0x77, 0x50, 0x7f, 0x06, 0x1b, -0xc1, 0xd3, 0xf1, 0x3f, 0x8f, 0x63, 0xa5, 0xe4, -0x7c, 0x2b, 0x58, 0x20, 0xd0, 0x3f, 0xee, 0xcb, -0x3e, 0xfb, 0x0f, 0x38, 0xd2, 0x72, 0x2e, 0x54, -0xf6, 0xe7, 0x4c, 0x80, 0x0f, 0x10, 0xff, 0xd7, -0xa8, 0xbc, 0x20, 0xff, 0x1c, 0xf4, 0x9f, 0x5f, -0x63, 0xce, 0xfb, 0x7b, 0xa3, 0x7b, 0xa5, 0x9d, -0xee, 0x0f, 0xdb, 0x02, 0x8e, 0x04, 0xc6, 0x4f, -0xeb, 0x81, 0x8c, 0xf8, 0x0c, 0x65, 0xff, 0x51, -0x13, 0xe8, 0x7d, 0x7f, 0xa4, 0x88, 0x7c, 0x28, -0xfe, 0x33, 0xbc, 0x1d, 0x6d, 0xf2, 0xc3, 0x01, -0xf9, 0xbc, 0x49, 0xef, 0x87, 0x72, 0xda, 0xfe, -0x03, 0xc3, 0xf1, 0xcf, 0x9d, 0x81, 0xfa, 0xcf, -0x0f, 0x32, 0xe2, 0x7f, 0x26, 0xac, 0xdd, 0xf2, -0x2a, 0x06, 0x33, 0xc5, 0xe3, 0x9f, 0xfb, 0xda, -0xb6, 0x59, 0x6c, 0x67, 0x08, 0xb6, 0xcd, 0xc4, -0x9f, 0x67, 0xf0, 0x9f, 0x50, 0x7f, 0xd8, 0x51, -0xdc, 0xaf, 0x53, 0xe9, 0x17, 0x5a, 0x4f, 0xc4, -0x9b, 0x19, 0xcf, 0xd7, 0xb9, 0x60, 0xfc, 0x8f, -0x8e, 0xa5, 0x9d, 0x41, 0x62, 0x9f, 0xb0, 0x89, -0x25, 0xdf, 0xfe, 0x43, 0xfa, 0x5f, 0x58, 0x65, -0xf7, 0x5e, 0xab, 0x3e, 0xd2, 0x14, 0x3e, 0x7f, -0x47, 0xbd, 0xf9, 0xbf, 0x8d, 0xfb, 0x5f, 0x88, -0xf7, 0x9a, 0xf6, 0x32, 0xb1, 0x5b, 0xf9, 0x20, -0xcb, 0x3e, 0xc6, 0xee, 0x0f, 0x6b, 0x99, 0x35, -0x46, 0x3c, 0xb7, 0x63, 0x8d, 0x17, 0xba, 0x4f, -0xf8, 0xcf, 0x31, 0xb9, 0xd5, 0x2a, 0x53, 0x39, -0x74, 0xb8, 0xf6, 0xb8, 0xb3, 0x6d, 0x32, 0xad, -0x2a, 0xe1, 0x6f, 0xc1, 0xfc, 0xaf, 0x77, 0x04, -0xcf, 0xfe, 0xfc, 0x2a, 0xec, 0xcf, 0xe1, 0xfa, -0x90, 0x99, 0xb0, 0x87, 0x74, 0xc6, 0xdb, 0x0e, -0xb7, 0x0b, 0xf3, 0x65, 0xdc, 0x16, 0x16, 0x9f, -0xfe, 0x99, 0x5d, 0x36, 0x08, 0x7b, 0xc4, 0x7c, -0xfd, 0x2f, 0x9c, 0xfa, 0xcf, 0x9d, 0x93, 0xc6, -0x4b, 0xca, 0x72, 0x58, 0xad, 0x79, 0x61, 0x3f, -0x9d, 0xac, 0xfe, 0xb0, 0x56, 0xfc, 0xcf, 0x32, -0x4c, 0x9b, 0x4f, 0xeb, 0x97, 0xd5, 0x95, 0xe3, -0xd5, 0xff, 0x45, 0xc9, 0x47, 0xf7, 0xec, 0x3f, -0xee, 0x7a, 0x9d, 0xfa, 0x5d, 0x53, 0xe8, 0xb5, -0x65, 0x12, 0xbc, 0x04, 0x91, 0xa2, 0xce, 0xb3, -0xfa, 0xc3, 0x12, 0xfd, 0xef, 0xd4, 0xdf, 0x50, -0xb0, 0x1a, 0xd9, 0x05, 0x1a, 0xf0, 0xe9, 0x13, -0x8e, 0x28, 0x38, 0x47, 0xf1, 0x4f, 0x6c, 0xff, -0x69, 0x9d, 0xaa, 0xb4, 0xcb, 0x1e, 0x36, 0x8c, -0xc4, 0xbb, 0x18, 0xeb, 0xa5, 0xfc, 0x5f, 0xf6, -0xfb, 0xd7, 0xb8, 0x95, 0x6d, 0xd1, 0x0f, 0x90, -0x22, 0xba, 0x4a, 0xa4, 0xdf, 0x38, 0x1c, 0xff, -0x57, 0x30, 0xfe, 0x67, 0xa4, 0x4c, 0x43, 0x2f, -0xa1, 0xc7, 0xc4, 0x9f, 0xa2, 0x17, 0xa5, 0xb8, -0x15, 0xf6, 0x03, 0xcb, 0x7d, 0xfc, 0xc7, 0xbb, -0xbf, 0xe3, 0xff, 0x7a, 0x10, 0xd1, 0x1e, 0xfd, -0x02, 0x58, 0xce, 0xf3, 0x7f, 0xb9, 0xe3, 0x3d, -0xfb, 0xcf, 0xdf, 0x49, 0xcd, 0xe8, 0xa0, 0x6c, -0xd3, 0x37, 0xa8, 0x94, 0x7d, 0x40, 0xf5, 0xf8, -0x8f, 0x3b, 0x9e, 0xf2, 0x7f, 0x2d, 0x02, 0xb8, -0xec, 0x70, 0x55, 0xbe, 0x32, 0xec, 0xe1, 0x9a, -0xf6, 0x7e, 0x5f, 0xd2, 0xff, 0xe2, 0xea, 0x85, -0xc0, 0x29, 0x53, 0x1c, 0x1e, 0x4f, 0xf9, 0xbf, -0x80, 0x6b, 0xfd, 0x28, 0x93, 0x6b, 0x71, 0x19, -0xc0, 0x0a, 0x55, 0x0c, 0xd9, 0x43, 0x1a, 0xa9, -0xfc, 0x77, 0xc5, 0xb0, 0xda, 0xc2, 0xa2, 0x45, -0xb5, 0xe0, 0xb2, 0xab, 0xd8, 0xfe, 0x13, 0xee, -0xbf, 0x40, 0xea, 0x3f, 0xdb, 0xf6, 0x9f, 0x95, -0xd9, 0xea, 0x7c, 0xd3, 0x79, 0x1b, 0x90, 0xb0, -0x9f, 0x3a, 0x56, 0xfe, 0xbb, 0xed, 0x3f, 0xca, -0x54, 0x9f, 0x90, 0xfe, 0x14, 0xbc, 0x8f, 0x41, -0xbe, 0x3f, 0xcc, 0x07, 0xa8, 0xfe, 0x17, 0x4e, -0xfd, 0xc3, 0x21, 0xc4, 0x76, 0x70, 0xdb, 0x0b, -0x35, 0x3e, 0xc0, 0xf2, 0x7f, 0x91, 0xfa, 0xbd, -0x6e, 0xfc, 0x4f, 0x5a, 0x0c, 0xb7, 0xf9, 0xb0, -0xc1, 0x7a, 0x35, 0xf3, 0x9a, 0xe0, 0x8e, 0x4f, -0xc5, 0x6c, 0x6b, 0xcf, 0x50, 0x5e, 0xfc, 0x05, -0x96, 0xa7, 0x21, 0xe5, 0x81, 0x2b, 0xc6, 0x5a, -0x4e, 0xfd, 0x67, 0x67, 0x92, 0x76, 0xbf, 0xd7, -0xf2, 0x87, 0x05, 0x06, 0xff, 0x21, 0xfe, 0x0e, -0x2f, 0x1f, 0x50, 0xd8, 0x56, 0xc0, 0xff, 0xc5, -0xe8, 0x7f, 0x51, 0x37, 0xd5, 0x88, 0xe4, 0x2f, -0x4c, 0x52, 0x61, 0x3f, 0x96, 0x29, 0x32, 0x10, -0xff, 0x33, 0xe0, 0xf9, 0xbf, 0x7e, 0x0e, 0xef, -0xd7, 0xda, 0xa0, 0x32, 0x22, 0xdd, 0x41, 0xd9, -0x7f, 0xc4, 0x36, 0x5e, 0x7f, 0xd8, 0xc6, 0xe3, -0x42, 0x3f, 0xb4, 0xda, 0x74, 0x86, 0x33, 0x98, -0xa8, 0xfe, 0x17, 0x5e, 0xfc, 0xcf, 0x5d, 0xa7, -0xd1, 0xf3, 0x8b, 0x1e, 0xcc, 0x9b, 0x18, 0xfc, -0x27, 0x64, 0xff, 0x99, 0xda, 0x78, 0xf7, 0xa6, -0xb7, 0xc0, 0xcf, 0x72, 0x7f, 0x34, 0xd5, 0x86, -0x0b, 0x21, 0x7e, 0xe8, 0x34, 0x8a, 0x55, 0xc3, -0xf5, 0x9f, 0xe7, 0xb9, 0xf9, 0x5f, 0x4d, 0x93, -0x22, 0xd6, 0x1e, 0x55, 0xac, 0x7e, 0xe8, 0xbe, -0xfe, 0x17, 0x56, 0xfe, 0x57, 0xe2, 0xc2, 0xa6, -0xb7, 0x6a, 0x5f, 0xed, 0xc3, 0xc0, 0x09, 0xfb, -0xd9, 0x78, 0xa1, 0xee, 0x92, 0x9b, 0x1a, 0xe6, -0xeb, 0x7f, 0xe1, 0xea, 0x9f, 0xd3, 0x70, 0xd0, -0x06, 0x44, 0xff, 0xb8, 0x85, 0x10, 0x89, 0xfd, -0xed, 0x07, 0xb6, 0xff, 0x6b, 0x4c, 0xd9, 0x21, -0x9e, 0x56, 0x10, 0x4d, 0x3a, 0x81, 0x14, 0x4b, -0x58, 0x5f, 0x11, 0xfb, 0x8f, 0xd5, 0x9f, 0x5a, -0xc0, 0xf6, 0xe7, 0xda, 0x49, 0xdc, 0x66, 0x65, -0x54, 0x49, 0xdf, 0xef, 0xea, 0x9f, 0x5a, 0x57, -0x9e, 0x8d, 0x54, 0xfd, 0xe7, 0xe4, 0xe3, 0xf8, -0x10, 0x99, 0x6a, 0x45, 0xfa, 0xd3, 0x32, 0x9b, -0xe3, 0xb0, 0xd2, 0xd0, 0x7a, 0x8f, 0x7b, 0xfa, -0x30, 0x0f, 0xde, 0x4b, 0xd8, 0x17, 0x9b, 0x3e, -0x00, 0xb8, 0x5e, 0x34, 0xeb, 0x7d, 0xb3, 0x89, -0xf4, 0x87, 0xcd, 0xa9, 0x1f, 0x29, 0x97, 0xcb, -0xd0, 0xc5, 0x99, 0xba, 0x8f, 0xc0, 0xab, 0xf8, -0xfe, 0x0c, 0x7f, 0x50, 0xf9, 0x01, 0x8a, 0xff, -0x6c, 0x77, 0x8a, 0xd4, 0x65, 0x3e, 0x90, 0x87, -0x02, 0x69, 0x5c, 0x2c, 0xfb, 0x0f, 0x3e, 0xef, -0xf0, 0xdb, 0xfd, 0xb0, 0xf8, 0x9f, 0x1a, 0xe2, -0x03, 0x9c, 0xf1, 0xcc, 0xfa, 0x3f, 0x65, 0x98, -0xf6, 0x30, 0xeb, 0x43, 0x52, 0xf9, 0xef, 0x74, -0xfd, 0x9f, 0x7f, 0x95, 0x57, 0x98, 0xcc, 0xfe, -0x56, 0x23, 0x65, 0xee, 0x7c, 0x2c, 0xfb, 0x8f, -0x68, 0xd3, 0x1e, 0x95, 0xef, 0xff, 0x5a, 0xd8, -0xeb, 0xfd, 0x05, 0xbb, 0xe9, 0xde, 0x77, 0x2a, -0xe7, 0x8e, 0x21, 0x30, 0xd9, 0xb2, 0xb4, 0xf2, -0x77, 0xa2, 0x1f, 0xa2, 0xdd, 0x74, 0x4f, 0x98, -0x2c, 0x7e, 0x7f, 0x05, 0x8a, 0x74, 0x77, 0xbc, -0xa5, 0xd8, 0x65, 0xf6, 0x45, 0x3f, 0xc4, 0x4f, -0x2c, 0xff, 0x70, 0x3f, 0x44, 0x56, 0x87, 0x44, -0xb9, 0xc0, 0xfd, 0xe7, 0x9a, 0xa5, 0xf5, 0x43, -0x54, 0x4b, 0x94, 0xbf, 0x5a, 0x48, 0xfe, 0x8c, -0x7e, 0x88, 0x09, 0x33, 0x24, 0xf3, 0x2f, 0xfa, -0x21, 0x16, 0x06, 0x9f, 0xe7, 0xf1, 0xbf, 0x63, -0xcf, 0xe3, 0x27, 0xeb, 0x0f, 0xeb, 0x44, 0x0e, -0x04, 0xc0, 0xef, 0x8d, 0x3e, 0x9c, 0x24, 0xd2, -0xfe, 0x4e, 0x40, 0xfe, 0x93, 0xbf, 0x2d, 0x7d, -0x68, 0xdd, 0xed, 0x8b, 0xfe, 0xb0, 0x81, 0xcf, -0x17, 0xfa, 0xf0, 0xff, 0xf9, 0xf8, 0xa3, 0x1d, -0x52, 0xaf, 0x7e, 0x5a, 0xbd, 0x11, 0x54, 0x8d, -0x5a, 0x60, 0x91, 0x1c, 0xfb, 0x99, 0xb4, 0xc3, -0xec, 0x51, 0xe7, 0xd4, 0x57, 0x1d, 0xc5, 0x20, -0x3b, 0x47, 0xae, 0x32, 0xaf, 0xf5, 0xc6, 0xaf, -0x5e, 0x25, 0xef, 0x10, 0x7a, 0xf4, 0xad, 0x2a, -0x18, 0x8f, 0xd9, 0x20, 0x49, 0x80, 0xe0, 0x00, -0xf3, 0x5a, 0x97, 0x0f, 0x03, 0x28, 0x0a, 0x1a, -0xec, 0xd2, 0x6a, 0x15, 0xd0, 0xe7, 0x00, 0x99, -0x02, 0x0d, 0xb0, 0xcb, 0x40, 0xc0, 0x6b, 0x2f, -0x83, 0xb7, 0xb8, 0xd0, 0x0b, 0xba, 0xc1, 0x6c, -0x30, 0x08, 0x05, 0xc3, 0x02, 0xc9, 0x01, 0xe1, -0x36, 0xa1, 0x1b, 0x6c, 0x49, 0xc5, 0x76, 0x0a, -0x06, 0x06, 0x20, 0x46, 0x8d, 0x3f, 0xda, 0x1d, -0xbb, 0x41, 0xf8, 0x3a, 0xdc, 0xd4, 0x21, 0xef, -0x8e, 0xdd, 0x25, 0xf4, 0xc0, 0xad, 0x5a, 0x72, -0xc2, 0x03, 0x02, 0x02, 0x23, 0x08, 0x50, 0xf3, -0x39, 0xaa, 0xeb, 0x5a, 0x56, 0x91, 0xc5, 0x18, -0xfa, 0x4b, 0x06, 0x48, 0x81, 0x32, 0x20, 0x10, -0x20, 0xbb, 0x80, 0xac, 0xf7, 0x68, 0x97, 0x7c, -0xbb, 0x90, 0x82, 0x6b, 0x34, 0x70, 0x9f, 0xdc, -0x28, 0x28, 0xf9, 0x0c, 0x50, 0x77, 0xcb, 0x0d, -0x82, 0x02, 0x32, 0x9a, 0x3a, 0x20, 0x6b, 0x36, -0xa0, 0xc7, 0xaf, 0x8b, 0xdd, 0x32, 0xba, 0x79, -0xe4, 0xd6, 0xd6, 0xfa, 0x59, 0xb1, 0x4c, 0x2e, -0x9b, 0xdf, 0xac, 0xc4, 0x2a, 0x63, 0x3a, 0xcc, -0x6a, 0xf5, 0x2d, 0x49, 0xd1, 0x06, 0xcb, 0x93, -0x80, 0x92, 0xcf, 0x5c, 0xa1, 0x1c, 0xdc, 0x6a, -0x26, 0xb3, 0x72, 0x42, 0xd8, 0x8a, 0x40, 0x4d, -0x6f, 0xac, 0x47, 0xd8, 0x04, 0x36, 0x9b, 0xc9, -0x74, 0xec, 0x8f, 0x05, 0x09, 0x83, 0x9b, 0x64, -0xaf, 0xfc, 0x2a, 0x1a, 0xaf, 0xe9, 0x0a, 0xa8, -0x05, 0x32, 0x44, 0xca, 0x06, 0x69, 0x3e, 0x5d, -0xd0, 0x90, 0x0a, 0xec, 0x84, 0x2a, 0x94, 0x55, -0x41, 0x46, 0xaa, 0x01, 0x03, 0xd0, 0x41, 0xc9, -0xc7, 0x10, 0x91, 0xe8, 0x81, 0x86, 0x54, 0x87, -0x05, 0x1a, 0xec, 0x50, 0x2c, 0x7c, 0x45, 0xd1, -0xca, 0x1c, 0xd0, 0x41, 0xc9, 0x27, 0x1b, 0x6b, -0x16, 0xbe, 0x09, 0xb6, 0xe8, 0xf5, 0x30, 0xb6, -0xcd, 0x02, 0xf3, 0xf2, 0x31, 0x43, 0x38, 0x05, -0xfe, 0x0c, 0x24, 0xf3, 0x31, 0xcd, 0x06, 0xf4, -0x7a, 0xf5, 0xb8, 0x01, 0x4e, 0x81, 0x1b, 0xb0, -0xe1, 0xc4, 0xfa, 0xbd, 0xb4, 0x24, 0x94, 0x6e, -0x07, 0xdd, 0x70, 0x36, 0xa8, 0x22, 0x80, 0xda, -0x3f, 0x9d, 0x72, 0x3a, 0x97, 0xd0, 0x3a, 0xd1, -0x5f, 0x96, 0xd3, 0x30, 0xa1, 0x49, 0x8a, 0x3a, -0x56, 0x9f, 0x1e, 0xc5, 0x57, 0xd4, 0x97, 0x80, -0x03, 0xa8, 0xdf, 0x0b, 0x7d, 0xd2, 0xe8, 0x9d, -0x4a, 0xc2, 0x3b, 0xc3, 0x01, 0xa6, 0x0b, 0x26, -0xbc, 0x2b, 0x94, 0x7c, 0x24, 0x21, 0x0d, 0x37, -0x68, 0x75, 0x78, 0x77, 0x59, 0x20, 0x51, 0x3f, -0x26, 0xa4, 0x73, 0x1b, 0xd2, 0x9b, 0x14, 0xf9, -0x98, 0x0b, 0xa8, 0xf1, 0x47, 0x33, 0x31, 0x23, -0xd7, 0xad, 0x6d, 0x41, 0xe3, 0x1d, 0x10, 0x43, -0x60, 0x14, 0x83, 0x64, 0xbf, 0xa0, 0xd9, 0x00, -0x52, 0xf2, 0xc9, 0x58, 0x92, 0xf3, 0x44, 0x88, -0xc0, 0x18, 0x02, 0x78, 0x21, 0x68, 0x45, 0x0e, -0xa0, 0xd7, 0x7b, 0x8b, 0x6c, 0xe4, 0x52, 0xda, -0x9a, 0x2e, 0xb0, 0x07, 0x81, 0xab, 0xb4, 0x35, -0x09, 0x30, 0x26, 0x6f, 0xcb, 0x25, 0xd2, 0x9d, -0x5d, 0x35, 0x7b, 0x64, 0xcd, 0x06, 0xb4, 0x3c, -0x8d, 0x58, 0xb7, 0xb0, 0x05, 0xdc, 0x0a, 0xeb, -0x35, 0x07, 0xc8, 0xe8, 0x0a, 0x58, 0x03, 0x6a, -0x60, 0xd2, 0x88, 0xa5, 0x6c, 0xa0, 0x53, 0xfb, -0xa7, 0x4c, 0xf8, 0x06, 0xec, 0x31, 0x92, 0xc3, -0xb1, 0x32, 0xa1, 0x03, 0xaa, 0x86, 0x9c, 0x8a, -0x95, 0x81, 0x0e, 0x98, 0x35, 0xea, 0x53, 0xd6, -0x15, 0x0b, 0x10, 0x73, 0x11, 0x30, 0x6b, 0xad, -0xbd, 0x50, 0xab, 0xcb, 0xb5, 0x02, 0x80, 0x1d, -0x9a, 0x8a, 0x9e, 0x85, 0x1a, 0x79, 0x40, 0xd7, -0xd4, 0x2e, 0xeb, 0x8a, 0x05, 0xd0, 0x31, 0xe6, -0xcd, 0x67, 0x8d, 0x58, 0x03, 0x07, 0x8c, 0x05, -0xaa, 0xb0, 0x46, 0xfa, 0x06, 0xdc, 0x6c, 0x24, -0x53, 0x55, 0x18, 0x9c, 0x34, 0xae, 0x47, 0xa0, -0xdc, 0x01, 0xd4, 0x7c, 0xc6, 0xd7, 0xc4, 0x76, -0xf4, 0xf5, 0x18, 0x5b, 0x53, 0xc9, 0x97, 0x63, -0x3b, 0x72, 0xfb, 0x8c, 0x6f, 0xa7, 0xe6, 0x61, -0x70, 0xda, 0xf8, 0xae, 0x7d, 0xc5, 0x02, 0xb4, -0x3e, 0x59, 0x23, 0xec, 0x80, 0xa7, 0x8d, 0x1b, -0x53, 0x55, 0x2f, 0x4b, 0x36, 0x10, 0x30, 0xe8, -0x31, 0xe6, 0xd8, 0x57, 0x2c, 0x60, 0xd6, 0x50, -0xe3, 0xd1, 0x4d, 0xd0, 0xfd, 0xbb, 0xc1, 0xcb, -0x36, 0x48, 0xa9, 0x18, 0x24, 0x8c, 0x4e, 0x74, -0x7f, 0xd0, 0x60, 0x03, 0xb3, 0x86, 0xda, 0x3f, -0x82, 0x06, 0xba, 0xd0, 0x13, 0xe3, 0xe9, 0x9f, -0xd8, 0x18, 0x02, 0x3d, 0xda, 0x1c, 0x5b, 0x11, -0x59, 0x00, 0x52, 0xbb, 0xad, 0x4c, 0xb8, 0x0d, -0x76, 0x1b, 0xb3, 0x53, 0xc9, 0x9d, 0x1e, 0x00, -0xb7, 0xe5, 0xba, 0x0d, 0x4b, 0xff, 0x34, 0xd8, -0x80, 0x1a, 0xbf, 0x5a, 0x4f, 0xa6, 0x85, 0x0d, -0x60, 0x13, 0x90, 0x61, 0xac, 0x57, 0xe8, 0x01, -0x5b, 0x41, 0xd2, 0xf4, 0x80, 0x90, 0x76, 0x00, -0x99, 0xcf, 0x6a, 0xb4, 0x7f, 0x46, 0x94, 0x16, -0xb1, 0x12, 0xed, 0x1f, 0x03, 0xa6, 0xd0, 0x23, -0x28, 0x78, 0xa0, 0x1f, 0xed, 0x1f, 0x0b, 0x40, -0x6a, 0xbd, 0xeb, 0x64, 0x63, 0x3f, 0xda, 0x3f, -0x95, 0x78, 0x77, 0xe5, 0x14, 0x3b, 0xc0, 0xcb, -0x03, 0x86, 0x0d, 0xe8, 0xf1, 0x9d, 0x0b, 0xb2, -0xa3, 0x9b, 0xdb, 0x6f, 0x55, 0x06, 0x91, 0xb6, -0xc9, 0x65, 0x35, 0xa4, 0x7f, 0x10, 0x18, 0x40, -0x6a, 0x47, 0x41, 0xfa, 0x27, 0x0b, 0x2d, 0x00, -0x28, 0xf9, 0x54, 0x0a, 0xd9, 0x89, 0xcd, 0xe9, -0xa4, 0x22, 0x77, 0x0a, 0x59, 0x13, 0x81, 0x44, -0x2c, 0x0c, 0x74, 0x4a, 0x3e, 0x40, 0x37, 0x54, -0x55, 0x96, 0x05, 0xc4, 0x38, 0x33, 0x58, 0xdb, -0x58, 0x2a, 0xd0, 0x06, 0x80, 0x00, 0x32, 0x9f, -0x8c, 0xd8, 0x08, 0xe1, 0x88, 0xd6, 0x35, 0x2c, -0x8a, 0x00, 0xc2, 0xb4, 0xa6, 0x28, 0x16, 0xd0, -0x10, 0x90, 0xca, 0x2c, 0x90, 0x50, 0xa8, 0xf9, -0xac, 0xd6, 0xcb, 0x2d, 0x25, 0x2f, 0x25, 0x61, -0xcc, 0xd6, 0xf6, 0xf3, 0xa0, 0xab, 0x7f, 0x08, -0x20, 0xeb, 0x1d, 0xd4, 0xe7, 0x58, 0xfa, 0x47, -0x1a, 0x84, 0x12, 0x06, 0xe8, 0x74, 0x30, 0x25, -0x43, 0xee, 0x01, 0x73, 0x90, 0xda, 0xa9, 0xd1, -0x80, 0x0d, 0xe8, 0xf9, 0xcb, 0x69, 0x21, 0x01, -0x3a, 0xd1, 0x5f, 0xb6, 0x80, 0x84, 0x9e, 0x27, -0x39, 0x0d, 0xf0, 0x83, 0xa5, 0x9a, 0x40, 0x13, -0x1c, 0x40, 0x0d, 0xb7, 0x95, 0x8c, 0x8e, 0xf4, -0xcf, 0xb5, 0x30, 0x61, 0x48, 0xdd, 0x60, 0x2f, -0xb8, 0x0e, 0x54, 0x00, 0x51, 0x07, 0x27, 0xf5, -0x66, 0x0c, 0xb0, 0x46, 0xa2, 0xc6, 0xcb, 0xd7, -0xea, 0x1b, 0xb2, 0x75, 0xf9, 0xbd, 0x47, 0x05, -0x04, 0x3a, 0x36, 0xd5, 0xd7, 0x23, 0xd0, 0xb1, -0x21, 0xbb, 0xa9, 0x5e, 0x1e, 0xcf, 0x35, 0x60, -0xa0, 0xca, 0xf4, 0xf8, 0x45, 0xb1, 0x3b, 0x46, -0xbf, 0x95, 0xde, 0xb2, 0x3b, 0xf6, 0x23, 0x0b, -0xcc, 0xde, 0x97, 0xb4, 0xc1, 0x96, 0x07, 0x92, -0xff, 0x90, 0x73, 0x80, 0x6f, 0xfe, 0x36, 0xe3, -0xc7, 0xf3, 0xb1, 0xc8, 0xa6, 0x8e, 0xe6, 0xd3, -0x6c, 0xcf, 0x27, 0x2f, 0x3b, 0xf3, 0xf1, 0x8d, -0xdf, 0x66, 0xd4, 0xa4, 0xe4, 0x35, 0xe8, 0xf7, -0x5a, 0x85, 0x0f, 0xb2, 0x32, 0xad, 0x66, 0xb7, -0x7c, 0x7b, 0x4d, 0x6a, 0x60, 0x4d, 0x43, 0xcd, -0xc0, 0x2a, 0x07, 0xd0, 0xe3, 0xe5, 0x8e, 0x6c, -0xcd, 0x66, 0xf9, 0x56, 0x74, 0x98, 0xc4, 0x10, -0x88, 0x25, 0x85, 0xd8, 0xaa, 0xd5, 0x59, 0xb0, -0x59, 0x4e, 0x82, 0xa4, 0xbe, 0x3a, 0xab, 0x6e, -0x4e, 0x24, 0x85, 0x24, 0xbd, 0x1f, 0x94, 0x06, -0x51, 0xd1, 0xfb, 0x54, 0x6d, 0x50, 0x69, 0xc8, -0x28, 0xd9, 0xbe, 0x7a, 0x04, 0x84, 0x4c, 0x0a, -0x83, 0x98, 0x72, 0xdb, 0x2d, 0xf6, 0x15, 0x7a, -0x3a, 0x95, 0x40, 0x84, 0x60, 0x04, 0xb4, 0xa0, -0x8d, 0x27, 0x42, 0x7d, 0x44, 0x6d, 0x91, 0x11, -0xc8, 0xdb, 0xc0, 0x14, 0x87, 0xf5, 0x03, 0xea, -0x35, 0x34, 0xdb, 0x06, 0x09, 0xb1, 0x0e, 0x0c, -0x98, 0x0d, 0xe9, 0xd4, 0x06, 0x69, 0x13, 0x38, -0x39, 0x96, 0x4c, 0x57, 0x21, 0xa0, 0x6e, 0x36, -0xaf, 0x47, 0xc0, 0xac, 0x53, 0x4f, 0x9a, 0xd7, -0xb7, 0x57, 0xd1, 0xf3, 0xa9, 0x10, 0xee, 0xea, -0xe8, 0xc9, 0x6f, 0xd5, 0xe6, 0x61, 0x1a, 0x30, -0x17, 0x7e, 0xdb, 0x06, 0xfb, 0xe0, 0x77, 0x11, -0x1f, 0x58, 0x73, 0x97, 0x70, 0x1a, 0x81, 0xbf, -0xa1, 0xe5, 0x1f, 0x5f, 0x97, 0x79, 0x3d, 0xff, -0xd4, 0x81, 0xc5, 0x15, 0x5f, 0xc1, 0xe0, 0xc9, -0x03, 0x8b, 0xd7, 0xc6, 0x6f, 0x59, 0x77, 0x62, -0xcf, 0x53, 0xcd, 0xff, 0x54, 0x11, 0xcf, 0xac, -0x3b, 0x89, 0xc1, 0x1f, 0xd0, 0xf3, 0x59, 0x76, -0xef, 0xcd, 0x97, 0xff, 0xe3, 0xc5, 0xf3, 0xef, -0x5f, 0x5c, 0x89, 0xc1, 0x33, 0xe7, 0x3f, 0xb8, -0xb8, 0xec, 0xd2, 0xc6, 0x33, 0x0f, 0x5d, 0x3e, -0xfb, 0xf1, 0xc5, 0x65, 0xf7, 0x6c, 0xbc, 0x8c, -0xc1, 0xc7, 0xe0, 0x0a, 0x3e, 0x2b, 0xfe, 0xb6, -0x62, 0x61, 0x66, 0x6d, 0x7e, 0xcf, 0xb6, 0x05, -0x17, 0xab, 0x7f, 0xd2, 0x79, 0x39, 0xff, 0xeb, -0x6d, 0x2b, 0xfe, 0x7e, 0xed, 0xbd, 0xaf, 0xad, -0xcd, 0x3f, 0xf2, 0xf1, 0xca, 0xcb, 0x6b, 0x17, -0xbd, 0xb6, 0xf6, 0xfc, 0x23, 0x67, 0xe9, 0xf1, -0x2b, 0xef, 0xb9, 0xf9, 0xcc, 0x43, 0xcf, 0x9c, -0x7d, 0x9f, 0x4c, 0xc3, 0x9e, 0xd8, 0xd9, 0x0f, -0xd0, 0xf8, 0x9b, 0xcf, 0x58, 0x33, 0xa4, 0xc7, -0x37, 0xcd, 0xef, 0x3a, 0xb3, 0xe7, 0xc6, 0xb3, -0x0f, 0xdc, 0xb6, 0x0c, 0xff, 0xc7, 0x43, 0x67, -0xdf, 0x7f, 0x1b, 0x81, 0xb7, 0xea, 0x9e, 0x19, -0x78, 0xff, 0x62, 0x53, 0xca, 0x02, 0xef, 0x7d, -0xcf, 0x37, 0xa1, 0xbe, 0x5e, 0x7d, 0x9f, 0xba, -0x48, 0xbd, 0x6f, 0xb4, 0x11, 0x01, 0x70, 0xa3, -0x5c, 0x71, 0x54, 0xec, 0xd5, 0xe7, 0xaa, 0x8b, -0xea, 0x2d, 0x80, 0xbe, 0x9a, 0x5b, 0x41, 0xcb, -0x53, 0x1e, 0xdc, 0x01, 0x10, 0x09, 0xac, 0x05, -0xe3, 0x83, 0x98, 0x0d, 0x6e, 0xb2, 0xf8, 0x21, -0x38, 0xed, 0x23, 0x8a, 0xf4, 0x78, 0x87, 0x1f, -0x5e, 0x05, 0xfa, 0x73, 0x18, 0xcc, 0x56, 0xe4, -0x9d, 0x2e, 0x3f, 0xf4, 0x00, 0xf4, 0x4d, 0xc8, -0x26, 0x69, 0xb9, 0x20, 0x7f, 0x53, 0x69, 0x40, -0x3e, 0xca, 0xaa, 0xbb, 0x84, 0x04, 0xec, 0x8c, -0xc3, 0x89, 0x6d, 0xed, 0xc2, 0xdc, 0x81, 0xaf, -0x69, 0x35, 0xc7, 0x64, 0xbc, 0x31, 0xbe, 0x76, -0x53, 0xcd, 0x84, 0x0d, 0xb4, 0x1a, 0xd3, 0x7f, -0x7f, 0x55, 0x29, 0x43, 0xfc, 0x70, 0x10, 0xb1, -0x2e, 0xef, 0xfe, 0x0a, 0x06, 0x7d, 0xe4, 0x2f, -0x92, 0x4f, 0x15, 0xa2, 0x85, 0x88, 0x1f, 0x1a, -0x00, 0x3d, 0x56, 0x82, 0x02, 0x11, 0x1b, 0x1c, -0x96, 0x9b, 0xd1, 0x95, 0x4c, 0xaf, 0xba, 0x0f, -0x33, 0x46, 0x98, 0x31, 0x7c, 0xef, 0x68, 0x5f, -0x91, 0xd7, 0x0d, 0xce, 0x7e, 0x6c, 0xf5, 0x11, -0x75, 0xc9, 0xc0, 0xb7, 0x72, 0xb5, 0x23, 0xab, -0x1e, 0xab, 0xb9, 0x46, 0xee, 0x32, 0x6f, 0xb1, -0xc1, 0x3a, 0xfb, 0x0a, 0x35, 0x7b, 0xb3, 0x0a, -0xd4, 0x81, 0xfa, 0x89, 0xd8, 0xc3, 0x60, 0x12, -0x4a, 0xa0, 0x1e, 0x71, 0x1f, 0xfb, 0xb4, 0x31, -0x63, 0x36, 0xa8, 0xc7, 0x40, 0x27, 0xff, 0x01, -0xbd, 0xaa, 0xaa, 0x2a, 0x7a, 0x97, 0xed, 0x06, -0xf8, 0x29, 0xc2, 0x6f, 0xa2, 0x82, 0x0a, 0x56, -0xa1, 0x7f, 0xc8, 0x59, 0x61, 0xb6, 0x6a, 0xbd, -0x34, 0xeb, 0x82, 0xe7, 0xbe, 0x46, 0xf7, 0xb7, -0x5f, 0x57, 0x35, 0xd9, 0xff, 0xa6, 0x2a, 0xfb, -0x5f, 0x39, 0xe9, 0xf1, 0xb2, 0x61, 0x2b, 0x49, -0xac, 0xe8, 0x53, 0x48, 0xe3, 0x23, 0xfd, 0x69, -0x08, 0xc3, 0x16, 0x31, 0x71, 0xbe, 0xaa, 0x81, -0xde, 0x78, 0x55, 0xd0, 0x45, 0x03, 0x0c, 0x83, -0xff, 0x6d, 0xdf, 0x7c, 0x5e, 0xa4, 0xb8, 0x82, -0x38, 0x5e, 0x6f, 0xe6, 0xed, 0xa4, 0xc5, 0xd9, -0xa5, 0x7b, 0x33, 0x0b, 0xad, 0x2c, 0x32, 0xa3, -0xab, 0x1e, 0xbc, 0xf4, 0x2c, 0x0a, 0x8a, 0x07, -0x9f, 0xbb, 0x33, 0xeb, 0xac, 0xb0, 0xda, 0x44, -0x54, 0x08, 0x39, 0xb4, 0xc1, 0x8b, 0xb7, 0xec, -0xcd, 0x4b, 0xe2, 0x9b, 0xcd, 0x45, 0xc4, 0xc3, -0xa2, 0x22, 0x0a, 0x82, 0x7b, 0xd0, 0xdc, 0x84, -0xfc, 0x09, 0x33, 0x0b, 0x19, 0x48, 0x4e, 0x42, -0x62, 0x6e, 0x21, 0x1b, 0xc8, 0xc5, 0xbb, 0x10, -0x72, 0x90, 0xb5, 0xea, 0xbd, 0xfe, 0xf1, 0x7a, -0xc7, 0x08, 0x7a, 0x88, 0x20, 0xf5, 0xbd, 0xec, -0x97, 0xda, 0x37, 0x4d, 0x75, 0xbf, 0x9a, 0xea, -0x4f, 0xf5, 0xcc, 0x1c, 0xa2, 0x9e, 0x65, 0xcd, -0x2e, 0x32, 0x61, 0x66, 0x4c, 0x64, 0x2d, 0x4f, -0x5f, 0x75, 0x17, 0x2c, 0x1f, 0xf6, 0x88, 0x0f, -0x0d, 0x28, 0xfa, 0x9b, 0x68, 0x6e, 0x67, 0xc6, -0xf2, 0x61, 0x7e, 0xbf, 0xa0, 0x33, 0x1f, 0xe7, -0xc3, 0xf9, 0xd4, 0xa8, 0x3c, 0xa2, 0xf2, 0xf5, -0x15, 0xb0, 0xd8, 0x89, 0xd8, 0x96, 0x9b, 0xf9, -0x41, 0x39, 0x32, 0x28, 0xe5, 0x63, 0xf8, 0xad, -0x0e, 0x6b, 0xd6, 0x78, 0x01, 0x9a, 0xe1, 0x57, -0xa9, 0xb1, 0x11, 0x5d, 0xe4, 0x23, 0xc6, 0xf9, -0x70, 0xdc, 0x14, 0xf5, 0x10, 0x8b, 0xb7, 0x1e, -0x1f, 0x4f, 0xb3, 0x74, 0x7c, 0x27, 0x1f, 0x85, -0x1b, 0xd9, 0x80, 0x2e, 0xa2, 0x7f, 0x6a, 0x02, -0x34, 0xb8, 0x5f, 0x64, 0xe6, 0xd2, 0xc8, 0x42, -0x9e, 0x4f, 0x4f, 0x11, 0x0d, 0xce, 0x26, 0x9f, -0x85, 0xa2, 0x06, 0xab, 0x86, 0x0f, 0x05, 0x45, -0xca, 0xa6, 0x28, 0x9f, 0x1e, 0x7d, 0xa5, 0x44, -0x67, 0xf3, 0x86, 0xc6, 0x7a, 0x41, 0x3e, 0x14, -0xf4, 0x95, 0x3b, 0x6b, 0xb4, 0x31, 0xe0, 0xe4, -0x73, 0x09, 0x69, 0x50, 0x27, 0xad, 0x18, 0x2e, -0x21, 0x28, 0xbe, 0x30, 0x58, 0x98, 0xf3, 0x61, -0x66, 0x54, 0x71, 0x7f, 0x17, 0x4b, 0x72, 0xb5, -0x3f, 0x9b, 0x9c, 0x09, 0x83, 0xd1, 0x7f, 0x1b, -0xe7, 0xfa, 0x23, 0x76, 0xae, 0xea, 0x47, 0xc9, -0x61, 0x4b, 0x83, 0x64, 0x76, 0x8d, 0xf0, 0x44, -0x66, 0x8d, 0xa9, 0xa4, 0x91, 0x62, 0x7d, 0x8c, -0x7c, 0xd8, 0x36, 0x58, 0x28, 0x46, 0xa9, 0x99, -0x19, 0x89, 0xd5, 0xfe, 0x6d, 0x34, 0x17, 0x33, -0x62, 0x9c, 0xd9, 0x74, 0xea, 0x67, 0x1a, 0xc7, -0x4c, 0xe4, 0x43, 0x25, 0xd7, 0x45, 0xa2, 0x97, -0xed, 0x58, 0x3a, 0x87, 0xdb, 0x34, 0xdd, 0xc3, -0x08, 0xf5, 0x1f, 0xdf, 0xed, 0x3f, 0x0a, 0xcb, -0xf5, 0x8a, 0x0e, 0x93, 0xda, 0x03, 0xf8, 0x01, -0xcd, 0xde, 0xa4, 0x16, 0x0a, 0xe4, 0x43, 0xed, -0x65, 0x26, 0x24, 0x53, 0xac, 0x87, 0x6e, 0x22, -0xaf, 0xb7, 0xa6, 0xbc, 0xc5, 0x35, 0xd8, 0x90, -0xc7, 0xc5, 0x3e, 0x1c, 0xd5, 0x82, 0x2d, 0x79, -0x1d, 0xcd, 0x19, 0xc7, 0x38, 0xf5, 0x2c, 0xbe, -0x40, 0x1a, 0xf4, 0xa2, 0x0a, 0xce, 0x0b, 0x58, -0x2d, 0x7b, 0xb0, 0x5a, 0xb0, 0xed, 0x5c, 0x25, -0x2c, 0xec, 0x89, 0x3b, 0x19, 0x28, 0x3a, 0xf9, -0x60, 0xfd, 0x34, 0x4d, 0x91, 0xc0, 0x2d, 0xa2, -0xc1, 0x8d, 0xa5, 0x12, 0x1f, 0xa6, 0xc6, 0xad, -0x9f, 0x05, 0xa9, 0x86, 0x8d, 0x66, 0xd7, 0xf3, -0x2b, 0x32, 0xee, 0xfb, 0x68, 0x82, 0x8a, 0x54, -0xda, 0x6f, 0x76, 0x8c, 0xe9, 0x1b, 0x03, 0xce, -0xf5, 0xc1, 0xf7, 0xcb, 0xa0, 0x11, 0x4d, 0x78, -0xf0, 0x4b, 0x13, 0x06, 0x8d, 0x1f, 0x45, 0x5d, -0x2c, 0x42, 0xac, 0x31, 0x82, 0xa6, 0x19, 0x0f, -0x8c, 0x51, 0xce, 0xf5, 0xf1, 0xa8, 0xff, 0x10, -0x1f, 0x82, 0xc2, 0x69, 0x14, 0x70, 0x3e, 0xf5, -0xe4, 0x82, 0xb0, 0xa0, 0xa8, 0xc6, 0xf8, 0x10, -0xf3, 0xd9, 0x3f, 0x4d, 0x7c, 0x88, 0xcd, 0x60, -0x3f, 0x32, 0xd9, 0x7c, 0x0b, 0xf9, 0x10, 0x52, -0x3e, 0xcc, 0x41, 0xd1, 0xc9, 0x47, 0xec, 0xe8, -0x3f, 0xa5, 0xb6, 0x93, 0x1b, 0xe7, 0xfa, 0xa8, -0xca, 0x55, 0x78, 0x08, 0x35, 0xfa, 0xe2, 0x40, -0x32, 0xf1, 0x30, 0x6b, 0x3b, 0x1e, 0x99, 0xf5, -0xbc, 0x23, 0x39, 0xf9, 0x24, 0xb8, 0x4d, 0x53, -0xb8, 0x4d, 0x9a, 0xf6, 0x0b, 0x37, 0x4e, 0xfb, -0x5b, 0x70, 0x5c, 0xdc, 0xc2, 0x48, 0xbc, 0x95, -0xfe, 0xcb, 0xe9, 0x3f, 0x31, 0x9e, 0xe0, 0x09, -0x35, 0xf5, 0x4d, 0xf5, 0x91, 0x7e, 0xba, 0x11, -0xa9, 0xba, 0x5f, 0x95, 0x30, 0x84, 0x48, 0x79, -0x64, 0x7e, 0x82, 0x34, 0xe2, 0xd4, 0x33, 0xbe, -0x53, 0x8f, 0xa9, 0xc9, 0xb8, 0x1a, 0xcb, 0xfb, -0xd0, 0x3e, 0x3d, 0xa9, 0xaa, 0x0d, 0x5c, 0xd6, -0x06, 0x2f, 0x46, 0xf3, 0x02, 0xda, 0xaa, 0x4e, -0x66, 0xd3, 0xc9, 0x67, 0x51, 0x5e, 0x19, 0x86, -0xd1, 0x52, 0x08, 0xdf, 0xcb, 0x64, 0x80, 0xa6, -0x1e, 0xa0, 0x19, 0x1a, 0x73, 0x37, 0x33, 0x6e, -0xff, 0x51, 0xc4, 0x87, 0x83, 0x0a, 0x3d, 0xa7, -0xdc, 0xf9, 0xd4, 0xd0, 0x89, 0x14, 0xd7, 0xa7, -0xd7, 0x49, 0xf6, 0x84, 0xb5, 0x25, 0xa1, 0x75, -0xe7, 0x6b, 0x1f, 0x41, 0xb1, 0x15, 0xdc, 0xcc, -0xb0, 0xf0, 0x81, 0x1c, 0xe3, 0x43, 0xec, 0x3f, -0x9d, 0x8b, 0xc1, 0x8c, 0xec, 0x9e, 0xf6, 0xfd, -0x4e, 0xec, 0x37, 0x64, 0x57, 0x04, 0xca, 0x1a, -0x08, 0x3a, 0x32, 0x0e, 0x6c, 0xc4, 0xa9, 0x1f, -0x2a, 0xc0, 0xfc, 0xb9, 0x83, 0xbf, 0x36, 0x81, -0x25, 0x09, 0xb6, 0x36, 0x45, 0x6e, 0x8a, 0x7a, -0x00, 0x69, 0xb1, 0x50, 0x95, 0xf9, 0xb0, 0x9f, -0x19, 0x1b, 0x71, 0xeb, 0x67, 0xa5, 0x7a, 0x41, -0xdd, 0x7b, 0xde, 0x3a, 0xaa, 0x57, 0x2a, 0x55, -0xf5, 0xdb, 0xf3, 0x83, 0x47, 0x27, 0x57, 0xc4, -0x05, 0x34, 0xc7, 0xd0, 0x54, 0x53, 0xe3, 0xe4, -0x23, 0x90, 0x07, 0x90, 0x0f, 0xf1, 0xa6, 0xff, -0xf3, 0x1c, 0xdd, 0xfd, 0x2f, 0x37, 0x0b, 0x0c, -0x78, 0x2b, 0x0f, 0x1c, 0xc9, 0xf8, 0x70, 0xf7, -0xd9, 0xb3, 0xc4, 0x87, 0xcf, 0xae, 0x1d, 0x31, -0x7c, 0xf8, 0xc4, 0xf0, 0xe1, 0xef, 0x64, 0x96, -0x9d, 0xe5, 0x70, 0x2a, 0xe3, 0xc3, 0x93, 0x37, -0xce, 0x13, 0x1f, 0x6e, 0xbf, 0x3e, 0x65, 0xc0, -0xec, 0x95, 0xe5, 0xc3, 0x5f, 0xb7, 0x5f, 0x6d, -0x97, 0x78, 0xec, 0x7d, 0x65, 0xb0, 0xf0, 0xe5, -0x3a, 0x1e, 0xf6, 0xdf, 0x14, 0x14, 0xe7, 0x1e, -0x2f, 0x93, 0x31, 0x7c, 0x68, 0x22, 0xdf, 0xba, -0xeb, 0x0d, 0x16, 0xfe, 0xf3, 0x37, 0xa5, 0x91, -0x81, 0xe2, 0x0d, 0x63, 0x2c, 0x1f, 0x52, 0xa4, -0xc4, 0xab, 0x27, 0x33, 0x3e, 0x3c, 0xb0, 0xef, -0xdc, 0x9f, 0x77, 0xda, 0xb4, 0xfe, 0xbb, 0x73, -0xa3, 0xcf, 0xe9, 0x85, 0x39, 0x6a, 0x7e, 0x78, -0xf6, 0x11, 0x8e, 0x58, 0xf8, 0xb6, 0xc6, 0xbf, -0x8b, 0xf5, 0x0f, 0x3f, 0x0a, 0x8b, 0xc5, 0x62, -0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0xfa, 0xd4, -0x65, 0x66, 0x07, 0xc9, 0xb3, 0x03, 0x8b, 0xc5, -0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x7a, -0xb7, 0xcc, 0xec, 0x50, 0xe3, 0xd9, 0x81, 0xc5, -0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, -0xbd, 0x5b, 0x66, 0x76, 0xf0, 0xcc, 0xec, 0xf0, -0xb1, 0x53, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b, -0xc5, 0x62, 0xb1, 0x58, 0xff, 0xa3, 0x22, 0xfa, -0x7d, 0x1c, 0x3c, 0xfb, 0x23, 0x02, 0x4d, 0xbf, -0x5a, 0xa9, 0x46, 0xa0, 0xde, 0xfb, 0xf3, 0x84, -0xf4, 0xb5, 0x13, 0x11, 0x6c, 0x88, 0xe2, 0x98, -0x7f, 0x7d, 0xb9, 0x73, 0xdd, 0x1b, 0x3b, 0x1c, -0x29, 0xc2, 0xf0, 0x33, 0x01, 0x00, diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c deleted file mode 100644 index 03bf9c8..0000000 --- a/board/esd/plu405/plu405.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> -#include <sja1000.h> - -#undef FPGA_DEBUG - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -/* fpga configuration data - gzip compressed and generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - -/* - * generate a short spike on the CAN tx line - * to bring the couplers in sync - */ -void init_coupler(u32 addr) -{ - struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr; - - /* reset */ - out_8(&ctrl->cr, CR_RR); - - /* dominant */ - out_8(&ctrl->btr0, 0x00); /* btr setup is required */ - out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */ - out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 | - OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1); - out_8(&ctrl->cr, 0x00); - - /* delay */ - in_8(&ctrl->cr); - in_8(&ctrl->cr); - in_8(&ctrl->cr); - in_8(&ctrl->cr); - - /* reset */ - out_8(&ctrl->cr, CR_RR); -} - -int board_early_init_f(void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to - * 512 ebc-clks -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -int misc_init_r(void) -{ - unsigned char *dst; - unsigned char fctr; - ulong len = sizeof(fpgadata); - int status; - int index; - int i; - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, - (uchar *)fpgadata, &len) != 0) { - printf("GUNZIP ERROR - must RESET board to recover\n"); - do_reset(NULL, 0, 0, NULL); - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low " - "after asserting PROGRAM*)\n"); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high " - "after deasserting PROGRAM*)\n"); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high " - "after programming FPGA)\n"); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc('\n'); - - free(dst); - - /* - * Reset FPGA via FPGA_DATA pin - */ - SET_FPGA(FPGA_PRG | FPGA_CLK); - udelay(1000); /* wait 1ms */ - SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); - udelay(1000); /* wait 1ms */ - - /* - * Reset external DUARTs - */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); - udelay(10); - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); - udelay(1000); - - /* - * Set NAND-FLASH GPIO signals to default - */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & - ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); - - /* - * Setup EEPROM write protection - */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); - out_be32((void*)GPIO0_TCR, - in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); - - /* - * Enable interrupts in exar duart mcr[3] - */ - out_8((void *)DUART0_BA + 4, 0x08); - out_8((void *)DUART1_BA + 4, 0x08); - - /* - * Enable auto RS485 mode in 2nd external uart - */ - out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */ - fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */ - fctr |= 0x08; /* enable RS485 mode */ - out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */ - out_8((void *)DUART1_BA + 3, 0); /* write LCR */ - - /* - * Init magnetic couplers - */ - if (!getenv("noinitcoupler")) { - init_coupler(CAN0_BA); - init_coupler(CAN1_BA); - } - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - - puts("Board: "); - - if (i == -1) - puts("### No HW ID - assuming PLU405"); - else - puts(str); - - putc('\n'); - return 0; -} - -#ifdef CONFIG_IDE_RESET -#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL) -void ide_set_reset(int on) -{ - /* - * Assert or deassert CompactFlash Reset Pin - */ - if (on) { /* assert RESET */ - out_be16((void *)FPGA_CTRL, - in_be16((void *)FPGA_CTRL) & - ~CONFIG_SYS_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - out_be16((void *)FPGA_CTRL, - in_be16((void *)FPGA_CTRL) | - CONFIG_SYS_FPGA_CTRL_CF_RESET); - } -} -#endif /* CONFIG_IDE_RESET */ - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable(unsigned dev_addr, int state) -{ - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & - ~CONFIG_SYS_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | - CONFIG_SYS_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = ((in_be32((void*)GPIO0_OR) & - CONFIG_SYS_EEPROM_WP) == 0); - break; - } - } - return state; -} - -int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts("Query of write access state failed.\n"); - } else { - printf("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, - state ? "en" : "dis"); - state = 0; - } - } else { - if (argv[1][0] == '0') { - /* Disable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1); - } - if (state < 0) - puts("Setup of write access state failed.\n"); - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/pmc405de/Kconfig b/board/esd/pmc405de/Kconfig deleted file mode 100644 index 4b05787..0000000 --- a/board/esd/pmc405de/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PMC405DE - -config SYS_BOARD - default "pmc405de" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "PMC405DE" - -endif diff --git a/board/esd/pmc405de/MAINTAINERS b/board/esd/pmc405de/MAINTAINERS deleted file mode 100644 index a891e23..0000000 --- a/board/esd/pmc405de/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PMC405DE BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/pmc405de/ -F: include/configs/PMC405DE.h -F: configs/PMC405DE_defconfig diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile deleted file mode 100644 index b3f6dcd..0000000 --- a/board/esd/pmc405de/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pmc405de.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/pmc405de/chip_config.c b/board/esd/pmc405de/chip_config.c deleted file mode 100644 index c06a6ae..0000000 --- a/board/esd/pmc405de/chip_config.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "133", - "CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66", - { - 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00 - } - }, - { - "266", - "CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66", - { - 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00 - } - }, - { - "333", - "CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111", - { - 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c deleted file mode 100644 index 31ac728..0000000 --- a/board/esd/pmc405de/pmc405de.c +++ /dev/null @@ -1,507 +0,0 @@ -/* - * (C) Copyright 2009 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <console.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/4xx_pci.h> -#include <command.h> -#include <malloc.h> - -/* - * PMC405-DE cpld registers - * - all registers are 8 bit - * - all registers are on 32 bit addesses - */ -struct pmc405de_cpld { - /* cpld design version */ - u8 version; - u8 reserved0[3]; - - /* misc. status lines */ - u8 status; - u8 reserved1[3]; - - /* - * gated control flags - * gate bit(s) must be written with '1' to - * access control flag - */ - u8 control; - u8 reserved2[3]; -}; - -#define CPLD_VERSION_MASK 0x0f -#define CPLD_CONTROL_POSTLED_N 0x01 -#define CPLD_CONTROL_POSTLED_GATE 0x02 -#define CPLD_CONTROL_RESETOUT_N 0x40 -#define CPLD_CONTROL_RESETOUT_N_GATE 0x80 - -DECLARE_GLOBAL_DATA_PTR; - -extern void __ft_board_setup(void *blob, bd_t *bd); -extern void pll_write(u32 a, u32 b); - -static int wait_for_pci_ready_done; - -static int is_monarch(void); -static int pci_is_66mhz(void); -static int board_revision(void); -static int cpld_revision(void); -static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div); - -int board_early_init_f(void) -{ - u32 pllmr0, pllmr1; - - /* - * check M66EN and patch PLB:PCI divider for 66MHz PCI - * - * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1 - * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2 - * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2 - * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3 - * - * calling upd_plb_pci_div() may end in calling pll_write() which will - * do a chip reset and never return. - */ - pllmr0 = mfdcr(CPC0_PLLMR0); - pllmr1 = mfdcr(CPC0_PLLMR1); - - if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) { - /* fCPU=333MHz, fPLB=111MHz */ - if (pci_is_66mhz()) - upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1); - else - upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2); - } else { - /* fCPU=133|266MHz, fPLB=133MHz */ - if (pci_is_66mhz()) - upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2); - else - upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3); - } - - /* - * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive - * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive - * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive - * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive - * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: - * - set ready timeout to 512 ebc-clks -> ca. 15 us - * - EBC lines are always driven - */ - mtebc(EBC0_CFG, 0xa8400000); - - return 0; -} - -static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div) -{ - if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div) - pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1); -} - -int misc_init_r(void) -{ - int i; - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - struct pmc405de_cpld *cpld = - (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; - - if (!is_monarch()) { - /* PCI configuration done: release EREADY */ - setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY); - setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY); - } - - /* turn off POST LED */ - out_8(&cpld->control, - CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE); - - /* turn on LEDs: RUN, A, B */ - clrbits_be32(&gpio0->or, - CONFIG_SYS_GPIO_LEDRUN_N | - CONFIG_SYS_GPIO_LEDA_N | - CONFIG_SYS_GPIO_LEDB_N); - - for (i=0; i < 200; i++) - udelay(1000); - - /* turn off LEDs: A, B */ - setbits_be32(&gpio0->or, - CONFIG_SYS_GPIO_LEDA_N | - CONFIG_SYS_GPIO_LEDB_N); - - return (0); -} - -static int is_monarch(void) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0; -} - -static int pci_is_66mhz(void) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN); -} - -static int board_revision(void) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >> - CONFIG_SYS_GPIO_HWREV_SHIFT); -} - -static int cpld_revision(void) -{ - struct pmc405de_cpld *cpld = - (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; - return ((in_8(&cpld->version) & CPLD_VERSION_MASK)); -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - puts("Board: esd GmbH - PMC-CPU/405-DE"); - - gd->board_type = board_revision(); - printf(", Rev 1.%ld, ", gd->board_type); - - if (!is_monarch()) - puts("non-"); - - printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n", - pci_is_66mhz() ? "66" : "33", cpld_revision()); - - return 0; -} - - -static void wait_for_pci_ready(void) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - int i; - char *s = getenv("pcidelay"); - - /* only wait once */ - if (wait_for_pci_ready_done) - return; - - /* - * We have our own handling of the pcidelay variable. - * Using CONFIG_PCI_BOOTDELAY enables pausing for host - * and adapter devices. For adapter devices we do not - * want this. - */ - if (s) { - int ms = simple_strtoul(s, NULL, 10); - printf("PCI: Waiting for %d ms\n", ms); - for (i=0; i<ms; i++) - udelay(1000); - } - - if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) { - printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); - while (1) { - if (ctrlc()) { - puts("abort\n"); - break; - } - if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) { - printf("done\n"); - break; - } - } - } - - wait_for_pci_ready_done = 1; -} - -/* - * Overwrite weak is_pci_host() - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - */ -int is_pci_host(struct pci_controller *hose) -{ - char *s; - - if (!is_monarch()) { - /* - * Overwrite PCI identification when running in - * non-monarch mode - * This should be moved into pci_target_init() - * when it is sometimes available for 405 CPUs - */ - pci_write_config_word(PCIDEVID_405GP, - PCI_SUBSYSTEM_ID, - CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); - pci_write_config_word(PCIDEVID_405GP, - PCI_CLASS_SUB_CODE, - CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); - } - - s = getenv("pciscan"); - if (s == NULL) { - if (is_monarch()) { - wait_for_pci_ready(); - return 1; - } else { - return 0; - } - } else { - if (!strcmp(s, "yes")) - return 1; - } - - return 0; -} - -/* - * Overwrite weak pci_pre_init() - * - * The default implementation enables the 405EP - * internal PCI arbiter. We do not want that - * on a PMC module. - */ -int pci_pre_init(struct pci_controller *hose) -{ - return 1; -} - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - - __ft_board_setup(blob, bd); - - /* - * Disable PCI in non-monarch mode. - */ - if (!is_monarch()) { - rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", - "disabled", sizeof("disabled"), 1); - if (rc) { - printf("Unable to update property status in PCI node, " - "err=%s\n", - fdt_strerror(rc)); - } - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable(unsigned dev_addr, int state) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - - if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO0. */ - clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO0. */ - setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32(&gpio0->or) & - CONFIG_SYS_GPIO_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1); - if (state < 0) { - puts("Query of write access state failed.\n"); - } else { - printf("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, - state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable( - CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable( - CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) - puts ("Setup of write access state failed.\n"); - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - -#if defined(CONFIG_PRAM) -#include <environment.h> - -int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 pram, nextbase, base; - char *v; - u32 param; - ulong *lptr; - - v = getenv("pram"); - if (v) - pram = simple_strtoul(v, NULL, 10); - else { - printf("Error: pram undefined. Please define pram in KiB\n"); - return 1; - } - - base = gd->bd->bi_memsize; -#if defined(CONFIG_LOGBUFFER) - base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; -#endif - /* - * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE - */ - param = base - (pram << 10); - printf("PARAM: @%08x\n", param); - debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base); - - /* clear entire PA ram */ - memset((void*)param, 0, (pram << 10)); - - /* reserve 4k for pointer field */ - nextbase = base - 4096; - lptr = (ulong*)(base); - - /* - * *(--lptr) = item_size; - * *(--lptr) = base - item_base = distance from field top; - */ - - /* env is first (4k aligned) */ - nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); - memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); - *(--lptr) = CONFIG_ENV_SIZE; /* size */ - *(--lptr) = base - nextbase; /* offset | type=0 */ - - /* free section */ - *(--lptr) = nextbase - param; /* size */ - *(--lptr) = (base - param) | 126; /* offset | type=126 */ - - /* terminate pointer field */ - *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); - *(--lptr) = 0; /* offset=0 -> terminator */ - return 0; -} -U_BOOT_CMD( - painit, 1, 1, do_painit, - "prepare PciAccess system", - "" -); -#endif /* CONFIG_PRAM */ - -int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; - setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N); - return 0; -} -U_BOOT_CMD( - selfreset, 1, 1, do_selfreset, - "assert self-reset# signal", - "" -); - -int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - struct pmc405de_cpld *cpld = - (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; - - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("PMC-RESETOUT# asserted\n"); - out_8(&cpld->control, - CPLD_CONTROL_RESETOUT_N_GATE); - } else { - /* deassert */ - printf("PMC-RESETOUT# deasserted\n"); - out_8(&cpld->control, - CPLD_CONTROL_RESETOUT_N | - CPLD_CONTROL_RESETOUT_N_GATE); - } - } else { - printf("PMC-RESETOUT# is %s\n", - (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ? - "inactive" : "active"); - } - return 0; -} -U_BOOT_CMD( - resetout, 2, 1, do_resetout, - "assert PMC-RESETOUT# signal", - "" -); diff --git a/board/esd/pmc440/Kconfig b/board/esd/pmc440/Kconfig deleted file mode 100644 index df8bd65..0000000 --- a/board/esd/pmc440/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_PMC440 - -config SYS_BOARD - default "pmc440" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "PMC440" - -endif diff --git a/board/esd/pmc440/MAINTAINERS b/board/esd/pmc440/MAINTAINERS deleted file mode 100644 index 32fb9ba..0000000 --- a/board/esd/pmc440/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PMC440 BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/pmc440/ -F: include/configs/PMC440.h -F: configs/PMC440_defconfig diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile deleted file mode 100644 index 708e9d1..0000000 --- a/board/esd/pmc440/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \ - ../common/cmd_loadpci.o -extra-y += init.o diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c deleted file mode 100644 index b7cd595..0000000 --- a/board/esd/pmc440/cmd_pmc440.c +++ /dev/null @@ -1,554 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <console.h> -#include <asm/io.h> -#include <asm/cache.h> -#include <asm/processor.h> -#if defined(CONFIG_LOGBUFFER) -#include <logbuff.h> -#endif - -#include "pmc440.h" - -int is_monarch(void); -int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); -int eeprom_write_enable(unsigned dev_addr, int state); - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_BSP) - -static int got_fifoirq; -static int got_hcirq; - -int fpga_interrupt(u32 arg) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg; - int rc = -1; /* not for us */ - u32 status = FPGA_IN32(&fpga->status); - - /* check for interrupt from fifo module */ - if (status & STATUS_FIFO_ISF) { - /* disable this int source */ - FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE); - rc = 0; - got_fifoirq = 1; /* trigger backend */ - } - - if (status & STATUS_HOST_ISF) { - FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE); - rc = 0; - got_hcirq = 1; - } - - return rc; -} - -int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - got_hcirq = 0; - - FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE); - FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE); - - irq_install_handler(IRQ0_FPGA, - (interrupt_handler_t *)fpga_interrupt, - fpga); - - FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE); - - while (!got_hcirq) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - break; - } - } - if (got_hcirq) - printf("Got interrupt!\n"); - - FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE); - irq_free_handler(IRQ0_FPGA); - return 0; -} -U_BOOT_CMD( - waithci, 1, 1, do_waithci, - "Wait for host control interrupt", - "" -); - -void dump_fifo(pmc440_fpga_t *fpga, int f, int *n) -{ - u32 ctrl; - - while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) { - printf("%5d %d %3d %08x", - (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL), - FPGA_IN32(&fpga->fifo[f].data)); - if (ctrl & FIFO_OVERFLOW) { - printf(" OVERFLOW\n"); - FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW); - } else - printf("\n"); - } -} - -int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - int i; - int n = 0; - u32 ctrl, data, f; - char str[] = "\\|/-"; - int abort = 0; - int count = 0; - int count2 = 0; - - switch (argc) { - case 1: - /* print all fifos status information */ - printf("fifo level status\n"); - printf("______________________________\n"); - for (i=0; i<FIFO_COUNT; i++) { - ctrl = FPGA_IN32(&fpga->fifo[i].ctrl); - printf(" %d %3d %s%s%s %s\n", - i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL), - ctrl & FIFO_FULL ? "FULL " : "", - ctrl & FIFO_EMPTY ? "EMPTY " : "", - ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY", - ctrl & FIFO_OVERFLOW ? "OVERFLOW" : ""); - } - break; - - case 2: - /* completely read out fifo 'n' */ - if (!strcmp(argv[1],"read")) { - printf(" # fifo level data\n"); - printf("______________________________\n"); - - for (i=0; i<FIFO_COUNT; i++) - dump_fifo(fpga, i, &n); - - } else if (!strcmp(argv[1],"wait")) { - got_fifoirq = 0; - - irq_install_handler(IRQ0_FPGA, - (interrupt_handler_t *)fpga_interrupt, - fpga); - - printf(" # fifo level data\n"); - printf("______________________________\n"); - - /* enable all fifo interrupts */ - FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG); - for (i=0; i<FIFO_COUNT; i++) { - /* enable interrupts from all fifos */ - FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE); - } - - while (1) { - /* wait loop */ - while (!got_fifoirq) { - count++; - if (!(count % 100)) { - count2++; - putc(0x08); /* backspace */ - putc(str[count2 % 4]); - } - - /* Abort if ctrl-c was pressed */ - if ((abort = ctrlc())) { - puts("\nAbort\n"); - break; - } - udelay(1000); - } - if (abort) - break; - - /* simple fifo backend */ - if (got_fifoirq) { - for (i=0; i<FIFO_COUNT; i++) - dump_fifo(fpga, i, &n); - - got_fifoirq = 0; - /* unmask global fifo irq */ - FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_FIFOIE_GATE | - HOSTCTRL_FIFOIE_FLAG); - } - } - - /* disable all fifo interrupts */ - FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE); - for (i=0; i<FIFO_COUNT; i++) - FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE); - - irq_free_handler(IRQ0_FPGA); - - } else { - printf("Usage:\nfifo %s\n", cmdtp->help); - return 1; - } - break; - - case 4: - case 5: - if (!strcmp(argv[1],"write")) { - /* get fifo number or fifo address */ - f = simple_strtoul(argv[2], NULL, 16); - - /* data paramter */ - data = simple_strtoul(argv[3], NULL, 16); - - /* get optional count parameter */ - n = 1; - if (argc >= 5) - n = (int)simple_strtoul(argv[4], NULL, 10); - - if (f < FIFO_COUNT) { - printf("writing %d x %08x to fifo %d\n", - n, data, f); - for (i=0; i<n; i++) - FPGA_OUT32(&fpga->fifo[f].data, data); - } else { - printf("writing %d x %08x to fifo port at " - "address %08x\n", - n, data, f); - for (i=0; i<n; i++) - out_be32((void *)f, data); - } - } else { - printf("Usage:\nfifo %s\n", cmdtp->help); - return 1; - } - break; - - default: - printf("Usage:\nfifo %s\n", cmdtp->help); - return 1; - } - return 0; -} -U_BOOT_CMD( - fifo, 5, 1, do_fifo, - "Fifo module operations", - "wait\nfifo read\n" - "fifo write fifo(0..3) data [cnt=1]\n" - "fifo write address(>=4) data [cnt=1]\n" - " - without arguments: print all fifo's status\n" - " - with 'wait' argument: interrupt driven read from all fifos\n" - " - with 'read' argument: read current contents from all fifos\n" - " - with 'write' argument: write 'data' 'cnt' times to " - "'fifo' or 'address'" -); - -int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong sdsdp[5]; - ulong delay; - int count=16; - - if (argc < 2) { - printf("Usage:\nsbe %s\n", cmdtp->help); - return -1; - } - - if (argc > 1) { - if (!strcmp(argv[1], "400")) { - /* PLB=133MHz, PLB/PCI=3 */ - printf("Bootstrapping for 400MHz\n"); - sdsdp[0]=0x8678624e; - sdsdp[1]=0x095fa030; - sdsdp[2]=0x40082350; - sdsdp[3]=0x0d050000; - } else if (!strcmp(argv[1], "533")) { - /* PLB=133MHz, PLB/PCI=3 */ - printf("Bootstrapping for 533MHz\n"); - sdsdp[0]=0x87788252; - sdsdp[1]=0x095fa030; - sdsdp[2]=0x40082350; - sdsdp[3]=0x0d050000; - } else if (!strcmp(argv[1], "667")) { - /* PLB=133MHz, PLB/PCI=3 */ - printf("Bootstrapping for 667MHz\n"); - sdsdp[0]=0x8778a256; - sdsdp[1]=0x095fa030; - sdsdp[2]=0x40082350; - sdsdp[3]=0x0d050000; - } else { - printf("Usage:\nsbe %s\n", cmdtp->help); - return -1; - } - } - - if (argc > 2) { - sdsdp[4] = 0; - if (argv[2][0]=='1') - sdsdp[4]=0x19750100; - else if (argv[2][0]=='0') - sdsdp[4]=0x19750000; - if (sdsdp[4]) - count += 4; - } - - if (argc > 3) { - delay = simple_strtoul(argv[3], NULL, 10); - if (delay > 20) - delay = 20; - sdsdp[4] |= delay; - } - - printf("Writing boot EEPROM ...\n"); - if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, - 0, (uchar*)sdsdp, count) != 0) - printf("bootstrap_eeprom_write failed\n"); - else - printf("done (dump via 'i2c md 52 0.1 14')\n"); - - return 0; -} -U_BOOT_CMD( - sbe, 4, 0, do_setup_bootstrap_eeprom, - "setup bootstrap eeprom", - "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]" -); - -#if defined(CONFIG_PRAM) -#include <environment.h> -#include <search.h> -#include <errno.h> - -int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 pram, nextbase, base; - char *v; - u32 param; - ulong *lptr; - - env_t *envp; - char *res; - int len; - - v = getenv("pram"); - if (v) - pram = simple_strtoul(v, NULL, 10); - else { - printf("Error: pram undefined. Please define pram in KiB\n"); - return 1; - } - - base = (u32)gd->ram_size; -#if defined(CONFIG_LOGBUFFER) - base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; -#endif - /* - * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE - */ - param = base - (pram << 10); - printf("PARAM: @%08x\n", param); - debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base); - - /* clear entire PA ram */ - memset((void*)param, 0, (pram << 10)); - - /* reserve 4k for pointer field */ - nextbase = base - 4096; - lptr = (ulong*)(base); - - /* - * *(--lptr) = item_size; - * *(--lptr) = base - item_base = distance from field top; - */ - - /* env is first (4k aligned) */ - nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); - envp = (env_t *)nextbase; - res = (char *)envp->data; - len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); - if (len < 0) { - error("Cannot export environment: errno = %d\n", errno); - return 1; - } - envp->crc = crc32(0, envp->data, ENV_SIZE); - - *(--lptr) = CONFIG_ENV_SIZE; /* size */ - *(--lptr) = base - nextbase; /* offset | type=0 */ - - /* free section */ - *(--lptr) = nextbase - param; /* size */ - *(--lptr) = (base - param) | 126; /* offset | type=126 */ - - /* terminate pointer field */ - *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); - *(--lptr) = 0; /* offset=0 -> terminator */ - return 0; -} -U_BOOT_CMD( - painit, 1, 1, do_painit, - "prepare PciAccess system", - "" -); -#endif /* CONFIG_PRAM */ - -int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - in_be32((void*)CONFIG_SYS_RESET_BASE); - return 0; -} -U_BOOT_CMD( - selfreset, 1, 1, do_selfreset, - "assert self-reset# signal", - "" -); - -int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - /* requiers bootet FPGA and PLD_IOEN_N active */ - if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) { - printf("Error: resetout requires a bootet FPGA\n"); - return -1; - } - - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("PMC-RESETOUT# asserted\n"); - FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_PMCRSTOUT_GATE); - } else { - /* deassert */ - printf("PMC-RESETOUT# deasserted\n"); - FPGA_OUT32(&fpga->hostctrl, - HOSTCTRL_PMCRSTOUT_GATE | - HOSTCTRL_PMCRSTOUT_FLAG); - } - } else { - printf("PMC-RESETOUT# is %s\n", - FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ? - "inactive" : "active"); - } - - return 0; -} -U_BOOT_CMD( - resetout, 2, 1, do_resetout, - "assert PMC-RESETOUT# signal", - "" -); - -int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (is_monarch()) { - printf("This command is only supported in non-monarch mode\n"); - return -1; - } - - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("inta# asserted\n"); - out_be32((void*)GPIO1_TCR, - in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE); - } else { - /* deassert */ - printf("inta# deasserted\n"); - out_be32((void*)GPIO1_TCR, - in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE); - } - } else { - printf("inta# is %s\n", - in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? - "active" : "inactive"); - } - return 0; -} -U_BOOT_CMD( - inta, 2, 1, do_inta, - "Assert/Deassert or query INTA# state in non-monarch mode", - "" -); - -/* test-only */ -int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong pciaddr; - - if (argc > 1) { - pciaddr = simple_strtoul(argv[1], NULL, 16); - - pciaddr &= 0xf0000000; - - /* map PCI address at 0xc0000000 in PLB space */ - - /* PMM1 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1MA, 0x00000000); - /* PMM1 Local Address */ - out32r(PCIL0_PMM1LA, 0xc0000000); - /* PMM1 PCI Low Address */ - out32r(PCIL0_PMM1PCILA, pciaddr); - /* PMM1 PCI High Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); - /* 256MB + No prefetching, and enable region */ - out32r(PCIL0_PMM1MA, 0xf0000001); - } else { - printf("Usage:\npmm %s\n", cmdtp->help); - } - return 0; -} -U_BOOT_CMD( - pmm, 2, 1, do_pmm, - "Setup pmm[1] registers", - "<pciaddr> (pciaddr will be aligned to 256MB)" -); - -#if defined(CONFIG_SYS_EEPROM_WREN) -int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts("Query of write access state failed.\n"); - } else { - printf("Write access for device 0x%0x is %sabled.\n", - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts("Setup of write access state failed.\n"); - } - } - - return state; -} -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - "" -); -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - -#endif /* CONFIG_CMD_BSP */ diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk deleted file mode 100644 index 9cb071e..0000000 --- a/board/esd/pmc440/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c deleted file mode 100644 index f876da8..0000000 --- a/board/esd/pmc440/fpga.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <spartan2.h> -#include <spartan3.h> -#include <command.h> -#include "fpga.h" -#include "pmc440.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_FPGA) - -#define USE_SP_CODE - -#ifdef USE_SP_CODE -xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_init_fn, - NULL, /* err */ - fpga_done_fn, - fpga_clk_fn, - fpga_cs_fn, - fpga_wr_fn, - NULL, /* rdata */ - fpga_wdata_fn, - fpga_busy_fn, - fpga_abort_fn, - fpga_post_config_fn, -}; -#else -xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = { - fpga_pre_config_fn, - fpga_pgm_fn, - fpga_clk_fn, - fpga_init_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_post_config_fn, -}; -#endif - -xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = { - ngcc_fpga_pre_config_fn, - ngcc_fpga_pgm_fn, - ngcc_fpga_clk_fn, - ngcc_fpga_init_fn, - ngcc_fpga_done_fn, - ngcc_fpga_wr_fn, - ngcc_fpga_post_config_fn -}; - -xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - XILINX_XC3S1200E_DESC( -#ifdef USE_SP_CODE - slave_parallel, -#else - slave_serial, -#endif - (void *)&pmc440_fpga_fns, - 0), - XILINX_XC2S200_DESC( - slave_serial, - (void *)&ngcc_fpga_fns, - 0) -}; - - -/* - * Set the active-low FPGA reset signal. - */ -void fpga_reset(int assert) -{ - debug("%s:%d: RESET ", __FUNCTION__, __LINE__); - if (assert) { - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA); - debug("asserted\n"); - } else { - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA); - debug("deasserted\n"); - } -} - - -/* - * Initialize the SelectMap interface. We assume that the mode and the - * initial state of all of the port pins have already been set! - */ -void fpga_serialslave_init(void) -{ - debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__, - __LINE__); - fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ -} - - -/* - * Set the FPGA's active-low SelectMap program line to the specified level - */ -int fpga_pgm_fn(int assert, int flush, int cookie) -{ - debug("%s:%d: FPGA PROGRAM ", - __FUNCTION__, __LINE__); - - if (assert) { - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG); - debug("asserted\n"); - } else { - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG); - debug("deasserted\n"); - } - return assert; -} - - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int fpga_init_fn(int cookie) -{ - if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT) - return 0; - else - return 1; -} - -#ifdef USE_SP_CODE -int fpga_abort_fn(int cookie) -{ - return 0; -} - - -int fpga_cs_fn(int assert_cs, int flush, int cookie) -{ - return assert_cs; -} - - -int fpga_busy_fn(int cookie) -{ - return 1; -} -#endif - - -/* - * Test the state of the active-high FPGA DONE pin - */ -int fpga_done_fn(int cookie) -{ - if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE) - return 1; - else - return 0; -} - - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int fpga_pre_config_fn(int cookie) -{ - debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset(true); - - /* release init# */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT); - /* disable PLD IOs */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N); - return 0; -} - - -/* - * FPGA post configuration function. Blip the FPGA reset line and then see if - * the FPGA appears to be running. - */ -int fpga_post_config_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - int rc=0; - char *s; - - debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); - - /* enable PLD0..7 pins */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N); - - fpga_reset(true); - udelay (100); - fpga_reset(false); - udelay (100); - - FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK); - - /* NGCC/CANDES only: enable ledlink */ - if ((s = getenv("bd_type")) && - ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) - FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); - - return rc; -} - - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - if (assert_clk) - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK); - else - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK); - - return assert_clk; -} - - -int fpga_wr_fn(int assert_write, int flush, int cookie) -{ - if (assert_write) - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA); - else - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA); - - return assert_write; -} - -#ifdef USE_SP_CODE -int fpga_wdata_fn(uchar data, int flush, int cookie) -{ - uchar val = data; - ulong or = in_be32((void*)GPIO1_OR); - int i = 7; - do { - /* Write data */ - if (val & 0x80) - or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA; - else - or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA); - - out_be32((void*)GPIO1_OR, or); - - /* Assert the clock */ - or |= GPIO1_FPGA_CLK; - out_be32((void*)GPIO1_OR, or); - val <<= 1; - i --; - } while (i > 0); - - /* Write last data bit (the 8th clock comes from the sp_load() code */ - if (val & 0x80) - or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA; - else - or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA); - - out_be32((void*)GPIO1_OR, or); - - return 0; -} -#endif - -#define NGCC_FPGA_PRG CLOCK_EN -#define NGCC_FPGA_DATA RESET_OUT -#define NGCC_FPGA_DONE CLOCK_IN -#define NGCC_FPGA_INIT IRIGB_R_IN -#define NGCC_FPGA_CLK CLOCK_OUT - -void ngcc_fpga_serialslave_init(void) -{ - debug("%s:%d: Initialize serial slave interface\n", - __FUNCTION__, __LINE__); - - /* make sure program pin is inactive */ - ngcc_fpga_pgm_fn(false, false, 0); -} - -/* - * Set the active-low FPGA reset signal. - */ -void ngcc_fpga_reset(int assert) -{ - debug("%s:%d: RESET ", __FUNCTION__, __LINE__); - - if (assert) { - FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N); - debug("asserted\n"); - } else { - FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N); - debug("deasserted\n"); - } -} - - -/* - * Set the FPGA's active-low SelectMap program line to the specified level - */ -int ngcc_fpga_pgm_fn(int assert, int flush, int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); - - if (assert) { - FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG); - debug("asserted\n"); - } else { - FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG); - debug("deasserted\n"); - } - - return assert; -} - - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int ngcc_fpga_init_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__); - if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) { - debug("high\n"); - return 0; - } else { - debug("low\n"); - return 1; - } -} - - -/* - * Test the state of the active-high FPGA DONE pin - */ -int ngcc_fpga_done_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__); - if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) { - debug("DONE high\n"); - return 1; - } else { - debug("low\n"); - return 0; - } -} - - -/* - * FPGA pre-configuration function. - */ -int ngcc_fpga_pre_config_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - - ngcc_fpga_reset(true); - FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00); - - ngcc_fpga_reset(true); - return 0; -} - - -/* - * FPGA post configuration function. Blip the FPGA reset line and then see if - * the FPGA appears to be running. - */ -int ngcc_fpga_post_config_fn(int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__); - - udelay (100); - ngcc_fpga_reset(false); - - FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); - - return 0; -} - - -int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - if (assert_clk) - FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK); - else - FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK); - - return assert_clk; -} - - -int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie) -{ - pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; - - if (assert_write) - FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA); - else - FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA); - - return assert_write; -} - - -/* - * Initialize the fpga. Return 1 on success, 0 on failure. - */ -int pmc440_init_fpga(void) -{ - char *s; - - debug("%s:%d: Initialize FPGA interface\n", - __FUNCTION__, __LINE__); - fpga_init(); - - fpga_serialslave_init (); - debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__); - fpga_add (fpga_xilinx, &fpga[0]); - - /* NGCC only */ - if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) { - ngcc_fpga_serialslave_init (); - debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__); - fpga_add (fpga_xilinx, &fpga[1]); - } - - return 0; -} -#endif /* CONFIG_FPGA */ diff --git a/board/esd/pmc440/fpga.h b/board/esd/pmc440/fpga.h deleted file mode 100644 index 3810788..0000000 --- a/board/esd/pmc440/fpga.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -extern int pmc440_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_init_fn(int cookie); -extern int fpga_err_fn(int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_cs_fn(int assert_cs, int flush, int cookie); -extern int fpga_wr_fn(int assert_write, int flush, int cookie); -extern int fpga_wdata_fn (uchar data, int flush, int cookie); -extern int fpga_read_data_fn(unsigned char *data, int cookie); -extern int fpga_write_data_fn(unsigned char data, int flush, int cookie); -extern int fpga_busy_fn(int cookie); -extern int fpga_abort_fn(int cookie ); -extern int fpga_pre_config_fn(int cookie ); -extern int fpga_post_config_fn(int cookie ); - -extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int ngcc_fpga_init_fn(int cookie); -extern int ngcc_fpga_done_fn(int cookie); -extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie); -extern int ngcc_fpga_pre_config_fn(int cookie ); -extern int ngcc_fpga_post_config_fn(int cookie ); diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S deleted file mode 100644 index 1f26fad..0000000 --- a/board/esd/pmc440/init.S +++ /dev/null @@ -1,69 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - */ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) - - /* TLB entries for DDR2 SDRAM are generated dynamically */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) - - /* TLB-entries for EBC */ - /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral - * tlb entry. - * This dummy entry is only for convinience in order not to modify the - * amount of entries. Currently OS/9 relies on this :-) - */ - tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for NAND */ - tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) - - /* TLB-entry for Internal Registers & OCM */ - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) - - /*TLB-entry PCI registers*/ - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) - - /* TLB-entry for peripherals */ - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - /* TLB-entry PCI IO space */ - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) - - /* TODO: what about high IO space */ - tlbtab_end diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c deleted file mode 100644 index 0d43505..0000000 --- a/board/esd/pmc440/pmc440.c +++ /dev/null @@ -1,906 +0,0 @@ -/* - * (Cg) Copyright 2007-2008 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. - * Based on board/amcc/sequoia/sequoia.c - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <console.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/ppc440.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/bitops.h> -#include <command.h> -#include <i2c.h> -#ifdef CONFIG_RESET_PHY_R -#include <miiphy.h> -#endif -#include <serial.h> -#include <asm/4xx_pci.h> -#include <usb.h> - -#include "fpga.h" -#include "pmc440.h" - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -extern void __ft_board_setup(void *blob, bd_t *bd); - -ulong flash_get_size(ulong base, int banknum); -static int pci_is_66mhz(void); -int is_monarch(void); -static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt); - -struct serial_device *default_serial_console(void) -{ - uchar buf[4]; - ulong delay; - int i; - ulong val; - - /* - * Use default console on P4 when strapping jumper - * is installed (bootstrap option != 'H'). - */ - mfsdr(SDR0_PINSTP, val); - if (((val & 0xf0000000) >> 29) != 7) - return &eserial2_device; - - ulong scratchreg = in_be32((void *)GPIO0_ISR3L); - if (!(scratchreg & 0x80)) { - /* mark scratchreg valid */ - scratchreg = (scratchreg & 0xffffff00) | 0x80; - - i2c_init_all(); - - i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, - 0x10, buf, 4); - if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { - scratchreg |= buf[2]; - - /* bringup delay for console */ - for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++) - udelay(1000); - } else - scratchreg |= 0x01; - out_be32((void *)GPIO0_ISR3L, scratchreg); - } - - if (scratchreg & 0x01) - return &eserial2_device; - else - return &eserial1_device; -} - -int board_early_init_f(void) -{ - u32 sdr0_cust0; - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; - - /* general EBC configuration (disable EBC timeouts) */ - mtdcr(EBC0_CFGADDR, EBC0_CFG); - mtdcr(EBC0_CFGDATA, 0xf8400000); - - /* Setup the GPIO pins */ - out_be32((void *)GPIO0_OR, 0x40000102); - out_be32((void *)GPIO0_TCR, 0x4c90011f); - out_be32((void *)GPIO0_OSRL, 0x28051400); - out_be32((void *)GPIO0_OSRH, 0x55005000); - out_be32((void *)GPIO0_TSRL, 0x08051400); - out_be32((void *)GPIO0_TSRH, 0x55005000); - out_be32((void *)GPIO0_ISR1L, 0x54000000); - out_be32((void *)GPIO0_ISR1H, 0x00000000); - out_be32((void *)GPIO0_ISR2L, 0x44000000); - out_be32((void *)GPIO0_ISR2H, 0x00000100); - out_be32((void *)GPIO0_ISR3L, 0x00000000); - out_be32((void *)GPIO0_ISR3H, 0x00000000); - - out_be32((void *)GPIO1_OR, 0x80002408); - out_be32((void *)GPIO1_TCR, 0xd6003c08); - out_be32((void *)GPIO1_OSRL, 0x0a5a0000); - out_be32((void *)GPIO1_OSRH, 0x00000000); - out_be32((void *)GPIO1_TSRL, 0x00000000); - out_be32((void *)GPIO1_TSRH, 0x00000000); - out_be32((void *)GPIO1_ISR1L, 0x00005555); - out_be32((void *)GPIO1_ISR1H, 0x40000000); - out_be32((void *)GPIO1_ISR2L, 0x04010000); - out_be32((void *)GPIO1_ISR2H, 0x00000000); - out_be32((void *)GPIO1_ISR3L, 0x01400000); - out_be32((void *)GPIO1_ISR3H, 0x00000000); - - /* patch PLB:PCI divider for 66MHz PCI */ - mfcpr(CPR0_SPCID, reg); - if (pci_is_66mhz() && (reg != 0x02000000)) { - mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ - - mfcpr(CPR0_ICFG, reg); - reg |= CPR0_ICFG_RLI_MASK; - mtcpr(CPR0_ICFG, reg); - - mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */ - } - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffff7ef); - mtdcr(UIC0TR, 0x00000000); - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffc7f5); - mtdcr(UIC1TR, 0x00000000); - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0x27ffffff); - mtdcr(UIC2TR, 0x00000000); - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* select Ethernet pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_4; - mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_4; - - /* enable 2nd IIC */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; - - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /* setup NAND FLASH */ - mfsdr(SDR0_CUST0, sdr0_cust0); - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); - mtsdr(SDR0_CUST0, sdr0_cust0); - - return 0; -} - -#if defined(CONFIG_MISC_INIT_F) -int misc_init_f(void) -{ - struct pci_controller hose; - hose.first_busno = 0; - hose.last_busno = 0; - hose.region_count = 0; - - if (getenv("pciearly") && (!is_monarch())) { - printf("PCI: early target init\n"); - pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA); - pci_target_init(&hose); - } - return 0; -} -#endif - -/* - * misc_init_r. - */ -int misc_init_r(void) -{ - uint pbcr; - int size_val = 0; - u32 reg; - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; - unsigned long sdr0_srst0, sdr0_srst1; - char *act = getenv("usbact"); - - /* - * FLASH stuff... - */ - - /* Re-do sizing to get full correct info */ - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - size_val = ffs(gd->bd->bi_flashsize) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - /* - * USB suff... - */ - if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - - /* - * An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; - - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /* - * Take USB out of reset: - * -Initial status = all cores are in reset - * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores - * -wait 1 ms - * -deassert reset to PHY - * -wait 1 ms - * -deassert reset to HOST - * -wait 4 ms - * -deassert all other resets - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ - SDR0_SRST1_P4OPB0 | \ - SDR0_SRST1_OPBA2 | \ - SDR0_SRST1_PLB42OPB1 | \ - SDR0_SRST1_OPB2PLB40); - mtsdr(SDR0_SRST1, sdr0_srst1); - udelay(1000); - - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; - mtsdr(SDR0_SRST1, sdr0_srst1); - udelay(1000); - - mfsdr(SDR0_SRST0, sdr0_srst0); - sdr0_srst0 &= ~SDR0_SRST0_USB2H; - mtsdr(SDR0_SRST0, sdr0_srst0); - udelay(4000); - - /* finally all the other resets */ - mtsdr(SDR0_SRST1, 0x00000000); - mtsdr(SDR0_SRST0, 0x00000000); - - if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { - /* enable power on USB socket */ - out_be32((void *)GPIO1_OR, - in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); - } - - printf("USB: Host\n"); - - } else if ((strcmp(act, "dev") == 0) || - (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) { - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x672c6000); - - udelay (1000); - mtsdr(SDR0_SRST0, 0x00000080); - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60206000); - - *(unsigned int *)(0xe0000350) = 0x00000001; - - udelay (1000); - mtsdr(SDR0_SRST1, 0x60306000); - - /* SDR Setting */ - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - mfsdr(SDR0_USB2D0CR, usb2d0cr); - mfsdr(SDR0_PFC1, sdr0_pfc1); - - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; - - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; - - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; - - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; - - mtsdr(SDR0_USB2H0CR, usb2h0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2D0CR, usb2d0cr); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - /*clear resets*/ - udelay(1000); - mtsdr(SDR0_SRST1, 0x00000000); - udelay(1000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Device\n"); - } - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - -#ifdef CONFIG_FPGA - pmc440_init_fpga(); -#endif - - /* turn off POST LED */ - out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N); - /* turn on RUN LED */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N); - return 0; -} - -int is_monarch(void) -{ - if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH) - return 0; - - return 1; -} - -static int pci_is_66mhz(void) -{ - if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN) - return 1; - return 0; -} - -static int board_revision(void) -{ - return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4); -} - -int checkboard(void) -{ - puts("Board: esd GmbH - PMC440"); - - gd->board_type = board_revision(); - printf(", Rev 1.%ld, ", gd->board_type); - - if (!is_monarch()) { - puts("non-"); - } - - printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33"); - return (0); -} - - -#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) -/* - * Assign interrupts to PCI devices. Some OSs rely on this. - */ -void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB}; - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, - int_line[PCI_DEV(dev) & 0x03]); -} -#endif - -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - char *ptmla_str, *ptmms_str; - - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0x80000000-0xBFFFFFFF - * ==> PCI address 0x80000000-0xBFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ - /* and enable region */ - - if (!is_monarch()) { - ptmla_str = getenv("ptm1la"); - ptmms_str = getenv("ptm1ms"); - if(NULL != ptmla_str && NULL != ptmms_str ) { - out32r(PCIL0_PTM1MS, - simple_strtoul(ptmms_str, NULL, 16)); - out32r(PCIL0_PTM1LA, - simple_strtoul(ptmla_str, NULL, 16)); - } else { - /* BAR1: default top 64MB of RAM */ - out32r(PCIL0_PTM1MS, 0xfc000001); - out32r(PCIL0_PTM1LA, 0x0c000000); - } - } else { - /* BAR1: default: complete 256MB RAM */ - out32r(PCIL0_PTM1MS, 0xf0000001); - out32r(PCIL0_PTM1LA, 0x00000000); - } - - ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */ - ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */ - if(NULL != ptmla_str && NULL != ptmms_str ) { - out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); - out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); - } else { - /* BAR2: default: 4MB FPGA */ - out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */ - } - - if (is_monarch()) { - /* BAR2: map FPGA registers behind system memory at 1GB */ - pci_hose_write_config_dword(hose, 0, - PCI_BASE_ADDRESS_2, 0x40000008); - } - - /* - * Set up Configuration registers - */ - - /* Program the board's vendor id */ - pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - - /* disabled for PMC405 backward compatibility */ - /* Configure command register as bus master */ - /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */ - - - /* 240nS PCI clock */ - pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_hose_write_config_word(hose, 0, PCI_ERREN, 0); - - if (!is_monarch()) { - /* Program the board's subsystem id/classcode */ - pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, - CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); - pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, - CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); - - /* PCI configuration done: release ERREADY */ - out_be32((void *)GPIO1_OR, - in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY); - out_be32((void *)GPIO1_TCR, - in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY); - } else { - /* Program the board's subsystem id/classcode */ - pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, - CONFIG_SYS_PCI_SUBSYS_ID_MONARCH); - pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, - CONFIG_SYS_PCI_CLASSCODE_MONARCH); - } - - /* enable host configuration */ - pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/* - * Override weak default pci_master_init() - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - /* - * Only configure the master in monach mode - */ - if (is_monarch()) - __pci_master_init(hose); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - -static void wait_for_pci_ready(void) -{ - if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) { - printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); - while (1) { - if (ctrlc()) { - puts("abort\n"); - break; - } - if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) { - printf("done\n"); - break; - } - } - } -} - -/* - * Override weak is_pci_host() - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - */ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - char *s = getenv("pciscan"); - if (s == NULL) - if (is_monarch()) { - wait_for_pci_ready(); - return 1; - } else - return 0; - else if (!strcmp(s, "yes")) - return 1; - - return 0; -} -#endif /* defined(CONFIG_PCI) */ - -#ifdef CONFIG_RESET_PHY_R -static int pmc440_setup_vsc8601(char *devname, int phy_addr, - unsigned short behavior, unsigned short method) -{ - /* adjust LED behavior */ - if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) { - printf("Phy%d: register write access failed\n", phy_addr); - return -1; - } - - miiphy_write(devname, phy_addr, 0x11, 0x0010); - miiphy_write(devname, phy_addr, 0x11, behavior); - miiphy_write(devname, phy_addr, 0x10, method); - miiphy_write(devname, phy_addr, 0x1f, 0x0000); - - return 0; -} - -static int pmc440_setup_ksz9031(char *devname, int phy_addr) -{ - unsigned short id1, id2; - - if (miiphy_read(devname, phy_addr, 2, &id1) || - miiphy_read(devname, phy_addr, 3, &id2)) { - printf("Phy%d: cannot read id\n", phy_addr); - return -1; - } - - if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) { - printf("Phy%d: unexpected id\n", phy_addr); - return -1; - } - - /* MMD 2.08: adjust tx_clk pad skew */ - miiphy_write(devname, phy_addr, 0x0d, 2); - miiphy_write(devname, phy_addr, 0x0e, 8); - miiphy_write(devname, phy_addr, 0x0d, 0x4002); - miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5)); - - return 0; -} - -void reset_phy(void) -{ - char *s; - unsigned short val_method, val_behavior; - - if (gd->board_type < 4) { - /* special LED setup for NGCC/CANDES */ - s = getenv("bd_type"); - if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { - val_method = 0x0e0a; - val_behavior = 0x0cf2; - } else { - /* PMC440 standard type */ - val_method = 0x0e10; - val_behavior = 0x0cf0; - } - - /* boards up to rev. 1.3 use Vitesse VSC8601 phys */ - pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR, - val_method, val_behavior); - pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR, - val_method, val_behavior); - } else { - /* rev. 1.4 uses a Micrel KSZ9031 */ - pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR); - pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR); - } -} -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) -/* - * Input: <dev_addr> I2C address of EEPROM device to enable. - * <state> -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if <state> was -1. - */ -int eeprom_write_enable(unsigned dev_addr, int state) -{ - if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) && - (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) - & GPIO0_EP_EEP)); - break; - } - } - return state; -} -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ - -#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 -int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) -{ - unsigned end = offset + cnt; - unsigned blk_off; - int rcode = 0; - -#if defined(CONFIG_SYS_EEPROM_WREN) - eeprom_write_enable(dev_addr, 1); -#endif - /* - * Write data until done or would cross a write page boundary. - * We must write the address again when changing pages - * because the address counter only increments within a page. - */ - while (offset < end) { - unsigned alen, len; - unsigned maxlen; - uchar addr[2]; - - blk_off = offset & 0xFF; /* block offset */ - - addr[0] = offset >> 8; /* block number */ - addr[1] = blk_off; /* block offset */ - alen = 2; - addr[0] |= dev_addr; /* insert device address */ - - len = end - offset; - -#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) -#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) - - maxlen = BOOT_EEPROM_PAGE_SIZE - - BOOT_EEPROM_PAGE_OFFSET(blk_off); - if (maxlen > I2C_RXTX_LEN) - maxlen = I2C_RXTX_LEN; - - if (len > maxlen) - len = maxlen; - - if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) - rcode = 1; - - buffer += len; - offset += len; - -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); -#endif - } -#if defined(CONFIG_SYS_EEPROM_WREN) - eeprom_write_enable(dev_addr, 0); -#endif - return rcode; -} - -static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) -{ - unsigned end = offset + cnt; - unsigned blk_off; - int rcode = 0; - - /* - * Read data until done or would cross a page boundary. - * We must write the address again when changing pages - * because the next page may be in a different device. - */ - while (offset < end) { - unsigned alen, len; - unsigned maxlen; - uchar addr[2]; - - blk_off = offset & 0xFF; /* block offset */ - - addr[0] = offset >> 8; /* block number */ - addr[1] = blk_off; /* block offset */ - alen = 2; - - addr[0] |= dev_addr; /* insert device address */ - - len = end - offset; - - maxlen = 0x100 - blk_off; - if (maxlen > I2C_RXTX_LEN) - maxlen = I2C_RXTX_LEN; - if (len > maxlen) - len = maxlen; - - if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) - rcode = 1; - buffer += len; - offset += len; - } - - return rcode; -} - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) -int board_usb_init(int index, enum usb_init_type init) -{ - char *act = getenv("usbact"); - int i; - - if ((act == NULL || strcmp(act, "host") == 0) && - !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) - /* enable power on USB socket */ - out_be32((void *)GPIO1_OR, - in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N); - - for (i=0; i<1000; i++) - udelay(1000); - - return 0; -} - -int usb_board_stop(void) -{ - /* disable power on USB socket */ - out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N); - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - return usb_board_stop(); -} -#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - int rc; - - __ft_board_setup(blob, bd); - - /* - * Disable PCI in non-monarch mode. - */ - if (!is_monarch()) { - rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status", - "disabled", sizeof("disabled"), 1); - if (rc) { - printf("Unable to update property status in PCI node, "); - printf("err=%s\n", fdt_strerror(rc)); - } - } - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h deleted file mode 100644 index 84e0b1f..0000000 --- a/board/esd/pmc440/pmc440.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PMC440_H__ -#define __PMC440_H__ - -/* - * GPIOs - */ -#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ -#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */ -#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */ -#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */ -#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */ -#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */ -#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */ - -#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */ -#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */ -#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ -#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ -#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ - -/* - * FPGA programming pin configuration - */ -#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ -#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ -#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ -#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */ -#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ -#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */ - -/* - * FPGA interface - */ -#define FPGA_BA CONFIG_SYS_FPGA_BASE0 -#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v)) -#define FPGA_IN32(p) in_be32((void*)(p)) -#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v)) -#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v)) - -struct pmc440_fifo_s { - u32 data; - u32 ctrl; -}; - -/* fifo ctrl register */ -#define FIFO_IE (1 << 15) -#define FIFO_OVERFLOW (1 << 10) -#define FIFO_EMPTY (1 << 9) -#define FIFO_FULL (1 << 8) -#define FIFO_LEVEL_MASK 0x000000ff - -#define FIFO_COUNT 4 - -struct pmc440_fpga_s { - u32 ctrla; - u32 status; - u32 ctrlb; - u32 pad1[0x40 / sizeof(u32) - 3]; - u32 irig_time; /* offset: 0x0040 */ - u32 irig_tod; - u32 irig_cf; - u32 pad2; - u32 irig_rx_time; /* offset: 0x0050 */ - u32 pad3[3]; - u32 hostctrl; /* offset: 0x0060 */ - u32 pad4[0x20 / sizeof(u32) - 1]; - struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */ -}; - -typedef struct pmc440_fpga_s pmc440_fpga_t; - -/* ctrl register */ -#define CTRL_HOST_IE (1 << 8) - -/* outputs */ -#define RESET_EN (1 << 31) -#define CLOCK_EN (1 << 30) -#define RESET_OUT (1 << 19) -#define CLOCK_OUT (1 << 22) -#define RESET_OUT (1 << 19) -#define IRIGB_R_OUT (1 << 14) - -/* status register */ -#define STATUS_VERSION_SHIFT 24 -#define STATUS_VERSION_MASK 0xff000000 -#define STATUS_HWREV_SHIFT 20 -#define STATUS_HWREV_MASK 0x00f00000 - -#define STATUS_CAN_ISF (1 << 11) -#define STATUS_CSTM_ISF (1 << 10) -#define STATUS_FIFO_ISF (1 << 9) -#define STATUS_HOST_ISF (1 << 8) - -/* inputs */ -#define RESET_IN (1 << 0) -#define CLOCK_IN (1 << 1) -#define IRIGB_R_IN (1 << 5) - -/* hostctrl register */ -#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) -#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) -#define HOSTCTRL_CSTM1IE_GATE (1 << 7) -#define HOSTCTRL_CSTM1IW_FLAG (1 << 6) -#define HOSTCTRL_CSTM0IE_GATE (1 << 5) -#define HOSTCTRL_CSTM0IW_FLAG (1 << 4) -#define HOSTCTRL_FIFOIE_GATE (1 << 3) -#define HOSTCTRL_FIFOIE_FLAG (1 << 2) -#define HOSTCTRL_HCINT_GATE (1 << 1) -#define HOSTCTRL_HCINT_FLAG (1 << 0) - -#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000) -#define NGCC_CTRL_FPGARST_N (1 << 2) - -/* - * FPGA to PPC interrupt - */ -#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */ -#define IRQ1_FPGA (32+30) /* UIC1 - custom module */ -#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */ -#define IRQ_ETH0 (64+ 4) /* UIC2 */ -#define IRQ_ETH1 ( 27) /* UIC0 */ -#define IRQ_RTC (64+ 0) /* UIC2 */ -#define IRQ_PCIA (64+ 1) /* UIC2 */ -#define IRQ_PCIB (32+18) /* UIC1 */ -#define IRQ_PCIC (32+19) /* UIC1 */ -#define IRQ_PCID (32+20) /* UIC1 */ - -#endif /* __PMC440_H__ */ diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c deleted file mode 100644 index c379e77..0000000 --- a/board/esd/pmc440/sdram.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2009 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu - * - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debug output */ -#undef DEBUG - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/ppc440.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern int denali_wait_for_dlllock(void); -extern void denali_core_search_data_eye(void); - -struct sdram_conf_s { - ulong size; - int rows; - int banks; -}; - -struct sdram_conf_s sdram_conf[] = { - {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */ - {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */ - {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */ -}; - -/* - * dram_init -- 440EPx's DDR controller is a DENALI Core - */ -int initdram_by_rb(int rows, int banks) -{ - ulong speed = get_bus_freq(0); - - mtsdram(DDR0_02, 0x00000000); - - mtsdram(DDR0_00, 0x0000190A); - mtsdram(DDR0_01, 0x01000000); - mtsdram(DDR0_03, 0x02030602); - mtsdram(DDR0_04, 0x0A020200); - mtsdram(DDR0_05, 0x02020308); - mtsdram(DDR0_06, 0x0102C812); - mtsdram(DDR0_07, 0x000D0100); - mtsdram(DDR0_08, 0x02430001); - mtsdram(DDR0_09, 0x00011D5F); - mtsdram(DDR0_10, 0x00000100); - mtsdram(DDR0_11, 0x0027C800); - mtsdram(DDR0_12, 0x00000003); - mtsdram(DDR0_14, 0x00000000); - mtsdram(DDR0_17, 0x19000000); - mtsdram(DDR0_18, 0x19191919); - mtsdram(DDR0_19, 0x19191919); - mtsdram(DDR0_20, 0x0B0B0B0B); - mtsdram(DDR0_21, 0x0B0B0B0B); - mtsdram(DDR0_22, 0x00267F0B); - mtsdram(DDR0_23, 0x00000000); - mtsdram(DDR0_24, 0x01010002); - if (speed > 133333334) - mtsdram(DDR0_26, 0x5B26050C); - else - mtsdram(DDR0_26, 0x5B260408); - mtsdram(DDR0_27, 0x0000682B); - mtsdram(DDR0_28, 0x00000000); - mtsdram(DDR0_31, 0x00000000); - - mtsdram(DDR0_42, - DDR0_42_ADDR_PINS_DECODE(14 - rows) | - 0x00000006); - mtsdram(DDR0_43, - DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) | - 0x030A0200); - - mtsdram(DDR0_44, 0x00000003); - mtsdram(DDR0_02, 0x00000001); - - denali_wait_for_dlllock(); - -#ifdef CONFIG_DDR_DATA_EYE - /* - * Perform data eye search if requested. - */ - denali_core_search_data_eye(); -#endif - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return 0; -} - -int dram_init(void) -{ - phys_size_t size; - int n; - - /* go through supported memory configurations */ - for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) { - size = sdram_conf[n].size; - - /* program TLB entries */ - program_tlb(0, CONFIG_SYS_SDRAM_BASE, size, - TLB_WORD2_I_ENABLE); - - /* - * setup denali core - */ - initdram_by_rb(sdram_conf[n].rows, - sdram_conf[n].banks); - - /* check for suitable configuration */ - if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) { - gd->ram_size = size; - return 0; - } - - /* delete TLB entries */ - remove_tlb(CONFIG_SYS_SDRAM_BASE, size); - } - - return -ENXIO; -} diff --git a/board/esd/vom405/Kconfig b/board/esd/vom405/Kconfig deleted file mode 100644 index ecdf8c9..0000000 --- a/board/esd/vom405/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_VOM405 - -config SYS_BOARD - default "vom405" - -config SYS_VENDOR - default "esd" - -config SYS_CONFIG_NAME - default "VOM405" - -endif diff --git a/board/esd/vom405/MAINTAINERS b/board/esd/vom405/MAINTAINERS deleted file mode 100644 index 385f60a..0000000 --- a/board/esd/vom405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -VOM405 BOARD -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> -S: Maintained -F: board/esd/vom405/ -F: include/configs/VOM405.h -F: configs/VOM405_defconfig diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile deleted file mode 100644 index 7cf5c02..0000000 --- a/board/esd/vom405/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Objects for Xilinx JTAG programming (CPLD) -CPLD = ../common/xilinx_jtag/lenval.o \ - ../common/xilinx_jtag/micro.o \ - ../common/xilinx_jtag/ports.o - -obj-y = vom405.o flash.o ../common/misc.o $(CPLD) diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c deleted file mode 100644 index 23e8164..0000000 --- a/board/esd/vom405/flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - int size_val = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - switch (size_b0) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - } - pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(EBC0_CFGDATA, pbcr); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c deleted file mode 100644 index 7de6f66..0000000 --- a/board/esd/vom405/vom405.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> -#include <malloc.h> -#include <sja1000.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void lxt971_no_sleep(void); - -/* - * generate a short spike on the CAN tx line - * to bring the couplers in sync - */ -void init_coupler(u32 addr) -{ - struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr; - - /* reset */ - out_8(&ctrl->cr, CR_RR); - - /* dominant */ - out_8(&ctrl->btr0, 0x00); /* btr setup is required */ - out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */ - out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 | - OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1); - out_8(&ctrl->cr, 0x00); - - /* delay */ - in_8(&ctrl->cr); - in_8(&ctrl->cr); - in_8(&ctrl->cr); - in_8(&ctrl->cr); - - /* reset */ - out_8(&ctrl->cr, CR_RR); -} - -int board_early_init_f (void) -{ - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive - * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive - * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive - * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us - */ - mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ - - /* - * Reset CPLD via GPIO12 (CS3) pin - */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12)); - udelay(1000); /* wait 1ms */ - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | (0x80000000 >> 12)); - udelay(1000); /* wait 1ms */ - - return 0; -} - -int misc_init_r (void) -{ - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Init magnetic coupler - */ - if (!getenv("noinitcoupler")) - init_coupler(CAN_BA); - - return (0); -} - -/* - * Check Board Identity: - */ -int checkboard (void) -{ - char str[64]; - int i = getenv_f("serial#", str, sizeof(str)); - int flashcnt; - int delay; - u8 *led_reg = (u8 *)(CAN_BA + 0x1000); - - puts ("Board: "); - - if (i == -1) { - puts ("### No HW ID - assuming VOM405"); - } else { - puts(str); - } - - printf(" (PLD-Version=%02d)\n", in_8(led_reg)); - - /* - * Flash LEDs - */ - for (flashcnt = 0; flashcnt < 3; flashcnt++) { - out_8(led_reg, 0x40); /* LED_B..D off */ - for (delay = 0; delay < 100; delay++) - udelay(1000); - out_8(led_reg, 0x47); /* LED_B..D on */ - for (delay = 0; delay < 50; delay++) - udelay(1000); - } - out_8(led_reg, 0x40); - - return 0; -} - -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif -} diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c deleted file mode 100644 index 35fa06a..0000000 --- a/board/gdsys/405ep/405ep.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/global_data.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#define REFLECTION_TESTPATTERN 0xdede -#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) - -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI -#define REFLECTION_TESTREG reflection_low -#else -#define REFLECTION_TESTREG reflection_high -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int get_fpga_state(unsigned dev) -{ - return gd->arch.fpga_state[dev]; -} - -int board_early_init_f(void) -{ - unsigned k; - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] = 0; - - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks - * -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - return 0; -} - -int board_early_init_r(void) -{ - unsigned k; - unsigned ctr; - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] = 0; - - /* - * reset FPGA - */ - gd405ep_init(); - - gd405ep_set_fpga_reset(1); - - gd405ep_setup_hw(); - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - ctr = 0; - while (!gd405ep_get_fpga_done(k)) { - udelay(100000); - if (ctr++ > 5) { - gd->arch.fpga_state[k] |= - FPGA_STATE_DONE_FAILED; - break; - } - } - } - - udelay(10); - - gd405ep_set_fpga_reset(0); - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - /* - * wait for fpga out of reset - */ - ctr = 0; - while (1) { - u16 val; - - FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); - - FPGA_GET_REG(k, REFLECTION_TESTREG, &val); - if (val == REFLECTION_TESTPATTERN_INV) - break; - - udelay(100000); - if (ctr++ > 5) { - gd->arch.fpga_state[k] |= - FPGA_STATE_REFLECTION_FAILED; - break; - } - } - } - - return 0; -} diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h deleted file mode 100644 index 5647dbc..0000000 --- a/board/gdsys/405ep/405ep.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __405EP_H_ -#define __405EP_H_ - -/* functions to be provided by board implementation */ -void gd405ep_init(void); -void gd405ep_set_fpga_reset(unsigned state); -void gd405ep_setup_hw(void); -int gd405ep_get_fpga_done(unsigned fpga); - -#endif /* __405EP_H_ */ diff --git a/board/gdsys/405ep/Kconfig b/board/gdsys/405ep/Kconfig deleted file mode 100644 index 20cb80f..0000000 --- a/board/gdsys/405ep/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -if TARGET_DLVISION_10G - -config SYS_BOARD - default "405ep" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "dlvision-10g" - -endif - -if TARGET_IO - -config SYS_BOARD - default "405ep" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "io" - -endif - -if TARGET_IOCON - -config SYS_BOARD - default "405ep" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "iocon" - -endif - -if TARGET_NEO - -config SYS_BOARD - default "405ep" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "neo" - -endif diff --git a/board/gdsys/405ep/MAINTAINERS b/board/gdsys/405ep/MAINTAINERS deleted file mode 100644 index 1403880..0000000 --- a/board/gdsys/405ep/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -405EP BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/405ep/ -F: include/configs/dlvision-10g.h -F: configs/dlvision-10g_defconfig -F: include/configs/io.h -F: configs/io_defconfig -F: include/configs/iocon.h -F: configs/iocon_defconfig -F: include/configs/neo.h -F: configs/neo_defconfig diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile deleted file mode 100644 index 857ec04..0000000 --- a/board/gdsys/405ep/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := 405ep.o -obj-$(CONFIG_NEO) += neo.o -obj-$(CONFIG_IO) += io.o -obj-$(CONFIG_IOCON) += iocon.o -obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c deleted file mode 100644 index b531786..0000000 --- a/board/gdsys/405ep/dlvision-10g.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#include "../common/osd.h" - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) -#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) - -#define LATCH2_MC2_PRESENT_N 0x0080 - -enum { - UNITTYPE_MAIN = 1<<0, - UNITTYPE_SERVER = 1<<1, - UNITTYPE_DISPLAYPORT = 1<<2, -}; - -enum { - HWVER_101 = 0, - HWVER_110 = 1, - HWVER_130 = 2, - HWVER_140 = 3, - HWVER_150 = 4, - HWVER_160 = 5, - HWVER_170 = 6, -}; - -enum { - AUDIO_NONE = 0, - AUDIO_TX = 1, - AUDIO_RX = 2, - AUDIO_RXTX = 3, -}; - -enum { - SYSCLK_156250 = 2, -}; - -enum { - RAM_NONE = 0, - RAM_DDR2_32 = 1, - RAM_DDR2_64 = 2, -}; - -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -int misc_init_r(void) -{ - /* - * Note: DTT has been removed. Please use UCLASS_THERMAL. - * - * startup fans - * - * dtt_init(); - */ - - return 0; -} - -static unsigned int get_hwver(void) -{ - u16 latch3 = in_le16((void *)LATCH3_BASE); - - return latch3 & 0x0003; -} - -static unsigned int get_mc2_present(void) -{ - u16 latch2 = in_le16((void *)LATCH2_BASE); - - return !(latch2 & LATCH2_MC2_PRESENT_N); -} - -static void print_fpga_info(unsigned dev) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned hardware_version; - unsigned feature_rs232; - unsigned feature_audio; - unsigned feature_sysclock; - unsigned feature_ramconfig; - unsigned feature_carrier_speed; - unsigned feature_carriers; - unsigned feature_video_channels; - int fpga_state = get_fpga_state(dev); - - printf("FPGA%d: ", dev); - - FPGA_GET_REG(dev, versions, &versions); - FPGA_GET_REG(dev, fpga_version, &fpga_version); - FPGA_GET_REG(dev, fpga_features, &fpga_features); - - hardware_version = versions & 0x000f; - - if (fpga_state - && !((hardware_version == HWVER_101) - && (fpga_state == FPGA_STATE_DONE_FAILED))) { - puts("not available\n"); - if (fpga_state & FPGA_STATE_DONE_FAILED) - puts(" Waiting for FPGA-DONE timed out.\n"); - if (fpga_state & FPGA_STATE_REFLECTION_FAILED) - puts(" FPGA reflection test failed.\n"); - return; - } - - unit_type = (versions >> 4) & 0x000f; - hardware_version = versions & 0x000f; - feature_rs232 = fpga_features & (1<<11); - feature_audio = (fpga_features >> 9) & 0x0003; - feature_sysclock = (fpga_features >> 7) & 0x0003; - feature_ramconfig = (fpga_features >> 5) & 0x0003; - feature_carrier_speed = fpga_features & (1<<4); - feature_carriers = (fpga_features >> 2) & 0x0003; - feature_video_channels = fpga_features & 0x0003; - - if (unit_type & UNITTYPE_MAIN) - printf("Mainchannel "); - else - printf("Videochannel "); - - if (unit_type & UNITTYPE_SERVER) - printf("Serverside "); - else - printf("Userside "); - - if (unit_type & UNITTYPE_DISPLAYPORT) - printf("DisplayPort"); - else - printf("DVI-DL"); - - switch (hardware_version) { - case HWVER_101: - printf(" HW-Ver 1.01\n"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10-1.20\n"); - break; - - case HWVER_130: - printf(" HW-Ver 1.30\n"); - break; - - case HWVER_140: - printf(" HW-Ver 1.40-1.43\n"); - break; - - case HWVER_150: - printf(" HW-Ver 1.50\n"); - break; - - case HWVER_160: - printf(" HW-Ver 1.60-1.61\n"); - break; - - case HWVER_170: - printf(" HW-Ver 1.70\n"); - break; - - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %sRS232", feature_rs232 ? "" : "no "); - - switch (feature_audio) { - case AUDIO_NONE: - printf(", no audio"); - break; - - case AUDIO_TX: - printf(", audio tx"); - break; - - case AUDIO_RX: - printf(", audio rx"); - break; - - case AUDIO_RXTX: - printf(", audio rx+tx"); - break; - - default: - printf(", audio %d(not supported)", feature_audio); - break; - } - - switch (feature_sysclock) { - case SYSCLK_156250: - printf(", clock 156.25 MHz"); - break; - - default: - printf(", clock %d(not supported)", feature_sysclock); - break; - } - - puts(",\n "); - - switch (feature_ramconfig) { - case RAM_NONE: - printf("no RAM"); - break; - - case RAM_DDR2_32: - printf("RAM 32 bit DDR2"); - break; - - case RAM_DDR2_64: - printf("RAM 64 bit DDR2"); - break; - - default: - printf("RAM %d(not supported)", feature_ramconfig); - break; - } - - printf(", %d carrier(s) %s", feature_carriers, - feature_carrier_speed ? "10 Gbit/s" : "of unknown speed"); - - printf(", %d video channel(s)\n", feature_video_channels); -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: "); - - puts("DLVision 10G"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -int last_stage_init(void) -{ - u16 versions; - - FPGA_GET_REG(0, versions, &versions); - - print_fpga_info(0); - if (get_mc2_present()) - print_fpga_info(1); - - if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER) - return 0; - - if (!get_fpga_state(0) || (get_hwver() == HWVER_101)) - osd_probe(0); - - if (get_mc2_present() && - (!get_fpga_state(1) || (get_hwver() == HWVER_101))) - osd_probe(1); - - return 0; -} - -void gd405ep_init(void) -{ -} - -void gd405ep_set_fpga_reset(unsigned state) -{ - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } -} - -void gd405ep_setup_hw(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); -} - -int gd405ep_get_fpga_done(unsigned fpga) -{ - return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); -} diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c deleted file mode 100644 index 1484469..0000000 --- a/board/gdsys/405ep/io.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#include <miiphy.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - -#define PHYREG_CONTROL 0 -#define PHYREG_PAGE_ADDRESS 22 -#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 -#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 - -enum { - UNITTYPE_CCD_SWITCH = 1, -}; - -enum { - HWVER_100 = 0, - HWVER_110 = 1, - HWVER_121 = 2, - HWVER_122 = 3, -}; - -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -int misc_init_r(void) -{ - /* - * Note: DTT has been removed. Please use UCLASS_THERMAL. - * - * startup fans - * - * dtt_init(); - */ - - return 0; -} - -int configure_gbit_phy(unsigned char addr) -{ - unsigned short value; - - /* select page 2 */ - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PAGE_ADDRESS, 0x0002)) - goto err_out; - /* disable SGMII autonegotiation */ - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a)) - goto err_out; - /* select page 0 */ - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PAGE_ADDRESS, 0x0000)) - goto err_out; - /* switch from powerdown to normal operation */ - if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value)) - goto err_out; - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004)) - goto err_out; - /* reset phy so settings take effect */ - if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr, - PHYREG_CONTROL, 0x9140)) - goto err_out; - - return 0; - -err_out: - printf("Error writing to the PHY addr=%02x\n", addr); - return -1; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: CATCenter Io"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -static void print_fpga_info(void) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned hardware_version; - unsigned feature_channels; - unsigned feature_expansion; - - FPGA_GET_REG(0, versions, &versions); - FPGA_GET_REG(0, fpga_version, &fpga_version); - FPGA_GET_REG(0, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - hardware_version = versions & 0x000f; - feature_channels = fpga_features & 0x007f; - feature_expansion = fpga_features & (1<<15); - - puts("FPGA: "); - - switch (unit_type) { - case UNITTYPE_CCD_SWITCH: - printf("CCD-Switch"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00\n"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10\n"); - break; - - case HWVER_121: - printf(" HW-Ver 1.21\n"); - break; - - case HWVER_122: - printf(" HW-Ver 1.22\n"); - break; - - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %d channel(s)", feature_channels); - - printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); -} - -/* - * setup Gbit PHYs - */ -int last_stage_init(void) -{ - unsigned int k; - - print_fpga_info(); - - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - - for (k = 0; k < 32; ++k) - configure_gbit_phy(k); - - /* take fpga serdes blocks out of reset */ - FPGA_SET_REG(0, quad_serdes_reset, 0); - - return 0; -} - -void gd405ep_init(void) -{ -} - -void gd405ep_set_fpga_reset(unsigned state) -{ - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } -} - -void gd405ep_setup_hw(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); -} - -int gd405ep_get_fpga_done(unsigned fpga) -{ - return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); -} diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c deleted file mode 100644 index 7db0e29..0000000 --- a/board/gdsys/405ep/iocon.c +++ /dev/null @@ -1,673 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <errno.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#include "../common/osd.h" -#include "../common/mclink.h" -#include "../common/phy.h" - -#include <i2c.h> -#include <pca953x.h> -#include <pca9698.h> - -#include <miiphy.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - -#define MAX_MUX_CHANNELS 2 - -enum { - UNITTYPE_MAIN_SERVER = 0, - UNITTYPE_MAIN_USER = 1, - UNITTYPE_VIDEO_SERVER = 2, - UNITTYPE_VIDEO_USER = 3, -}; - -enum { - HWVER_100 = 0, - HWVER_104 = 1, - HWVER_110 = 2, - HWVER_120 = 3, - HWVER_200 = 4, - HWVER_210 = 5, - HWVER_220 = 6, - HWVER_230 = 7, -}; - -enum { - FPGA_HWVER_200 = 0, - FPGA_HWVER_210 = 1, -}; - -enum { - COMPRESSION_NONE = 0, - COMPRESSION_TYPE1_DELTA = 1, - COMPRESSION_TYPE1_TYPE2_DELTA = 3, -}; - -enum { - AUDIO_NONE = 0, - AUDIO_TX = 1, - AUDIO_RX = 2, - AUDIO_RXTX = 3, -}; - -enum { - SYSCLK_147456 = 0, -}; - -enum { - RAM_DDR2_32 = 0, - RAM_DDR3_32 = 1, -}; - -enum { - CARRIER_SPEED_1G = 0, - CARRIER_SPEED_2_5G = 1, -}; - -enum { - MCFPGA_DONE = 1 << 0, - MCFPGA_INIT_N = 1 << 1, - MCFPGA_PROGRAM_N = 1 << 2, - MCFPGA_UPDATE_ENABLE_N = 1 << 3, - MCFPGA_RESET_N = 1 << 4, -}; - -enum { - GPIO_MDC = 1 << 14, - GPIO_MDIO = 1 << 15, -}; - -unsigned int mclink_fpgacount; -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) -{ - int res; - - switch (fpga) { - case 0: - out_le16(reg, data); - break; - default: - res = mclink_send(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_send reg %02lx data %04x returned %d\n", - regoff, data, res); - return res; - } - break; - } - - return 0; -} - -int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) -{ - int res; - - switch (fpga) { - case 0: - *data = in_le16(reg); - break; - default: - if (fpga > mclink_fpgacount) - return -EINVAL; - res = mclink_receive(fpga - 1, regoff, data); - if (res < 0) { - printf("mclink_receive reg %02lx returned %d\n", - regoff, res); - return res; - } - } - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: "); - - puts("IoCon"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -static void print_fpga_info(unsigned int fpga, bool rgmii2_present) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned hardware_version; - unsigned feature_compression; - unsigned feature_osd; - unsigned feature_audio; - unsigned feature_sysclock; - unsigned feature_ramconfig; - unsigned feature_carrier_speed; - unsigned feature_carriers; - unsigned feature_video_channels; - - int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM; - - FPGA_GET_REG(fpga, versions, &versions); - FPGA_GET_REG(fpga, fpga_version, &fpga_version); - FPGA_GET_REG(fpga, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - feature_compression = (fpga_features & 0xe000) >> 13; - feature_osd = fpga_features & (1<<11); - feature_audio = (fpga_features & 0x0600) >> 9; - feature_sysclock = (fpga_features & 0x0180) >> 7; - feature_ramconfig = (fpga_features & 0x0060) >> 5; - feature_carrier_speed = fpga_features & (1<<4); - feature_carriers = (fpga_features & 0x000c) >> 2; - feature_video_channels = fpga_features & 0x0003; - - if (legacy) - printf("legacy "); - - switch (unit_type) { - case UNITTYPE_MAIN_USER: - printf("Mainchannel"); - break; - - case UNITTYPE_VIDEO_USER: - printf("Videochannel"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - if (unit_type == UNITTYPE_MAIN_USER) { - if (legacy) - hardware_version = - (in_le16((void *)LATCH2_BASE)>>8) & 0x0f; - else - hardware_version = - (!!pca9698_get_value(0x20, 24) << 0) - | (!!pca9698_get_value(0x20, 25) << 1) - | (!!pca9698_get_value(0x20, 26) << 2) - | (!!pca9698_get_value(0x20, 27) << 3); - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00,"); - break; - - case HWVER_104: - printf(" HW-Ver 1.04,"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10,"); - break; - - case HWVER_120: - printf(" HW-Ver 1.20-1.21,"); - break; - - case HWVER_200: - printf(" HW-Ver 2.00,"); - break; - - case HWVER_210: - printf(" HW-Ver 2.10,"); - break; - - case HWVER_220: - printf(" HW-Ver 2.20,"); - break; - - case HWVER_230: - printf(" HW-Ver 2.30,"); - break; - - default: - printf(" HW-Ver %d(not supported),", - hardware_version); - break; - } - if (rgmii2_present) - printf(" RGMII2,"); - } - - if (unit_type == UNITTYPE_VIDEO_USER) { - hardware_version = versions & 0x000f; - switch (hardware_version) { - case FPGA_HWVER_200: - printf(" HW-Ver 2.00,"); - break; - - case FPGA_HWVER_210: - printf(" HW-Ver 2.10,"); - break; - - default: - printf(" HW-Ver %d(not supported),", - hardware_version); - break; - } - } - - printf(" FPGA V %d.%02d\n features:", - fpga_version / 100, fpga_version % 100); - - - switch (feature_compression) { - case COMPRESSION_NONE: - printf(" no compression"); - break; - - case COMPRESSION_TYPE1_DELTA: - printf(" type1-deltacompression"); - break; - - case COMPRESSION_TYPE1_TYPE2_DELTA: - printf(" type1-deltacompression, type2-inlinecompression"); - break; - - default: - printf(" compression %d(not supported)", feature_compression); - break; - } - - printf(", %sosd", feature_osd ? "" : "no "); - - switch (feature_audio) { - case AUDIO_NONE: - printf(", no audio"); - break; - - case AUDIO_TX: - printf(", audio tx"); - break; - - case AUDIO_RX: - printf(", audio rx"); - break; - - case AUDIO_RXTX: - printf(", audio rx+tx"); - break; - - default: - printf(", audio %d(not supported)", feature_audio); - break; - } - - puts(",\n "); - - switch (feature_sysclock) { - case SYSCLK_147456: - printf("clock 147.456 MHz"); - break; - - default: - printf("clock %d(not supported)", feature_sysclock); - break; - } - - switch (feature_ramconfig) { - case RAM_DDR2_32: - printf(", RAM 32 bit DDR2"); - break; - - case RAM_DDR3_32: - printf(", RAM 32 bit DDR3"); - break; - - default: - printf(", RAM %d(not supported)", feature_ramconfig); - break; - } - - printf(", %d carrier(s) %s", feature_carriers, - feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); - - printf(", %d video channel(s)\n", feature_video_channels); -} - -int last_stage_init(void) -{ - int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - u16 fpga_features; - int feature_carrier_speed; - bool ch0_rgmii2_present = false; - - FPGA_GET_REG(0, fpga_features, &fpga_features); - feature_carrier_speed = fpga_features & (1<<4); - - if (!legacy) { - /* Turn on Parade DP501 */ - pca9698_direction_output(0x20, 9, 1); - - ch0_rgmii2_present = !pca9698_get_value(0x20, 30); - } - - /* wait for FPGA done; then reset FPGA */ - for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { - unsigned int ctr = 0; - - if (i2c_probe(mclink_controllers[k])) - continue; - - while (!(pca953x_get_val(mclink_controllers[k]) - & MCFPGA_DONE)) { - udelay(100000); - if (ctr++ > 5) { - printf("no done for mclink_controller %d\n", k); - break; - } - } - - pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); - udelay(10); - pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, - MCFPGA_RESET_N); - } - - if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) { - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { - if ((mux_ch == 1) && !ch0_rgmii2_present) - continue; - - setup_88e1518(bb_miiphy_buses[0].name, mux_ch); - } - } - - /* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); - - mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; - slaves = mclink_probe(); - mclink_fpgacount = 0; - - print_fpga_info(0, ch0_rgmii2_present); - osd_probe(0); - - if (slaves <= 0) - return 0; - - mclink_fpgacount = slaves; - - for (k = 1; k <= slaves; ++k) { - FPGA_GET_REG(k, fpga_features, &fpga_features); - feature_carrier_speed = fpga_features & (1<<4); - - print_fpga_info(k, false); - osd_probe(k); - if (feature_carrier_speed == CARRIER_SPEED_1G) { - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, bb_miiphy_buses[k].name, - MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - setup_88e1518(bb_miiphy_buses[k].name, 0); - } - } - - return 0; -} - -/* - * provide access to fpga gpios (for I2C bitbang) - * (these may look all too simple but make iocon.h much more readable) - */ -void fpga_gpio_set(unsigned int bus, int pin) -{ - FPGA_SET_REG(bus, gpio.set, pin); -} - -void fpga_gpio_clear(unsigned int bus, int pin) -{ - FPGA_SET_REG(bus, gpio.clear, pin); -} - -int fpga_gpio_get(unsigned int bus, int pin) -{ - u16 val; - - FPGA_GET_REG(bus, gpio.read, &val); - - return val & pin; -} - -void gd405ep_init(void) -{ - unsigned int k; - - if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */ - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM; - } else { - pca9698_direction_output(0x20, 4, 1); - } -} - -void gd405ep_set_fpga_reset(unsigned state) -{ - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - - if (legacy) { - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } - } else { - pca9698_set_value(0x20, 4, state ? 0 : 1); - } -} - -void gd405ep_setup_hw(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); -} - -int gd405ep_get_fpga_done(unsigned fpga) -{ - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - - if (legacy) - return in_le16((void *)LATCH2_BASE) - & CONFIG_SYS_FPGA_DONE(fpga); - else - return pca9698_get_value(0x20, 20); -} - -/* - * FPGA MII bitbang implementation - */ - -struct fpga_mii { - unsigned fpga; - int mdio; -} fpga_mii[] = { - { 0, 1}, - { 1, 1}, - { 2, 1}, - { 3, 1}, -}; - -static int mii_dummy_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int mii_mdio_active(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (fpga_mii->mdio) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - return 0; -} - -static int mii_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - - return 0; -} - -static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); - - fpga_mii->mdio = v; - - return 0; -} - -static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - u16 gpio; - struct fpga_mii *fpga_mii = bus->priv; - - FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); - - *v = ((gpio & GPIO_MDIO) != 0); - - return 0; -} - -static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct fpga_mii *fpga_mii = bus->priv; - - if (v) - FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); - else - FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); - - return 0; -} - -static int mii_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = "board0", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[0], - }, - { - .name = "board1", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[1], - }, - { - .name = "board2", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[2], - }, - { - .name = "board3", - .init = mii_dummy_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &fpga_mii[3], - }, -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c deleted file mode 100644 index ad88af2..0000000 --- a/board/gdsys/405ep/neo.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -#include "405ep.h" -#include <gdsys_fpga.h> - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - -enum { - UNITTYPE_CCX16 = 1, - UNITTYPE_CCIP216 = 2, -}; - -enum { - HWVER_300 = 3, -}; - -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -int misc_init_r(void) -{ - /* - * Note: DTT has been removed. Please use UCLASS_THERMAL. - * - * startup fans - * - * dtt_init(); - */ - - return 0; -} - -int checkboard(void) -{ - char *s = getenv("serial#"); - - puts("Board: CATCenter Neo"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - puts("\n"); - - return 0; -} - -static void print_fpga_info(void) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - int fpga_state = get_fpga_state(0); - unsigned unit_type; - unsigned hardware_version; - unsigned feature_channels; - - puts("FPGA: "); - if (fpga_state & FPGA_STATE_DONE_FAILED) { - printf(" done timed out\n"); - return; - } - - if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { - printf(" refelectione test failed\n"); - return; - } - - FPGA_GET_REG(0, versions, &versions); - FPGA_GET_REG(0, fpga_version, &fpga_version); - FPGA_GET_REG(0, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - hardware_version = versions & 0x000f; - feature_channels = fpga_features & 0x007f; - - switch (unit_type) { - case UNITTYPE_CCX16: - printf("CCX-Switch"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - switch (hardware_version) { - case HWVER_300: - printf(" HW-Ver 3.00-3.12\n"); - break; - - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %d channel(s)\n", feature_channels); -} - -int last_stage_init(void) -{ - print_fpga_info(); - - return 0; -} - -void gd405ep_init(void) -{ -} - -void gd405ep_set_fpga_reset(unsigned state) -{ - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } -} - -void gd405ep_setup_hw(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); -} - -int gd405ep_get_fpga_done(unsigned fpga) -{ - /* - * Neo hardware has no FPGA-DONE GPIO - */ - return 1; -} diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c deleted file mode 100644 index 9e1c57f..0000000 --- a/board/gdsys/405ex/405ex.c +++ /dev/null @@ -1,244 +0,0 @@ -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/ppc405.h> -#include <asm/processor.h> -#include <asm/io.h> - -#include <gdsys_fpga.h> - -#include "405ex.h" - -#define REFLECTION_TESTPATTERN 0xdede -#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) - -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI -#define REFLECTION_TESTREG reflection_low -#else -#define REFLECTION_TESTREG reflection_high -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int get_fpga_state(unsigned dev) -{ - return gd->arch.fpga_state[dev]; -} - -int board_early_init_f(void) -{ - u32 val; - - /*--------------------------------------------------------------------+ - | Interrupt controller setup - +--------------------------------------------------------------------+ - +---------------------------------------------------------------------+ - |Interrupt| Source | Pol. | Sensi.| Crit. | - +---------+-----------------------------------+-------+-------+-------+ - | IRQ 00 | UART0 | High | Level | Non | - | IRQ 01 | UART1 | High | Level | Non | - | IRQ 02 | IIC0 | High | Level | Non | - | IRQ 03 | TBD | High | Level | Non | - | IRQ 04 | TBD | High | Level | Non | - | IRQ 05 | EBM | High | Level | Non | - | IRQ 06 | BGI | High | Level | Non | - | IRQ 07 | IIC1 | Rising| Edge | Non | - | IRQ 08 | SPI | High | Lvl/ed| Non | - | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | - | IRQ 10 | MAL TX EOB | High | Level | Non | - | IRQ 11 | MAL RX EOB | High | Level | Non | - | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | - | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | - | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | - | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | - | IRQ 16 | PCIE0 AL | high | Level | Non | - | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | - | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | - | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | - | IRQ 20 | PCIE0 TCR | High | Level | Non | - | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | - | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | - | IRQ 23 | Security EIP-94 | High | Level | Non | - | IRQ 24 | EMAC0 interrupt | High | Level | Non | - | IRQ 25 | EMAC1 interrupt | High | Level | Non | - | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | - | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | - | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | - | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | - | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | - | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | - |---------------------------------------------------------------------- - | IRQ 32 | MAL Serr | High | Level | Non | - | IRQ 33 | MAL Txde | High | Level | Non | - | IRQ 34 | MAL Rxde | High | Level | Non | - | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | - | IRQ 36 | PCIE0 DCR Error | High | Level | Non | - | IRQ 37 | EBC | High |Lvl Edg| Non | - | IRQ 38 | NDFC | High | Level | Non | - | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | - | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | - | IRQ 41 | PCIE1 AL | high | Level | Non | - | IRQ 42 | PCIE1 VPD access | rising| edge | Non | - | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | - | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | - | IRQ 45 | PCIE1 TCR | High | Level | Non | - | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | - | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | - | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | - | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | - | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | - | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | - | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | - | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | - | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | - | IRQ 55 | Serial ROM | High | Level | Non | - | IRQ 56 | GPT Decrement Pulse | High | Level | Non | - | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | - | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | - | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | - | IRQ 60 | EMAC0 Wake-up | High | Level | Non | - | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | - | IRQ 62 | EMAC1 Wake-up | High | Level | Non | - |---------------------------------------------------------------------- - | IRQ 64 | PE0 AL | High | Level | Non | - | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | - | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | - | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | - | IRQ 68 | PE0 TCR | High | Level | Non | - | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | - | IRQ 70 | PE0 DCR Error | High | Level | Non | - | IRQ 71 | Reserved | N/A | N/A | Non | - | IRQ 72 | PE1 AL | High | Level | Non | - | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | - | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | - | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | - | IRQ 76 | PE1 TCR | High | Level | Non | - | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | - | IRQ 78 | PE1 DCR Error | High | Level | Non | - | IRQ 79 | Reserved | N/A | N/A | Non | - | IRQ 80 | PE2 AL | High | Level | Non | - | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | - | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | - | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | - | IRQ 84 | PE2 TCR | High | Level | Non | - | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | - | IRQ 86 | PE2 DCR Error | High | Level | Non | - | IRQ 87 | Reserved | N/A | N/A | Non | - | IRQ 88 | External IRQ(5) | Progr | Progr | Non | - | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | - | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | - | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | - | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | - | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | - | IRQ 94 | Reserved | N/A | N/A | Non | - | IRQ 95 | Reserved | N/A | N/A | Non | - |--------------------------------------------------------------------- - +---------+-----------------------------------+-------+-------+------*/ - /*--------------------------------------------------------------------+ - | Initialise UIC registers. Clear all interrupts. Disable all - | interrupts. - | Set critical interrupt values. Set interrupt polarities. Set - | interrupt trigger levels. Make bit 0 High priority. Clear all - | interrupts again. - +-------------------------------------------------------------------*/ - - mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ - mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ - mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ - mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ - mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */ - mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */ - /* Except cascade UIC0 and UIC1 */ - mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ - mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ - mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ - mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ - mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */ - mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ - - /* - * Note: Some cores are still in reset when the chip starts, so - * take them out of reset - */ - mtsdr(SDR0_SRST, 0); - - /* - * Configure PFC (Pin Function Control) registers - */ - val = SDR0_PFC1_GPT_FREQ; - mtsdr(SDR0_PFC1, val); - - return 0; -} - -int board_early_init_r(void) -{ - unsigned k; - unsigned ctr; - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] = 0; - - /* - * reset FPGA - */ - gd405ex_init(); - - gd405ex_set_fpga_reset(1); - - gd405ex_setup_hw(); - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - ctr = 0; - while (!gd405ex_get_fpga_done(k)) { - udelay(100000); - if (ctr++ > 5) { - gd->arch.fpga_state[k] |= - FPGA_STATE_DONE_FAILED; - break; - } - } - } - - udelay(10); - - gd405ex_set_fpga_reset(0); - - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - /* - * wait for fpga out of reset - */ - ctr = 0; - while (1) { - u16 val; - - FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); - - FPGA_GET_REG(k, REFLECTION_TESTREG, &val); - if (val == REFLECTION_TESTPATTERN_INV) - break; - - udelay(100000); - if (ctr++ > 5) { - gd->arch.fpga_state[k] |= - FPGA_STATE_REFLECTION_FAILED; - break; - } - } - } - - return 0; -} diff --git a/board/gdsys/405ex/405ex.h b/board/gdsys/405ex/405ex.h deleted file mode 100644 index b15623f..0000000 --- a/board/gdsys/405ex/405ex.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __405EX_H_ -#define __405EX_H_ - -/* functions to be provided by board implementation */ -void gd405ex_init(void); -void gd405ex_set_fpga_reset(unsigned state); -void gd405ex_setup_hw(void); -int gd405ex_get_fpga_done(unsigned fpga); - -#endif /* __405EX_H_ */ diff --git a/board/gdsys/405ex/Kconfig b/board/gdsys/405ex/Kconfig deleted file mode 100644 index 52a8d89..0000000 --- a/board/gdsys/405ex/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IO64 - -config SYS_BOARD - default "405ex" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "io64" - -endif diff --git a/board/gdsys/405ex/MAINTAINERS b/board/gdsys/405ex/MAINTAINERS deleted file mode 100644 index 395b1ac..0000000 --- a/board/gdsys/405ex/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -405EX BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/405ex/ -F: include/configs/io64.h -F: configs/io64_defconfig diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile deleted file mode 100644 index a668460..0000000 --- a/board/gdsys/405ex/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := 405ex.o -obj-$(CONFIG_IO64) += io64.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o diff --git a/board/gdsys/405ex/chip_config.c b/board/gdsys/405ex/chip_config.c deleted file mode 100644 index 37e76c4..0000000 --- a/board/gdsys/405ex/chip_config.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", - { - 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { - 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66", - { - 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", - { - 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, - { - "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, - 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", - { - 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c deleted file mode 100644 index 9ef965bb..0000000 --- a/board/gdsys/405ex/io64.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * based on kilauea.c - * by Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/ppc405.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/ppc4xx-gpio.h> -#include <flash.h> - -#include <pca9698.h> - -#include "405ex.h" -#include <gdsys_fpga.h> - -#include <miiphy.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define PHYREG_CONTROL 0 -#define PHYREG_PAGE_ADDRESS 22 -#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 -#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 -#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17 -#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21 - -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) -#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) - -enum { - UNITTYPE_CCD_SWITCH = 1, -}; - -enum { - HWVER_100 = 0, - HWVER_110 = 1, -}; - -struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; - -static inline void blank_string(int size) -{ - int i; - - for (i = 0; i < size; i++) - putc('\b'); - for (i = 0; i < size; i++) - putc(' '); - for (i = 0; i < size; i++) - putc('\b'); -} - -/* - * Board early initialization function - */ -int misc_init_r(void) -{ - /* - * Note: DTT has been removed. Please use UCLASS_THERMAL. - * - * startup fans - * - * dtt_init(); - */ - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); -#endif - - return 0; -} - -static void print_fpga_info(unsigned dev) -{ - u16 versions; - u16 fpga_version; - u16 fpga_features; - int fpga_state = get_fpga_state(dev); - - unsigned unit_type; - unsigned hardware_version; - unsigned feature_channels; - unsigned feature_expansion; - - FPGA_GET_REG(dev, versions, &versions); - FPGA_GET_REG(dev, fpga_version, &fpga_version); - FPGA_GET_REG(dev, fpga_features, &fpga_features); - - printf("FPGA%d: ", dev); - if (fpga_state & FPGA_STATE_PLATFORM) - printf("(legacy) "); - - if (fpga_state & FPGA_STATE_DONE_FAILED) { - printf(" done timed out\n"); - return; - } - - if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { - printf(" refelectione test failed\n"); - return; - } - - unit_type = (versions & 0xf000) >> 12; - hardware_version = versions & 0x000f; - feature_channels = fpga_features & 0x007f; - feature_expansion = fpga_features & (1<<15); - - switch (unit_type) { - case UNITTYPE_CCD_SWITCH: - printf("CCD-Switch"); - break; - - default: - printf("UnitType %d(not supported)", unit_type); - break; - } - - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00\n"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10\n"); - break; - - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; - } - - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); - - printf(" %d channel(s)", feature_channels); - - printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); -} - -int checkboard(void) -{ - char *s = getenv("serial#"); - - printf("Board: CATCenter Io64\n"); - - if (s != NULL) { - puts(", serial# "); - puts(s); - } - - return 0; -} - -int configure_gbit_phy(char *bus, unsigned char addr) -{ - unsigned short value; - - /* select page 0 */ - if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) - goto err_out; - /* switch to powerdown */ - if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, - &value)) - goto err_out; - if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, - value | 0x0004)) - goto err_out; - /* select page 2 */ - if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) - goto err_out; - /* disable SGMII autonegotiation */ - if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48)) - goto err_out; - /* select page 0 */ - if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) - goto err_out; - /* switch from powerdown to normal operation */ - if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, - &value)) - goto err_out; - if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, - value & ~0x0004)) - goto err_out; - /* reset phy so settings take effect */ - if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140)) - goto err_out; - - return 0; - -err_out: - printf("Error writing to the PHY addr=%02x\n", addr); - return -1; -} - -int verify_gbit_phy(char *bus, unsigned char addr) -{ - unsigned short value; - - /* select page 2 */ - if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) - goto err_out; - /* verify SGMII link status */ - if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value)) - goto err_out; - if (!(value & (1 << 10))) - return -2; - - return 0; - -err_out: - printf("Error writing to the PHY addr=%02x\n", addr); - return -1; -} - -int last_stage_init(void) -{ - unsigned int k; - unsigned int fpga; - int failed = 0; - char str_phys[] = "Setup PHYs -"; - char str_serdes[] = "Start SERDES blocks"; - char str_channels[] = "Start FPGA channels"; - char str_locks[] = "Verify SERDES locks"; - char str_hicb[] = "Verify HICB status"; - char str_status[] = "Verify PHY status -"; - char slash[] = "\\|/-\\|/-"; - - print_fpga_info(0); - print_fpga_info(1); - - /* setup Gbit PHYs */ - puts("TRANS: "); - puts(str_phys); - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - - for (k = 0; k < 32; ++k) { - configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); - putc('\b'); - putc(slash[k % 8]); - } - - mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - - for (k = 0; k < 32; ++k) { - configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); - putc('\b'); - putc(slash[k % 8]); - } - blank_string(strlen(str_phys)); - - /* take fpga serdes blocks out of reset */ - puts(str_serdes); - udelay(500000); - FPGA_SET_REG(0, quad_serdes_reset, 0); - FPGA_SET_REG(1, quad_serdes_reset, 0); - blank_string(strlen(str_serdes)); - - /* take channels out of reset */ - puts(str_channels); - udelay(500000); - for (fpga = 0; fpga < 2; ++fpga) { - for (k = 0; k < 32; ++k) - FPGA_SET_REG(fpga, ch[k].config_int, 0); - } - blank_string(strlen(str_channels)); - - /* verify channels serdes lock */ - puts(str_locks); - udelay(500000); - for (fpga = 0; fpga < 2; ++fpga) { - for (k = 0; k < 32; ++k) { - u16 status; - FPGA_GET_REG(fpga, ch[k].status_int, &status); - if (!(status & (1 << 4))) { - failed = 1; - printf("fpga %d channel %d: no serdes lock\n", - fpga, k); - } - /* reset events */ - FPGA_SET_REG(fpga, ch[k].status_int, 0); - } - } - blank_string(strlen(str_locks)); - - /* verify hicb_status */ - puts(str_hicb); - for (fpga = 0; fpga < 2; ++fpga) { - for (k = 0; k < 32; ++k) { - u16 status; - FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status); - if (status) - printf("fpga %d hicb %d: hicb status %04x\n", - fpga, k, status); - /* reset events */ - FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0); - } - } - blank_string(strlen(str_hicb)); - - /* verify phy status */ - puts(str_status); - for (k = 0; k < 32; ++k) { - if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) { - printf("verify baseboard phy %d failed\n", k); - failed = 1; - } - putc('\b'); - putc(slash[k % 8]); - } - for (k = 0; k < 32; ++k) { - if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) { - printf("verify extensionboard phy %d failed\n", k); - failed = 1; - } - putc('\b'); - putc(slash[k % 8]); - } - blank_string(strlen(str_status)); - - printf("Starting 64 channels %s\n", failed ? "failed" : "ok"); - - return 0; -} - -void gd405ex_init(void) -{ - unsigned int k; - - if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */ - for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM; - } else { - pca9698_direction_output(0x22, 39, 1); - } -} - -void gd405ex_set_fpga_reset(unsigned state) -{ - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - - if (legacy) { - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); - } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - } - } else { - pca9698_set_value(0x22, 39, state ? 0 : 1); - } -} - -void gd405ex_setup_hw(void) -{ - gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0); - gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1); -} - -int gd405ex_get_fpga_done(unsigned fpga) -{ - int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; - - if (legacy) - return in_le16((void *)LATCH3_BASE) - & CONFIG_SYS_FPGA_DONE(fpga); - else - return pca9698_get_value(0x22, fpga ? 9 : 8); -} diff --git a/board/gdsys/dlvision/Kconfig b/board/gdsys/dlvision/Kconfig deleted file mode 100644 index 8db4fbe..0000000 --- a/board/gdsys/dlvision/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DLVISION - -config SYS_BOARD - default "dlvision" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "dlvision" - -endif diff --git a/board/gdsys/dlvision/MAINTAINERS b/board/gdsys/dlvision/MAINTAINERS deleted file mode 100644 index e4d40f8..0000000 --- a/board/gdsys/dlvision/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DLVISION BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/dlvision/ -F: include/configs/dlvision.h -F: configs/dlvision_defconfig diff --git a/board/gdsys/dlvision/Makefile b/board/gdsys/dlvision/Makefile deleted file mode 100644 index 755eb4c..0000000 --- a/board/gdsys/dlvision/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = dlvision.o diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c deleted file mode 100644 index 32f7ba3..0000000 --- a/board/gdsys/dlvision/dlvision.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * (C) Copyright 2009 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> - -enum { - HWTYPE_DLVISION_CPU = 0, - HWTYPE_DLVISION_CON = 1, -}; - -#define HWREV_100 6 - -int board_early_init_f(void) -{ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks - * -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - /* - * setup io-latches - */ - out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0); - out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002); - out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000); - return 0; -} - -int misc_init_r(void) -{ - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26); - u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36); - u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76); - u8 unit_type; - u8 local_con; - u8 audio; - u8 hardware_version; - - printf("Board: "); - - unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00; - local_con = (channel2_msr & 0x20) ? 0x01 : 0x00; - audio = (channel3_msr & 0x20) ? 0x01 : 0x00; - hardware_version = - ((channel7_msr & 0x20) ? 0x01 : 0x00) - | ((channel7_msr & 0x80) ? 0x02 : 0x00) - | ((channel7_msr & 0x40) ? 0x04 : 0x00); - - switch (unit_type) { - case HWTYPE_DLVISION_CON: - printf("DL-Vision-CON"); - break; - - case HWTYPE_DLVISION_CPU: - printf("DL-Vision-CPU"); - break; - - default: - printf("UnitType %d, unsupported", unit_type); - break; - } - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - puts("\n "); - - switch (hardware_version) { - case HWREV_100: - printf("HW-Ver 1.00"); - break; - - default: - printf("HW-Ver %d, unsupported", - hardware_version); - break; - } - - if (local_con) - printf(", local console"); - - if (audio) - printf(", audio support"); - - puts("\n"); - - return 0; -} diff --git a/board/gdsys/gdppc440etx/Kconfig b/board/gdsys/gdppc440etx/Kconfig deleted file mode 100644 index 1f21c89..0000000 --- a/board/gdsys/gdppc440etx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_GDPPC440ETX - -config SYS_BOARD - default "gdppc440etx" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "gdppc440etx" - -endif diff --git a/board/gdsys/gdppc440etx/MAINTAINERS b/board/gdsys/gdppc440etx/MAINTAINERS deleted file mode 100644 index cd8d1c6..0000000 --- a/board/gdsys/gdppc440etx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -GDPPC440ETX BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/gdppc440etx/ -F: include/configs/gdppc440etx.h -F: configs/gdppc440etx_defconfig diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile deleted file mode 100644 index 7e3fc38..0000000 --- a/board/gdsys/gdppc440etx/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = gdppc440etx.o -extra-y += init.o diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk deleted file mode 100644 index 73341a5..0000000 --- a/board/gdsys/gdppc440etx/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# G&D 440EP/GR ETX-Module -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c deleted file mode 100644 index 04191df..0000000 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * (C) Copyright 2008 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * Based on board/amcc/yosemite/yosemite.c - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/4xx_pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* info for FLASH chips */ -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -int board_early_init_f(void) -{ - register uint reg; - - /* - * Setup the external bus controller/chip selects - */ - mfebc(EBC0_CFG, reg); - mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */ - - /* - * Setup the GPIO pins - */ - - /* setup Address lines for flash size 64Meg. */ - out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000); - - /* setup emac */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); - out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); - out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); - - /* UART0 and UART1*/ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000); - out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000); - out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000); - out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000); - - /* disable boot-eeprom WP */ - out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000); - out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000); - out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000); - out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000); - out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000); - - /* external interrupts IRQ0...3 */ - out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); - out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); - out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); - - - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ - mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - /* - * Setup other serial configuration - */ - mfsdr(SDR0_PCI0, reg); - mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ - mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ - - return 0; -} - -int misc_init_r(void) -{ - uint pbcr; - int size_val; - uint sz; - - /* Re-do sizing to get full correct info */ - mfebc(PB0CR, pbcr); - - if (gd->bd->bi_flashsize > 0x08000000) - panic("Max. flash banksize is 128 MB!\n"); - - for (sz = gd->bd->bi_flashsize, size_val = 7; - ((sz & 0x08000000) == 0) && (size_val > 0); --size_val) - sz <<= 1; - - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(PB0CR, pbcr); - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override weak pci_pre_init() - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - /* First call common code */ - __pci_pre_init(hose); - - /* enable 66 MHz ext. Clock */ - out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); - out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000); - - return 1; -} -#endif /* defined(CONFIG_PCI) */ diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S deleted file mode 100644 index 2db84b5..0000000 --- a/board/gdsys/gdppc440etx/init.S +++ /dev/null @@ -1,59 +0,0 @@ -/* -* (C) Copyright 2008 -* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de -* -* based on board/amcc/yosemite/init.S -* original Copyright not specified there - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> - -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use - * the speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, - 0, AC_RWX | SA_G/*|SA_I*/) - - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G ) - - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, - 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, - 0, AC_RW | SA_IG ) - - /* PCI */ - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, - 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, - 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, - 0, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, - 0, AC_RW | SA_IG ) - - tlbtab_end diff --git a/board/gdsys/intip/Kconfig b/board/gdsys/intip/Kconfig deleted file mode 100644 index 479bb12..0000000 --- a/board/gdsys/intip/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_INTIP - -config SYS_BOARD - default "intip" - -config SYS_VENDOR - default "gdsys" - -config SYS_CONFIG_NAME - default "intip" - -endif diff --git a/board/gdsys/intip/MAINTAINERS b/board/gdsys/intip/MAINTAINERS deleted file mode 100644 index c99d507..0000000 --- a/board/gdsys/intip/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -INTIP BOARD -M: Dirk Eibach <eibach@gdsys.de> -S: Maintained -F: board/gdsys/intip/ -F: include/configs/intip.h -F: configs/devconcenter_defconfig -F: configs/intip_defconfig diff --git a/board/gdsys/intip/Makefile b/board/gdsys/intip/Makefile deleted file mode 100644 index 2fbc983..0000000 --- a/board/gdsys/intip/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := intip.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/gdsys/intip/chip_config.c b/board/gdsys/intip/chip_config.c deleted file mode 100644 index ea276a3..0000000 --- a/board/gdsys/intip/chip_config.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2008-2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0, - 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/gdsys/intip/config.mk b/board/gdsys/intip/config.mk deleted file mode 100644 index c8c53e2..0000000 --- a/board/gdsys/intip/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2008-2010 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# G&D CompactCenter -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S deleted file mode 100644 index 1fc2a2f..0000000 --- a/board/gdsys/intip/init.S +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2009 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * Based on board/amcc/canyonlands/init.S - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to - * use the speed up boot process. It is patched after relocation to - * enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_RWX | SA_G) /* TLB 0 */ - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, - 0, AC_RWX | SA_G) -#endif - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, - AC_RW | SA_IG) - - /* TLB-entry for NVRAM */ - tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4, - AC_RW | SA_IG) - - /* TLB-entry for UART */ - tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4, - AC_RW | SA_IG) - - /* TLB-entry for IO */ - tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4, - AC_RW | SA_IG) - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, - AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, - 4, AC_RWX | SA_IG) - - /* AHB: Internal USB Peripherals (USB, SATA) */ - tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, - AC_RWX | SA_IG) - - tlbtab_end diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c deleted file mode 100644 index 2d7d789..0000000 --- a/board/gdsys/intip/intip.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * (C) Copyright 2009 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * Based on board/amcc/canyonlands/canyonlands.c - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc440.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <i2c.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/4xx_pcie.h> -#include <asm/ppc4xx-gpio.h> - -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -DECLARE_GLOBAL_DATA_PTR; - -#define CONFIG_SYS_BCSR3_PCIE 0x10 - -int board_early_init_f(void) -{ - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - /* - * Configure PFC (Pin Function Control) registers - * enable GPIO 49-63 - * UART0: 4 pins - */ - mtsdr(SDR0_PFC0, 0x00007fff); - mtsdr(SDR0_PFC1, 0x00040000); - - /* Enable PCI host functionality in SDR0_PCI0 */ - mtsdr(SDR0_PCI0, 0xe0000000); - - mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - - /* Trigger board component reset */ - out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff); - out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff); - udelay(50); - out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf); - out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf); - udelay(50); - out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff); - out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff); - - return 0; -} - -int get_cpu_num(void) -{ - int cpu = NA_OR_UNKNOWN_CPU; - - return cpu; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - -#ifdef CONFIG_DEVCONCENTER - printf("Board: DevCon-Center"); -#else - printf("Board: Intip"); -#endif - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int board_early_init_r(void) -{ - /* - * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH - * (Spansion 29GL512), but the boot EBC mapping only supports a maximum - * of 16MBytes (4.ff00.0000 - 4.ffff.ffff). - * To solve this problem, the FLASH has to get remapped to another - * EBC address which accepts bigger regions: - * - * 0xfn00.0000 -> 4.cn00.0000 - */ - - u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ? - EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB; - - /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */ - mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L - | bxcr_bw - | EBC_BXCR_BU_RW - | EBC_BXCR_BW_16BIT); - - /* Remove TLB entry of boot EBC mapping */ - remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); - - /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */ - program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); - - /* - * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address - * 0xfc00.0000 is possible - */ - - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return 0; -} - -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - u32 eth_cfg; - - /* - * Set EMAC mode/configuration (GMII, SGMII, RGMII...). - * This is board specific, so let's do it here. - */ - mfsdr(SDR0_ETH_CFG, eth_cfg); - /* disable SGMII mode */ - eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | - SDR0_ETH_CFG_SGMII1_ENABLE | - SDR0_ETH_CFG_SGMII0_ENABLE); - /* Set the for 2 RGMII mode */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ - eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL; - mtsdr(SDR0_ETH_CFG, eth_cfg); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - return 0; -} - -#ifdef CONFIG_OF_BOARD_SETUP -extern void __ft_board_setup(void *blob, bd_t *bd); - -int ft_board_setup(void *blob, bd_t *bd) -{ - __ft_board_setup(blob, bd); - - fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", - "disabled", sizeof("disabled"), 1); - - fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", - "disabled", sizeof("disabled"), 1); - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 1b8e035..86b257f 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -9,7 +9,6 @@ #include <command.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/ppc4xx-gpio.h> #include <asm/global_data.h> #include "mpc8308.h" diff --git a/board/liebherr/lwmon5/Kconfig b/board/liebherr/lwmon5/Kconfig deleted file mode 100644 index ec8349d..0000000 --- a/board/liebherr/lwmon5/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_LWMON5 - -config SYS_BOARD - default "lwmon5" - -config SYS_VENDOR - default "liebherr" - -config SYS_CONFIG_NAME - default "lwmon5" - -endif diff --git a/board/liebherr/lwmon5/MAINTAINERS b/board/liebherr/lwmon5/MAINTAINERS deleted file mode 100644 index df45730..0000000 --- a/board/liebherr/lwmon5/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -LWMON5 BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/liebherr/lwmon5/ -F: include/configs/lwmon5.h -F: configs/lwmon5_defconfig diff --git a/board/liebherr/lwmon5/Makefile b/board/liebherr/lwmon5/Makefile deleted file mode 100644 index 02478ca..0000000 --- a/board/liebherr/lwmon5/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = lwmon5.o kbd.o sdram.o -extra-y += init.o diff --git a/board/liebherr/lwmon5/config.mk b/board/liebherr/lwmon5/config.mk deleted file mode 100644 index d0348e8..0000000 --- a/board/liebherr/lwmon5/config.mk +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# lwmon5 (440EPx) -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/liebherr/lwmon5/init.S b/board/liebherr/lwmon5/init.S deleted file mode 100644 index e5207c2..0000000 --- a/board/liebherr/lwmon5/init.S +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) -#endif - - /* TLB-entry for PCI Memory */ - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG) - - /* TLB-entry for the FPGA Chip select 2 */ - tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G) - - /* TLB-entry for the FPGA Chip select 3 */ - tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G) - - /* TLB-entry for the LIME Controller */ - tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G) - tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G) - tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G) - tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G) - - /* TLB-entry for Internal Registers & OCM */ - tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I) - - /*TLB-entry PCI registers*/ - tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG) - - /* TLB-entry for peripherals */ - tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) - - tlbtab_end diff --git a/board/liebherr/lwmon5/kbd.c b/board/liebherr/lwmon5/kbd.c deleted file mode 100644 index d6c0a20..0000000 --- a/board/liebherr/lwmon5/kbd.c +++ /dev/null @@ -1,491 +0,0 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2001, 2002 - * DENX Software Engineering - * Wolfgang Denk, wd@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include <common.h> -#include <i2c.h> -#include <command.h> -#include <console.h> -#include <post.h> -#include <serial.h> -#include <malloc.h> - -#include <linux/types.h> -#include <linux/string.h> /* for strdup */ - -DECLARE_GLOBAL_DATA_PTR; - -static void kbd_init (void); -static int compare_magic (uchar *kbd_data, uchar *str); - -/*--------------------- Local macros and constants --------------------*/ -#define _NOT_USED_ 0xFFFFFFFF - -/*------------------------- dspic io expander -----------------------*/ -#define DSPIC_PON_STATUS_REG 0x80A -#define DSPIC_PON_INV_STATUS_REG 0x80C -#define DSPIC_PON_KEY_REG 0x810 -/*------------------------- Keyboard controller -----------------------*/ -/* command codes */ -#define KEYBD_CMD_READ_KEYS 0x01 -#define KEYBD_CMD_READ_VERSION 0x02 -#define KEYBD_CMD_READ_STATUS 0x03 -#define KEYBD_CMD_RESET_ERRORS 0x10 - -/* status codes */ -#define KEYBD_STATUS_MASK 0x3F -#define KEYBD_STATUS_H_RESET 0x20 -#define KEYBD_STATUS_BROWNOUT 0x10 -#define KEYBD_STATUS_WD_RESET 0x08 -#define KEYBD_STATUS_OVERLOAD 0x04 -#define KEYBD_STATUS_ILLEGAL_WR 0x02 -#define KEYBD_STATUS_ILLEGAL_RD 0x01 - -/* Number of bytes returned from Keyboard Controller */ -#define KEYBD_VERSIONLEN 2 /* version information */ - -/* - * This is different from the "old" lwmon dsPIC kbd controller - * implementation. Now the controller still answers with 9 bytes, - * but the last 3 bytes are always "0x06 0x07 0x08". So we just - * set the length to compare to 6 instead of 9. - */ -#define KEYBD_DATALEN 6 /* normal key scan data */ - -/* maximum number of "magic" key codes that can be assigned */ - -static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; -static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR; - -static uchar *key_match (uchar *); - -#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */ - -/*********************************************************************** -F* Function: int board_postclk_init (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: This function is the board_postclk_init() method implementation -Z* for the lwmon board. - * - ***********************************************************************/ -int board_postclk_init (void) -{ - kbd_init(); - - return (0); -} - -static void kbd_init (void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar tmp_data[KEYBD_DATALEN]; - uchar val, errcd; - int i; - - i2c_set_bus_num(0); - - gd->arch.kbd_status = 0; - - /* Forced by PIC. Delays <= 175us loose */ - udelay(1000); - - /* Read initial keyboard error code */ - val = KEYBD_CMD_READ_STATUS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, &errcd, 1); - /* clear unused bits */ - errcd &= KEYBD_STATUS_MASK; - /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */ - errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT); - if (errcd) { - gd->arch.kbd_status |= errcd << 8; - } - /* Reset error code and verify */ - val = KEYBD_CMD_RESET_ERRORS; - i2c_write (kbd_addr, 0, 0, &val, 1); - udelay(1000); /* delay NEEDED by keyboard PIC !!! */ - - val = KEYBD_CMD_READ_STATUS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, &val, 1); - - val &= KEYBD_STATUS_MASK; /* clear unused bits */ - if (val) { /* permanent error, report it */ - gd->arch.kbd_status |= val; - return; - } - - /* - * Read current keyboard state. - * - * After the error reset it may take some time before the - * keyboard PIC picks up a valid keyboard scan - the total - * scan time is approx. 1.6 ms (information by Martin Rajek, - * 28 Sep 2002). We read a couple of times for the keyboard - * to stabilize, using a big enough delay. - * 10 times should be enough. If the data is still changing, - * we use what we get :-( - */ - - memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */ - for (i=0; i<10; ++i) { - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) { - /* consistent state, done */ - break; - } - /* remeber last state, delay, and retry */ - memcpy (tmp_data, kbd_data, KEYBD_DATALEN); - udelay (5000); - } -} - - -/* Read a register from the dsPIC. */ -int _dspic_read(ushort reg, ushort *data) -{ - uchar buf[sizeof(*data)]; - int rval; - - if (i2c_read(dspic_addr, reg, 2, buf, 2)) - return -1; - - rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data)); - *data = (buf[0] << 8) | buf[1]; - - return rval; -} - - -/*********************************************************************** -F* Function: int misc_init_r (void) P*A*Z* - * -P* Parameters: none -P* -P* Returnvalue: int -P* - 0 is always returned, even in the case of a keyboard -P* error. - * -Z* Intention: This function is the misc_init_r() method implementation -Z* for the lwmon board. -Z* The keyboard controller is initialized and the result -Z* of a read copied to the environment variable "keybd". -Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for -Z* this key, and if found display to the LCD will be enabled. -Z* The keys in "keybd" are checked against the magic -Z* keycommands defined in the environment. -Z* See also key_match(). - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int misc_init_r_kbd (void) -{ - uchar kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - uchar kbd_init_status = gd->arch.kbd_status >> 8; - uchar kbd_status = gd->arch.kbd_status; - uchar val; - ushort data, inv_data; - char *str; - int i; - - if (kbd_init_status) { - printf ("KEYBD: Error %02X\n", kbd_init_status); - } - if (kbd_status) { /* permanent error, report it */ - printf ("*** Keyboard error code %02X ***\n", kbd_status); - sprintf (keybd_env, "%02X", kbd_status); - setenv ("keybd", keybd_env); - return 0; - } - - /* - * Now we know that we have a working keyboard, so disable - * all output to the LCD except when a key press is detected. - */ - - if ((console_assign (stdout, "serial") < 0) || - (console_assign (stderr, "serial") < 0)) { - printf ("Can't assign serial port as output device\n"); - } - - /* Read Version */ - val = KEYBD_CMD_READ_VERSION; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN); - printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]); - - /* Read current keyboard state */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - /* read out start key from bse01 received via can */ - _dspic_read(DSPIC_PON_STATUS_REG, &data); - /* check highbyte from status register */ - if (data > 0xFF) { - _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data); - - /* check inverse data */ - if ((data+inv_data) == 0xFFFF) { - /* don't overwrite local key */ - if (kbd_data[1] == 0) { - /* read key value */ - _dspic_read(DSPIC_PON_KEY_REG, &data); - str = (char *)&data; - /* swap bytes */ - kbd_data[1] = str[1]; - kbd_data[2] = str[0]; - printf("CAN received startkey: 0x%X\n", data); - } - } - } - - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - } - - setenv ("keybd", keybd_env); - - str = strdup ((char *)key_match (kbd_data)); /* decode keys */ -#ifdef KEYBD_SET_DEBUGMODE - if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */ - if ((console_assign (stdout, "lcd") < 0) || - (console_assign (stderr, "lcd") < 0)) { - printf ("Can't assign LCD display as output device\n"); - } - } -#endif /* KEYBD_SET_DEBUGMODE */ -#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */ - setenv ("preboot", str); /* set or delete definition */ -#endif /* CONFIG_PREBOOT */ - if (str != NULL) { - free (str); - } - return (0); -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -static int compare_magic (uchar *kbd_data, uchar *str) -{ - uchar compare[KEYBD_DATALEN-1]; - char *nxt; - int i; - - /* Don't include modifier byte */ - memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); - - for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) { - uchar c; - int k; - - c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16); - - if (str == (uchar *)nxt) { /* invalid character */ - break; - } - - /* - * Check if this key matches the input. - * Set matches to zero, so they match only once - * and we can find duplicates or extra keys - */ - for (k = 0; k < sizeof(compare); ++k) { - if (compare[k] == '\0') /* only non-zero entries */ - continue; - if (c == compare[k]) { /* found matching key */ - compare[k] = '\0'; - break; - } - } - if (k == sizeof(compare)) { - return -1; /* unmatched key */ - } - } - - /* - * A full match leaves no keys in the `compare' array, - */ - for (i = 0; i < sizeof(compare); ++i) { - if (compare[i]) - { - return -1; - } - } - - return 0; -} - -/*********************************************************************** -F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z* - * -P* Parameters: uchar *kbd_data -P* - The keys to match against our magic definitions -P* -P* Returnvalue: uchar * -P* - != NULL: Pointer to the corresponding command(s) -P* NULL: No magic is about to happen - * -Z* Intention: Check if pressed key(s) match magic sequence, -Z* and return the command string associated with that key(s). -Z* -Z* If no key press was decoded, NULL is returned. -Z* -Z* Note: the first character of the argument will be -Z* overwritten with the "magic charcter code" of the -Z* decoded key(s), or '\0'. -Z* -Z* Note: the string points to static environment data -Z* and must be saved before you call any function that -Z* modifies the environment. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -static uchar *key_match (uchar *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - uchar *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can pe appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - debug ("### Check magic \"%s\"\n", magic); - if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - - cmd = getenv (cmd_name); - debug ("### Set PREBOOT to $(%s): \"%s\"\n", - cmd_name, cmd ? cmd : "<<NULL>>"); - *kbd_data = *suffix; - return ((uchar *)cmd); - } - } - debug ("### Delete PREBOOT\n"); - *kbd_data = '\0'; - return (NULL); -} -#endif /* CONFIG_PREBOOT */ - -/*********************************************************************** -F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag, -F* int argc, char * const argv[]) P*A*Z* - * -P* Parameters: cmd_tbl_t *cmdtp -P* - Pointer to our command table entry -P* int flag -P* - If the CMD_FLAG_REPEAT bit is set, then this call is -P* a repetition -P* int argc -P* - Argument count -P* char * const argv[] -P* - Array of the actual arguments -P* -P* Returnvalue: int -P* - 0 is always returned. - * -Z* Intention: Implement the "kbd" command. -Z* The keyboard status is read. The result is printed on -Z* the console and written into the "keybd" environment -Z* variable. - * -D* Design: wd@denx.de -C* Coding: wd@denx.de -V* Verification: dzu@denx.de - ***********************************************************************/ -int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - uchar kbd_data[KEYBD_DATALEN]; - char keybd_env[2 * KEYBD_DATALEN + 1]; - uchar val; - int i; - -#if 0 /* Done in kbd_init */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - puts ("Keys:"); - for (i = 0; i < KEYBD_DATALEN; ++i) { - sprintf (keybd_env + i + i, "%02X", kbd_data[i]); - printf (" %02x", kbd_data[i]); - } - putc ('\n'); - setenv ("keybd", keybd_env); - return 0; -} - -U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "read keyboard status", - "" -); - -/*----------------------------- Utilities -----------------------------*/ - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - uchar kbd_data[KEYBD_DATALEN]; - uchar val; - - /* Read keys */ - val = KEYBD_CMD_READ_KEYS; - i2c_write (kbd_addr, 0, 0, &val, 1); - i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); - - return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0); -} -#endif diff --git a/board/liebherr/lwmon5/lwmon5.c b/board/liebherr/lwmon5/lwmon5.c deleted file mode 100644 index bb99a3b..0000000 --- a/board/liebherr/lwmon5/lwmon5.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * (C) Copyright 2007-2013 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/ppc440.h> -#include <asm/processor.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/io.h> -#include <post.h> -#include <flash.h> -#include <video.h> -#include <mtd/cfi_flash.h> - -DECLARE_GLOBAL_DATA_PTR; - -static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST; - -ulong flash_get_size(ulong base, int banknum); -int misc_init_r_kbd(void); - -int board_early_init_f(void) -{ - u32 sdr0_pfc1, sdr0_pfc2; - u32 reg; - - /* PLB Write pipelining disabled. Denali Core workaround */ - mtdcr(PLB4A0_ACR, 0xDE000000); - mtdcr(PLB4A1_ACR, 0xDE000000); - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */ - mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */ - mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */ - mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */ - mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - /* Trace Pins are disabled. SDR0_PFC0 Register */ - mtsdr(SDR0_PFC0, 0x0); - - /* select Ethernet pins */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - /* SMII via ZMII */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | - SDR0_PFC1_SELECT_CONFIG_6; - mfsdr(SDR0_PFC2, sdr0_pfc2); - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | - SDR0_PFC2_SELECT_CONFIG_6; - - /* enable SPI (SCP) */ - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; - - mtsdr(SDR0_PFC2, sdr0_pfc2); - mtsdr(SDR0_PFC1, sdr0_pfc1); - - mtsdr(SDR0_PFC4, 0x80000000); - - /* PCI arbiter disabled */ - /* PCI Host Configuration disbaled */ - mfsdr(SDR0_PCI0, reg); - reg = 0; - mtsdr(SDR0_PCI0, 0x00000000 | reg); - - gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); - -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 - /* enable the LSB transmitter */ - gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); - /* enable the CAN transmitter */ - gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); - - reg = 0; /* reuse as counter */ - out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, - in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) - & ~CONFIG_SYS_DSPIC_TEST_MASK); - while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { - udelay(1000); - } - if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { - /* set "boot error" flag */ - out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, - in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | - CONFIG_SYS_DSPIC_TEST_MASK); - } -#endif - - /* - * Reset PHY's: - * The PHY's need a 2nd reset pulse, since the MDIO address is latched - * upon reset, and with the first reset upon powerup, the addresses are - * not latched reliable, since the IRQ line is multiplexed with an - * MDIO address. A 2nd reset at this time will make sure, that the - * correct address is latched. - */ - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); - gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); - udelay(1000); - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); - gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); - udelay(1000); - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); - gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); - - return 0; -} - -/* - * Override weak default with board specific version - */ -phys_addr_t cfi_flash_bank_addr(int bank) -{ - return lwmon5_cfi_flash_bank_addr[bank]; -} - -/* - * Override the weak default mapping function with a board specific one - */ -u32 flash_get_bank_size(int cs, int idx) -{ - return flash_info[idx].size; -} - -int board_early_init_r(void) -{ - u32 val0, val1; - - /* - * lwmon5 is manufactured in 2 different board versions: - * The lwmon5a board has 64MiB NOR flash instead of the - * 128MiB of the original lwmon5. Unfortunately the CFI driver - * will report 2 banks of 64MiB even for the smaller flash - * chip, since the bank is mirrored. To fix this, we bring - * one bank into CFI query mode and read its response. This - * enables us to detect the real number of flash devices/ - * banks which will be used later on by the common CFI driver. - */ - - /* Put bank 0 into CFI command mode and read */ - out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098); - val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP); - val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP); - - /* Reset flash again out of query mode */ - out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0); - - /* When not identical, we have 2 different flash devices/banks */ - if (val0 != val1) - return 0; - - /* - * Now we're sure that we're running on a LWMON5a board with - * only 64MiB NOR flash in one bank: - * - * Set flash base address and bank count for CFI driver probing. - */ - cfi_flash_num_flash_banks = 1; - lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0; - - return 0; -} - -int misc_init_r(void) -{ - u32 pbcr; - int size_val = 0; - u32 reg; - unsigned long usb2d0cr = 0; - unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1, sdr0_srst; - - /* - * FLASH stuff... - */ - - /* Re-do sizing to get full correct info */ - - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - mfebc(PB0CR, pbcr); - size_val = ffs(gd->bd->bi_flashsize) - 21; - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(PB0CR, pbcr); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, 0); - - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, - &flash_info[cfi_flash_num_flash_banks - 1]); - - /* Env protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, - &flash_info[cfi_flash_num_flash_banks - 1]); - - /* - * USB suff... - */ - - /* Reset USB */ - /* Reset of USB2PHY0 must be active at least 10 us */ - mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D); - udelay(2000); - - mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI | - SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 | - SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40); - udelay(2000); - - /* Errata CHIP_6 */ - - /* 1. Set internal PHY configuration */ - /* SDR Setting */ - mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB0, usb2d0cr); - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mfsdr(SDR0_USB2H0CR, usb2h0cr); - - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ - usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ - - /* - * An 8-bit/60MHz interface is the only possible alternative - * when connecting the Device to the PHY - */ - usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ - - mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB0, usb2d0cr); - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB2H0CR, usb2h0cr); - - /* 2. De-assert internal PHY reset */ - mfsdr(SDR0_SRST1, sdr0_srst); - sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY; - mtsdr(SDR0_SRST1, sdr0_srst); - - /* 3. Wait for more than 1 ms */ - udelay(2000); - - /* 4. De-assert USB 2.0 Host main reset */ - mfsdr(SDR0_SRST0, sdr0_srst); - sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H; - mtsdr(SDR0_SRST0, sdr0_srst); - udelay(1000); - - /* 5. De-assert reset of OPB2 cores */ - mfsdr(SDR0_SRST1, sdr0_srst); - sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1; - sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40; - sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2; - mtsdr(SDR0_SRST1, sdr0_srst); - udelay(1000); - - /* 6. Set EHCI Configure FLAG */ - - /* 7. Reassert internal PHY reset: */ - mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); - udelay(1000); - - /* - * Clear resets - */ - mtsdr(SDR0_SRST1, 0x00000000); - mtsdr(SDR0_SRST0, 0x00000000); - - printf("USB: Host(int phy) Device(ext phy)\n"); - - /* - * Clear PLB4A0_ACR[WRP] - * This fix will make the MAL burst disabling patch for the Linux - * EMAC driver obsolete. - */ - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; - mtdcr(PLB4A0_ACR, reg); - - /* - * Init matrix keyboard - */ - misc_init_r_kbd(); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: %s", __stringify(CONFIG_HOSTNAME)); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -void hw_watchdog_reset(void) -{ - int val; -#if defined(CONFIG_WD_MAX_RATE) - unsigned long long ct = get_ticks(); - - /* - * Don't allow watch-dog triggering more frequently than - * the predefined value CONFIG_WD_MAX_RATE [ticks]. - */ - if (ct >= gd->arch.wdt_last) { - if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE) - return; - } else { - /* Time base counter had been reset */ - if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) < - CONFIG_WD_MAX_RATE) - return; - } - gd->arch.wdt_last = get_ticks(); -#endif - - /* - * Toggle watchdog output - */ - val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0; - gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val); -} - -int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - if (argc < 2) - return cmd_usage(cmdtp); - - if ((strcmp(argv[1], "on") == 0)) - gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1); - else if ((strcmp(argv[1], "off") == 0)) - gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0); - else - return cmd_usage(cmdtp); - - return 0; -} - -U_BOOT_CMD( - eepromwp, 2, 0, do_eeprom_wp, - "eeprom write protect off/on", - "<on|off> - enable (on) or disable (off) I2C EEPROM write protect" -); - -#if defined(CONFIG_VIDEO) -#include <video_fb.h> -#include <mb862xx.h> - -extern GraphicDevice mb862xx; - -static const gdc_regs init_regs [] = { - { 0x0100, 0x00000f00 }, - { 0x0020, 0x801401df }, - { 0x0024, 0x00000000 }, - { 0x0028, 0x00000000 }, - { 0x002c, 0x00000000 }, - { 0x0110, 0x00000000 }, - { 0x0114, 0x00000000 }, - { 0x0118, 0x01df0280 }, - { 0x0004, 0x031f0000 }, - { 0x0008, 0x027f027f }, - { 0x000c, 0x015f028f }, - { 0x0010, 0x020c0000 }, - { 0x0014, 0x01df01ea }, - { 0x0018, 0x00000000 }, - { 0x001c, 0x01e00280 }, - { 0x0100, 0x80010f00 }, - { 0x0, 0x0 } -}; - -const gdc_regs *board_get_regs(void) -{ - return init_regs; -} - -/* Returns Lime base address */ -unsigned int board_video_init(void) -{ - /* - * Reset Lime controller - */ - gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); - udelay(500); - gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); - - mb862xx.winSizeX = 640; - mb862xx.winSizeY = 480; - mb862xx.gdfBytesPP = 2; - mb862xx.gdfIndex = GDF_15BIT_555RGB; - - return CONFIG_SYS_LIME_BASE_0; -} - -#define DEFAULT_BRIGHTNESS 0x64 - -static void board_backlight_brightness(int brightness) -{ - if (brightness > 0) { - /* pwm duty, lamp on */ - out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness); - out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701); - } else { - /* lamp off */ - out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00); - out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00); - } -} - -void board_backlight_switch(int flag) -{ - char * param; - int rc; - - if (flag) { - param = getenv("brightness"); - rc = param ? simple_strtol(param, NULL, 10) : -1; - if (rc < 0) - rc = DEFAULT_BRIGHTNESS; - } else { - rc = 0; - } - board_backlight_brightness(rc); -} - -#if defined(CONFIG_CONSOLE_EXTRA_INFO) -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str(int line_number, char *info) -{ - if (line_number == 1) - strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); - else - info [0] = '\0'; -} -#endif /* CONFIG_CONSOLE_EXTRA_INFO */ -#endif /* CONFIG_VIDEO */ - -void board_reset(void) -{ - gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1); -} - -#ifdef CONFIG_SPL_OS_BOOT -/* - * lwmon5 specific implementation of spl_start_uboot() - * - * RETURN - * 0 if booting into OS is selected (default) - * 1 if booting into U-Boot is selected - */ -int spl_start_uboot(void) -{ - char s[8]; - - env_init(); - getenv_f("boot_os", s, sizeof(s)); - if ((s != NULL) && (strcmp(s, "yes") == 0)) - return 0; - - return 1; -} - -/* - * This function is called from the SPL U-Boot version for - * early init stuff, that needs to be done for OS (e.g. Linux) - * booting. Doing it later in the real U-Boot would not work - * in case that the SPL U-Boot boots Linux directly. - */ -void spl_board_init(void) -{ - const gdc_regs *regs = board_get_regs(); - - /* - * Setup PFC registers, mainly for ethernet support - * later on in Linux - */ - board_early_init_f(); - - /* enable the LSB transmitter */ - gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); - - /* - * Clear resets - */ - mtsdr(SDR0_SRST1, 0x00000000); - mtsdr(SDR0_SRST0, 0x00000000); - - /* - * Reset Lime controller - */ - gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); - udelay(500); - gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); - - out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF); - udelay(300); - out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR); - - while (regs->index) { - out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) + - regs->index, regs->value); - regs++; - } - - board_backlight_brightness(DEFAULT_BRIGHTNESS); -} -#endif diff --git a/board/liebherr/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c deleted file mode 100644 index 4a65d74..0000000 --- a/board/liebherr/lwmon5/sdram.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * (C) Copyright 2007-2013 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - -#include <common.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <asm/cache.h> -#include <asm/ppc440.h> -#include <watchdog.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory - * region. Right now the cache should still be disabled in U-Boot because of the - * EMAC driver, that need it's buffer descriptor to be located in non cached - * memory. - * - * If at some time this restriction doesn't apply anymore, just define - * CONFIG_4xx_DCACHE in the board config file and this code should setup - * everything correctly. - */ -#ifdef CONFIG_4xx_DCACHE -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ -#else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ -#endif - -/*-----------------------------------------------------------------------------+ - * Prototypes - *-----------------------------------------------------------------------------*/ -extern int denali_wait_for_dlllock(void); -extern void denali_core_search_data_eye(void); -extern void dcbz_area(u32 start_address, u32 num_bytes); - -static u32 is_ecc_enabled(void) -{ - u32 val; - - mfsdram(DDR0_22, val); - val &= DDR0_22_CTRL_RAW_MASK; - if (val) - return 1; - else - return 0; -} - -void board_add_ram_info(int use_default) -{ - PPC4xx_SYS_INFO board_cfg; - u32 val; - - if (is_ecc_enabled()) - puts(" (ECC"); - else - puts(" (ECC not"); - - get_sys_info(&board_cfg); - printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000); - - mfsdram(DDR0_03, val); - val = DDR0_03_CASLAT_DECODE(val); - printf(", CL%d)", val); -} - -#ifdef CONFIG_DDR_ECC -static void wait_ddr_idle(void) -{ - /* - * Controller idle status cannot be determined for Denali - * DDR2 code. Just return here. - */ -} - -static void program_ecc(u32 start_address, - u32 num_bytes, - u32 tlb_word2_i_value) -{ - u32 val; - u32 current_addr = start_address; - u32 size; - int bytes_remaining; - - sync(); - wait_ddr_idle(); - - /* - * Because of 440EPx errata CHIP 11, we don't touch the last 256 - * bytes of SDRAM. - */ - bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE; - - /* - * We have to write the ECC bytes by zeroing and flushing in smaller - * steps, since the whole 256MByte takes too long for the external - * watchdog. - */ - while (bytes_remaining > 0) { - size = min((64 << 20), bytes_remaining); - - /* Write zero's to SDRAM */ - dcbz_area(current_addr, size); - - /* Write modified dcache lines back to memory */ - clean_dcache_range(current_addr, current_addr + size); - - current_addr += 64 << 20; - bytes_remaining -= 64 << 20; - WATCHDOG_RESET(); - } - - sync(); - wait_ddr_idle(); - - /* Clear error status */ - mfsdram(DDR0_00, val); - mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); - - /* Set 'int_mask' parameter to functionnal value */ - mfsdram(DDR0_01, val); - mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF)); - - sync(); - wait_ddr_idle(); -} -#endif - -/************************************************************************* - * - * dram_init -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -int dram_init(void) -{ - /* CL=4 */ - mtsdram(DDR0_02, 0x00000000); - - mtsdram(DDR0_00, 0x0000190A); - mtsdram(DDR0_01, 0x01000000); - mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ - - mtsdram(DDR0_04, 0x0B030300); - mtsdram(DDR0_05, 0x02020308); - mtsdram(DDR0_06, 0x0003C812); - mtsdram(DDR0_07, 0x00090100); - mtsdram(DDR0_08, 0x03c80001); - mtsdram(DDR0_09, 0x00011D5F); - mtsdram(DDR0_10, 0x00000100); - mtsdram(DDR0_11, 0x000CC800); - mtsdram(DDR0_12, 0x00000003); - mtsdram(DDR0_14, 0x00000000); - mtsdram(DDR0_17, 0x1e000000); - mtsdram(DDR0_18, 0x1e1e1e1e); - mtsdram(DDR0_19, 0x1e1e1e1e); - mtsdram(DDR0_20, 0x0B0B0B0B); - mtsdram(DDR0_21, 0x0B0B0B0B); -#ifdef CONFIG_DDR_ECC - mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ -#else - mtsdram(DDR0_22, 0x00267F0B); -#endif - - mtsdram(DDR0_23, 0x01000000); - mtsdram(DDR0_24, 0x01010001); - - mtsdram(DDR0_26, 0x2D93028A); - mtsdram(DDR0_27, 0x0784682B); - - mtsdram(DDR0_28, 0x00000080); - mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000008); - - mtsdram(DDR0_43, 0x050A0200); - mtsdram(DDR0_44, 0x00000005); - mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ - - denali_wait_for_dlllock(); - -#if defined(CONFIG_DDR_DATA_EYE) - /* -----------------------------------------------------------+ - * Perform data eye search if requested. - * ----------------------------------------------------------*/ - program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, - TLB_WORD2_I_ENABLE); - denali_core_search_data_eye(); - remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); -#endif - - /* - * Program tlb entries for this size (dynamic) - */ - program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, - MY_TLB_WORD2_I_ENABLE); - -#if defined(CONFIG_DDR_ECC) -#if defined(CONFIG_4xx_DCACHE) - /* - * If ECC is enabled, initialize the parity bits. - */ - program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0); -#else /* CONFIG_4xx_DCACHE */ - /* - * Setup 2nd TLB with same physical address but different virtual address - * with cache enabled. This is done for fast ECC generation. - */ - program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); - - /* - * If ECC is enabled, initialize the parity bits. - */ - program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); - - /* - * Now after initialization (auto-calibration and ECC generation) - * remove the TLB entries with caches enabled and program again with - * desired cache functionality - */ - remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20); -#endif /* CONFIG_4xx_DCACHE */ -#endif /* CONFIG_DDR_ECC */ - - /* - * Clear possible errors resulting from data-eye-search. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20; - - return 0; -} diff --git a/board/mosaixtech/icon/Kconfig b/board/mosaixtech/icon/Kconfig deleted file mode 100644 index 3145a06..0000000 --- a/board/mosaixtech/icon/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_ICON - -config SYS_BOARD - default "icon" - -config SYS_VENDOR - default "mosaixtech" - -config SYS_CONFIG_NAME - default "icon" - -endif diff --git a/board/mosaixtech/icon/MAINTAINERS b/board/mosaixtech/icon/MAINTAINERS deleted file mode 100644 index f3af072..0000000 --- a/board/mosaixtech/icon/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -ICON BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/mosaixtech/icon/ -F: include/configs/icon.h -F: configs/icon_defconfig diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile deleted file mode 100644 index d554a8b..0000000 --- a/board/mosaixtech/icon/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2009-2010 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := icon.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/mosaixtech/icon/chip_config.c b/board/mosaixtech/icon/chip_config.c deleted file mode 100644 index 3c5706f..0000000 --- a/board/mosaixtech/icon/chip_config.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2009-2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "400-133", "CPU: 400 PLB: 133 OPB: 66 EBC: 66", - { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "500-166", "CPU: 500 PLB: 166 OPB: 83 EBC: 83", - { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "533-133", "CPU: 533 PLB: 133 OPB: 66 EBC: 66", - { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "667-133", "CPU: 667 PLB: 133 OPB: 66 EBC: 66", - { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "667-166", "CPU: 667 PLB: 166 OPB: 83 EBC: 83", - { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 } - }, - { - "800-160", "CPU: 800 PLB: 160 OPB: 53 EBC: 17", - { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/mosaixtech/icon/config.mk b/board/mosaixtech/icon/config.mk deleted file mode 100644 index b689fd0..0000000 --- a/board/mosaixtech/icon/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2009-2010 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c deleted file mode 100644 index 7558234..0000000 --- a/board/mosaixtech/icon/icon.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * (C) Copyright 2009-2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <i2c.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <netdev.h> -#include <video.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/ppc4xx-gpio.h> -#include <asm/4xx_pcie.h> -#include <linux/errno.h> -#include <asm/mmu.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - unsigned long mfr; - - /* - * Interrupt controller setup for the ICON 440SPe board. - * - *-------------------------------------------------------------------- - * IRQ | Source | Pol. | Sensi.| Crit. - *--------+-----------------------------------+-------+-------+------- - * IRQ 00 | UART0 | High | Level | Non - * IRQ 01 | UART1 | High | Level | Non - * IRQ 02 | IIC0 | High | Level | Non - * IRQ 03 | IIC1 | High | Level | Non - * IRQ 04 | PCI0X0 MSG IN | High | Level | Non - * IRQ 05 | PCI0X0 CMD Write | High | Level | Non - * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non - * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non - * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non - * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non - * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non - * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit - * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non - * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non - * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non - * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non - * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non - * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit - * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non - * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non - * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non - * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non - * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non - * IRQ 23 | I2O Inbound Doorbell | High | Level | Non - * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non - * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non - * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non - * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non - * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non - * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non - * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non - * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. - *-------------------------------------------------------------------- - * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non - * IRQ 33 | MAL Serr | High | Level | Non - * IRQ 34 | MAL Txde | High | Level | Non - * IRQ 35 | MAL Rxde | High | Level | Non - * IRQ 36 | DMC CE or DMC UE | High | Level | Non - * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non - * IRQ 38 | MAL TX EOB | High | Level | Non - * IRQ 39 | MAL RX EOB | High | Level | Non - * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non - * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non - * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non - * IRQ 43 | L2 Cache | Risin | Edge | Non - * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non - * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non - * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non - * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non - * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non - * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non - * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non - * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non - * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non - * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non - * IRQ 54 | DMA Error | High | Level | Non - * IRQ 55 | DMA I2O Error | High | Level | Non - * IRQ 56 | Serial ROM | High | Level | Non - * IRQ 57 | PCIX0 Error | High | Edge | Non - * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non - * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non - * IRQ 60 | EMAC0 Interrupt | High | Level | Non - * IRQ 61 | EMAC0 Wake-up | High | Level | Non - * IRQ 62 | Reserved | High | Level | Non - * IRQ 63 | XOR | High | Level | Non - *-------------------------------------------------------------------- - * IRQ 64 | PE0 AL | High | Level | Non - * IRQ 65 | PE0 VPD Access | Risin | Edge | Non - * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non - * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non - * IRQ 68 | PE0 TCR | High | Level | Non - * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non - * IRQ 70 | PE0 DCR Error | High | Level | Non - * IRQ 71 | Reserved | N/A | N/A | Non - * IRQ 72 | PE1 AL | High | Level | Non - * IRQ 73 | PE1 VPD Access | Risin | Edge | Non - * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non - * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non - * IRQ 76 | PE1 TCR | High | Level | Non - * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non - * IRQ 78 | PE1 DCR Error | High | Level | Non - * IRQ 79 | Reserved | N/A | N/A | Non - * IRQ 80 | PE2 AL | High | Level | Non - * IRQ 81 | PE2 VPD Access | Risin | Edge | Non - * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non - * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non - * IRQ 84 | PE2 TCR | High | Level | Non - * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non - * IRQ 86 | PE2 DCR Error | High | Level | Non - * IRQ 87 | Reserved | N/A | N/A | Non - * IRQ 88 | External IRQ(5) | Progr | Progr | Non - * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non - * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non - * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non - * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non - * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non - * IRQ 94 | Reserved | N/A | N/A | Non - * IRQ 95 | Reserved | N/A | N/A | Non - *-------------------------------------------------------------------- - * IRQ 96 | PE0 INTA | High | Level | Non - * IRQ 97 | PE0 INTB | High | Level | Non - * IRQ 98 | PE0 INTC | High | Level | Non - * IRQ 99 | PE0 INTD | High | Level | Non - * IRQ 100| PE1 INTA | High | Level | Non - * IRQ 101| PE1 INTB | High | Level | Non - * IRQ 102| PE1 INTC | High | Level | Non - * IRQ 103| PE1 INTD | High | Level | Non - * IRQ 104| PE2 INTA | High | Level | Non - * IRQ 105| PE2 INTB | High | Level | Non - * IRQ 106| PE2 INTC | High | Level | Non - * IRQ 107| PE2 INTD | Risin | Edge | Non - * IRQ 108| PCI Express MSI Level 4 | Risin | Edge | Non - * IRQ 109| PCI Express MSI Level 5 | Risin | Edge | Non - * IRQ 110| PCI Express MSI Level 6 | Risin | Edge | Non - * IRQ 111| PCI Express MSI Level 7 | Risin | Edge | Non - * IRQ 116| PCI Express MSI Level 12 | Risin | Edge | Non - * IRQ 112| PCI Express MSI Level 8 | Risin | Edge | Non - * IRQ 113| PCI Express MSI Level 9 | Risin | Edge | Non - * IRQ 114| PCI Express MSI Level 10 | Risin | Edge | Non - * IRQ 115| PCI Express MSI Level 11 | Risin | Edge | Non - * IRQ 117| PCI Express MSI Level 13 | Risin | Edge | Non - * IRQ 118| PCI Express MSI Level 14 | Risin | Edge | Non - * IRQ 119| PCI Express MSI Level 15 | Risin | Edge | Non - * IRQ 120| PCI Express MSI Level 16 | Risin | Edge | Non - * IRQ 121| PCI Express MSI Level 17 | Risin | Edge | Non - * IRQ 122| PCI Express MSI Level 18 | Risin | Edge | Non - * IRQ 123| PCI Express MSI Level 19 | Risin | Edge | Non - * IRQ 124| PCI Express MSI Level 20 | Risin | Edge | Non - * IRQ 125| PCI Express MSI Level 21 | Risin | Edge | Non - * IRQ 126| PCI Express MSI Level 22 | Risin | Edge | Non - * IRQ 127| PCI Express MSI Level 23 | Risin | Edge | Non - */ - - /* - * Put UICs in PowerPC 440SPe mode. - * Initialise UIC registers. Clear all interrupts. Disable all - * interrupts. Set critical interrupt values. Set interrupt polarities. - * Set interrupt trigger levels. Make bit 0 High priority. Clear all - * interrupts again. - */ - mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ - mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical IRQs */ - mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ - mtdcr(UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ - mtdcr(UIC3SR, 0x00000000); /* clear all interrupts*/ - mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts*/ - - mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC2ER, 0x00000000); /* disable all interrupts*/ - mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical IRQs */ - mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ - mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ - mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ - mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ - mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ - - mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts*/ - mtdcr(UIC1ER, 0x00000000); /* disable all interrupts*/ - mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical IRQs */ - mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ - mtdcr(UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ - mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ - mtdcr(UIC1SR, 0x00000000); /* clear all interrupts*/ - mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts*/ - - mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ - mtdcr(UIC0ER, 0x00000000); /* disable all int. excepted cascade */ - mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical IRQs */ - mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ - mtdcr(UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ - mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */ - mtdcr(UIC0SR, 0x00000000); /* clear all interrupts*/ - mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts*/ - - mfsdr(SDR0_MFR, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(SDR0_MFR, mfr); - - mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); - - out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR); - out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR); - out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR); - - return 0; -} - -int board_early_init_r(void) -{ - /* - * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the - * boot EBC mapping only supports a maximum of 16MBytes - * (4.ff00.0000 - 4.ffff.ffff). - * To solve this problem, the FLASH has to get remapped to another - * EBC address which accepts bigger regions: - * - * 0xfc00.0000 -> 4.ec00.0000 - */ - - /* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */ - mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); - - /* Remove TLB entry of boot EBC mapping */ - remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); - - /* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */ - program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); - - /* - * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address - * 0xfc00.0000 is possible - */ - - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: ICON"); - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -/* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - * - * Tested successfully with the following SODIMM: - * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) - * - * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state, - * directly after power-up. Only after running for more than 10 minutes - * real stable auto-calibration windows could be found. - */ -u32 ddr_wrdtr(u32 default_val) -{ - return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV; -} - -u32 ddr_clktr(u32 default_val) -{ - return SDRAM_CLKTR_CLKP_180_DEG_ADV; -} - -/* - * Override the weak default implementation and return the - * last PCIe slot number (max number - 1). - */ -int board_pcie_last(void) -{ - /* Only 2 PCIe ports used on ICON, so the last one is 1 */ - return 1; -} - -/* - * Video - */ -#ifdef CONFIG_VIDEO_SM501 -#include <sm501.h> - -#define DISPLAY_WIDTH 640 -#define DISPLAY_HEIGHT 480 - -static const SMI_REGS sm502_init_regs[] = { - {0x00004, 0x0}, - {0x00040, 0x00021847}, - {0x00044, 0x091a0a01}, /* 24 MHz pixclk */ - {0x00054, 0x0}, - {0x00048, 0x00021847}, - {0x0004C, 0x091a0a01}, - {0x00054, 0x1}, - {0x80004, 0xc428bb17}, - {0x8000C, 0x00000000}, - {0x80010, 0x0a000a00}, - {0x80014, 0x02800000}, - {0x80018, 0x01e00000}, - {0x8001C, 0x00000000}, - {0x80020, 0x01e00280}, - {0x80024, 0x02fa027f}, - {0x80028, 0x004a0280}, - {0x8002C, 0x020c01df}, - {0x80030, 0x000201e7}, - {0x80200, 0x00010000}, - {0x00008, 0x20000000}, /* gpio29 is pwm0, LED_PWM */ - {0x0000C, 0x3f000000}, /* gpio56 - gpio61 as flat panel data pins */ - {0x10020, 0x25725728}, /* 20 kHz pwm0, 50 % duty cycle, disabled */ - {0x80000, 0x0f010106}, /* vsync & hsync pos, disp on */ - {0, 0} -}; - -/* - * Return a pointer to the register initialization table. - */ -const SMI_REGS *board_get_regs(void) -{ - return sm502_init_regs; -} - -int board_get_width(void) -{ - return DISPLAY_WIDTH; -} - -int board_get_height(void) -{ - return DISPLAY_HEIGHT; -} - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * Return text to be printed besides the logo. - */ -void video_get_info_str(int line_number, char *info) -{ - if (line_number == 1) - strcpy(info, " Board: ICON"); - else - info[0] = '\0'; -} -#endif - -#endif /* CONFIG_VIDEO_SM501 */ diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S deleted file mode 100644 index c28a3a3..0000000 --- a/board/mosaixtech/icon/init.S +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2009-2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - */ - - .section .bootpg,"ax" - - .globl tlbtab -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to - * use the speed up boot process. It is patched after relocation to - * enable SA_I. - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, - 4, AC_RWX | SA_G) /* TLB 0 */ - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, - AC_RWX | SA_I) - - tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, - AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, - CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H, - AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, - AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, - AC_RW | SA_IG) - tlbtab_end diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c deleted file mode 100644 index 31636b3..0000000 --- a/board/mpl/common/common_util.c +++ /dev/null @@ -1,677 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <video_fb.h> -#include "common_util.h" -#include <asm/processor.h> -#include <asm/byteorder.h> -#include <i2c.h> -#include <pci.h> -#include <malloc.h> -#include <bzlib.h> -#include <video.h> - -#ifdef CONFIG_PIP405 -#include "../pip405/pip405.h" -#include <asm/4xx_pci.h> -#endif -#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T) -#include "../mip405/mip405.h" -#include <asm/4xx_pci.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern int mem_test(ulong start, ulong ramsize, int quiet); - -#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ -#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN /* ugly, but it works for now */ - -#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \ - || defined(CONFIG_TARGET_MIP405T) -/*----------------------------------------------------------------------- - * On PIP/MIP405 we have 3 (4) possible boot mode - * - * - Boot from Flash (Flash CS = CS0, MPS CS = CS1) - * - Boot from MPS (Flash CS = CS1, MPS CS = CS0) - * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1) - * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0) - * The flash init is the first board specific routine which is called - * after code relocation (running from SDRAM) - * The first thing we do is to map the Flash CS to the Flash area and - * the MPS CS to the MPS area. Since the flash size is unknown at this - * point, we use the max flash size and the lowest flash address as base. - * - * After flash detection we adjust the size of the CS area accordingly. - * update_flash_size() will fix in wrong values in the flash_info structure, - * misc_init_r() will fix the values in the board info structure - */ -int get_boot_mode(void) -{ - unsigned long pbcr; - int res = 0; - pbcr = mfdcr(CPC0_PSR); - if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) - /* boot via MPS or MPS mapping */ - res = BOOT_MPS; - if (pbcr & PSR_ROM_LOC) - /* boot via PCI.. */ - res |= BOOT_PCI; - return res; -} - -/* Map the flash high (in boot area) - This code can only be executed from SDRAM (after relocation). -*/ -void setup_cs_reloc(void) -{ - int mode; - /* - * since we are relocated, we can set-up the CS finaly - * but first of all, switch off PCI mapping (in case it - * was a PCI boot) - */ - out32r(PMM0MA, 0L); - /* get boot mode */ - mode = get_boot_mode(); - /* - * we map the flash high in every case - * first find out to which CS the flash is attached to - */ - if (mode & BOOT_MPS) { - /* map flash high on CS1 and MPS on CS0 */ - mtdcr(EBC0_CFGADDR, PB0AP); - mtdcr(EBC0_CFGDATA, MPS_AP); - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, MPS_CR); - /* - * we use the default values (max values) for the flash - * because its real size is not yet known - */ - mtdcr(EBC0_CFGADDR, PB1AP); - mtdcr(EBC0_CFGDATA, FLASH_AP); - mtdcr(EBC0_CFGADDR, PB1CR); - mtdcr(EBC0_CFGDATA, FLASH_CR_B); - } else { - /* map flash high on CS0 and MPS on CS1 */ - mtdcr(EBC0_CFGADDR, PB1AP); - mtdcr(EBC0_CFGDATA, MPS_AP); - mtdcr(EBC0_CFGADDR, PB1CR); - mtdcr(EBC0_CFGDATA, MPS_CR); - /* - * we use the default values (max values) for the flash - * because its real size is not yet known - */ - mtdcr(EBC0_CFGADDR, PB0AP); - mtdcr(EBC0_CFGDATA, FLASH_AP); - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, FLASH_CR_B); - } -} -#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) */ - -#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE -/* adjust flash start and protection info */ -int update_flash_size(int flash_size) -{ - int i = 0, mode; - flash_info_t *info = &flash_info[0]; - unsigned long flashcr; - unsigned long flash_base = (0 - flash_size) & 0xFFF00000; - - if (flash_size > 128*1024*1024) { - printf("\n ### ERROR, wrong flash size: %X, reset board ###\n", - flash_size); - hang(); - } - - if ((flash_size >> 20) != 0) - i = __ilog2(flash_size >> 20); - - /* set up flash CS according to the size */ - mode = get_boot_mode(); - if (mode & BOOT_MPS) { - /* flash is on CS1 */ - mtdcr(EBC0_CFGADDR, PB1CR); - flashcr = mfdcr(EBC0_CFGDATA); - /* we map the flash high in every case */ - flashcr &= 0x0001FFFF; /* mask out address bits */ - flashcr |= flash_base; /* start addr */ - flashcr |= (i << 17); /* size addr */ - mtdcr(EBC0_CFGADDR, PB1CR); - mtdcr(EBC0_CFGDATA, flashcr); - } else { - /* flash is on CS0 */ - mtdcr(EBC0_CFGADDR, PB0CR); - flashcr = mfdcr(EBC0_CFGDATA); - /* we map the flash high in every case */ - flashcr &= 0x0001FFFF; /* mask out address bits */ - flashcr |= flash_base; /* start addr */ - flashcr |= (i << 17); /* size addr */ - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, flashcr); - } - - for (i = 0; i < info->sector_count; i++) - /* adjust sector start address */ - info->start[i] = flash_base + - (info->start[i] - CONFIG_SYS_FLASH_BASE); - - /* unprotect all sectors */ - flash_protect(FLAG_PROTECT_CLEAR, - info->start[0], - 0xFFFFFFFF, - info); - flash_protect_default(); - /* protect reset vector too*/ - flash_protect(FLAG_PROTECT_SET, - info->start[info->sector_count-1], - 0xFFFFFFFF, - info); - - return 0; -} -#endif - -static int -mpl_prg(uchar *src, ulong size) -{ - ulong start; - flash_info_t *info = &flash_info[0]; - int i, rc; -#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) || \ - defined(CONFIG_TARGET_MIP405T) - char *copystr = (char *)src; - ulong *magic = (ulong *)src; - - if (uimage_to_cpu (magic[0]) != IH_MAGIC) { - puts("Bad Magic number\n"); - return -1; - } - /* some more checks before we delete the Flash... */ - /* Checking the ISO_STRING prevents to program a - * wrong Firmware Image into the flash. - */ - i = 4; /* skip Magic number */ - while (1) { - if (strncmp(©str[i], "MEV-", 4) == 0) - break; - if (i++ >= 0x100) { - puts("Firmware Image for unknown Target\n"); - return -1; - } - } - /* we have the ISO STRING, check */ - if (strncmp(©str[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) { - printf("Wrong Firmware Image: %s\n", ©str[i]); - return -1; - } - start = 0 - size; - - /* unprotect sectors used by u-boot */ - flash_protect(FLAG_PROTECT_CLEAR, - start, - 0xFFFFFFFF, - info); - - /* search start sector */ - for (i = info->sector_count-1; i > 0; i--) - if (start >= info->start[i]) - break; - - /* now erase flash */ - printf("Erasing at %lx (sector %d) (start %lx)\n", - start,i,info->start[i]); - if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) { - puts("ERROR "); - flash_perror(rc); - return (1); - } -#endif - printf("flash erased, programming from 0x%lx 0x%lx Bytes\n", - (ulong)src, size); - if ((rc = flash_write ((char *)src, start, size)) != 0) { - puts("ERROR "); - flash_perror(rc); - return (1); - } - puts("OK programming done\n"); - return 0; -} - - -static int -mpl_prg_image(uchar *ld_addr) -{ - unsigned long len; - uchar *data; - image_header_t *hdr = (image_header_t *)ld_addr; - int rc; - -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if (!image_check_magic (hdr)) { - puts("Bad Magic Number\n"); - return 1; - } - image_print_contents (hdr); - if (!image_check_os (hdr, IH_OS_U_BOOT)) { - puts("No U-Boot Image\n"); - return 1; - } - if (!image_check_type (hdr, IH_TYPE_FIRMWARE)) { - puts("No Firmware Image\n"); - return 1; - } - if (!image_check_hcrc (hdr)) { - puts("Bad Header Checksum\n"); - return 1; - } - puts("Verifying Checksum ... "); - if (!image_check_dcrc (hdr)) { - puts("Bad Data CRC\n"); - return 1; - } - puts("OK\n"); - - data = (uchar *)image_get_data (hdr); - len = image_get_data_size (hdr); - - if (image_get_comp (hdr) != IH_COMP_NONE) { - uchar *buf; - /* reserve space for uncompressed image */ - if ((buf = malloc(IMAGE_SIZE)) == NULL) { - puts("Insufficient space for decompression\n"); - return 1; - } - - switch (image_get_comp (hdr)) { - case IH_COMP_GZIP: - puts("Uncompressing (GZIP) ... "); - rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len); - if (rc != 0) { - puts("GUNZIP ERROR\n"); - free(buf); - return 1; - } - puts("OK\n"); - break; -#ifdef CONFIG_BZIP2 - case IH_COMP_BZIP2: - puts("Uncompressing (BZIP2) ... "); - { - uint retlen = IMAGE_SIZE; - rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen, - (char *)data, len, 0, 0); - len = retlen; - } - if (rc != BZ_OK) { - printf ("BUNZIP2 ERROR: %d\n", rc); - free(buf); - return 1; - } - puts("OK\n"); - break; -#endif - default: - printf ("Unimplemented compression type %d\n", - image_get_comp (hdr)); - free(buf); - return 1; - } - - rc = mpl_prg(buf, len); - free(buf); - } else { - rc = mpl_prg(data, len); - } - - return(rc); -} - -void get_backup_values(backup_t *buf) -{ - i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); -} - -void set_backup_values(int overwrite) -{ - backup_t back; - int i; - - get_backup_values(&back); - if(!overwrite) { - if(strncmp(back.signature,"MPL\0",4)==0) { - puts("Not possible to write Backup\n"); - return; - } - } - memcpy(back.signature,"MPL\0",4); - i = getenv_f("serial#",back.serial_name,16); - if(i < 0) { - puts("Not possible to write Backup\n"); - return; - } - back.serial_name[16]=0; - i = getenv_f("ethaddr",back.eth_addr,20); - if(i < 0) { - puts("Not possible to write Backup\n"); - return; - } - back.eth_addr[20]=0; - i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); -} - -void clear_env_values(void) -{ - backup_t back; - unsigned char env_crc[4]; - - memset(&back,0xff,sizeof(backup_t)); - memset(env_crc,0x00,4); - i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); - i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4); -} - -/* - * check crc of "older" environment - */ -int check_env_old_size(ulong oldsize) -{ - ulong crc, len, new; - unsigned off; - uchar buf[64]; - - /* read old CRC */ - eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, - CONFIG_ENV_OFFSET, - (uchar *)&crc, sizeof(ulong)); - - new = 0; - len = oldsize; - off = sizeof(long); - len = oldsize-off; - while (len > 0) { - int n = (len > sizeof(buf)) ? sizeof(buf) : len; - - eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n); - new = crc32 (new, buf, n); - len -= n; - off += n; - } - - return (crc == new); -} - -static ulong oldsizes[] = { - 0x200, - 0x800, - 0 -}; - -void copy_old_env(ulong size) -{ - uchar name_buf[64]; - uchar value_buf[0x800]; - uchar c; - ulong len; - unsigned off; - uchar *name, *value; - - name = &name_buf[0]; - value = &value_buf[0]; - len=size; - off = sizeof(long); - while (len > off) { - eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1); - if(c != '=') { - *name++=c; - off++; - } - else { - *name++='\0'; - off++; - do { - eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1); - *value++=c; - off++; - if(c == '\0') - break; - } while(len > off); - name = &name_buf[0]; - value = &value_buf[0]; - if(strncmp((char *)name,"baudrate",8)!=0) { - setenv((char *)name,(char *)value); - } - - } - } -} - - -void check_env(void) -{ - char *s; - int i=0; - char buf[32]; - backup_t back; - - s=getenv("serial#"); - if(!s) { - while(oldsizes[i]) { - if(check_env_old_size(oldsizes[i])) - break; - i++; - } - if(!oldsizes[i]) { - /* no old environment has been found */ - get_backup_values (&back); - if (strncmp (back.signature, "MPL\0", 4) == 0) { - sprintf (buf, "%s", back.serial_name); - setenv ("serial#", buf); - sprintf (buf, "%s", back.eth_addr); - setenv ("ethaddr", buf); - printf ("INFO: serial# and ethaddr recovered, use saveenv\n"); - return; - } - } - else { - copy_old_env(oldsizes[i]); - puts("INFO: old environment ajusted, use saveenv\n"); - } - } - else { - /* check if back up is set */ - get_backup_values(&back); - if(strncmp(back.signature,"MPL\0",4)!=0) { - set_backup_values(0); - } - } -} - -int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong ld_addr; - int result; - ulong size = IMAGE_SIZE; - ulong src = MULTI_PURPOSE_SOCKET_ADDR; - backup_t back; - - if (strcmp(argv[1], "flash") == 0) - { -#if defined(CONFIG_CMD_FDC) - if (strcmp(argv[2], "floppy") == 0) { - char *local_args[3]; - extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]); - puts("\nupdating bootloader image from floppy\n"); - local_args[0] = argv[0]; - if(argc==4) { - local_args[1] = argv[3]; - local_args[2] = NULL; - ld_addr=simple_strtoul(argv[3], NULL, 16); - result=do_fdcboot(cmdtp, 0, 2, local_args); - } - else { - local_args[1] = NULL; - ld_addr=CONFIG_SYS_LOAD_ADDR; - result=do_fdcboot(cmdtp, 0, 1, local_args); - } - result=mpl_prg_image((uchar *)ld_addr); - return result; - } -#endif - if (strcmp(argv[2], "mem") == 0) { - if(argc==4) { - ld_addr=simple_strtoul(argv[3], NULL, 16); - } - else { - ld_addr=load_addr; - } - printf ("\nupdating bootloader image from memory at %lX\n",ld_addr); - result=mpl_prg_image((uchar *)ld_addr); - return result; - } - if (strcmp(argv[2], "mps") == 0) { - puts("\nupdating bootloader image from MPS\n"); - result=mpl_prg((uchar *)src,size); - return result; - } - } - if (strcmp(argv[1], "clearenvvalues") == 0) - { - if (strcmp(argv[2], "yes") == 0) - { - clear_env_values(); - return 0; - } - } - if (strcmp(argv[1], "getback") == 0) { - get_backup_values(&back); - back.signature[3]=0; - back.serial_name[16]=0; - back.eth_addr[20]=0; - printf("GetBackUp: signature: %s\n",back.signature); - printf(" serial#: %s\n",back.serial_name); - printf(" ethaddr: %s\n",back.eth_addr); - return 0; - } - if (strcmp(argv[1], "setback") == 0) { - set_backup_values(1); - return 0; - } - return cmd_usage(cmdtp); -} - -#ifdef CONFIG_VIDEO -/****************************************************** - * Routines to display the Board information - * to the screen (since the VGA will be initialized as last, - * we must resend the infos) - */ - -#ifdef CONFIG_CONSOLE_EXTRA_INFO -extern GraphicDevice ctfb; -extern int get_boot_mode(void); - -void video_get_info_str (int line_number, char *info) -{ - /* init video info strings for graphic console */ - PPC4xx_SYS_INFO sys_info; - char rev; - int i,boot; - unsigned long pvr; - char buf[64]; - char buf1[32], buf2[32], buf3[32], buf4[32]; - char cpustr[16]; - char *s, *e, bc; - switch (line_number) - { - case 2: - /* CPU and board infos */ - pvr=get_pvr(); - get_sys_info (&sys_info); - switch (pvr) { - case PVR_405GP_RB: rev='B'; break; - case PVR_405GP_RC: rev='C'; break; - case PVR_405GP_RD: rev='D'; break; - case PVR_405GP_RE: rev='E'; break; - case PVR_405GPR_RB: rev='B'; break; - default: rev='?'; break; - } - if(pvr==PVR_405GPR_RB) - sprintf(cpustr,"PPC405GPr %c",rev); - else - sprintf(cpustr,"PPC405GP %c",rev); - /* Board info */ - i=0; - s=getenv ("serial#"); -#ifdef CONFIG_PIP405 - if (!s || strncmp (s, "PIP405", 6)) { - strcpy(buf,"### No HW ID - assuming PIP405"); - } -#endif -#if defined(CONFIG_TARGET_MIP405) || defined(CONFIG_TARGET_MIP405T) - if (!s || strncmp (s, "MIP405", 6)) { - strcpy(buf,"### No HW ID - assuming MIP405"); - } -#endif - else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - for (; s < e; ++s) { - if (*s == '_') { - ++s; - break; - } - buf[i++] = *s; - } - strcpy(&buf[i]," SN "); - i+=4; - for (; s < e; ++s) { - buf[i++] = *s; - } - buf[i++]=0; - } - sprintf (info," %s %s %s MHz (%s/%s/%s MHz)", - buf, cpustr, - strmhz (buf1, gd->cpu_clk), - strmhz (buf2, sys_info.freqPLB), - strmhz (buf3, sys_info.freqPLB / sys_info.pllOpbDiv), - strmhz (buf4, sys_info.freqPLB / sys_info.pllExtBusDiv)); - return; - case 3: - /* Memory Info */ - boot = get_boot_mode(); - bc = in8 (CONFIG_PORT_ADDR); - sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s", - gd->bd->bi_memsize / 0x100000, - gd->bd->bi_flashsize / 0x100000, - bc, - (boot & BOOT_MPS) ? "MPS boot" : "Flash boot", - ctfb.modeIdent); - return; - case 1: - strcpy(buf, CONFIG_IDENT_STRING); - sprintf (info, " %s", &buf[1]); - return; - } - /* no more info lines */ - *info = 0; - return; -} -#endif /* CONFIG_CONSOLE_EXTRA_INFO */ - -#endif /* CONFIG_VIDEO */ diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h deleted file mode 100644 index 127853d..0000000 --- a/board/mpl/common/common_util.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _COMMON_UTIL_H_ -#define _COMMON_UTIL_H_ - -typedef struct { - char signature[4]; - char serial_name[17]; /* "MIP405_1000xxxxx" */ - char eth_addr[21]; /* "00:60:C2:0a:00:00" */ -} backup_t; - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -void get_backup_values(backup_t *buf); - -#define BOOT_MPS 0x01 -#define BOOT_PCI 0x02 -int get_boot_mode(void); -void setup_cs_reloc(void); - -void check_env(void); - -#endif /* _COMMON_UTIL_H_ */ diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c deleted file mode 100644 index 54ec66b..0000000 --- a/board/mpl/common/isa.c +++ /dev/null @@ -1,470 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * SPDX-License-Identifier: GPL-2.0+ - * - * TODO: clean-up - */ - -#include <common.h> -#include <asm/processor.h> -#include <stdio_dev.h> -#include "isa.h" -#include "piix4_pci.h" -#include "kbd.h" -#include "video.h" - - -#undef ISA_DEBUG - -#ifdef ISA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#if defined(CONFIG_PIP405) - -extern int drv_isa_kbd_init (void); - -/* fdc (logical device 0) */ -const SIO_LOGDEV_TABLE sio_fdc[] = { - {0x60, 3}, /* set IO to FDPort (3F0) */ - {0x61, 0xF0}, /* set IO to FDPort (3F0) */ - {0x70, 06}, /* set IRQ 6 for FDPort */ - {0x74, 02}, /* set DMA 2 for FDPort */ - {0xF0, 0x05}, /* set to PS2 type */ - {0xF1, 0x00}, /* default value */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; -/* paralell port (logical device 3) */ -const SIO_LOGDEV_TABLE sio_pport[] = { - {0x60, 3}, /* set IO to PPort (378) */ - {0x61, 0x78}, /* set IO to PPort (378) */ - {0x70, 07}, /* set IRQ 7 for PPort */ - {0xF1, 00}, /* set PPort to normal */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; -/* paralell port (logical device 3) Floppy assigned to lpt */ -const SIO_LOGDEV_TABLE sio_pport_fdc[] = { - {0x60, 3}, /* set IO to PPort (378) */ - {0x61, 0x78}, /* set IO to PPort (378) */ - {0x70, 07}, /* set IRQ 7 for PPort */ - {0xF1, 02}, /* set PPort to Floppy */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; -/* uart 1 (logical device 4) */ -const SIO_LOGDEV_TABLE sio_com1[] = { - {0x60, 3}, /* set IO to COM1 (3F8) */ - {0x61, 0xF8}, /* set IO to COM1 (3F8) */ - {0x70, 04}, /* set IRQ 4 for COM1 */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; -/* uart 2 (logical device 5) */ -const SIO_LOGDEV_TABLE sio_com2[] = { - {0x60, 2}, /* set IO to COM2 (2F8) */ - {0x61, 0xF8}, /* set IO to COM2 (2F8) */ - {0x70, 03}, /* set IRQ 3 for COM2 */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; - -/* keyboard controller (logical device 7) */ -const SIO_LOGDEV_TABLE sio_keyboard[] = { - {0x70, 1}, /* set IRQ 1 for keyboard */ - {0x72, 12}, /* set IRQ 12 for mouse */ - {0xF0, 0}, /* disable Port92 (this is a PowerPC!!) */ - {0x30, 1}, /* and activate the device */ - {0xFF, 0} /* end of device table */ -}; - - -/******************************************************************************* -* Config SuperIO FDC37C672 -********************************************************************************/ -unsigned char open_cfg_super_IO(int address) -{ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */ - if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */ - return true; - else - return false; -} - -void close_cfg_super_IO(int address) -{ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */ -} - - -unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr) -{ - /* assuming config reg is open */ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ - return in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1); -} - -void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data) -{ - /* assuming config reg is open */ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */ -} - -void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev) -{ - while (ldt->index != 0xFF) { - write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val); - ldt++; - } /* endwhile */ -} - -void isa_sio_loadtable(void) -{ - char *s = getenv("floppy"); - /* setup Floppy device 0*/ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0); - /* setup parallel port device 3 */ - if(s && !strncmp(s, "lpt", 3)) { - printf("SIO: Floppy assigned to LPT\n"); - /* floppy is assigned to the LPT */ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3); - } - else { - /*printf("Floppy assigned to internal port\n");*/ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3); - } - /* setup Com1 port device 4 */ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4); - /* setup Com2 port device 5 */ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5); - /* setup keyboards device 7 */ - isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7); -} - - -void isa_sio_setup(void) -{ - if (open_cfg_super_IO(SIO_CFG_PORT) == true) - { - isa_sio_loadtable(); - close_cfg_super_IO(0x3F0); - } -} -#endif - -/****************************************************************************** - * IRQ Controller - * we use the Vector mode - */ - -struct isa_irq_action { - interrupt_handler_t *handler; - void *arg; - int count; -}; - -static struct isa_irq_action isa_irqs[16]; - - -/* - * This contains the irq mask for both 8259A irq controllers, - */ -static unsigned int cached_irq_mask = 0xfff9; - -#define cached_imr1 (unsigned char)cached_irq_mask -#define cached_imr2 (unsigned char)(cached_irq_mask>>8) -#define IMR_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1 -#define IMR_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1 -#define ICW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1 -#define ICW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1 -#define ICW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2 -#define ICW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2 -#define ICW3_1 ICW2_1 -#define ICW3_2 ICW2_2 -#define ICW4_1 ICW2_1 -#define ICW4_2 ICW2_2 -#define ISR_1 ICW1_1 -#define ISR_2 ICW1_2 - - -void disable_8259A_irq(unsigned int irq) -{ - unsigned int mask = 1 << irq; - - cached_irq_mask |= mask; - if (irq & 8) - out8(IMR_2,cached_imr2); - else - out8(IMR_1,cached_imr1); -} - -void enable_8259A_irq(unsigned int irq) -{ - unsigned int mask = ~(1 << irq); - - cached_irq_mask &= mask; - if (irq & 8) - out8(IMR_2,cached_imr2); - else - out8(IMR_1,cached_imr1); -} -/* -int i8259A_irq_pending(unsigned int irq) -{ - unsigned int mask = 1<<irq; - int ret; - - if (irq < 8) - ret = inb(0x20) & mask; - else - ret = inb(0xA0) & (mask >> 8); - spin_unlock_irqrestore(&i8259A_lock, flags); - - return ret; -} -*/ - -/* - * This function assumes to be called rarely. Switching between - * 8259A registers is slow. - */ -int i8259A_irq_real(unsigned int irq) -{ - int value; - int irqmask = 1<<irq; - - if (irq < 8) { - out8(ISR_1,0x0B); /* ISR register */ - value = in8(ISR_1) & irqmask; - out8(ISR_1,0x0A); /* back to the IRR register */ - return value; - } - out8(ISR_2,0x0B); /* ISR register */ - value = in8(ISR_2) & (irqmask >> 8); - out8(ISR_2,0x0A); /* back to the IRR register */ - return value; -} - -/* - * Careful! The 8259A is a fragile beast, it pretty - * much _has_ to be done exactly like this (mask it - * first, _then_ send the EOI, and the order of EOI - * to the two 8259s is important! - */ -void mask_and_ack_8259A(unsigned int irq) -{ - unsigned int irqmask = 1 << irq; - unsigned int temp_irqmask = cached_irq_mask; - /* - * Lightweight spurious IRQ detection. We do not want - * to overdo spurious IRQ handling - it's usually a sign - * of hardware problems, so we only do the checks we can - * do without slowing down good hardware unnecesserily. - * - * Note that IRQ7 and IRQ15 (the two spurious IRQs - * usually resulting from the 8259A-1|2 PICs) occur - * even if the IRQ is masked in the 8259A. Thus we - * can check spurious 8259A IRQs without doing the - * quite slow i8259A_irq_real() call for every IRQ. - * This does not cover 100% of spurious interrupts, - * but should be enough to warn the user that there - * is something bad going on ... - */ - if (temp_irqmask & irqmask) - goto spurious_8259A_irq; - temp_irqmask |= irqmask; - -handle_real_irq: - if (irq & 8) { - in8(IMR_2); /* DUMMY - (do we need this?) */ - out8(IMR_2,(unsigned char)(temp_irqmask>>8)); - out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */ - out8(ISR_1,0x62); /* 'Specific EOI' to master-IRQ2 */ - out8(IMR_2,cached_imr2); /* turn it on again */ - } else { - in8(IMR_1); /* DUMMY - (do we need this?) */ - out8(IMR_1,(unsigned char)temp_irqmask); - out8(ISR_1,0x60+irq); /* 'Specific EOI' to master */ - out8(IMR_1,cached_imr1); /* turn it on again */ - } - - return; - -spurious_8259A_irq: - /* - * this is the slow path - should happen rarely. - */ - if (i8259A_irq_real(irq)) - /* - * oops, the IRQ _is_ in service according to the - * 8259A - not spurious, go handle it. - */ - goto handle_real_irq; - - { - static int spurious_irq_mask; - /* - * At this point we can be sure the IRQ is spurious, - * lets ACK and report it. [once per IRQ] - */ - if (!(spurious_irq_mask & irqmask)) { - PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq); - spurious_irq_mask |= irqmask; - } - /* irq_err_count++; */ - /* - * Theoretically we do not have to handle this IRQ, - * but in Linux this does not cause problems and is - * simpler for us. - */ - goto handle_real_irq; - } -} - -void init_8259A(void) -{ - out8(IMR_1,0xff); /* mask all of 8259A-1 */ - out8(IMR_2,0xff); /* mask all of 8259A-2 */ - - out8(ICW1_1,0x11); /* ICW1: select 8259A-1 init */ - out8(ICW2_1,0x20 + 0); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */ - out8(ICW3_1,0x04); /* 8259A-1 (the master) has a slave on IR2 */ - out8(ICW4_1,0x01); /* master expects normal EOI */ - out8(ICW1_2,0x11); /* ICW2: select 8259A-2 init */ - out8(ICW2_2,0x20 + 8); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */ - out8(ICW3_2,0x02); /* 8259A-2 is a slave on master's IR2 */ - out8(ICW4_2,0x01); /* (slave's support for AEOI in flat mode - is to be investigated) */ - udelay(10000); /* wait for 8259A to initialize */ - out8(IMR_1,cached_imr1); /* restore master IRQ mask */ - udelay(10000); /* wait for 8259A to initialize */ - out8(IMR_2,cached_imr2); /* restore slave IRQ mask */ -} - - -#define PCI_INT_ACK_ADDR 0xEED00000 - -int handle_isa_int(void) -{ - unsigned long irqack; - unsigned char irq; - /* first we acknokledge the int via the PCI bus */ - irqack=in32(PCI_INT_ACK_ADDR); - /* now we get the ISRs */ - in8(ISR_2); - in8(ISR_1); - irq=(unsigned char)irqack; - irq-=32; -/* if((irq==7)&&((isr1&0x80)==0)) { - PRINTF("IRQ7 detected but not in ISR\n"); - } - else { -*/ /* we should handle cascaded interrupts here also */ - { -/* printf("ISA Irq %d\n",irq); */ - isa_irqs[irq].count++; - if(irq!=2) { /* just swallow the cascade irq 2 */ - if (isa_irqs[irq].handler != NULL) - (*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */ - else { - PRINTF ("bogus interrupt vector 0x%x\n", irq); - } - } - } - /* issue EOI instruction to clear the IRQ */ - mask_and_ack_8259A(irq); - return 0; -} - - -/****************************************************************** - * Install and free an ISA interrupt handler. - */ - -void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) -{ - if (isa_irqs[vec].handler != NULL) { - printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n", - vec, (uint)handler, (uint)isa_irqs[vec].handler); - } - isa_irqs[vec].handler = handler; - isa_irqs[vec].arg = arg; - enable_8259A_irq(vec); - PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask); - -} - -void isa_irq_free_handler(int vec) -{ - disable_8259A_irq(vec); - isa_irqs[vec].handler = NULL; - isa_irqs[vec].arg = NULL; - PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask); - -} - -/****************************************************************************/ -void isa_init_irq_contr(void) -{ - int i; - /* disable all Interrupts */ - /* first write icws controller 1 */ - for(i=0;i<16;i++) - { - isa_irqs[i].handler=NULL; - isa_irqs[i].arg=NULL; - isa_irqs[i].count=0; - } - init_8259A(); - out8(IMR_2,0xFF); -} -/*************************************************************************/ - -void isa_show_irq(void) -{ - int vec; - - printf ("\nISA Interrupt-Information:\n"); - printf ("Nr Routine Arg Count\n"); - - for (vec=0; vec<16; vec++) { - if (isa_irqs[vec].handler != NULL) { - printf ("%02d %08lx %08lx %d\n", - vec, - (ulong)isa_irqs[vec].handler, - (ulong)isa_irqs[vec].arg, - isa_irqs[vec].count); - } - } -} - -int isa_irq_get_count(int vec) -{ - return(isa_irqs[vec].count); -} - -/****************************************************************** - * Init the ISA bus and devices. - */ - -#if defined(CONFIG_PIP405) - -int isa_init(void) -{ - isa_sio_setup(); - isa_init_irq_contr(); - drv_isa_kbd_init(); - return 0; -} -#endif diff --git a/board/mpl/common/isa.h b/board/mpl/common/isa.h deleted file mode 100644 index c706d67..0000000 --- a/board/mpl/common/isa.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ISA_H_ -#define _ISA_H_ -/* Super IO */ -#define SIO_CFG_PORT 0x3F0 /* Config Port Address */ - -#if defined(CONFIG_PIP405) -/* table fore SIO initialization */ -typedef struct { - const uchar index; - const uchar val; -} SIO_LOGDEV_TABLE; - -typedef struct { - const uchar ldev; - const SIO_LOGDEV_TABLE *ldev_table; -} SIO_TABLE; - - -unsigned char open_cfg_super_IO(int address); -unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr); -void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data); -void close_cfg_super_IO(int address); -void isa_sio_setup(void); -#endif - -void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg); -void isa_irq_free_handler(int vec); -int handle_isa_int(void); -void isa_init_irq_contr(void); -void isa_show_irq(void); -int isa_irq_get_count(int vec); - - -#endif diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c deleted file mode 100644 index 36b1694..0000000 --- a/board/mpl/common/kbd.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Source partly derived from: - * linux/drivers/char/pc_keyb.c - */ -#include <common.h> -#include <console.h> -#include <asm/processor.h> -#include <stdio_dev.h> -#include "isa.h" -#include "kbd.h" - - -unsigned char kbd_read_status(void); -unsigned char kbd_read_input(void); -void kbd_send_data(unsigned char data); -void disable_8259A_irq(unsigned int irq); -void enable_8259A_irq(unsigned int irq); - -/* used only by send_data - set by keyboard_interrupt */ - - -#undef KBG_DEBUG - -#ifdef KBG_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - -#define KBD_STAT_KOBF 0x01 -#define KBD_STAT_IBF 0x02 -#define KBD_STAT_SYS 0x04 -#define KBD_STAT_CD 0x08 -#define KBD_STAT_LOCK 0x10 -#define KBD_STAT_MOBF 0x20 -#define KBD_STAT_TI_OUT 0x40 -#define KBD_STAT_PARERR 0x80 - -#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */ -#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */ -#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */ -/* - * Keyboard Controller Commands - */ - -#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ -#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ -#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ -#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ -#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ -#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ -#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ -#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ -#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ -#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ -#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if - initiated by the auxiliary device */ -#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ - -/* - * Keyboard Commands - */ - -#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ -#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ -#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ -#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ -#define KBD_CMD_RESET 0xFF /* Reset */ - -/* - * Keyboard Replies - */ - -#define KBD_REPLY_POR 0xAA /* Power on reset */ -#define KBD_REPLY_ACK 0xFA /* Command ACK */ -#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ - -/* - * Status Register Bits - */ - -#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ -#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ -#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ -#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ -#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ -#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ -#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ -#define KBD_STAT_PERR 0x80 /* Parity error */ - -#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF) - -/* - * Controller Mode Register Bits - */ - -#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ -#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ -#define KBD_MODE_SYS 0x04 /* The system flag (?) */ -#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ -#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ -#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ -#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ -#define KBD_MODE_RFU 0x80 - - -#define KDB_DATA_PORT 0x60 -#define KDB_COMMAND_PORT 0x64 - -#define LED_SCR 0x01 /* scroll lock led */ -#define LED_CAP 0x04 /* caps lock led */ -#define LED_NUM 0x02 /* num lock led */ - -#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ - - -static volatile char kbd_buffer[KBD_BUFFER_LEN]; -static volatile int in_pointer = 0; -static volatile int out_pointer = 0; - - -static unsigned char num_lock = 0; -static unsigned char caps_lock = 0; -static unsigned char scroll_lock = 0; -static unsigned char shift = 0; -static unsigned char ctrl = 0; -static unsigned char alt = 0; -static unsigned char e0 = 0; -static unsigned char leds = 0; - -#define DEVNAME "kbd" - -/* Simple translation table for the keys */ - -static unsigned char kbd_plain_xlate[] = { - 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */ - 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ - 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -static unsigned char kbd_shift_xlate[] = { - 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */ - 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */ - 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */ - 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -static unsigned char kbd_ctrl_xlate[] = { - 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */ - 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */ - 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */ - 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ - '\r',0xff,0xff - }; - -/****************************************************************** - * Init - ******************************************************************/ -int isa_kbd_init(void) -{ - char* result; - result=kbd_initialize(); - if(result==NULL) { - PRINTF("AT Keyboard initialized\n"); - irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL); - isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL); - return (1); - } else { - printf("%s\n",result); - return (-1); - } -} - -#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -extern int overwrite_console (void); -#else -int overwrite_console (void) -{ - return (0); -} -#endif - -int drv_isa_kbd_init (void) -{ - int error; - struct stdio_dev kbddev ; - char *stdinname = getenv ("stdin"); - - if(isa_kbd_init()==-1) - return -1; - memset (&kbddev, 0, sizeof(kbddev)); - strcpy(kbddev.name, DEVNAME); - kbddev.flags = DEV_FLAGS_INPUT; - kbddev.getc = kbd_getc ; - kbddev.tstc = kbd_testc ; - - error = stdio_register (&kbddev); - if(error==0) { - /* check if this is the standard input device */ - if(strcmp(stdinname,DEVNAME)==0) { - /* reassign the console */ - if(overwrite_console()) { - return 1; - } - error=console_assign(stdin,DEVNAME); - if(error==0) - return 1; - else - return error; - } - return 1; - } - return error; -} - -/****************************************************************** - * Queue handling - ******************************************************************/ -/* puts character in the queue and sets up the in and out pointer */ -void kbd_put_queue(char data) -{ - if((in_pointer+1)==KBD_BUFFER_LEN) { - if(out_pointer==0) { - return; /* buffer full */ - } else{ - in_pointer=0; - } - } else { - if((in_pointer+1)==out_pointer) - return; /* buffer full */ - in_pointer++; - } - kbd_buffer[in_pointer]=data; - return; -} - -/* test if a character is in the queue */ -int kbd_testc(struct stdio_dev *dev) -{ - if(in_pointer==out_pointer) - return(0); /* no data */ - else - return(1); -} -/* gets the character from the queue */ -int kbd_getc(struct stdio_dev *dev) -{ - char c; - while(in_pointer==out_pointer); - if((out_pointer+1)==KBD_BUFFER_LEN) - out_pointer=0; - else - out_pointer++; - c=kbd_buffer[out_pointer]; - return (int)c; - -} - - -/* set LEDs */ - -void kbd_set_leds(void) -{ - if(caps_lock==0) - leds&=~LED_CAP; /* switch caps_lock off */ - else - leds|=LED_CAP; /* switch on LED */ - if(num_lock==0) - leds&=~LED_NUM; /* switch LED off */ - else - leds|=LED_NUM; /* switch on LED */ - if(scroll_lock==0) - leds&=~LED_SCR; /* switch LED off */ - else - leds|=LED_SCR; /* switch on LED */ - kbd_send_data(KBD_CMD_SET_LEDS); - kbd_send_data(leds); -} - - -void handle_keyboard_event (unsigned char scancode) -{ - unsigned char keycode; - - /* Convert scancode to keycode */ - PRINTF ("scancode %x\n", scancode); - if (scancode == 0xe0) { - e0 = 1; /* special charakters */ - return; - } - if (e0 == 1) { - e0 = 0; /* delete flag */ - if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */ - ((scancode & 0x7F) == 0x1D) || /* the right alt key */ - ((scancode & 0x7F) == 0x35) || /* the right '/' key */ - ((scancode & 0x7F) == 0x1C))) - /* the right enter key */ - /* we swallow unknown e0 codes */ - return; - } - /* special cntrl keys */ - switch (scancode) { - case 0x2A: - case 0x36: /* shift pressed */ - shift = 1; - return; /* do nothing else */ - case 0xAA: - case 0xB6: /* shift released */ - shift = 0; - return; /* do nothing else */ - case 0x38: /* alt pressed */ - alt = 1; - return; /* do nothing else */ - case 0xB8: /* alt released */ - alt = 0; - return; /* do nothing else */ - case 0x1d: /* ctrl pressed */ - ctrl = 1; - return; /* do nothing else */ - case 0x9d: /* ctrl released */ - ctrl = 0; - return; /* do nothing else */ - case 0x46: /* scrollock pressed */ - scroll_lock = ~scroll_lock; - kbd_set_leds (); - return; /* do nothing else */ - case 0x3A: /* capslock pressed */ - caps_lock = ~caps_lock; - kbd_set_leds (); - return; - case 0x45: /* numlock pressed */ - num_lock = ~num_lock; - kbd_set_leds (); - return; - case 0xC6: /* scroll lock released */ - case 0xC5: /* num lock released */ - case 0xBA: /* caps lock released */ - return; /* just swallow */ - } - if ((scancode & 0x80) == 0x80) /* key released */ - return; - /* now, decide which table we need */ - if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown scancode %X\n", scancode); - return; /* swallow it */ - } - /* setup plain code first */ - keycode = kbd_plain_xlate[scancode]; - if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */ - if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown caps-locked scancode %X\n", scancode); - return; /* swallow it */ - } - keycode = kbd_shift_xlate[scancode]; - if (keycode < 'A') { /* we only want the alphas capital */ - keycode = kbd_plain_xlate[scancode]; - } - } - if (shift == 1) { /* shift overwrites caps_lock */ - if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown shifted scancode %X\n", scancode); - return; /* swallow it */ - } - keycode = kbd_shift_xlate[scancode]; - } - if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */ - if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown ctrl scancode %X\n", scancode); - return; /* swallow it */ - } - keycode = kbd_ctrl_xlate[scancode]; - } - /* check if valid keycode */ - if (keycode == 0xff) { - PRINTF ("unkown scancode %X\n", scancode); - return; /* swallow unknown codes */ - } - - kbd_put_queue (keycode); - PRINTF ("%x\n", keycode); -} - -/* - * This reads the keyboard status port, and does the - * appropriate action. - * - */ -unsigned char handle_kbd_event(void) -{ - unsigned char status = kbd_read_status(); - unsigned int work = 10000; - - while ((--work > 0) && (status & KBD_STAT_OBF)) { - unsigned char scancode; - - scancode = kbd_read_input(); - - /* Error bytes must be ignored to make the - Synaptics touchpads compaq use work */ - /* Ignore error bytes */ - if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) - { - if (status & KBD_STAT_MOUSE_OBF) - ; /* not supported: handle_mouse_event(scancode); */ - else - handle_keyboard_event(scancode); - } - status = kbd_read_status(); - } - if (!work) - PRINTF("pc_keyb: controller jammed (0x%02X).\n", status); - return status; -} - - -/****************************************************************************** - * Lowlevel Part of keyboard section - */ -unsigned char kbd_read_status(void) -{ - return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); -} - -unsigned char kbd_read_input(void) -{ - return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); -} - -void kbd_write_command(unsigned char cmd) -{ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); -} - -void kbd_write_output(unsigned char data) -{ - out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); -} - -int kbd_read_data(void) -{ - int val; - unsigned char status; - - val = -1; - status = kbd_read_status(); - if (status & KBD_STAT_OBF) { - val = kbd_read_input(); - if (status & (KBD_STAT_GTO | KBD_STAT_PERR)) - val = -2; - } - return val; -} - -int kbd_wait_for_input(void) -{ - unsigned long timeout; - int val; - - timeout = KBD_TIMEOUT; - val=kbd_read_data(); - while(val < 0) - { - if(timeout--==0) - return -1; - udelay(1000); - val=kbd_read_data(); - } - return val; -} - - -int kb_wait(void) -{ - unsigned long timeout = KBC_TIMEOUT * 10; - - do { - unsigned char status = handle_kbd_event(); - if (!(status & KBD_STAT_IBF)) - return 0; /* ok */ - udelay(1000); - timeout--; - } while (timeout); - return 1; -} - -void kbd_write_command_w(int data) -{ - if(kb_wait()) - PRINTF("timeout in kbd_write_command_w\n"); - kbd_write_command(data); -} - -void kbd_write_output_w(int data) -{ - if(kb_wait()) - PRINTF("timeout in kbd_write_output_w\n"); - kbd_write_output(data); -} - -void kbd_send_data(unsigned char data) -{ - unsigned char status; - disable_8259A_irq(1); /* disable interrupt */ - kbd_write_output_w(data); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - enable_8259A_irq(1); /* enable interrupt */ -} - - -char * kbd_initialize(void) -{ - int status; - - in_pointer = 0; /* delete in Buffer */ - out_pointer = 0; - /* - * Test the keyboard interface. - * This seems to be the only way to get it going. - * If the test is successful a x55 is placed in the input buffer. - */ - kbd_write_command_w(KBD_CCMD_SELF_TEST); - if (kbd_wait_for_input() != 0x55) - return "Kbd: failed self test"; - /* - * Perform a keyboard interface test. This causes the controller - * to test the keyboard clock and data lines. The results of the - * test are placed in the input buffer. - */ - kbd_write_command_w(KBD_CCMD_KBD_TEST); - if (kbd_wait_for_input() != 0x00) - return "Kbd: interface failed self test"; - /* - * Enable the keyboard by allowing the keyboard clock to run. - */ - kbd_write_command_w(KBD_CCMD_KBD_ENABLE); - status = kbd_wait_for_input(); - /* - * Reset keyboard. If the read times out - * then the assumption is that no keyboard is - * plugged into the machine. - * This defaults the keyboard to scan-code set 2. - * - * Set up to try again if the keyboard asks for RESEND. - */ - do { - kbd_write_output_w(KBD_CMD_RESET); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - break; - if (status != KBD_REPLY_RESEND) { - PRINTF("status: %X\n",status); - return "Kbd: reset failed, no ACK"; - } - } while (1); - if (kbd_wait_for_input() != KBD_REPLY_POR) - return "Kbd: reset failed, no POR"; - - /* - * Set keyboard controller mode. During this, the keyboard should be - * in the disabled state. - * - * Set up to try again if the keyboard asks for RESEND. - */ - do { - kbd_write_output_w(KBD_CMD_DISABLE); - status = kbd_wait_for_input(); - if (status == KBD_REPLY_ACK) - break; - if (status != KBD_REPLY_RESEND) - return "Kbd: disable keyboard: no ACK"; - } while (1); - - kbd_write_command_w(KBD_CCMD_WRITE_MODE); - kbd_write_output_w(KBD_MODE_KBD_INT - | KBD_MODE_SYS - | KBD_MODE_DISABLE_MOUSE - | KBD_MODE_KCC); - - /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */ - kbd_write_command_w(KBD_CCMD_READ_MODE); - if (!(kbd_wait_for_input() & KBD_MODE_KCC)) { - /* - * If the controller does not support conversion, - * Set the keyboard to scan-code set 1. - */ - kbd_write_output_w(0xF0); - kbd_wait_for_input(); - kbd_write_output_w(0x01); - kbd_wait_for_input(); - } - kbd_write_output_w(KBD_CMD_ENABLE); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: enable keyboard: no ACK"; - - /* - * Finally, set the typematic rate to maximum. - */ - kbd_write_output_w(KBD_CMD_SET_RATE); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: Set rate: no ACK"; - kbd_write_output_w(0x00); - if (kbd_wait_for_input() != KBD_REPLY_ACK) - return "Kbd: Set rate: no ACK"; - return NULL; -} - -void kbd_interrupt(void) -{ - handle_kbd_event(); -} diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h deleted file mode 100644 index b549e20..0000000 --- a/board/mpl/common/kbd.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _KBD_H_ -#define _KBD_H_ - -struct stdio_dev; - -int kbd_testc(struct stdio_dev *sdev); -int kbd_getc(struct stdio_dev *sdev); -extern void kbd_interrupt(void); -extern char *kbd_initialize(void); - -unsigned char kbd_is_init(void); -#define KBD_INTERRUPT 1 -#endif diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c deleted file mode 100644 index ad97ffa..0000000 --- a/board/mpl/common/pci.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/* - * Adapted for PIP405 03.07.01 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * TODO: Clean-up - */ - -#include <common.h> -#include <pci.h> -#include "isa.h" - -#ifdef CONFIG_405GP -#ifdef CONFIG_PCI - -DECLARE_GLOBAL_DATA_PTR; - -#include "piix4_pci.h" -#include "pci_parts.h" - -void pci_405gp_init(struct pci_controller *hose); - -void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) -{ - struct pci_pip405_config_entry *table; - int i; - - table = (struct pci_pip405_config_entry *)entry->priv[0]; - - for (i = 0; table[i].width; i++) { -#ifdef DEBUG - printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", - table[i].index, table[i].val, table[i].width); -#endif - - switch (table[i].width) { - case 1: - pci_hose_write_config_byte(hose, dev, - table[i].index, table[i].val); - break; - case 2: - pci_hose_write_config_word(hose, dev, - table[i].index, table[i].val); - break; - case 4: - pci_hose_write_config_dword(hose, dev, - table[i].index, table[i].val); - break; - } - } -} - - -static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = 0xff; - unsigned char pin; - /* - * Write pci interrupt line register - */ - if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */ - return; - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); - if ((pin == 0) || (pin > 4)) - return; - - int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -#ifdef DEBUG - printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", - PCI_DEV(dev), dev, int_line, int_line); -#endif -} - - -static struct pci_controller hose = { -config_table: pci_pip405_config_table, -fixup_irq : pci_pip405_fixup_irq, -}; - - -void pci_init_board(void) -{ - /*we want the ptrs to RAM not flash (ie don't use init list)*/ - hose.fixup_irq = pci_pip405_fixup_irq; - hose.config_table = pci_pip405_config_table; -#ifdef DEBUG - printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n", - pci_pip405_fixup_irq, pci_pip405_config_table, hose); -#endif - pci_405gp_init(&hose); -} - -#endif /* CONFIG_PCI */ -#endif /* CONFIG_405GP */ diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h deleted file mode 100644 index 75e8cae..0000000 --- a/board/mpl/common/pci_parts.h +++ /dev/null @@ -1,176 +0,0 @@ - /* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _PCI_PARTS_H_ -#define _PCI_PARTS_H_ - - -/* Board specific file containing: - * - PCI Memory Mapping - * - PCI IO Mapping - * - PCI Interrupt Mapping - */ - -/* PIP405 PCI INT Routing: - * IRQ0 VECTOR - * PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31) - * VGA IDSEL = AD17 INTB# 29 - * SCSI IDSEL = AD18 INTC# 30 - * PC104 IDSEL0 = AD20 INTA# 28 - * PC104 IDSEL1 = AD21 INTB# 29 - * PC104 IDSEL2 = AD22 INTC# 30 - * PC104 IDSEL3 = AD23 INTD# 31 - * - * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00 - * ^ ^ ^ ^ ^ - * 31 23 15 10 7 - * E = Enabled - * B = Bussnumber - * D = Devicenumber (Device0 = AD10) - * F = Functionnumber - * R = Registernumber - * - * Device = (busdevfunc>>11) + 10 - * Vector = devicenumber % 4 + 28 - * - */ -#define PCI_HIGHEST_ON_BOARD_ID 19 -/*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */ -#define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28 - - -/* PCI Device List for PIP405 */ - -/* Mapping: - * +-------------+------------+------------+--------------------------------+ - * | PCI MemAddr | PCI IOAddr | Local Addr | Device / Function | - * +-------------+------------+------------+--------------------------------+ - * | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) | - * | 0x00FFFFFF | | 0xA0FFFFFF | | - * +-------------+------------+------------+--------------------------------+ - * | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) | - * | | 0x0000FFFF | 0xE800FFFF | | - * +-------------+------------+------------+--------------------------------+ - * | 0x80000000 | | 0x80000000 | VGA Controller Memory | - * | 0x80FFFFFF | | 0x80FFFFFF | | - * +-------------+------------+------------+--------------------------------+ - * | 0x81000000 | | 0x81000000 | SCSI Controller Memory | - * | 0x81FFFFFF | | 0x81FFFFFF | | - * +-------------+------------+------------+--------------------------------+ - */ - -struct pci_pip405_config_entry { - int index; /* address */ - unsigned long val; /* value */ - int width; /* data size */ -}; - -extern void pci_pip405_write_regs(struct pci_controller *, - pci_dev_t, - struct pci_config_table *); - -/* PIIX4 ISA Bridge Function 0 */ -static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = { - {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */ - {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */ - {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */ - {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */ - {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */ -#if defined(CONFIG_PIP405) - {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */ - {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */ -#endif - {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */ - { } /* end of device table */ -}; - -/* PIIX4 IDE Controller Function 1 */ -static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = { - {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */ - {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ -#if !defined(CONFIG_TARGET_MIP405T) - {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */ -#else - {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */ -#endif - { } /* end of device table */ -}; - -/* PIIX4 USB Controller Function 2 */ -static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = { -#if !defined(CONFIG_TARGET_MIP405T) - {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */ - {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */ - {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */ - {0xC0, 0x2000, 2}, /* Legacy support */ - {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */ -#endif - { } /* end of device table */ -}; - -/* PIIX4 Power Management Function 3 */ -static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = { - {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */ - {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */ - {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */ - {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ - { } /* end of device table */ -}; -/* PPC405 Dummy only used to prevent autosetup on this host bridge */ -static struct pci_pip405_config_entry ppc405_dummy[] = { - { } /* end of device table */ -}; - -void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry); - - -static struct pci_config_table pci_pip405_config_table[]={ - {PCI_VENDOR_ID_IBM, /* 405 dummy */ - PCI_DEVICE_ID_IBM_405GP, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 0, - pci_pip405_write_regs, {(unsigned long) ppc405_dummy}}, - - {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */ - PCI_DEVICE_ID_INTEL_82371AB_0, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 0, - pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}}, - - {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */ - PCI_DEVICE_ID_INTEL_82371AB, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 1, - pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}}, - - {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */ - PCI_DEVICE_ID_INTEL_82371AB_2, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 2, - pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}}, - - {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */ - PCI_DEVICE_ID_INTEL_82371AB_3, - PCI_ANY_ID, - PCI_ANY_ID, PCI_ANY_ID, 3, - pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}}, - - {PCI_ANY_ID, - PCI_ANY_ID, - PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_405gp_setup_vga}, - - {PCI_ANY_ID, - PCI_ANY_ID, - PCI_CLASS_NOT_DEFINED_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_405gp_setup_vga}, - - { } -}; -#endif /* _PCI_PARTS_H_ */ diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h deleted file mode 100644 index c19b64e..0000000 --- a/board/mpl/common/piix4_pci.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef _PIIX4_PCI_H -#define _PIIX4_PCI_H - -/*************************************************************************** -* Defines PIIX4 Config Registers -****************************************************************************/ - -/* Function 0 ISA Bridge */ -#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */ -#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */ -#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/ -#define PCI_CFG_PIIX4_SERIRQ 0x64 -#define PCI_CFG_PIIX4_TOM 0x69 -#define PCI_CFG_PIIX4_MSTAT 0x6A -#define PCI_CFG_PIIX4_MBDMA 0x76 -#define PCI_CFG_PIIX4_APICBS 0x80 -#define PCI_CFG_PIIX4_DLC 0x82 -#define PCI_CFG_PIIX4_PDMACFG 0x90 -#define PCI_CFG_PIIX4_DDMABS 0x92 -#define PCI_CFG_PIIX4_GENCFG 0xB0 -#define PCI_CFG_PIIX4_RTCCFG 0xCB - -/* IO Addresses */ -#define PIIX4_ISA_DMA1_CH0BA 0x00 -#define PIIX4_ISA_DMA1_CH0CA 0x01 -#define PIIX4_ISA_DMA1_CH1BA 0x02 -#define PIIX4_ISA_DMA1_CH1CA 0x03 -#define PIIX4_ISA_DMA1_CH2BA 0x04 -#define PIIX4_ISA_DMA1_CH2CA 0x05 -#define PIIX4_ISA_DMA1_CH3BA 0x06 -#define PIIX4_ISA_DMA1_CH3CA 0x07 -#define PIIX4_ISA_DMA1_CMDST 0x08 -#define PIIX4_ISA_DMA1_REQ 0x09 -#define PIIX4_ISA_DMA1_WSBM 0x0A -#define PIIX4_ISA_DMA1_CH_MOD 0x0B -#define PIIX4_ISA_DMA1_CLR_PT 0x0C -#define PIIX4_ISA_DMA1_M_CLR 0x0D -#define PIIX4_ISA_DMA1_CLR_M 0x0E -#define PIIX4_ISA_DMA1_RWAMB 0x0F - -#define PIIX4_ISA_DMA2_CH0BA 0xC0 -#define PIIX4_ISA_DMA2_CH0CA 0xC1 -#define PIIX4_ISA_DMA2_CH1BA 0xC2 -#define PIIX4_ISA_DMA2_CH1CA 0xC3 -#define PIIX4_ISA_DMA2_CH2BA 0xC4 -#define PIIX4_ISA_DMA2_CH2CA 0xC5 -#define PIIX4_ISA_DMA2_CH3BA 0xC6 -#define PIIX4_ISA_DMA2_CH3CA 0xC7 -#define PIIX4_ISA_DMA2_CMDST 0xD0 -#define PIIX4_ISA_DMA2_REQ 0xD2 -#define PIIX4_ISA_DMA2_WSBM 0xD4 -#define PIIX4_ISA_DMA2_CH_MOD 0xD6 -#define PIIX4_ISA_DMA2_CLR_PT 0xD8 -#define PIIX4_ISA_DMA2_M_CLR 0xDA -#define PIIX4_ISA_DMA2_CLR_M 0xDC -#define PIIX4_ISA_DMA2_RWAMB 0xDE - -#define PIIX4_ISA_INT1_ICW1 0x20 -#define PIIX4_ISA_INT1_OCW2 0x20 -#define PIIX4_ISA_INT1_OCW3 0x20 -#define PIIX4_ISA_INT1_ICW2 0x21 -#define PIIX4_ISA_INT1_ICW3 0x21 -#define PIIX4_ISA_INT1_ICW4 0x21 -#define PIIX4_ISA_INT1_OCW1 0x21 - -#define PIIX4_ISA_INT1_ELCR 0x4D0 - -#define PIIX4_ISA_INT2_ICW1 0xA0 -#define PIIX4_ISA_INT2_OCW2 0xA0 -#define PIIX4_ISA_INT2_OCW3 0xA0 -#define PIIX4_ISA_INT2_ICW2 0xA1 -#define PIIX4_ISA_INT2_ICW3 0xA1 -#define PIIX4_ISA_INT2_ICW4 0xA1 -#define PIIX4_ISA_INT2_OCW1 0xA1 -#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */ - -#define PIIX4_ISA_INT2_ELCR 0x4D1 - -#define PIIX4_ISA_TMR0_CNT_ST 0x40 -#define PIIX4_ISA_TMR1_CNT_ST 0x41 -#define PIIX4_ISA_TMR2_CNT_ST 0x42 -#define PIIX4_ISA_TMR_TCW 0x43 - -#define PIIX4_ISA_RST_XBUS 0x60 - -#define PIIX4_ISA_NMI_CNT_ST 0x61 -#define PIIX4_ISA_NMI_ENABLE 0x70 - -#define PIIX4_ISA_RTC_INDEX 0x70 -#define PIIX4_ISA_RTC_DATA 0x71 -#define PIIX4_ISA_RTCEXT_IND 0x70 -#define PIIX4_ISA_RTCEXT_DATA 0x71 - -#define PIIX4_ISA_DMA1_CH2LPG 0x81 -#define PIIX4_ISA_DMA1_CH3LPG 0x82 -#define PIIX4_ISA_DMA1_CH1LPG 0x83 -#define PIIX4_ISA_DMA1_CH0LPG 0x87 -#define PIIX4_ISA_DMA2_CH2LPG 0x89 -#define PIIX4_ISA_DMA2_CH3LPG 0x8A -#define PIIX4_ISA_DMA2_CH1LPG 0x8B -#define PIIX4_ISA_DMA2_LPGRFR 0x8F - -#define PIIX4_ISA_PORT_92 0x92 - -#define PIIX4_ISA_APM_CONTRL 0xB2 -#define PIIX4_ISA_APM_STATUS 0xB3 - -#define PIIX4_ISA_COCPU_ERROR 0xF0 - -/* Function 1 IDE Controller */ -#define PCI_CFG_PIIX4_BMIBA 0x20 -#define PCI_CFG_PIIX4_IDETIM 0x40 -#define PCI_CFG_PIIX4_SIDETIM 0x44 -#define PCI_CFG_PIIX4_UDMACTL 0x48 -#define PCI_CFG_PIIX4_UDMATIM 0x4A - -/* Function 2 USB Controller */ -#define PCI_CFG_PIIX4_SBRNUM 0x60 -#define PCI_CFG_PIIX4_LEGSUP 0xC0 - -/* Function 3 Power Management */ -#define PCI_CFG_PIIX4_PMBA 0x40 -#define PCI_CFG_PIIX4_CNTA 0x44 -#define PCI_CFG_PIIX4_CNTB 0x48 -#define PCI_CFG_PIIX4_GPICTL 0x4C -#define PCI_CFG_PIIX4_DEVRESD 0x50 -#define PCI_CFG_PIIX4_DEVACTA 0x54 -#define PCI_CFG_PIIX4_DEVACTB 0x58 -#define PCI_CFG_PIIX4_DEVRESA 0x5C -#define PCI_CFG_PIIX4_DEVRESB 0x60 -#define PCI_CFG_PIIX4_DEVRESC 0x64 -#define PCI_CFG_PIIX4_DEVRESE 0x68 -#define PCI_CFG_PIIX4_DEVRESF 0x6C -#define PCI_CFG_PIIX4_DEVRESG 0x70 -#define PCI_CFG_PIIX4_DEVRESH 0x74 -#define PCI_CFG_PIIX4_DEVRESI 0x78 -#define PCI_CFG_PIIX4_PMMISC 0x80 -#define PCI_CFG_PIIX4_SMBBA 0x90 - - -#endif diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c deleted file mode 100644 index 8399407..0000000 --- a/board/mpl/common/usb_uhci.c +++ /dev/null @@ -1,1042 +0,0 @@ -/* - * Part of this code has been derived from linux: - * Universal Host Controller Interface driver for USB (take II). - * - * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar) - * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice) - * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader) - * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter) - * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support - * from usb-ohci.c by Adam Richter, adam@yggdrasil.com). - * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c) - * - * HW-initalization based on material of - * - * (C) Copyright 1999 Linus Torvalds - * (C) Copyright 1999 Johannes Erdfelt - * (C) Copyright 1999 Randy Dunlap - * (C) Copyright 1999 Gregory P. Smith - * - * - * Adapted for U-Boot: - * (C) Copyright 2001 Denis Peter, MPL AG Switzerland - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/********************************************************************** - * How it works: - * ------------- - * The framelist / Transfer descriptor / Queue Heads are similar like - * in the linux usb_uhci.c. - * - * During initialization, the following skeleton is allocated in init_skel: - * - * framespecific | common chain - * - * framelist[] - * [ 0 ]-----> TD ---------\ - * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL - * ... TD ---------/ - * [1023]-----> TD --------/ - * - * ^^ ^^ ^^ ^^ ^^ - * 7 TDs for 1 TD for Start of Start of End Chain - * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain - * - * - * Since this is a bootloader, the isochronous transfer descriptor have been removed. - * - * Interrupt Transfers. - * -------------------- - * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They - * will be inserted after the appropriate (depending the interval setting) skeleton TD. - * If an interrupt has been detected the dev->irqhandler is called. The status and number - * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the - * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned, - * the interrupt TD will be reactivated. - * - * Control Transfers - * ----------------- - * Control Transfers are issued by filling the tmp_td with the appropriate data and connect - * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued, - * the programm has to wait for completion. This does not allows asynchronous data transfer. - * - * Bulk Transfers - * -------------- - * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect - * them to the qh_bulk queue header. Before other control/bulk transfers can be issued, - * the programm has to wait for completion. This does not allows asynchronous data transfer. - * - * - */ - -#include <common.h> -#include <pci.h> - -#ifdef CONFIG_USB_UHCI - -#include <usb.h> -#include "usb_uhci.h" - -#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */ -#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */ - - -#undef USB_UHCI_DEBUG - -#ifdef USB_UHCI_DEBUG -#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define USB_UHCI_PRINTF(fmt,args...) -#endif - - -static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */ -unsigned int usb_base_addr; /* base address */ - -static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */ -static uhci_qh_t qh_cntrl; /* control Queue Head */ -static uhci_qh_t qh_bulk; /* bulk Queue Head */ -static uhci_qh_t qh_end; /* end Queue Head */ -static uhci_td_t td_last; /* last TD (linked with end chain) */ - -/* temporary tds */ -static uhci_td_t tmp_td[USB_MAX_TEMP_TD]; /* temporary bulk/control td's */ -static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD]; /* temporary interrupt td's */ - -static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */ - -static struct virt_root_hub rh; /* struct for root hub */ - -/********************************************************************** - * some forward decleration - */ -int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, - void *buffer, int transfer_len,struct devrequest *setup); - -/* fill a td with the approproiate data. Link, status, info and buffer - * are used by the USB controller itselfes, dev is used to identify the - * "connected" device - */ -void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status, - unsigned long info, unsigned long buffer, unsigned long dev) -{ - td->link=swap_32(link); - td->status=swap_32(status); - td->info=swap_32(info); - td->buffer=swap_32(buffer); - td->dev_ptr=dev; -} - -/* fill a qh with the approproiate data. Head and element are used by the USB controller - * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh. - * Please note, that after completion of the td chain, the entry element is removed / - * marked invalid by the USB controller. - */ -void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element) -{ - qh->head=swap_32(head); - qh->element=swap_32(element); - qh->dev_ptr=0L; -} - -/* get the status of a td->status - */ -unsigned long usb_uhci_td_stat(unsigned long status) -{ - unsigned long result=0; - result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0; - result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0; - result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0; - result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0; - result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0; - result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0; - result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0; - return result; -} - -/* get the status and the transferred len of a td chain. - * called from the completion handler - */ -int usb_get_td_status(uhci_td_t *td,struct usb_device *dev) -{ - unsigned long temp,info; - unsigned long stat; - uhci_td_t *mytd=td; - - if(dev->devnum==rh.devnum) - return 0; - dev->act_len=0; - stat=0; - do { - temp=swap_32((unsigned long)mytd->status); - stat=usb_uhci_td_stat(temp); - info=swap_32((unsigned long)mytd->info); - if(((info & 0xff)!= USB_PID_SETUP) && - (((info >> 21) & 0x7ff)!= 0x7ff) && - (temp & 0x7FF)!=0x7ff) - { /* if not setup and not null data pack */ - dev->act_len+=(temp & 0x7FF) + 1; /* the transferred len is act_len + 1 */ - } - if(stat) { /* status no ok */ - dev->status=stat; - return -1; - } - temp=swap_32((unsigned long)mytd->link); - mytd=(uhci_td_t *)(temp & 0xfffffff0); - }while((temp & 0x1)==0); /* process all TDs */ - dev->status=stat; - return 0; /* Ok */ -} - - -/*------------------------------------------------------------------- - * LOW LEVEL STUFF - * assembles QHs und TDs for control, bulk and iso - *-------------------------------------------------------------------*/ - -/* Submits a control message. That is a Setup, Data and Status transfer. - * Routine does not wait for completion. - */ -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int transfer_len,struct devrequest *setup) -{ - unsigned long destination, status; - int maxsze = usb_maxpacket(dev, pipe); - unsigned long dataptr; - int len; - int pktsze; - int i=0; - - if (!maxsze) { - USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe); - return -1; - } - if(((pipe>>8)&0x7f)==rh.devnum) { - /* this is the root hub -> redirect it */ - return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup); - } - USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze); - /* The "pipe" thing contains the destination in bits 8--18 */ - destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */ - /* 3 errors */ - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); - /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */ - /* Build the TD for the control request, try forever, 8 bytes of data */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev); -#if 0 - { - char *sp=(char *)setup; - printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe, - sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]); - } -#endif - dataptr = (unsigned long)buffer; - len=transfer_len; - - /* If direction is "send", change the frame from SETUP (0x2D) - to OUT (0xE1). Else change it from SETUP to IN (0x69). */ - destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN); - while (len > 0) { - /* data stage */ - pktsze = len; - i++; - if (pktsze > maxsze) - pktsze = maxsze; - destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); - - dataptr += pktsze; - len -= pktsze; - } - - /* Build the final TD for control status */ - /* It's only IN if the pipe is out AND we aren't expecting data */ - - destination &= ~UHCI_PID; - if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0)) - destination |= USB_PID_IN; - else - destination |= USB_PID_OUT; - destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */ - i++; - status &=~TD_CTRL_SPD; - /* no limit on errors on final packet , 0 bytes of data */ - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev); - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); /* queue status td */ - /* usb_show_td(i+1);*/ - USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i); - /* first mark the control QH element terminated */ - qh_cntrl.element=0xffffffffL; - /* set qh active */ - qh_cntrl.dev_ptr=(unsigned long)dev; - /* fill in tmp_td_chain */ - qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]); - return 0; -} - -/*------------------------------------------------------------------- - * Prepare TDs for bulk transfers. - */ -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len) -{ - unsigned long destination, status,info; - unsigned long dataptr; - int maxsze = usb_maxpacket(dev, pipe); - int len; - int i=0; - - if(transfer_len < 0) { - printf("Negative transfer length in submit_bulk\n"); - return -1; - } - if (!maxsze) - return -1; - /* The "pipe" thing contains the destination in bits 8--18. */ - destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe); - /* 3 errors */ - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27); - /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */ - /* Build the TDs for the bulk request */ - len = transfer_len; - dataptr = (unsigned long)buffer; - do { - int pktsze = len; - if (pktsze > maxsze) - pktsze = maxsze; - /* pktsze bytes of data */ - info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) | - (usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE); - - if((len-pktsze)==0) - status |= TD_CTRL_IOC; /* last one generates INT */ - - usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */ - if(i>0) - tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); - i++; - dataptr += pktsze; - len -= pktsze; - usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); - } while (len > 0); - /* first mark the bulk QH element terminated */ - qh_bulk.element=0xffffffffL; - /* set qh active */ - qh_bulk.dev_ptr=(unsigned long)dev; - /* fill in tmp_td_chain */ - qh_bulk.element=swap_32((unsigned long)&tmp_td[0]); - return 0; -} - - -/* search a free interrupt td - */ -uhci_td_t *uhci_alloc_int_td(void) -{ - int i; - for(i=0;i<USB_MAX_TEMP_INT_TD;i++) { - if(tmp_int_td[i].dev_ptr==0) /* no device assigned -> free TD */ - return &tmp_int_td[i]; - } - return NULL; -} - -#if 0 -void uhci_show_temp_int_td(void) -{ - int i; - for(i=0;i<USB_MAX_TEMP_INT_TD;i++) { - if((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */ - printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr); - } - printf("all others temp_tds are free\n"); -} -#endif -/*------------------------------------------------------------------- - * submits USB interrupt (ie. polling ;-) - */ -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval) -{ - int nint, n; - unsigned long status, destination; - unsigned long info,tmp; - uhci_td_t *mytd; - if (interval < 0 || interval >= 256) - return -1; - - if (interval == 0) - nint = 0; - else { - for (nint = 0, n = 1; nint <= 8; nint++, n += n) /* round interval down to 2^n */ - { - if(interval < n) { - interval = n / 2; - break; - } - } - nint--; - } - - USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint); - mytd=uhci_alloc_int_td(); - if(mytd==NULL) { - printf("No free INT TDs found\n"); - return -1; - } - status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27); -/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27); -*/ - - destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21); - - info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE); - tmp = swap_32(td_int[nint].link); - usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev); - /* Link it */ - tmp = swap_32((unsigned long)mytd); - td_int[nint].link=tmp; - - usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)); - - return 0; -} - -/********************************************************************** - * Low Level functions - */ - - -void reset_hc(void) -{ - - /* Global reset for 100ms */ - out16r( usb_base_addr + USBPORTSC1,0x0204); - out16r( usb_base_addr + USBPORTSC2,0x0204); - out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS); - /* Turn off all interrupts */ - out16r(usb_base_addr + USBINTR,0); - mdelay(50); - out16r( usb_base_addr + USBCMD,0); - mdelay(10); -} - -void start_hc(void) -{ - int timeout = 1000; - - while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) { - if (!--timeout) { - printf("USBCMD_HCRESET timed out!\n"); - break; - } - } - /* Turn on all interrupts */ - out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP); - /* Start at frame 0 */ - out16r(usb_base_addr + USBFRNUM,0); - /* set Framebuffer base address */ - out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist); - /* Run and mark it configured with a 64-byte max packet */ - out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP); -} - -/* Initialize the skeleton - */ -void usb_init_skel(void) -{ - unsigned long temp; - int n; - - for(n=0;n<USB_MAX_TEMP_INT_TD;n++) - tmp_int_td[n].dev_ptr=0L; /* no devices connected */ - /* last td */ - usb_fill_td(&td_last,UHCI_PTR_TERM,TD_CTRL_IOC ,0,0,0L); - /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */ - /* End Queue Header */ - usb_fill_qh(&qh_end,UHCI_PTR_TERM,(unsigned long)&td_last); - /* Bulk Queue Header */ - temp=(unsigned long)&qh_end; - usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH,UHCI_PTR_TERM); - /* Control Queue Header */ - temp=(unsigned long)&qh_bulk; - usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH,UHCI_PTR_TERM); - /* 1ms Interrupt td */ - temp=(unsigned long)&qh_cntrl; - usb_fill_td(&td_int[0],temp | UHCI_PTR_QH,0,0,0,0L); - temp=(unsigned long)&td_int[0]; - for(n=1; n<8; n++) - usb_fill_td(&td_int[n],temp,0,0,0,0L); - for (n = 0; n < 1024; n++) { - /* link all framelist pointers to one of the interrupts */ - int m, o; - if ((n&127)==127) - framelist[n]= swap_32((unsigned long)&td_int[0]); - else - for (o = 1, m = 2; m <= 128; o++, m += m) - if ((n & (m - 1)) == ((m - 1) / 2)) - framelist[n]= swap_32((unsigned long)&td_int[o]); - } -} - -/* check the common skeleton for completed transfers, and update the status - * of the "connected" device. Called from the IRQ routine. - */ -void usb_check_skel(void) -{ - struct usb_device *dev; - /* start with the control qh */ - if(qh_cntrl.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */ - { - dev=(struct usb_device *)qh_cntrl.dev_ptr; - usb_get_td_status(&tmp_td[0],dev); /* update status */ - if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ - qh_cntrl.dev_ptr=0; - } - } - /* now process the bulk */ - if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */ - { - dev=(struct usb_device *)qh_bulk.dev_ptr; - usb_get_td_status(&tmp_td[0],dev); /* update status */ - if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */ - qh_bulk.dev_ptr=0; - } - } -} - -/* check the interrupt chain, ubdate the status of the appropriate device, - * call the appropriate irqhandler and reactivate the TD if the irqhandler - * returns with 1 - */ -void usb_check_int_chain(void) -{ - int i,res; - unsigned long link,status; - struct usb_device *dev; - uhci_td_t *td,*prevtd; - - for(i=0;i<8;i++) { - prevtd = &td_int[i]; /* the first previous td is the skeleton td */ - link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */ - td=(uhci_td_t *)link; /* assign it */ - /* all interrupt TDs are finally linked to the td_int[0]. - * so we process all until we find the td_int[0]. - * if int0 chain points to a QH, we're also done - */ - while(((i>0) && (link != (unsigned long)&td_int[0])) || - ((i==0) && !(swap_32(td->link) & UHCI_PTR_QH))) - { - /* check if a device is assigned with this td */ - status=swap_32(td->status); - if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) { - /* td is not active and a device is assigned -> call irqhandler */ - dev=(struct usb_device *)td->dev_ptr; - dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transferred length */ - dev->irq_status=usb_uhci_td_stat(status); /* get status */ - res=dev->irq_handle(dev); /* call irqhandler */ - if(res==1) { - /* reactivate */ - status|=TD_CTRL_ACTIVE; - td->status=swap_32(status); - prevtd=td; /* previous td = this td */ - } - else { - prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */ - /* remove device pointer */ - td->dev_ptr=0L; - } - } /* if we call the irq handler */ - link=swap_32(td->link) & 0xfffffff0; /* next in chain */ - td=(uhci_td_t *)link; /* assign it */ - } /* process all td in this int chain */ - } /* next interrupt chain */ -} - - -/* usb interrupt service routine. - */ -void handle_usb_interrupt(void) -{ - unsigned short status; - - /* - * Read the interrupt status, and write it back to clear the - * interrupt cause - */ - - status = in16r(usb_base_addr + USBSTS); - - if (!status) /* shared interrupt, not mine */ - return; - if (status != 1) { - /* remove host controller halted state */ - if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) { - out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD)); - } - } - usb_check_int_chain(); /* call interrupt handlers for int tds */ - usb_check_skel(); /* call completion handler for common transfer routines */ - out16r(usb_base_addr+USBSTS,status); -} - - -/* init uhci - */ -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - unsigned char temp; - int busdevfunc; - - busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */ - if(busdevfunc==-1) { - printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID); - return -1; - } - pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp); - irqvec = temp; - irq_free_handler(irqvec); - USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec); - pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp); - USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp); - pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); - USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); - usb_base_addr&=0xFFFFFFF0; - usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS; - rh.devnum = 0; - usb_init_skel(); - reset_hc(); - start_hc(); - irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL); - return 0; -} - -/* stop uhci - */ -int usb_lowlevel_stop(int index) -{ - if(irqvec==-1) - return 1; - irq_free_handler(irqvec); - reset_hc(); - irqvec = -1; - return 0; -} - -/******************************************************************************************* - * Virtual Root Hub - * Since the uhci does not have a real HUB, we simulate one ;-) - */ -#undef USB_RH_DEBUG - -#ifdef USB_RH_DEBUG -#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args) -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex); -static void usb_display_Req(unsigned short req); -#else -#define USB_RH_PRINTF(fmt,args...) -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {} -static void usb_display_Req(unsigned short req) {} -#endif - -#define WANT_USB_ROOT_HUB_HUB_DES -#include <usbroothubdes.h> -#undef WANT_USB_ROOT_HUB_HUB_DES - -/* - * Root Hub Control Pipe (interrupt Pipes are not supported) - */ - - -int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd) -{ - void *data = buffer; - int leni = transfer_len; - int len = 0; - int status = 0; - int stat = 0; - int i; - - unsigned short cstatus; - - unsigned short bmRType_bReq; - unsigned short wValue; - unsigned short wIndex; - unsigned short wLength; - - if (usb_pipeint(pipe)) { - printf("Root-Hub submit IRQ: NOT implemented\n"); -#if 0 - uhci->rh.urb = urb; - uhci->rh.send = 1; - uhci->rh.interval = urb->interval; - rh_init_int_timer (urb); -#endif - return 0; - } - bmRType_bReq = cmd->requesttype | cmd->request << 8; - wValue = swap_16(cmd->value); - wIndex = swap_16(cmd->index); - wLength = swap_16(cmd->length); - usb_display_Req(bmRType_bReq); - for (i = 0; i < 8; i++) - rh.c_p_r[i] = 0; - USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n", - dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength); - - switch (bmRType_bReq) { - /* Request Destination: - without flags: Device, - RH_INTERFACE: interface, - RH_ENDPOINT: endpoint, - RH_CLASS means HUB here, - RH_OTHER | RH_CLASS almost ever means HUB_PORT here - */ - - case RH_GET_STATUS: - *(unsigned short *) data = swap_16(1); - len=2; - break; - case RH_GET_STATUS | RH_INTERFACE: - *(unsigned short *) data = swap_16(0); - len=2; - break; - case RH_GET_STATUS | RH_ENDPOINT: - *(unsigned short *) data = swap_16(0); - len=2; - break; - case RH_GET_STATUS | RH_CLASS: - *(unsigned long *) data = swap_32(0); - len=4; - break; /* hub power ** */ - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - - status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1)); - cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) | - ((status & USBPORTSC_PEC) >> (3 - 1)) | - (rh.c_p_r[wIndex - 1] << (0 + 4)); - status = (status & USBPORTSC_CCS) | - ((status & USBPORTSC_PE) >> (2 - 1)) | - ((status & USBPORTSC_SUSP) >> (12 - 2)) | - ((status & USBPORTSC_PR) >> (9 - 4)) | - (1 << 8) | /* power on ** */ - ((status & USBPORTSC_LSDA) << (-8 + 9)); - - *(unsigned short *) data = swap_16(status); - *(unsigned short *) (data + 2) = swap_16(cstatus); - len=4; - break; - case RH_CLEAR_FEATURE | RH_ENDPOINT: - switch (wValue) { - case (RH_ENDPOINT_STALL): - len=0; - break; - } - break; - - case RH_CLEAR_FEATURE | RH_CLASS: - switch (wValue) { - case (RH_C_HUB_OVER_CURRENT): - len=0; /* hub power over current ** */ - break; - } - break; - - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - usb_display_wValue(wValue,wIndex); - switch (wValue) { - case (RH_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) & ~USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_SUSPEND): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) & ~USBPORTSC_SUSP; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_POWER): - len=0; /* port power ** */ - break; - case (RH_C_PORT_CONNECTION): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_CSC; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_C_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PEC; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_C_PORT_SUSPEND): -/*** WR_RH_PORTSTAT(RH_PS_PSSC); */ - len=0; - break; - case (RH_C_PORT_OVER_CURRENT): - len=0; - break; - case (RH_C_PORT_RESET): - rh.c_p_r[wIndex - 1] = 0; - len=0; - break; - } - break; - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - usb_display_wValue(wValue,wIndex); - switch (wValue) { - case (RH_PORT_SUSPEND): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_SUSP; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_RESET): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PR; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - mdelay(10); - status = (status & 0xfff5) & ~USBPORTSC_PR; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - udelay(10); - status = (status & 0xfff5) | USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - mdelay(10); - status = (status & 0xfff5) | 0xa; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - case (RH_PORT_POWER): - len=0; /* port power ** */ - break; - case (RH_PORT_ENABLE): - status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1)); - status = (status & 0xfff5) | USBPORTSC_PE; - out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status); - len=0; - break; - } - break; - - case RH_SET_ADDRESS: - rh.devnum = wValue; - len=0; - break; - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case (0x01): /* device descriptor */ - i=sizeof(root_hub_config_des); - status=i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_dev_des, len); - break; - case (0x02): /* configuration descriptor */ - i=sizeof(root_hub_config_des); - status=i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_config_des, len); - break; - case (0x03): /*string descriptors */ - if(wValue==0x0300) { - i=sizeof(root_hub_str_index0); - status = i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_str_index0, len); - break; - } - if(wValue==0x0301) { - i=sizeof(root_hub_str_index1); - status = i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_str_index1, len); - break; - } - stat = USB_ST_STALLED; - } - break; - - case RH_GET_DESCRIPTOR | RH_CLASS: - root_hub_hub_des[2] = 2; - i=sizeof(root_hub_hub_des); - status= i > wLength ? wLength : i; - len = leni > status ? status : leni; - memcpy (data, root_hub_hub_des, len); - break; - case RH_GET_CONFIGURATION: - *(unsigned char *) data = 0x01; - len = 1; - break; - case RH_SET_CONFIGURATION: - len=0; - break; - default: - stat = USB_ST_STALLED; - } - USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat, - in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2)); - dev->act_len=len; - dev->status=stat; - return stat; - -} - -/******************************************************************************** - * Some Debug Routines - */ - -#ifdef USB_RH_DEBUG - -static void usb_display_Req(unsigned short req) -{ - USB_RH_PRINTF("- Root-Hub Request: "); - switch (req) { - case RH_GET_STATUS: - USB_RH_PRINTF("Get Status "); - break; - case RH_GET_STATUS | RH_INTERFACE: - USB_RH_PRINTF("Get Status Interface "); - break; - case RH_GET_STATUS | RH_ENDPOINT: - USB_RH_PRINTF("Get Status Endpoint "); - break; - case RH_GET_STATUS | RH_CLASS: - USB_RH_PRINTF("Get Status Class"); - break; /* hub power ** */ - case RH_GET_STATUS | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Get Status Class Others"); - break; - case RH_CLEAR_FEATURE | RH_ENDPOINT: - USB_RH_PRINTF("Clear Feature Endpoint "); - break; - case RH_CLEAR_FEATURE | RH_CLASS: - USB_RH_PRINTF("Clear Feature Class "); - break; - case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Clear Feature Other Class "); - break; - case RH_SET_FEATURE | RH_OTHER | RH_CLASS: - USB_RH_PRINTF("Set Feature Other Class "); - break; - case RH_SET_ADDRESS: - USB_RH_PRINTF("Set Address "); - break; - case RH_GET_DESCRIPTOR: - USB_RH_PRINTF("Get Descriptor "); - break; - case RH_GET_DESCRIPTOR | RH_CLASS: - USB_RH_PRINTF("Get Descriptor Class "); - break; - case RH_GET_CONFIGURATION: - USB_RH_PRINTF("Get Configuration "); - break; - case RH_SET_CONFIGURATION: - USB_RH_PRINTF("Get Configuration "); - break; - default: - USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req); - } - USB_RH_PRINTF("\n"); - -} - -static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) -{ - switch (wValue) { - case (RH_PORT_ENABLE): - USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex); - break; - case (RH_PORT_SUSPEND): - USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex); - break; - case (RH_PORT_POWER): - USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex); - break; - case (RH_C_PORT_CONNECTION): - USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex); - break; - case (RH_C_PORT_ENABLE): - USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex); - break; - case (RH_C_PORT_SUSPEND): - USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex); - break; - case (RH_C_PORT_OVER_CURRENT): - USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex); - break; - case (RH_C_PORT_RESET): - USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex); - break; - default: - USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex); - break; - } -} - -#endif - - -#ifdef USB_UHCI_DEBUG - -static int usb_display_td(uhci_td_t *td) -{ - unsigned long tmp; - int valid; - - printf("TD at %p:\n",td); - - tmp=swap_32(td->link); - printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0, - ((tmp & 0x4)==0x4) ? "Depth" : "Breath", - ((tmp & 0x2)==0x2) ? "QH" : "TD", - ((tmp & 0x1)==0x1) ? "invalid" : "valid"); - valid=((tmp & 0x1)==0x0); - tmp=swap_32(td->status); - printf(" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n", - (((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable", - ((tmp>>28)&0x3), - (((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed", - (((tmp>>25)&0x1)==0x1) ? "ISO " : "", - (((tmp>>24)&0x1)==0x1) ? "IOC " : "", - (((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ", - (((tmp>>22)&0x1)==0x1) ? "Stalled" : "", - (((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "", - (((tmp>>20)&0x1)==0x1) ? "Babble" : "", - (((tmp>>19)&0x1)==0x1) ? "NAK" : "", - (((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "", - (tmp&0x7ff)); - tmp=swap_32(td->info); - printf(" MaxLen 0x%lX\n",((tmp>>21)&0x7FF)); - printf(" %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "", - ((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF); - tmp=swap_32(td->buffer); - printf(" Buffer 0x%08lX\n",tmp); - printf(" DEV %08lX\n",td->dev_ptr); - return valid; -} - - -void usb_show_td(int max) -{ - int i; - if(max>0) { - for(i=0;i<max;i++) { - usb_display_td(&tmp_td[i]); - } - } - else { - i=0; - do { - printf("tmp_td[%d]\n",i); - }while(usb_display_td(&tmp_td[i++])); - } -} - - -#endif -#endif /* CONFIG_USB_UHCI */ - -/* EOF */ diff --git a/board/mpl/common/usb_uhci.h b/board/mpl/common/usb_uhci.h deleted file mode 100644 index 582015f..0000000 --- a/board/mpl/common/usb_uhci.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Note: Part of this code has been derived from linux - */ -#ifndef _USB_UHCI_H_ -#define _USB_UHCI_H_ - - -/* Command register */ -#define USBCMD 0 -#define USBCMD_RS 0x0001 /* Run/Stop */ -#define USBCMD_HCRESET 0x0002 /* Host reset */ -#define USBCMD_GRESET 0x0004 /* Global reset */ -#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ -#define USBCMD_FGR 0x0010 /* Force Global Resume */ -#define USBCMD_SWDBG 0x0020 /* SW Debug mode */ -#define USBCMD_CF 0x0040 /* Config Flag (sw only) */ -#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ - -/* Status register */ -#define USBSTS 2 -#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ -#define USBSTS_ERROR 0x0002 /* Interrupt due to error */ -#define USBSTS_RD 0x0004 /* Resume Detect */ -#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */ -#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */ -#define USBSTS_HCH 0x0020 /* HC Halted */ - -/* Interrupt enable register */ -#define USBINTR 4 -#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ -#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ -#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ -#define USBINTR_SP 0x0008 /* Short packet interrupt enable */ - -#define USBFRNUM 6 -#define USBFLBASEADD 8 -#define USBSOF 12 - -/* USB port status and control registers */ -#define USBPORTSC1 16 -#define USBPORTSC2 18 -#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */ -#define USBPORTSC_CSC 0x0002 /* Connect Status Change */ -#define USBPORTSC_PE 0x0004 /* Port Enable */ -#define USBPORTSC_PEC 0x0008 /* Port Enable Change */ -#define USBPORTSC_LS 0x0030 /* Line Status */ -#define USBPORTSC_RD 0x0040 /* Resume Detect */ -#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ -#define USBPORTSC_PR 0x0200 /* Port Reset */ -#define USBPORTSC_SUSP 0x1000 /* Suspend */ - -/* Legacy support register */ -#define USBLEGSUP 0xc0 -#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ - -#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */ -#define UHCI_PID 0xff /* PID MASK */ - -#define UHCI_PTR_BITS 0x000F -#define UHCI_PTR_TERM 0x0001 -#define UHCI_PTR_QH 0x0002 -#define UHCI_PTR_DEPTH 0x0004 - -/* for TD <status>: */ -#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ -#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ -#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ -#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ -#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ -#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ -#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ -#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ -#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ -#define TD_CTRL_NAK (1 << 19) /* NAK Received */ -#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ -#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ -#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ - -#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ - TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) - -#define TD_TOKEN_TOGGLE 19 - -/* ------------------------------------------------------------------------------------ - Virtual Root HUB - ------------------------------------------------------------------------------------ */ -/* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 - -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 -/* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 - -/* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 - -/* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 - -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 - -/* Our Vendor Specific feature */ -#define RH_REMOVE_EP 0x00 - - -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 - - -/* Transfer descriptor structure */ -typedef struct { - unsigned long link; /* next td/qh (LE)*/ - unsigned long status; /* status of the td */ - unsigned long info; /* Max Lenght / Endpoint / device address and PID */ - unsigned long buffer; /* pointer to data buffer (LE) */ - unsigned long dev_ptr; /* pointer to the assigned device (BE) */ - unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */ -} uhci_td_t, *puhci_td_t; - -/* Queue Header structure */ -typedef struct { - unsigned long head; /* Next QH (LE)*/ - unsigned long element; /* Queue element pointer (LE) */ - unsigned long res[5]; /* reserved */ - unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */ -} uhci_qh_t, *puhci_qh_t; - -struct virt_root_hub { - int devnum; /* Address of Root Hub endpoint */ - int numports; /* number of ports */ - int c_p_r[8]; /* C_PORT_RESET */ -}; - - -#endif /* _USB_UHCI_H_ */ diff --git a/board/mpl/mip405/Kconfig b/board/mpl/mip405/Kconfig deleted file mode 100644 index e003a43..0000000 --- a/board/mpl/mip405/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if TARGET_MIP405 || TARGET_MIP405T - -config SYS_BOARD - default "mip405" - -config SYS_VENDOR - default "mpl" - -config SYS_CONFIG_NAME - default "MIP405" - -config ISO_STRING - string - default "MEV-10082-001" if TARGET_MIP405T - default "MEV-10072-001" if TARGET_MIP405 - -endif diff --git a/board/mpl/mip405/MAINTAINERS b/board/mpl/mip405/MAINTAINERS deleted file mode 100644 index b323e5a..0000000 --- a/board/mpl/mip405/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -MIP405 BOARD -M: Denis Peter <d.peter@mpl.ch> -S: Maintained -F: board/mpl/mip405/ -F: include/configs/MIP405.h -F: configs/MIP405_defconfig -F: configs/MIP405T_defconfig diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile deleted file mode 100644 index 5bcf130..0000000 --- a/board/mpl/mip405/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mip405.o cmd_mip405.o \ - ../common/pci.o \ - ../common/usb_uhci.o \ - ../common/common_util.o -obj-y += init.o diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c deleted file mode 100644 index ca6f0af..0000000 --- a/board/mpl/mip405/cmd_mip405.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * hacked for MIP405 - */ - -#include <common.h> -#include <command.h> -#include "mip405.h" -#include "../common/common_util.h" - - -extern void print_mip405_info(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - - -/* ------------------------------------------------------------------------- */ - -int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - - ulong led_on; - - if (strcmp(argv[1], "info") == 0) - { - print_mip405_info(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - led_on = (ulong)simple_strtoul(argv[2], NULL, 10); - user_led0(led_on); - return 0; - } - return (do_mplcommon(cmdtp, flag, argc, argv)); -} -U_BOOT_CMD( - mip405, 8, 1, do_mip405, - "MIP405 specific Cmds", - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" - "mip405 flash mps - updates U-Boot with image from MPS\n" - "mip405 info - displays board information\n" - "mip405 led <on> - switches LED on (on=1) or off (on=0)" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S deleted file mode 100644 index 2ea2e29..0000000 --- a/board/mpl/mip405/init.S +++ /dev/null @@ -1,200 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/*----------------------------------------------------------------------------- - * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * Bank 0 - Flash or Multi Purpose Socket - * Bank 1 - Multi Purpose Socket or Flash (set in C-Code) - * Bank 2 - UART 1 (set in C-Code) - * Bank 3 - UART 2 (set in C-Code) - * Bank 4 - not used - * Bank 5 - not used - * Bank 6 - not used - * Bank 7 - PLD Register - *-----------------------------------------------------------------------------*/ - -#include <configs/MIP405.h> -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> -#include "mip405.h" - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - mfdcr r3,CPC0_PSR /* get strapping reg */ - andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ - bnelr /* jump back if PCI boot */ - - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 14; used to prefetch */ - mtctr r4 /* 14 cache lines to fit this function */ - /* in cache (gives us 8x14=112 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 14 cache lines */ - - /*------------------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. - *------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------------- - * decide boot up mode - *----------------------------------------------------------------------- */ - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - mfdcr r4,EBC0_CFGDATA - - andi. r0, r4, 0x2000 /* mask out irrelevant bits */ - beq 0f /* jump if 8 bit bus width */ - - /* setup 16 bit things - *----------------------------------------------------------------------- - * Memory Bank 0 (16 Bit Flash) initialization - *---------------------------------------------------------------------- */ - - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,(FLASH_AP_B)@h - ori r4,r4,(FLASH_AP_B)@l - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(FLASH_CR_B)@h - ori r4,r4,(FLASH_CR_B)@l - mtdcr EBC0_CFGDATA,r4 - b 1f - -0: - - /* 8Bit boot mode: */ - /*----------------------------------------------------------------------- - * Memory Bank 0 Multi Purpose Socket initialization - *----------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,(MPS_AP_B)@h - ori r4,r4,(MPS_AP_B)@l - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(MPS_CR_B)@h - ori r4,r4,(MPS_CR_B)@l - - mtdcr EBC0_CFGDATA,r4 - - -1: - /*----------------------------------------------------------------------- - * Memory Bank 2-3-4-5-6 (not used) initialization - *-----------------------------------------------------------------------*/ - addi r4,0,PB1CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB2CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB3CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB4CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB5CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB6CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB7CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - nop /* pass2 DCR errata #8 */ - blr - -#if defined(CONFIG_BOOT_PCI) - .section .bootpg,"ax" - .globl _start_pci -/******************************************* - */ - -_start_pci: - /* first handle errata #68 / PCI_18 */ - iccci r0, r0 /* invalidate I-cache */ - lis r31, 0 - mticcr r31 /* ICCR = 0 (all uncachable) */ - isync - - mfccr0 r28 /* set CCR0[24] = 1 */ - ori r28, r28, 0x0080 - mtccr0 r28 - - /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ - lis r28, 0xEF40 - addi r28, r28, 0x0004 - stw r31, 0x0C(r28) /* clear PMM0PCIHA */ - lis r29, 0xFFF8 /* open 512 kByte */ - addi r29, r29, 0x0001/* and enable this region */ - stwbrx r29, r0, r28 /* write PMM0MA */ - - lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ - addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ - - lis r31, 0x8000 /* set en bit bus 0 */ - ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ - stwbrx r31, r0, r28 /* write it */ - - lwbrx r31, r0, r29 /* load XBCS register */ - oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ - stwbrx r31, r0, r29 /* write back XBCS register */ - - nop - nop - b _start /* normal start */ -#endif diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c deleted file mode 100644 index 4d8671f..0000000 --- a/board/mpl/mip405/mip405.c +++ /dev/null @@ -1,805 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * TODO: clean-up - */ - -/* - * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM? - * - * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being - * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum - * parameters from the datasheet are: - * Tclk = 7.5ns (CL = 2) - * Trp = 15ns - * Trc = 60ns - * Trcd = 15ns - * Trfc = 66ns - * - * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock - * period is 10ns and the parameters needed for the Timing Register are: - * CASL = CL = 2 clock cycles - * PTA = Trp = 15ns / 10ns = 2 clock cycles - * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles - * LDF = 2 clock cycles (but can be extended to meet board-level timing) - * RFTA = Trfc = 66ns / 10ns= 7 clock cycles - * RCD = Trcd = 15ns / 10ns= 2 clock cycles - * - * The actual bit settings in the register would be: - * - * CASL = 0b01 - * PTA = 0b01 - * CTP = 0b10 - * LDF = 0b01 - * RFTA = 0b011 - * RCD = 0b01 - * - * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc - * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay - * defined as Trc rather than Trfc. - * When using DIMM modules, most but not all of the required timing parameters can be read - * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc - * are not available from the EEPROM - */ - -#include <common.h> -#include "mip405.h" -#include <asm/processor.h> -#include <asm/ppc4xx.h> -#include <asm/ppc4xx-i2c.h> -#include <miiphy.h> -#include "../common/common_util.h" -#include <stdio_dev.h> -#include <i2c.h> -#include <rtc.h> - -DECLARE_GLOBAL_DATA_PTR; - -#undef SDRAM_DEBUG -#define ENABLE_ECC /* for ecc boards */ - -/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ -#ifndef __ldiv_t_defined -typedef struct { - long int quot; /* Quotient */ - long int rem; /* Remainder */ -} ldiv_t; -extern ldiv_t ldiv (long int __numer, long int __denom); -# define __ldiv_t_defined 1 -#endif - - -#define PLD_PART_REG PER_PLD_ADDR + 0 -#define PLD_VERS_REG PER_PLD_ADDR + 1 -#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 -#define PLD_IRQ_REG PER_PLD_ADDR + 3 -#define PLD_COM_MODE_REG PER_PLD_ADDR + 4 -#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 - -#define MEGA_BYTE (1024*1024) - -typedef struct { - unsigned char boardtype; /* Board revision and Population Options */ - unsigned char cal; /* cas Latency (will be programmend as cal-1) */ - unsigned char trp; /* datain27 in clocks */ - unsigned char trcd; /* datain29 in clocks */ - unsigned char tras; /* datain30 in clocks */ - unsigned char tctp; /* tras - trcd in clocks */ - unsigned char am; /* Address Mod (will be programmed as am-1) */ - unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */ - unsigned char ecc; /* if true, ecc is enabled */ -} sdram_t; -#if defined(CONFIG_TARGET_MIP405T) -const sdram_t sdram_table[] = { - { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 2, /* Address Mode = 2 (12x9x4) */ - 3, /* size value (32MByte) */ - 0}, /* ECC disabled */ - { 0xff, /* terminator */ - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff } -}; -#else -const sdram_t sdram_table[] = { - { 0x0f, /* Rev A, 128MByte -1 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 3, /* Address Mode = 3 */ - 5, /* size value */ - 1}, /* ECC enabled */ - { 0x07, /* Rev A, 64MByte -2 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 2, /* Address Mode = 2 */ - 4, /* size value */ - 1}, /* ECC enabled */ - { 0x03, /* Rev A, 128MByte -4 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 3, /* Address Mode = 3 */ - 5, /* size value */ - 1}, /* ECC enabled */ - { 0x1f, /* Rev B, 128MByte -3 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 3, /* Address Mode = 3 */ - 5, /* size value */ - 1}, /* ECC enabled */ - { 0x2f, /* Rev C, 128MByte -3 Board */ - 3, /* Case Latenty = 3 */ - 3, /* trp 20ns / 7.5 ns datain[27] */ - 3, /* trcd 20ns /7.5 ns (datain[29]) */ - 6, /* tras 44ns /7.5 ns (datain[30]) */ - 4, /* tcpt 44 - 20ns = 24ns */ - 3, /* Address Mode = 3 */ - 5, /* size value */ - 1}, /* ECC enabled */ - { 0xff, /* terminator */ - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff, - 0xff } -}; -#endif /*CONFIG_TARGET_MIP405T */ -void SDRAM_err (const char *s) -{ -#ifndef SDRAM_DEBUG - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); -#endif - serial_puts ("\n"); - serial_puts (s); - serial_puts ("\n enable SDRAM_DEBUG for more info\n"); - for (;;); -} - - -unsigned char get_board_revcfg (void) -{ - out8 (PER_BOARD_ADDR, 0); - return (in8 (PER_BOARD_ADDR)); -} - - -#ifdef SDRAM_DEBUG - -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - - -int init_sdram (void) -{ - unsigned long tmp, baseaddr; - unsigned short i; - unsigned char trp_clocks, - trcd_clocks, - tras_clocks, - trc_clocks; - unsigned char cal_val; - unsigned char bc; - unsigned long sdram_tim, sdram_bank; - - /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/ - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); - /* set up the pld */ - mtdcr (EBC0_CFGADDR, PB7AP); - mtdcr (EBC0_CFGDATA, PLD_AP); - mtdcr (EBC0_CFGADDR, PB7CR); - mtdcr (EBC0_CFGDATA, PLD_CR); - /* THIS IS OBSOLETE */ - /* set up the board rev reg*/ - mtdcr (EBC0_CFGADDR, PB5AP); - mtdcr (EBC0_CFGDATA, BOARD_AP); - mtdcr (EBC0_CFGADDR, PB5CR); - mtdcr (EBC0_CFGDATA, BOARD_CR); -#ifdef SDRAM_DEBUG - /* get all informations from PLD */ - serial_puts ("\nPLD Part 0x"); - bc = in8 (PLD_PART_REG); - write_hex (bc); - serial_puts ("\nPLD Vers 0x"); - bc = in8 (PLD_VERS_REG); - write_hex (bc); - serial_puts ("\nBoard Rev 0x"); - bc = in8 (PLD_BOARD_CFG_REG); - write_hex (bc); - serial_puts ("\n"); -#endif - /* check board */ - bc = in8 (PLD_PART_REG); -#if defined(CONFIG_TARGET_MIP405T) - if((bc & 0x80)==0) - SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n"); -#else - if((bc & 0x80)==0x80) - SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); -#endif - /* set-up the chipselect machine */ - mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */ - tmp = mfdcr (EBC0_CFGDATA); - if ((tmp & 0x00002000) == 0) { - /* MPS Boot, set up the flash */ - mtdcr (EBC0_CFGADDR, PB1AP); - mtdcr (EBC0_CFGDATA, FLASH_AP); - mtdcr (EBC0_CFGADDR, PB1CR); - mtdcr (EBC0_CFGDATA, FLASH_CR); - } else { - /* Flash boot, set up the MPS */ - mtdcr (EBC0_CFGADDR, PB1AP); - mtdcr (EBC0_CFGDATA, MPS_AP); - mtdcr (EBC0_CFGADDR, PB1CR); - mtdcr (EBC0_CFGDATA, MPS_CR); - } - /* set up UART0 (CS2) and UART1 (CS3) */ - mtdcr (EBC0_CFGADDR, PB2AP); - mtdcr (EBC0_CFGDATA, UART0_AP); - mtdcr (EBC0_CFGADDR, PB2CR); - mtdcr (EBC0_CFGDATA, UART0_CR); - mtdcr (EBC0_CFGADDR, PB3AP); - mtdcr (EBC0_CFGDATA, UART1_AP); - mtdcr (EBC0_CFGADDR, PB3CR); - mtdcr (EBC0_CFGDATA, UART1_CR); - bc = in8 (PLD_BOARD_CFG_REG); -#ifdef SDRAM_DEBUG - serial_puts ("\nstart SDRAM Setup\n"); - serial_puts ("\nBoard Rev: "); - write_hex (bc); - serial_puts ("\n"); -#endif - i = 0; - baseaddr = CONFIG_SYS_SDRAM_BASE; - while (sdram_table[i].sz != 0xff) { - if (sdram_table[i].boardtype == bc) - break; - i++; - } - if (sdram_table[i].boardtype != bc) - SDRAM_err ("No SDRAM table found for this board!!!\n"); -#ifdef SDRAM_DEBUG - serial_puts (" found table "); - write_hex (i); - serial_puts (" \n"); -#endif - /* since the ECC initialisation needs some time, - * we show that we're alive - */ - if (sdram_table[i].ecc) - serial_puts ("\nInitializing SDRAM, Please stand by"); - cal_val = sdram_table[i].cal - 1; /* Cas Latency */ - trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */ - trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ - tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ - /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ - /* trc_clocks is sum of trp_clocks + tras_clocks */ - trc_clocks = trp_clocks + tras_clocks; - /* get SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; - /* insert CASL value */ - sdram_tim |= ((unsigned long) (cal_val)) << 23; - /* insert PTA value */ - sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18; - /* insert CTP value */ - sdram_tim |= - ((unsigned long) (trc_clocks - trp_clocks - - trcd_clocks)) << 16; - /* insert LDF (always 01) */ - sdram_tim |= ((unsigned long) 0x01) << 14; - /* insert RFTA value */ - sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2; - /* insert RCD value */ - sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0; - - tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */ - /* insert SZ value; */ - tmp |= ((unsigned long) sdram_table[i].sz << 17); - /* get SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; - sdram_bank |= (baseaddr | tmp | 0x01); - -#ifdef SDRAM_DEBUG - serial_puts ("sdtr: "); - write_4hex (sdram_tim); - serial_puts ("\n"); -#endif - - /* write SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - mtdcr (SDRAM0_CFGDATA, sdram_tim); - -#ifdef SDRAM_DEBUG - serial_puts ("mb0cf: "); - write_4hex (sdram_bank); - serial_puts ("\n"); -#endif - - /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - mtdcr (SDRAM0_CFGDATA, sdram_bank); - - if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ - /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; - tmp |= 0x07F00000; - } else { - /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; - tmp |= 0x05F00000; - } - /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - mtdcr (SDRAM0_CFGDATA, tmp); - /* enable ECC if used */ -#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) - if (sdram_table[i].ecc) { - /* disable checking for all banks */ - unsigned long *p; -#ifdef SDRAM_DEBUG - serial_puts ("disable ECC.. "); -#endif - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp &= 0xff0fffff; /* disable all banks */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - /* set up SDRAM Controller with ECC enabled */ -#ifdef SDRAM_DEBUG - serial_puts ("setup SDRAM Controller.. "); -#endif - mtdcr (SDRAM0_CFGDATA, tmp); - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (600); -#ifdef SDRAM_DEBUG - serial_puts ("fill the memory..\n"); -#endif - serial_puts ("."); - /* now, fill all the memory */ - tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz); - p = (unsigned long) 0; - while ((unsigned long) p < tmp) { - *p++ = 0L; - if (!((unsigned long) p % 0x00800000)) /* every 8MByte */ - serial_puts ("."); - } - /* enable bank 0 */ - serial_puts ("."); -#ifdef SDRAM_DEBUG - serial_puts ("enable ECC\n"); -#endif - udelay (400); - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - tmp |= 0x00800000; /* enable bank 0 */ - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (400); - } else -#endif - { - /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - udelay (400); - } - serial_puts ("\n"); - return (0); -} - -int board_early_init_f (void) -{ - init_sdram (); - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the PIP405 board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive - | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive - | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for MIP405 board: - | An interrupt taken for the SouthBridge (IRQ 25) indicates that - | the Interrupt Controller in the South Bridge has caused the - | interrupt. The IC must be read to determine which device - | caused the interrupt. - | - +-------------------------------------------------------------------------*/ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - return 0; -} - -int board_early_init_r(void) -{ - int mode; - - /* - * since we are relocated, we can finally enable i-cache - * and set up the flash CS correctly - */ - icache_enable(); - setup_cs_reloc(); - /* get and display boot mode */ - mode = get_boot_mode(); - if (mode & BOOT_PCI) - printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? - "MPS" : "Flash"); - else - printf("%s Boot\n", (mode & BOOT_MPS) ? - "MPS" : "Flash"); - - return 0; -} - -/* - * Get some PLD Registers - */ - -unsigned short get_pld_parvers (void) -{ - unsigned short result; - unsigned char rc; - - rc = in8 (PLD_PART_REG); - result = (unsigned short) rc << 8; - rc = in8 (PLD_VERS_REG); - result |= rc; - return result; -} - - -void user_led0 (unsigned char on) -{ - if (on) - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4)); - else - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb)); -} - - -void ide_set_reset (int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - if (idereset) - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1)); - else { - udelay (10000); - out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe)); - } -} - - -/* ------------------------------------------------------------------------- */ - -void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var) -{ -#if !defined(CONFIG_TARGET_MIP405T) - unsigned char bc,rc,tmp; - int i; - - bc = in8 (PLD_BOARD_CFG_REG); - tmp = ~bc; - tmp &= 0xf; - rc = 0; - for (i = 0; i < 4; i++) { - rc <<= 1; - rc += (tmp & 0x1); - tmp >>= 1; - } - rc++; - if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */ - || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */ - && (rc==0x1)) /* Population Option 1 is a -3 */ - rc=3; - *pcbrev=(bc >> 4) & 0xf; - *var=rc; -#else - unsigned char bc; - bc = in8 (PLD_BOARD_CFG_REG); - *pcbrev=(bc >> 4) & 0xf; - *var=16-(bc & 0xf); -#endif -} - -/* - * Check Board Identity: - */ -/* serial String: "MIP405_1000" OR "MIP405T_1000" */ -#if !defined(CONFIG_TARGET_MIP405T) -#define BOARD_NAME "MIP405" -#else -#define BOARD_NAME "MIP405T" -#endif - -int checkboard (void) -{ - char s[50]; - unsigned char bc, var; - int i; - backup_t *b = (backup_t *) s; - - puts ("Board: "); - get_pcbrev_var(&bc,&var); - i = getenv_f("serial#", (char *)s, 32); - if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) { - get_backup_values (b); - if (strncmp (b->signature, "MPL\0", 4) != 0) { - puts ("### No HW ID - assuming " BOARD_NAME); - printf ("-%d Rev %c", var, 'A' + bc); - } else { - b->serial_name[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-%d Rev %c SN: %s", b->serial_name, var, - 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]); - } - } else { - s[sizeof(BOARD_NAME)-1] = 0; - printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc, - &s[sizeof(BOARD_NAME)]); - } - bc = in8 (PLD_EXT_CONF_REG); - printf (" Boot Config: 0x%x\n", bc); - return (0); -} - - -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -/* - dram_init() reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration -*/ -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -static int test_dram (unsigned long ramsize); - -int dram_init(void) -{ - - unsigned long bank_reg[4], tmp, bank_size; - int i; - unsigned long TotalSize; - - /* since the DRAM controller is allready set up, calculate the size with the - bank registers */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - bank_reg[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - bank_reg[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - bank_reg[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - bank_reg[3] = mfdcr (SDRAM0_CFGDATA); - TotalSize = 0; - for (i = 0; i < 4; i++) { - if ((bank_reg[i] & 0x1) == 0x1) { - tmp = (bank_reg[i] >> 17) & 0x7; - bank_size = 4 << tmp; - TotalSize += bank_size; - } - } - mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); - tmp = mfdcr (SDRAM0_CFGDATA); - - if (!tmp) - printf ("No "); - printf ("ECC "); - - test_dram (TotalSize * MEGA_BYTE); - gd->ram_size = TotalSize * MEGA_BYTE; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -static int test_dram (unsigned long ramsize) -{ -#ifdef SDRAM_DEBUG - mem_test (0L, ramsize, 1); -#endif - /* not yet implemented */ - return (1); -} - -/* used to check if the time in RTC is valid */ -static unsigned long start; -static struct rtc_time tm; - -int misc_init_r (void) -{ - /* adjust flash start and size as well as the offset */ - gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; - gd->bd->bi_flashoffset=0; - - /* check, if RTC is running */ - rtc_get (&tm); - start=get_timer(0); - /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) - mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); - - return (0); -} - - -void print_mip405_rev (void) -{ - unsigned char part, vers, pcbrev, var; - - get_pcbrev_var(&pcbrev,&var); - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n", - var, pcbrev + 'A', part & 0x7F, vers); -} - - -extern int mk_date (char *, struct rtc_time *); - -int last_stage_init (void) -{ - unsigned long stop; - struct rtc_time newtm; - char *s; - - /* write correct LED configuration */ - if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) { - printf ("Error writing to the PHY\n"); - } - /* since LED/CFG2 is not connected on the -2, - * write to correct capability information */ - if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) { - printf ("Error writing to the PHY\n"); - } - print_mip405_rev (); - stdio_print_current_devices (); - check_env (); - /* check if RTC time is valid */ - stop=get_timer(start); - while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */ - udelay(1000); - stop=get_timer(start); - } - rtc_get (&newtm); - if(tm.tm_sec==newtm.tm_sec) { - s=getenv("defaultdate"); - if(!s) - mk_date ("010112001970", &newtm); - else - if(mk_date (s, &newtm)!=0) { - printf("RTC: Bad date format in defaultdate\n"); - return 0; - } - rtc_reset (); - rtc_set(&newtm); - } - return 0; -} - -/*************************************************************************** - * some helping routines - */ - -int overwrite_console (void) -{ - /* return true if console should be overwritten */ - return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0); -} - - -/************************************************************************ -* Print MIP405 Info -************************************************************************/ -void print_mip405_info (void) -{ - unsigned char part, vers, cfg, irq_reg, com_mode, ext; - - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - cfg = in8 (PLD_BOARD_CFG_REG); - irq_reg = in8 (PLD_IRQ_REG); - com_mode = in8 (PLD_COM_MODE_REG); - ext = in8 (PLD_EXT_CONF_REG); - - printf ("PLD Part %d version %d\n", part & 0x7F, vers); - printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A'); - printf ("Population Options %d %d %d %d\n", (cfg) & 0x1, - (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1); - printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off"); - printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3); -#if !defined(CONFIG_TARGET_MIP405T) - printf ("User Config Switch %d %d %d %d %d %d %d %d\n", - (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, - (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, - (ext >> 6) & 0x1, (ext >> 7) & 0x1); - printf ("SER1 uses handshakes %s\n", - (ext & 0x80) ? "DTR/DSR" : "RTS/CTS"); -#else - printf ("User Config Switch %d %d %d %d %d %d %d %d\n", - (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1, - (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1, - (ext >> 6) & 0x1,(ext >> 7) & 0x1); -#endif - printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted"); - printf ("IRQs:\n"); - printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active"); -#if !defined(CONFIG_TARGET_MIP405T) - printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active"); - printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active"); -#endif - printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active"); - printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active"); - printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active"); -} diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h deleted file mode 100644 index b1f69aa..0000000 --- a/board/mpl/mip405/mip405.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - /**************************************************************************** - * Global routines used for MIP405 - *****************************************************************************/ -#ifndef __ASSEMBLY__ -/*int switch_cs(unsigned char boot);*/ - -extern int mem_test(unsigned long start, unsigned long ramsize,int mode); - -void user_led0(unsigned char on); - - -#endif -/* timings */ -/* PLD (CS7) */ -#define PLD_BME 0 /* Burst disable */ -#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */ -#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define PLD_OEN 1 /* Cycles from CS low to OE low */ -#define PLD_WBN 1 /* Cycles from CS low to WE low */ -#define PLD_WBF 1 /* Cycles from WE high to CS high */ -#define PLD_TH 2 /* Number of hold cycles after transfer */ -#define PLD_RE 0 /* Ready disabled */ -#define PLD_SOR 1 /* Sample on Ready disabled */ -#define PLD_BEM 0 /* Byte Write only active on Write cycles */ -#define PLD_PEN 0 /* Parity disable */ -#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \ - (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define PLD_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define PLD_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define PLD_BW 0 /* 16Bit */ -#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13)) - - -/* timings */ - -#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024)) -/* Dummy CS to get the board revision */ -#define BOARD_BME 0 /* Burst disable */ -#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ -#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define BOARD_OEN 1 /* Cycles from CS low to OE low */ -#define BOARD_WBN 1 /* Cycles from CS low to WE low */ -#define BOARD_WBF 1 /* Cycles from WE high to CS high */ -#define BOARD_TH 2 /* Number of hold cycles after transfer */ -#define BOARD_RE 0 /* Ready disabled */ -#define BOARD_SOR 1 /* Sample on Ready disabled */ -#define BOARD_BEM 0 /* Byte Write only active on Write cycles */ -#define BOARD_PEN 0 /* Parity disable */ -#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \ - (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define BOARD_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define BOARD_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define BOARD_BW 0 /* 16Bit */ -#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13)) - - -/* UART0 CS2 */ -#define UART0_BME 0 /* Burst disable */ -#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */ -#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define UART0_OEN 1 /* Cycles from CS low to OE low */ -#define UART0_WBN 1 /* Cycles from CS low to WE low */ -#define UART0_WBF 1 /* Cycles from WE high to CS high */ -#define UART0_TH 2 /* Number of hold cycles after transfer */ -#define UART0_RE 0 /* Ready disabled */ -#define UART0_SOR 1 /* Sample on Ready disabled */ -#define UART0_BEM 0 /* Byte Write only active on Write cycles */ -#define UART0_PEN 0 /* Parity disable */ -#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \ - (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define UART0_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define UART0_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define UART0_BW 0 /* 8Bit */ -#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) - -/* UART1 CS3 */ -#define UART1_AP UART0_AP /* same timing as UART0 */ -#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) - - -/* Flash CS0 or CS 1 */ -/* 0x7F8FFE80 slowest timing at all... */ -#define FLASH_BME_B 1 /* Burst enable */ -#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ -#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define FLASH_BME 0 /* Burst disable */ -#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define FLASH_OEN 1 /* Cycles from CS low to OE low */ -#define FLASH_WBN 1 /* Cycles from CS low to WE low */ -#define FLASH_WBF 1 /* Cycles from WE high to CS high */ -#define FLASH_TH 2 /* Number of hold cycles after transfer */ -#define FLASH_RE 0 /* Ready disabled */ -#define FLASH_SOR 1 /* Sample on Ready disabled */ -#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ -#define FLASH_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) -/* Access Parameter Register for Boot */ -#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define FLASH_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define FLASH_BW 1 /* 16Bit */ -/* CR register for Boot */ -#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) -/* CR register for non Boot */ -#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) - -/* MPS CS1 or CS0 */ -/* Boot CS: */ -#define MPS_BME_B 1 /* Burst enable */ -#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ -#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define MPS_BME 0 /* Burst disable */ -#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define MPS_OEN 1 /* Cycles from CS low to OE low */ -#define MPS_WBN 1 /* Cycles from CS low to WE low */ -#define MPS_WBF 1 /* Cycles from WE high to CS high */ -#define MPS_TH 2 /* Number of hold cycles after transfer */ -#define MPS_RE 0 /* Ready disabled */ -#define MPS_SOR 1 /* Sample on Ready disabled */ -#define MPS_BEM 0 /* Byte Write only active on Write cycles */ -#define MPS_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) -/* Access Parameter Register for Boot */ -#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define MPS_BS 2 /* 4 MByte */ -#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define MPS_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define MPS_BW 0 /* 8Bit */ -/* CR register for Boot */ -#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13)) -/* CR register for non Boot */ -#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) diff --git a/board/mpl/pip405/Kconfig b/board/mpl/pip405/Kconfig deleted file mode 100644 index e7ae6af..0000000 --- a/board/mpl/pip405/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PIP405 - -config SYS_BOARD - default "pip405" - -config SYS_VENDOR - default "mpl" - -config SYS_CONFIG_NAME - default "PIP405" - -config ISO_STRING - string - default "MEV-10066-001" -endif diff --git a/board/mpl/pip405/MAINTAINERS b/board/mpl/pip405/MAINTAINERS deleted file mode 100644 index 9b3b974..0000000 --- a/board/mpl/pip405/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PIP405 BOARD -M: Denis Peter <d.peter@mpl.ch> -S: Maintained -F: board/mpl/pip405/ -F: include/configs/PIP405.h -F: configs/PIP405_defconfig diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile deleted file mode 100644 index 0a3d059..0000000 --- a/board/mpl/pip405/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pip405.o cmd_pip405.o \ - ../common/pci.o \ - ../common/isa.o \ - ../common/kbd.o \ - ../common/usb_uhci.o \ - ../common/common_util.o -obj-y += init.o diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README deleted file mode 100644 index f039817..0000000 --- a/board/mpl/pip405/README +++ /dev/null @@ -1,371 +0,0 @@ -U-Boot Changes due to PIP405 Port: -=================================== - -Changed files: -============== -- MAKEALL added PIP405 -- makefile added PIP405 -- common/Makefile added Floppy disk and SCSI support -- common/board.c added PIP405, SCSI support, get_PCI_freq() -- common/bootm.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE -- common/cmd_i2c.c added "defined(CONFIG_PIP405)" -- common/cmd_ide.c changed div. functions to work with block device - description - added ATAPI support -- common/command.c added SCSI and Floppy support -- common/console.c replaced // with /* comments - added console settings from environment -- common/devices.c added ISA keyboard init -- common/main.c corrected the read of bootdelay -- arch/powerpc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405 -- arch/powerpc/cpu/ppc4xx/i2c.c added 16bit read write I2C support - added page write -- arch/powerpc/cpu/ppc4xx/speed.c added get_PCI_freq -- arch/powerpc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING -- disk/Makefile added part_iso for CD support -- disk/part.c changed to work with block device description - added ISO CD support - added dev_print (was ide_print in cmd_ide.c) -- disk/part_dos.c changed to work with block device description -- disk/part_mac.c changed to work with block device description -- include/ata.h added ATAPI commands -- include/cmd_bsp.h added PIP405 commands definitions -- include/cmd_condefs.h added Floppy and SCSI support -- include/cmd_disk.h changed to work with block device description -- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_SCSI -- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_SCSI -- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4 -- include/i2c.h added "defined(CONFIG_PIP405)" -- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE -- include/u-boot.h moved partitions functions definitions to part.h - added "defined(CONFIG_PIP405)" - added get_PCI_freq() definition -- rtc/Makefile added MC146818 RTC support -- tools/mkimage.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE - -Added files: -============ -- board/pip405 directory for PIP405 -- board/pip405/cmd_pip405.c board specific commands -- board/pip405/config.mk config make -- board/pip405/flash.c flash support -- board/pip405/init.s start-up -- board/pip405/kbd.c keyboard support -- board/pip405/kbd.h keyboard support -- board/pip405/Makefile Makefile -- board/pip405/pci_piix4.h southbridge definitions -- board/pip405/pci_pip405.c PCI support for PIP405 -- board/pip405/pci_pip405.h PCI support for PIP405 -- board/pip405/pip405.c PIP405 board init -- board/pip405/pip405.h PIP405 board init -- board/pip405/pip405_isa.c ISA support -- board/pip405/pip405_isa.h ISA support -- board/pip405/u-boot.lds Linker description -- board/pip405/u-boot.lds.debugLinker description debug -- board/pip405/sym53c8xx.c SYM53C810A support -- board/pip405/sym53c8xx_defs.h SYM53C810A definitions -- board/pip405/vga_table.h definitions of tables for VGA -- board/pip405/video.c CT69000 support -- board/pip405/video.h CT69000 support -- common/cmd_fdc.c Floppy disk support -- common/cmd_scsi.c SCSI support -- disk/part_iso.c ISO CD ROM support -- disk/part_iso.h ISO CD ROM support -- include/cmd_fdc.h command forFloppy disk support -- include/cmd_scsi.h command for SCSI support -- include/part.h partitions functions definitions - (was part of u-boot.h) -- include/scsi.h SCSI support -- rtc/mc146818.c MC146818 RTC support - - -New Config Switches: -==================== -For detailed description, refer to the corresponding paragraph in the -section "Changes". - -New Commands: -------------- -CONFIG_SCSI SCSI Support -CONFIG_CMF_FDC Floppy disk support - -IDE additions: --------------- -CONFIG_IDE_RESET_ROUTINE defines that instead of a reset Pin, - the routine ide_set_reset(int idereset) is used. -ATAPI support (experimental) ----------------------------- -CONFIG_ATAPI enables ATAPI Support - -SCSI support (experimental) only SYM53C8xx supported ----------------------------------------------------- -CONFIG_SCSI_SYM53C8XX type of SCSI controller -CONFIG_SYS_SCSI_MAX_LUN 8 number of supported LUNs -CONFIG_SYS_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6) -CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN - maximum of Target devices (multiple LUN support - for boot) - -ISO (CD-Boot) partition support (Experimental) ----------------------------------------------- -CONFIG_ISO_PARTITION CD-boot support - -RTC ----- -CONFIG_RTC_MC146818 MC146818 RTC support - -Video: ------- -CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip - CONFIG_VIDEO must be defined also - -External peripheral base address: ---------------------------------- -CONFIG_SYS_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts - _must_ be defined for ISA-bus parts - -Identify: ---------- -CONFIG_IDENT_STRING added to the U_BOOT_VERSION String - -Environment / Console: ----------------------- - -CONFIG_SYS_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from - the values stored in the evironment. - -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the - values stored in the environment or the standard - serial in/out put should be assigned to the console. - -CONFIG_SYS_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching - are stored in the environment. - -PIP405 specific: ----------------- -CONFIG_PORT_ADDR address used to read boot configuration -MULTI_PURPOSE_SOCKET_ADDR address of the multi purpose socked -SDRAM_EEPROM_WRITE_ADDRESS addresses of the serial presence detect -SDRAM_EEPROM_READ_ADDRESS EEPROM on the SDRAM module. - - -Changes: -======== - -Added Devices: -============== - -Floppy support: ---------------- -Support of a standard floppy disk controller at address CONFIG_SYS_ISA_IO_BASE_ADDRESS -+ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk -with a image header (see: mkimage). No interrupts and no DMA are used for this. -Added files: -- common/cmd_fdc.c -- include/cmd_fdc.h - -SCSI support: -------------- -Support for Symbios SYM53C810A chip. Implemented as follows: -- without disconnect -- only asynchrounous -- multiple LUN support (caution, needs a lot of RAM. define CONFIG_SYS_SCSI_MAX_LUN 1 to - save RAM) -- multiple SCSI ID support -- no write support -- analyses the MAC, DOS and ISO pratition similar to the IDE support -- allows booting from SCSI devices similar to the IDE support. -The device numbers are not assigned like they are within the IDE support. The first -device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all -LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the -device descriptors are not yet dynamically allocated. 56 boot devices are overkill -anyway. Please refer to the section "Todo" chapter "block device support enhancement". -The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus. -Added files: -- common/cmd_scsi.c -- common/board.c -- include/cmd_scsi.h -- include/scsi.h -- board/pip405/sym53c8xx.c -- board/pip405/sym53c8xx_defs.h - -ATAPI support (IDE changes): ----------------------------- -Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c. -To support a hardreset, when the IDE reset pin is not connected to the -CONFIG_SYS_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When -this switch is enabled the routine void ide_set_reset(int idereset) must be -within the board specific files. -Only read from ATAPI devices are supported. -Found out that the function trim_trail cuts off the last character if the whole -string is filled. Added function cpy_ident instead, which trims also leading -spaces and copies the string in the buffer. -Changed files: -- common/cmd_ide.c -- include/ata.h - -ISO partition support: ----------------------- -Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain -the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0. -The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI -("diskboot") and SCSI ("scsiboot") devices. -Added files: -- disk/iso_part.c -- disk/iso_part.h - -Block device changes: ---------------------- -To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter -blk_desc will be used when accessing the functions in these files. The block -device descriptor (blk_desc) contains a pointer to the read routine of the -device, which will be used to read blocks from the device. -Renamed function ide_print to dev_print and moved it to the file disk/part.c to use -it for IDE ATAPI and SCSI devices. -Please refer to the section "Todo" chapter "block device support enhancement". -Added files: -- include/part.h -changed files: -- disk/dos_part.c -- disk/dos_part.h -- disk/mac_part.c -- disk/mac_part.h -- disk/part.c -- common/cmd_ide.c -- include/u-boot.h - - -MC146818 RTC support: ---------------------- -Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO -base address must be defined with CONFIG_SYS_ISA_IO_BASE_ADDRESS. -Added files: -- rtc/mc146818.c - -Standard ISA bus Keyboard support: ----------------------------------- -Added support for the standard PC kyeboard controller. For the PIP405 the superIO -controller must be set up previously. The keyboard uses the standard ISA IRQ, so -the ISA PIC must also be set up. -Added files: -- board/pip405/kbd.c -- board/pip405/kbd.h -- board/pip405/pip405_isa.c -- board/pip405/pip405_isa.h - -Chips and Technologie 69000 VGA controller support: ---------------------------------------------------- -Added support for the CT69000 VGA controller. -Added files: -- board/pip405/video.c -- board/pip405/video.h -- board/pip405/vga_table.h - - -Changed Items: -============== - -Identify: ---------- -Added the config variable CONFIG_IDENT_STRING which will be added to the -"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate -and custom versions. -Changed files: -- arch/powerpc/cpu/ppc4xx/start.s - -Firmware Image: ---------------- -Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the -U-Boot update with prior CRC check. -Changed files: -- include/image.h -- tools/mkimage.c -- common/cmd_bootm.c - -Correct PCI Frequency for PPC405: ---------------------------------- -Added function (in arch/powerpc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU. -The PCI Frequency will now be set correct in the board description in common/board.c. -(was set to the busfreq before). -Changed files: -- arch/powerpc/cpu/ppc4xx/speed.c -- common/board.c - -I2C Stuff: ----------- -Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c. -Added 16bit read/write support for I2C (PPC405), and page write to -I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE. -Changed files: -- arch/powerpc/cpu/ppc4xx/i2c.c -- common/cmd_i2c.c - -Environment / Console: ----------------------- -Although in README.console described, the U-Boot has not assinged the values -found in the environment to the console. Corrected this behavior, but only if -CONFIG_SYS_CONSOLE_IS_IN_ENV is defined. -If CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the -values stored in the environment or the standard serial in/output should be -assigned to the console. This is useful if the environment values are not correct. -If CONFIG_SYS_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at -start-up time will be written to the environment. This means that if the -environment values are overwritten by the overwrite_console() routine, they will be -stored in the environment. -Changed files: -- common/console.c - -Correct bootdelay intepretation: --------------------------------- -Changed bootdelay read from the environment from simple_strtoul (unsigned) to -simple_strtol (signed), to be able to get a bootdelay of -1. -Changed files: -- common/main.c - -Todo: -===== - -Block device support enhancement: ---------------------------------- -Consider to unify the block device handling. Instead of using diskboot for IDE, -scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only -one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1", -"fd0" ???) to boot from. The other ide commands can be handled in the same way -("dev hda read.." instead of "ide read.." or "dev sda read.." instead of -"scsi read..."). Todo this, a common way of assign a block device to its name -(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0, -hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for -floppy ???) must be defined. -Maybe there are better ideas to do this. - -Console assingment: -------------------- -Consider to initialize and assign the console stdin, stdout and stderr as soon as -possible to see the boot messages also on an other console than serial. - - -Todo for PIP405: -================ - -LCD support for VGA: --------------------- -Add LCD support for the CT69000 - -Default environment: --------------------- -Consider to write a default environment to the OTP part of the EEPROM and use it -if the normal environment is not valid. Useful for serial# and ethaddr values. - -Watchdog: ---------- -Implement Watchdog. - -Files clean-up: ---------------- -Following files needs to be cleaned up: -- cmd_pip405.c -- flash.c -- pci_pip405.c -- pip405.c -- pip405_isa.c -Consider to split up the files in their functions. diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c deleted file mode 100644 index 43b182e..0000000 --- a/board/mpl/pip405/cmd_pip405.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * hacked for PIP405 - */ - -#include <common.h> -#include <command.h> -#include "pip405.h" -#include "../common/common_util.h" - - -extern void print_pip405_info(void); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - - -/* ------------------------------------------------------------------------- */ - -int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - - ulong led_on,led_nr; - - if (strcmp(argv[1], "info") == 0) - { - print_pip405_info(); - return 0; - } - if (strcmp(argv[1], "led") == 0) - { - led_nr = (ulong)simple_strtoul(argv[2], NULL, 10); - led_on = (ulong)simple_strtoul(argv[3], NULL, 10); - if(!led_nr) - user_led0(led_on); - else - user_led1(led_on); - return 0; - } - - return (do_mplcommon(cmdtp, flag, argc, argv)); -} -U_BOOT_CMD( - pip405, 6, 1, do_pip405, - "PIP405 specific Cmds", - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" - "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n" - "pip405 flash mps - updates U-Boot with image from MPS" -); - -/* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S deleted file mode 100644 index 292393e..0000000 --- a/board/mpl/pip405/init.S +++ /dev/null @@ -1,197 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/*----------------------------------------------------------------------------- - * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from - * cache since you can not reliably change a peripheral banks - * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT - * execute the code that modifies bank 0 timings from ROM, so - * we run it from cache. - * Bank 0 - Flash or Multi Purpose Socket - * Bank 1 - Multi Purpose Socket or Flash - * Bank 2 - not used - * Bank 3 - not used - * Bank 4 - not used - * Bank 5 - not used - * Bank 6 - used to switch on the 12V for the Multipurpose socket - * Bank 7 - Config Register - *-----------------------------------------------------------------------------*/ - -#include <configs/PIP405.h> -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> -#include <asm/ppc4xx.h> -#include "pip405.h" - - .globl ext_bus_cntlr_init - ext_bus_cntlr_init: - mflr r4 /* save link register */ - mfdcr r3,CPC0_PSR /* get strapping reg */ - andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ - bnelr /* jump back if PCI boot */ - - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 14; used to prefetch */ - mtctr r4 /* 14 cache lines to fit this function */ - /* in cache (gives us 8x14=112 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 14 cache lines */ - - /*------------------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing - * bank 0 timings. - *------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------------- - * decide boot up mode - *----------------------------------------------------------------------- */ - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - mfdcr r4,EBC0_CFGDATA - - andi. r0, r4, 0x2000 /* mask out irrelevant bits */ - beq 0f /* jump if 8 bit bus width */ - - /* setup 16 bit things - *----------------------------------------------------------------------- - * Memory Bank 0 (16 Bit Flash) initialization - *---------------------------------------------------------------------- */ - - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,(FLASH_AP_B)@h - ori r4,r4,(FLASH_AP_B)@l - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(FLASH_CR_B)@h - ori r4,r4,(FLASH_CR_B)@l - mtdcr EBC0_CFGDATA,r4 - b 1f - -0: - /* 8Bit boot mode: */ - /*----------------------------------------------------------------------- - * Memory Bank 0 Multi Purpose Socket initialization - *----------------------------------------------------------------------- */ - /* 0x7F8FFE80 slowest boot */ - addi r4,0,PB1AP - mtdcr EBC0_CFGADDR,r4 - addis r4,0,(MPS_AP_B)@h - ori r4,r4,(MPS_AP_B)@l - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB0CR - mtdcr EBC0_CFGADDR,r4 - /* BS=0x010(4MB),BU=0x3(R/W), */ - addis r4,0,(MPS_CR_B)@h - ori r4,r4,(MPS_CR_B)@l - mtdcr EBC0_CFGDATA,r4 - - -1: - /*----------------------------------------------------------------------- - * Memory Bank 2-3-4-5-6 (not used) initialization - *-----------------------------------------------------------------------*/ - addi r4,0,PB1CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB2CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB3CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB4CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB5CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB6CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - - addi r4,0,PB7CR - mtdcr EBC0_CFGADDR,r4 - addis r4,0,0x0000 - ori r4,r4,0x0000 - mtdcr EBC0_CFGDATA,r4 - nop /* pass2 DCR errata #8 */ - blr - -#if defined(CONFIG_BOOT_PCI) - .section .bootpg,"ax" - .globl _start_pci -/******************************************* - */ - -_start_pci: - /* first handle errata #68 / PCI_18 */ - iccci r0, r0 /* invalidate I-cache */ - lis r31, 0 - mticcr r31 /* ICCR = 0 (all uncachable) */ - isync - - mfccr0 r28 /* set CCR0[24] = 1 */ - ori r28, r28, 0x0080 - mtccr0 r28 - - /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ - lis r28, 0xEF40 - addi r28, r28, 0x0004 - stw r31, 0x0C(r28) /* clear PMM0PCIHA */ - lis r29, 0xFFF8 /* open 512 kByte */ - addi r29, r29, 0x0001/* and enable this region */ - stwbrx r29, r0, r28 /* write PMM0MA */ - - lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ - addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ - - lis r31, 0x8000 /* set en bit bus 0 */ - ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ - stwbrx r31, r0, r28 /* write it */ - - lwbrx r31, r0, r29 /* load XBCS register */ - oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ - stwbrx r31, r0, r29 /* write back XBCS register */ - - nop - nop - b _start /* normal start */ -#endif diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c deleted file mode 100644 index 408518d..0000000 --- a/board/mpl/pip405/pip405.c +++ /dev/null @@ -1,958 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - * - * TODO: clean-up - */ - -#include <common.h> -#include "pip405.h" -#include <asm/processor.h> -#include <i2c.h> -#include <stdio_dev.h> -#include "../common/isa.h" -#include "../common/common_util.h" - -DECLARE_GLOBAL_DATA_PTR; - -#undef SDRAM_DEBUG - -/* stdlib.h causes some compatibility problems; should fixe these! -- wd */ -#ifndef __ldiv_t_defined -typedef struct { - long int quot; /* Quotient */ - long int rem; /* Remainder */ -} ldiv_t; -extern ldiv_t ldiv (long int __numer, long int __denom); - -# define __ldiv_t_defined 1 -#endif - - -typedef enum { - SDRAM_NO_ERR, - SDRAM_SPD_COMM_ERR, - SDRAM_SPD_CHKSUM_ERR, - SDRAM_UNSUPPORTED_ERR, - SDRAM_UNKNOWN_ERR -} SDRAM_ERR; - -typedef struct { - const unsigned char mode; - const unsigned char row; - const unsigned char col; - const unsigned char bank; -} SDRAM_SETUP; - -static const SDRAM_SETUP sdram_setup_table[] = { - {1, 11, 9, 2}, - {1, 11, 10, 2}, - {2, 12, 9, 4}, - {2, 12, 10, 4}, - {3, 13, 9, 4}, - {3, 13, 10, 4}, - {3, 13, 11, 4}, - {4, 12, 8, 2}, - {4, 12, 8, 4}, - {5, 11, 8, 2}, - {5, 11, 8, 4}, - {6, 13, 8, 2}, - {6, 13, 8, 4}, - {7, 13, 9, 2}, - {7, 13, 10, 2}, - {0, 0, 0, 0} -}; - -static const unsigned char cal_indextable[] = { - 9, 23, 25 -}; - - -/* - * translate ns.ns/10 coding of SPD timing values - * into 10 ps unit values - */ - -unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version) -{ - unsigned short ns, ns10; - - /* isolate upper nibble */ - ns = (spd_byte >> 4) & 0x0F; - /* isolate lower nibble */ - ns10 = (spd_byte & 0x0F); - - return (ns * 100 + ns10 * 10); -} - -/* - * translate ns.ns/4 coding of SPD timing values - * into 10 ps unit values - */ - -unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version) -{ - unsigned short ns, ns4; - - /* isolate upper 6 bits */ - ns = (spd_byte >> 2) & 0x3F; - /* isloate lower 2 bits */ - ns4 = (spd_byte & 0x03); - - return (ns * 100 + ns4 * 25); -} - -/* - * translate ns coding of SPD timing values - * into 10 ps unit values - */ - -unsigned short NSto10PS (unsigned char spd_byte) -{ - return (spd_byte * 100); -} - -void SDRAM_err (const char *s) -{ -#ifndef SDRAM_DEBUG - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); -#endif - serial_puts ("\n"); - serial_puts (s); - serial_puts ("\n enable SDRAM_DEBUG for more info\n"); - for (;;); -} - - -#ifdef SDRAM_DEBUG - -void write_hex (unsigned char i) -{ - char cc; - - cc = i >> 4; - cc &= 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); - cc = i & 0xf; - if (cc > 9) - serial_putc (cc + 55); - else - serial_putc (cc + 48); -} - -void write_4hex (unsigned long val) -{ - write_hex ((unsigned char) (val >> 24)); - write_hex ((unsigned char) (val >> 16)); - write_hex ((unsigned char) (val >> 8)); - write_hex ((unsigned char) val); -} - -#endif - -int board_early_init_f (void) -{ - unsigned char datain[128]; - unsigned long sdram_size = 0; - SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; - unsigned long memclk; - unsigned long tmemclk = 0; - unsigned long tmp, bank, baseaddr, bank_size; - unsigned short i; - unsigned char rows, cols, banks, sdram_banks, density; - unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, - trc_clocks; - unsigned char cal_index, cal_val, spd_version, spd_chksum; - unsigned char buf[8]; -#ifdef SDRAM_DEBUG - unsigned char tctp_clocks; -#endif - - /* set up the config port */ - mtdcr (EBC0_CFGADDR, PB7AP); - mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); - mtdcr (EBC0_CFGADDR, PB7CR); - mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR); - - memclk = get_bus_freq (tmemclk); - tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - -#ifdef SDRAM_DEBUG - (void) get_clocks (); - gd->baudrate = 9600; - serial_init (); - serial_puts ("\nstart SDRAM Setup\n"); -#endif - - /* Read Serial Presence Detect Information */ - i2c_set_bus_num(0); - for (i = 0; i < 128; i++) - datain[i] = 127; - i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); -#ifdef SDRAM_DEBUG - serial_puts ("\ni2c_read returns "); - write_hex (i); - serial_puts ("\n"); -#endif - -#ifdef SDRAM_DEBUG - for (i = 0; i < 128; i++) { - write_hex (datain[i]); - serial_puts (" "); - if (((i + 1) % 16) == 0) - serial_puts ("\n"); - } - serial_puts ("\n"); -#endif - spd_chksum = 0; - for (i = 0; i < 63; i++) { - spd_chksum += datain[i]; - } /* endfor */ - if (datain[63] != spd_chksum) { -#ifdef SDRAM_DEBUG - serial_puts ("SPD chksum: 0x"); - write_hex (datain[63]); - serial_puts (" != calc. chksum: 0x"); - write_hex (spd_chksum); - serial_puts ("\n"); -#endif - SDRAM_err ("SPD checksum Error"); - } - /* SPD seems to be ok, use it */ - - /* get SPD version */ - spd_version = datain[62]; - - /* do some sanity checks on the kind of RAM */ - if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */ - (datain[2] != 0x04) || /* if not SDRAM */ - (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ - (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ - (datain[126] == 0x66)) /* or a 66MHz modules */ - SDRAM_err ("unsupported SDRAM"); -#ifdef SDRAM_DEBUG - serial_puts ("SDRAM sanity ok\n"); -#endif - - /* get number of rows/cols/banks out of byte 3+4+5 */ - rows = datain[3]; - cols = datain[4]; - banks = datain[5]; - - /* get number of SDRAM banks out of byte 17 and - supported CAS latencies out of byte 18 */ - sdram_banks = datain[17]; - supported_cal = datain[18] & ~0x81; - - while (t->mode != 0) { - if ((t->row == rows) && (t->col == cols) - && (t->bank == sdram_banks)) - break; - t++; - } /* endwhile */ - -#ifdef SDRAM_DEBUG - serial_puts ("rows: "); - write_hex (rows); - serial_puts (" cols: "); - write_hex (cols); - serial_puts (" banks: "); - write_hex (banks); - serial_puts (" mode: "); - write_hex (t->mode); - serial_puts ("\n"); -#endif - if (t->mode == 0) - SDRAM_err ("unsupported SDRAM"); - /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */ -#ifdef SDRAM_DEBUG - serial_puts ("tRP: "); - write_hex (datain[27]); - serial_puts ("\ntRCD: "); - write_hex (datain[29]); - serial_puts ("\ntRAS: "); - write_hex (datain[30]); - serial_puts ("\n"); -#endif - - trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk; - trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk; - tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk; - density = datain[31]; - - /* trc_clocks is sum of trp_clocks + tras_clocks */ - trc_clocks = trp_clocks + tras_clocks; - -#ifdef SDRAM_DEBUG - /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ - tctp_clocks = - ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + - (tmemclk - 1)) / tmemclk; - - serial_puts ("c_RP: "); - write_hex (trp_clocks); - serial_puts ("\nc_RCD: "); - write_hex (trcd_clocks); - serial_puts ("\nc_RAS: "); - write_hex (tras_clocks); - serial_puts ("\nc_RC: (RP+RAS): "); - write_hex (trc_clocks); - serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): "); - write_hex (tctp_clocks); - serial_puts ("\nt_CTP: RAS - RCD: "); - write_hex ((unsigned - char) ((NSto10PS (datain[30]) - - NSto10PS (datain[29])) >> 8)); - write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29]))); - serial_puts ("\ntmemclk: "); - write_hex ((unsigned char) (tmemclk >> 8)); - write_hex ((unsigned char) (tmemclk)); - serial_puts ("\n"); -#endif - - - cal_val = 255; - for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) { - /* is this CAS latency supported ? */ - if ((supported_cal >> i) & 0x01) { - buf[0] = datain[cal_indextable[cal_index]]; - if (cal_index < 2) { - if (NS10to10PS (buf[0], spd_version) <= tmemclk) - cal_val = i; - } else { - /* SPD bytes 25+26 have another format */ - if (NS4to10PS (buf[0], spd_version) <= tmemclk) - cal_val = i; - } /* endif */ - cal_index++; - } /* endif */ - } /* endfor */ -#ifdef SDRAM_DEBUG - serial_puts ("CAL: "); - write_hex (cal_val + 1); - serial_puts ("\n"); -#endif - - if (cal_val == 255) - SDRAM_err ("unsupported SDRAM"); - - /* get SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; - /* insert CASL value */ -/* tmp |= ((unsigned long)cal_val) << 23; */ - tmp |= ((unsigned long) cal_val) << 23; - /* insert PTA value */ - tmp |= ((unsigned long) (trp_clocks - 1)) << 18; - /* insert CTP value */ -/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */ - tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16; - /* insert LDF (always 01) */ - tmp |= ((unsigned long) 0x01) << 14; - /* insert RFTA value */ - tmp |= ((unsigned long) (trc_clocks - 4)) << 2; - /* insert RCD value */ - tmp |= ((unsigned long) (trcd_clocks - 1)) << 0; - -#ifdef SDRAM_DEBUG - serial_puts ("sdtr: "); - write_4hex (tmp); - serial_puts ("\n"); -#endif - - /* write SDRAM timing register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_TR); - mtdcr (SDRAM0_CFGDATA, tmp); - baseaddr = CONFIG_SYS_SDRAM_BASE; - bank_size = (((unsigned long) density) << 22) / 2; - /* insert AM value */ - tmp = ((unsigned long) t->mode - 1) << 13; - /* insert SZ value; */ - switch (bank_size) { - case 0x00400000: - tmp |= ((unsigned long) 0x00) << 17; - break; - case 0x00800000: - tmp |= ((unsigned long) 0x01) << 17; - break; - case 0x01000000: - tmp |= ((unsigned long) 0x02) << 17; - break; - case 0x02000000: - tmp |= ((unsigned long) 0x03) << 17; - break; - case 0x04000000: - tmp |= ((unsigned long) 0x04) << 17; - break; - case 0x08000000: - tmp |= ((unsigned long) 0x05) << 17; - break; - case 0x10000000: - tmp |= ((unsigned long) 0x06) << 17; - break; - default: - SDRAM_err ("unsupported SDRAM"); - } /* endswitch */ - /* get SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; - bank |= (baseaddr | tmp | 0x01); -#ifdef SDRAM_DEBUG - serial_puts ("bank0: baseaddr: "); - write_4hex (baseaddr); - serial_puts (" banksize: "); - write_4hex (bank_size); - serial_puts (" mb0cf: "); - write_4hex (bank); - serial_puts ("\n"); -#endif - baseaddr += bank_size; - sdram_size += bank_size; - - /* write SDRAM bank 0 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - mtdcr (SDRAM0_CFGDATA, bank); - - /* get SDRAM bank 1 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; - sdram_size = 0; - -#ifdef SDRAM_DEBUG - serial_puts ("bank1: baseaddr: "); - write_4hex (baseaddr); - serial_puts (" banksize: "); - write_4hex (bank_size); -#endif - if (banks == 2) { - bank |= (baseaddr | tmp | 0x01); - baseaddr += bank_size; - sdram_size += bank_size; - } /* endif */ -#ifdef SDRAM_DEBUG - serial_puts (" mb1cf: "); - write_4hex (bank); - serial_puts ("\n"); -#endif - /* write SDRAM bank 1 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - mtdcr (SDRAM0_CFGDATA, bank); - - /* get SDRAM bank 2 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; - - bank |= (baseaddr | tmp | 0x01); - -#ifdef SDRAM_DEBUG - serial_puts ("bank2: baseaddr: "); - write_4hex (baseaddr); - serial_puts (" banksize: "); - write_4hex (bank_size); - serial_puts (" mb2cf: "); - write_4hex (bank); - serial_puts ("\n"); -#endif - - baseaddr += bank_size; - sdram_size += bank_size; - - /* write SDRAM bank 2 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - mtdcr (SDRAM0_CFGDATA, bank); - - /* get SDRAM bank 3 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; - -#ifdef SDRAM_DEBUG - serial_puts ("bank3: baseaddr: "); - write_4hex (baseaddr); - serial_puts (" banksize: "); - write_4hex (bank_size); -#endif - - if (banks == 2) { - bank |= (baseaddr | tmp | 0x01); - baseaddr += bank_size; - sdram_size += bank_size; - } - /* endif */ -#ifdef SDRAM_DEBUG - serial_puts (" mb3cf: "); - write_4hex (bank); - serial_puts ("\n"); -#endif - - /* write SDRAM bank 3 register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - mtdcr (SDRAM0_CFGDATA, bank); - - - /* get SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; - - if (tmemclk < NSto10PS (16)) - tmp |= 0x05F00000; - else - tmp |= 0x03F80000; - - /* write SDRAM refresh interval register */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR); - mtdcr (SDRAM0_CFGDATA, tmp); - - /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; - mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG); - mtdcr (SDRAM0_CFGDATA, tmp); - - - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the PIP405 board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive - | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive - | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for PIP405 board: - | An interrupt taken for the SouthBridge (IRQ 25) indicates that - | the Interrupt Controller in the South Bridge has caused the - | interrupt. The IC must be read to determine which device - | caused the interrupt. - | - +-------------------------------------------------------------------------*/ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - -int board_early_init_r(void) -{ - int mode; - - /* - * since we are relocated, we can finally enable i-cache - * and set up the flash CS correctly - */ - icache_enable(); - setup_cs_reloc(); - /* get and display boot mode */ - mode = get_boot_mode(); - if (mode & BOOT_PCI) - printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? - "MPS" : "Flash"); - else - printf("%s Boot\n", (mode & BOOT_MPS) ? - "MPS" : "Flash"); - - return 0; -} -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - char s[50]; - unsigned char bc; - int i; - backup_t *b = (backup_t *) s; - - puts ("Board: "); - - i = getenv_f("serial#", (char *)s, 32); - if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { - get_backup_values (b); - if (strncmp (b->signature, "MPL\0", 4) != 0) { - puts ("### No HW ID - assuming PIP405"); - } else { - b->serial_name[6] = 0; - printf ("%s SN: %s", b->serial_name, - &b->serial_name[7]); - } - } else { - s[6] = 0; - printf ("%s SN: %s", s, &s[7]); - } - bc = in8 (CONFIG_PORT_ADDR); - printf (" Boot Config: 0x%x\n", bc); - return (0); -} - - -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -/* - dram_init() reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration -*/ -/* ------------------------------------------------------------------------- */ -/* ------------------------------------------------------------------------- */ -static int test_dram (unsigned long ramsize); - -int dram_init(void) -{ - unsigned long bank_reg[4], tmp, bank_size; - int i, ds; - unsigned long TotalSize; - - ds = 0; - /* since the DRAM controller is allready set up, - * calculate the size with the bank registers - */ - mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); - bank_reg[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); - bank_reg[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); - bank_reg[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); - bank_reg[3] = mfdcr (SDRAM0_CFGDATA); - TotalSize = 0; - for (i = 0; i < 4; i++) { - if ((bank_reg[i] & 0x1) == 0x1) { - tmp = (bank_reg[i] >> 17) & 0x7; - bank_size = 4 << tmp; - TotalSize += bank_size; - } else - ds = 1; - } - if (ds == 1) - printf ("single-sided DIMM "); - else - printf ("double-sided DIMM "); - test_dram (TotalSize * 1024 * 1024); - /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */ - (void) get_clocks(); - if (gd->cpu_clk > 220000000) - TotalSize /= 2; - gd->ram_size = TotalSize * 1024 * 1024; - - return 0; -} - -/* ------------------------------------------------------------------------- */ - - -static int test_dram (unsigned long ramsize) -{ - /* not yet implemented */ - return (1); -} - -int misc_init_r (void) -{ - /* adjust flash start and size as well as the offset */ - gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; - gd->bd->bi_flashoffset=0; - - /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) - mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); - - return (0); -} - -/*************************************************************************** - * some helping routines - */ - -int overwrite_console (void) -{ - /* return true if console should be overwritten */ - return in8(CONFIG_PORT_ADDR) & 0x1; -} - - -extern int isa_init (void); - - -void print_pip405_rev (void) -{ - unsigned char part, vers, cfg; - - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - cfg = in8 (PLD_BOARD_CFG_REG); - printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n", - 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf, - vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf); -} - -extern void check_env(void); - - -int last_stage_init (void) -{ - print_pip405_rev (); - isa_init (); - stdio_print_current_devices (); - check_env(); - return 0; -} - -/************************************************************************ -* Print PIP405 Info -************************************************************************/ -void print_pip405_info (void) -{ - unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr, - compwr, nicvga, scsirst; - - part = in8 (PLD_PART_REG); - vers = in8 (PLD_VERS_REG); - cfg = in8 (PLD_BOARD_CFG_REG); - ledu = in8 (PLD_LED_USER_REG); - sysman = in8 (PLD_SYS_MAN_REG); - flashcom = in8 (PLD_FLASH_COM_REG); - can = in8 (PLD_CAN_REG); - serpwr = in8 (PLD_SER_PWR_REG); - compwr = in8 (PLD_COM_PWR_REG); - nicvga = in8 (PLD_NIC_VGA_REG); - scsirst = in8 (PLD_SCSI_RST_REG); - printf ("PLD Part %d version %d\n", - part & 0xf, vers & 0xf); - printf ("PLD Part %d version %d\n", - (part >> 4) & 0xf, (vers >> 4) & 0xf); - printf ("Board Revision %c\n", (cfg & 0xf) + 'A'); - printf ("Population Options %d %d %d %d\n", - (cfg >> 4) & 0x1, (cfg >> 5) & 0x1, - (cfg >> 6) & 0x1, (cfg >> 7) & 0x1); - printf ("User LED0 %s User LED1 %s\n", - ((ledu & 0x1) == 0x1) ? "on" : "off", - ((ledu & 0x2) == 0x2) ? "on" : "off"); - printf ("Additionally Options %d %d\n", - (ledu >> 2) & 0x1, (ledu >> 3) & 0x1); - printf ("User Config Switch %d %d %d %d\n", - (ledu >> 4) & 0x1, (ledu >> 5) & 0x1, - (ledu >> 6) & 0x1, (ledu >> 7) & 0x1); - switch (sysman & 0x3) { - case 0: - printf ("PCI Clocks are running\n"); - break; - case 1: - printf ("PCI Clocks are stopped in POS State\n"); - break; - case 2: - printf ("PCI Clocks are stopped when PCI_STP# is asserted\n"); - break; - case 3: - printf ("PCI Clocks are stopped\n"); - break; - } - switch ((sysman >> 2) & 0x3) { - case 0: - printf ("Main Clocks are running\n"); - break; - case 1: - printf ("Main Clocks are stopped in POS State\n"); - break; - case 2: - case 3: - printf ("PCI Clocks are stopped\n"); - break; - } - printf ("INIT asserts %sINT2# (SMI)\n", - ((sysman & 0x10) == 0x10) ? "" : "not "); - printf ("INIT asserts %sINT1# (NMI)\n", - ((sysman & 0x20) == 0x20) ? "" : "not "); - printf ("INIT occurred %d\n", (sysman >> 6) & 0x1); - printf ("SER1 is routed to %s\n", - ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232"); - printf ("COM2 is routed to %s\n", - ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232"); - printf ("RS485 is configured as %s duplex\n", - ((flashcom & 0x4) == 0x4) ? "full" : "half"); - printf ("RS485 is connected to %s\n", - ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2"); - printf ("SER1 uses handshakes %s\n", - ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS"); - printf ("Bootflash is %swriteprotected\n", - ((flashcom & 0x20) == 0x20) ? "not " : ""); - printf ("Bootflash VPP is %s\n", - ((flashcom & 0x40) == 0x40) ? "on" : "off"); - printf ("Bootsector is %swriteprotected\n", - ((flashcom & 0x80) == 0x80) ? "not " : ""); - switch ((can) & 0x3) { - case 0: - printf ("CAN Controller is on address 0x1000..0x10FF\n"); - break; - case 1: - printf ("CAN Controller is on address 0x8000..0x80FF\n"); - break; - case 2: - printf ("CAN Controller is on address 0xE000..0xE0FF\n"); - break; - case 3: - printf ("CAN Controller is disabled\n"); - break; - } - switch ((can >> 2) & 0x3) { - case 0: - printf ("CAN Controller Reset is ISA Reset\n"); - break; - case 1: - printf ("CAN Controller Reset is ISA Reset and POS State\n"); - break; - case 2: - case 3: - printf ("CAN Controller is in reset\n"); - break; - } - if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13)) - printf ("CAN Interrupt is disabled\n"); - else - printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf); - switch (serpwr & 0x3) { - case 0: - printf ("SER0 Drivers are enabled\n"); - break; - case 1: - printf ("SER0 Drivers are disabled in the POS state\n"); - break; - case 2: - case 3: - printf ("SER0 Drivers are disabled\n"); - break; - } - switch ((serpwr >> 2) & 0x3) { - case 0: - printf ("SER1 Drivers are enabled\n"); - break; - case 1: - printf ("SER1 Drivers are disabled in the POS state\n"); - break; - case 2: - case 3: - printf ("SER1 Drivers are disabled\n"); - break; - } - switch (compwr & 0x3) { - case 0: - printf ("COM1 Drivers are enabled\n"); - break; - case 1: - printf ("COM1 Drivers are disabled in the POS state\n"); - break; - case 2: - case 3: - printf ("COM1 Drivers are disabled\n"); - break; - } - switch ((compwr >> 2) & 0x3) { - case 0: - printf ("COM2 Drivers are enabled\n"); - break; - case 1: - printf ("COM2 Drivers are disabled in the POS state\n"); - break; - case 2: - case 3: - printf ("COM2 Drivers are disabled\n"); - break; - } - switch ((nicvga) & 0x3) { - case 0: - printf ("PHY is running\n"); - break; - case 1: - printf ("PHY is in Power save mode in POS state\n"); - break; - case 2: - case 3: - printf ("PHY is in Power save mode\n"); - break; - } - switch ((nicvga >> 2) & 0x3) { - case 0: - printf ("VGA is running\n"); - break; - case 1: - printf ("VGA is in Power save mode in POS state\n"); - break; - case 2: - case 3: - printf ("VGA is in Power save mode\n"); - break; - } - printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not "); - printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not "); - printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1, - (nicvga >> 7) & 0x1); - switch ((scsirst) & 0x3) { - case 0: - printf ("SCSI Controller is running\n"); - break; - case 1: - printf ("SCSI Controller is in Power save mode in POS state\n"); - break; - case 2: - case 3: - printf ("SCSI Controller is in Power save mode\n"); - break; - } - printf ("SCSI termination is %s\n", - ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled"); - printf ("SCSI Controller is %sreseted\n", - ((scsirst & 0x10) == 0x10) ? "" : "not "); - printf ("IDE disks are %sreseted\n", - ((scsirst & 0x20) == 0x20) ? "" : "not "); - printf ("ISA Bus is %sreseted\n", - ((scsirst & 0x40) == 0x40) ? "" : "not "); - printf ("Super IO is %sreseted\n", - ((scsirst & 0x80) == 0x80) ? "" : "not "); -} - -void user_led0 (unsigned char on) -{ - if (on == true) - out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); - else - out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); -} - -void user_led1 (unsigned char on) -{ - if (on == true) - out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); - else - out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); -} - -void ide_set_reset (int idereset) -{ - /* if reset = 1 IDE reset will be asserted */ - unsigned char resreg; - - resreg = in8 (PLD_SCSI_RST_REG); - if (idereset == 1) - resreg |= 0x20; - else { - udelay(10000); - resreg &= 0xdf; - } - out8 (PLD_SCSI_RST_REG, resreg); -} diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h deleted file mode 100644 index 1f07d79..0000000 --- a/board/mpl/pip405/pip405.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - /**************************************************************************** - * Global routines used for PIP405 - *****************************************************************************/ - -#ifndef __ASSEMBLY__ - -extern int mem_test(unsigned long start, unsigned long ramsize,int mode); - -void print_pip405_info(void); - -void user_led0(unsigned char on); -void user_led1(unsigned char on); - - -#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800 -#define PLD_PART_REG PLD_BASE_ADDRESS + 0 -#define PLD_VERS_REG PLD_BASE_ADDRESS + 1 -#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2 -#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3 -#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4 -#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5 -#define PLD_CAN_REG PLD_BASE_ADDRESS + 6 -#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7 -#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8 -#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9 -#define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA - -#define PIIX4_VENDOR_ID 0x8086 -#define PIIX4_IDE_DEV_ID 0x7111 - -#endif - -/* timings */ - -/* CS Config register (CS7) */ -#define CONFIG_PORT_BME 0 /* Burst disable */ -#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ -#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */ -#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */ -#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */ -#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */ -#define CONFIG_PORT_RE 0 /* Ready disabled */ -#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */ -#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */ -#define CONFIG_PORT_PEN 0 /* Parity disable */ -#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ - (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define CONFIG_PORT_BS 0 /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define CONFIG_PORT_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define CONFIG_PORT_BW 0 /* 16Bit */ -#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13)) - -/* Flash CS0 or CS 1 */ -/* 0x7F8FFE80 slowest timing at all... */ -#define FLASH_BME_B 1 /* Burst enable */ -#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ -#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define FLASH_BME 0 /* Burst disable */ -#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define FLASH_OEN 1 /* Cycles from CS low to OE low */ -#define FLASH_WBN 1 /* Cycles from CS low to WE low */ -#define FLASH_WBF 1 /* Cycles from WE high to CS high */ -#define FLASH_TH 2 /* Number of hold cycles after transfer */ -#define FLASH_RE 0 /* Ready disabled */ -#define FLASH_SOR 1 /* Sample on Ready disabled */ -#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ -#define FLASH_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) -/* Access Parameter Register for Boot */ -#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ - (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define FLASH_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define FLASH_BW 1 /* 16Bit */ -/* CR register for Boot */ -#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) -/* CR register for non Boot */ -#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) - -/* MPS CS1 or CS0 */ -/* Boot CS: */ -#define MPS_BME_B 1 /* Burst enable */ -#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ -#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define MPS_BME 0 /* Burst disable */ -#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ -#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ -#define MPS_OEN 1 /* Cycles from CS low to OE low */ -#define MPS_WBN 1 /* Cycles from CS low to WE low */ -#define MPS_WBF 1 /* Cycles from WE high to CS high */ -#define MPS_TH 2 /* Number of hold cycles after transfer */ -#define MPS_RE 0 /* Ready disabled */ -#define MPS_SOR 1 /* Sample on Ready disabled */ -#define MPS_BEM 0 /* Byte Write only active on Write cycles */ -#define MPS_PEN 0 /* Parity disable */ -/* Access Parameter Register for non Boot */ -#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) -/* Access Parameter Register for Boot */ -#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ - (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) - -/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ -#define MPS_BS 2 /* 4 MByte */ -#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ -/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ -#define MPS_BU 3 /* R/W */ -/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ -#define MPS_BW 0 /* 8Bit */ -/* CR register for Boot */ -#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) -/* CR register for non Boot */ -#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug deleted file mode 100644 index 890f592..0000000 --- a/board/mpl/pip405/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/t3corp/Kconfig b/board/t3corp/Kconfig deleted file mode 100644 index 82ed4c9..0000000 --- a/board/t3corp/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_T3CORP - -config SYS_BOARD - default "t3corp" - -config SYS_CONFIG_NAME - default "t3corp" - -endif diff --git a/board/t3corp/MAINTAINERS b/board/t3corp/MAINTAINERS deleted file mode 100644 index eaf28c4..0000000 --- a/board/t3corp/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -T3CORP BOARD -M: Stefan Roese <sr@denx.de> -S: Maintained -F: board/t3corp/ -F: include/configs/t3corp.h -F: configs/t3corp_defconfig diff --git a/board/t3corp/Makefile b/board/t3corp/Makefile deleted file mode 100644 index 928d895..0000000 --- a/board/t3corp/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2010 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := t3corp.o -obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o -extra-y += init.o diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c deleted file mode 100644 index 3a6c514..0000000 --- a/board/t3corp/chip_config.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx_config.h> - -struct ppc4xx_config ppc4xx_config_val[] = { - { - "600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67", - { - 0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83", - { - 0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0, - 0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1000", "CPU:1000 PLB: 200 OPB: 100 EBC: 100", - { - 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, - { - "1066", "CPU:1066 PLB: 266 OPB: 88 EBC: 88", - { - 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, - 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 - } - }, -}; - -int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/t3corp/config.mk b/board/t3corp/config.mk deleted file mode 100644 index f7ac755..0000000 --- a/board/t3corp/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2010 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/t3corp/init.S b/board/t3corp/init.S deleted file mode 100644 index 7ae9c43..0000000 --- a/board/t3corp/init.S +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm-offsets.h> -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - */ - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to - * use the speed up boot process. It is patched after relocation to - * enable SA_I - */ - tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, - CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the DDR(2) detection - * routine. - */ - -#ifdef CONFIG_SYS_INIT_RAM_DCACHE - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, - AC_RWX | SA_G) -#endif - - tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd, - AC_RW | SA_IG) - - tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd, - AC_RW | SA_IG) - - /* PCIe UTL register */ - tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG) - - /* TLB-entry for FPGA(s) */ - tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M, - CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG) - tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4, - AC_RW | SA_IG) - tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4, - AC_RW | SA_IG) - - /* TLB-entry for OCM */ - tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, - AC_RWX | SA_I) - - /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, - CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG) - - tlbtab_end diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c deleted file mode 100644 index 586c6f9..0000000 --- a/board/t3corp/t3corp.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * (C) Copyright 2010 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc440.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <i2c.h> -#include <mtd/cfi_flash.h> -#include <asm/processor.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/4xx_pcie.h> -#include <asm/ppc4xx-gpio.h> - -int board_early_init_f(void) -{ - /* - * Setup the interrupt controller polarities, triggers, etc. - */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC0SR, 0xffffffff); /* clear all */ - - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000000); /* all non-critical */ - mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */ - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - /* - * Configure PFC (Pin Function Control) registers - * enable GPIO 49-63 - * UART0: 4 pins - */ - mtsdr(SDR0_PFC0, 0x00007fff); - mtsdr(SDR0_PFC1, 0x00040000); - - /* Enable PCI host functionality in SDR0_PCI0 */ - mtsdr(SDR0_PCI0, 0xe0000000); - - mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ - - /* Setup PLB4-AHB bridge based on the system address map */ - mtdcr(AHB_TOP, 0x8000004B); - mtdcr(AHB_BOT, 0x8000004B); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - printf("Board: T3CORP"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return 0; -} - -int board_early_init_r(void) -{ - /* - * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the - * boot EBC mapping only supports a maximum of 16MBytes - * (4.ff00.0000 - 4.ffff.ffff). - * To solve this problem, the flash has to get remapped to another - * EBC address which accepts bigger regions: - * - * 0xfn00.0000 -> 4.cn00.0000 - */ - - /* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */ - mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB | - EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); - - /* Remove TLB entry of boot EBC mapping */ - remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); - - /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */ - program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); - - /* - * Now accessing of the whole 64Mbytes of NOR flash at virtual address - * 0xfc00.0000 is possible - */ - - /* - * Clear potential errors resulting from auto-calibration. - * If not done, then we could get an interrupt later on when - * exceptions are enabled. - */ - set_mcsr(get_mcsr()); - - return 0; -} - -int misc_init_r(void) -{ - u32 sdr0_srst1 = 0; - u32 eth_cfg; - - /* - * Set EMAC mode/configuration (GMII, SGMII, RGMII...). - * This is board specific, so let's do it here. - */ - mfsdr(SDR0_ETH_CFG, eth_cfg); - /* disable SGMII mode */ - eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE | - SDR0_ETH_CFG_SGMII1_ENABLE | - SDR0_ETH_CFG_SGMII0_ENABLE); - /* Set the for 2 RGMII mode */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ - eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL; - eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL; - mtsdr(SDR0_ETH_CFG, eth_cfg); - - /* - * The AHB Bridge core is held in reset after power-on or reset - * so enable it now - */ - mfsdr(SDR0_SRST1, sdr0_srst1); - sdr0_srst1 &= ~SDR0_SRST1_AHB; - mtsdr(SDR0_SRST1, sdr0_srst1); - - return 0; -} - -int board_pcie_last(void) -{ - /* - * Only PCIe0 for now, PCIe1 hangs on this board - */ - return 0; -} - -/* - * Board specific WRDTR and CLKTR values used by the auto- - * calibration code (4xx_ibm_ddr2_autocalib.c). - */ -static struct sdram_timing board_scan_options[] = { - {1, 2}, - {-1, -1} -}; - -struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val) -{ - return board_scan_options; -} - -/* - * Accessor functions replacing the "weak" functions in - * drivers/mtd/cfi_flash.c - * - * The NOR flash devices "behind" the FPGA's (Xilinx DS617) - * can only be read correctly in 16bit mode. We need to emulate - * 8bit and 32bit reads here in the board specific code. - */ -u8 flash_read8(void *addr) -{ - u16 val = __raw_readw((void *)((u32)addr & ~1)); - - if ((u32)addr & 1) - return val; - - return val >> 8; -} - -u32 flash_read32(void *addr) -{ - return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2)); -} - -void flash_cmd_reset(flash_info_t *info) -{ - /* - * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and - * needs the Spansion type reset commands. The other flash chip - * is located behind a FPGA (Xilinx DS617) and needs the Intel type - * reset command. - */ - if (info->start[0] == CONFIG_SYS_FLASH_BASE) - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); - else - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); -} diff --git a/board/xes/xpedite1000/Kconfig b/board/xes/xpedite1000/Kconfig deleted file mode 100644 index 4d0ab2f..0000000 --- a/board/xes/xpedite1000/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_XPEDITE1000 - -config SYS_BOARD - default "xpedite1000" - -config SYS_VENDOR - default "xes" - -config SYS_CONFIG_NAME - default "xpedite1000" - -endif diff --git a/board/xes/xpedite1000/MAINTAINERS b/board/xes/xpedite1000/MAINTAINERS deleted file mode 100644 index 055ce6a..0000000 --- a/board/xes/xpedite1000/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -XPEDITE1000 BOARD -M: Peter Tyser <ptyser@xes-inc.com> -S: Maintained -F: board/xes/xpedite1000/ -F: include/configs/xpedite1000.h -F: configs/xpedite1000_defconfig diff --git a/board/xes/xpedite1000/Makefile b/board/xes/xpedite1000/Makefile deleted file mode 100644 index 308de91..0000000 --- a/board/xes/xpedite1000/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = xpedite1000.o -extra-y += init.o diff --git a/board/xes/xpedite1000/README b/board/xes/xpedite1000/README deleted file mode 100644 index 1da8b80..0000000 --- a/board/xes/xpedite1000/README +++ /dev/null @@ -1,82 +0,0 @@ - XES XPedite1000 Board - - Last Update: December 29, 2003 -======================================================================= - -This file contains some handy info regarding U-Boot and the XES -XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional -information. - - -SWITCH SETTINGS & JUMPERS -========================== - -Jumpers selected for AMD29LV040B flash part as the boot flash. - - -I2C Strap EEPROM & Environment Settings -======================================= - -The XPedite1000 uses a single I2C eeprom for the 440 strappings and for -the environment variables. The first page (256 bytes) contains the -strappings and the 2 EMAC HW Ethernet addresses. Be careful not to -change the 1st page of the EEPROM! Unpopulated jumper J560 can get you -out of trouble as it disables the strapping read from EEPROM. - -I2C probe -===================== - -The i2c utilities work and have been tested on Rev B. of the 440GX. See -README.ebony for more information about i2c probing with the 440. - - -GETTING OUT OF I2C TROUBLE -=========================== - -(Direct quote from README.ebony) -If you're like me ... you may have screwed up your bootstrap serial -eeprom ... or worse, your SPD eeprom when experimenting with the -i2c commands. If so, here are some ideas on how to get out of -trouble: - -Serial bootstrap eeprom corruption: ------------------------------------ -Power down the board and set the following straps: - -J560 - closed - -This will select the default sys0 and sys1 settings (the serial -eeproms are not used). Then power up the board and fix the serial -eeprom using the 'i2c mm' command. Here are the values I currently -use: - -=> i2c md 50 0 10 - -0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00 .}B............. - -Once you have the eeproms set correctly change the -J560 straps as you desire. - - -PPC440GX Ethernet EMACs -======================= - -The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1. PHYs are connected -only to emac 2 & 3. The HW Ethernet addresses are read from the i2c eeprom and -placed in the bd info structure for enet2addr and enet3addr. The ethernet driver -senses that enetaddr and enet1addr are 0's and does not use them. - -As of this writing gigabit ethernet and the TCPIP acceleration hardware is not -supported. - - -Flash Support -============= - -As of this writing, there is support for the 1/2mb boot flash only. User flash -is not yet supported. - - -Regards, ---Travis -<travis.sawyer@sandburst.com> diff --git a/board/xes/xpedite1000/config.mk b/board/xes/xpedite1000/config.mk deleted file mode 100644 index ec7651e..0000000 --- a/board/xes/xpedite1000/config.mk +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2002-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# XES XPedite1000 PPC440GX -# - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif diff --git a/board/xes/xpedite1000/init.S b/board/xes/xpedite1000/init.S deleted file mode 100644 index 9708ecc..0000000 --- a/board/xes/xpedite1000/init.S +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <ppc_asm.tmpl> -#include <asm/mmu.h> -#include <config.h> -#include <asm/ppc4xx.h> - -/* - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - */ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) - tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG) - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG ) - tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) - tlbtab_end diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug deleted file mode 100644 index 04089ae..0000000 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2002-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/ppc4xx/start.o (.text) - board/xes/xpedite1000/init.o (.text) - arch/powerpc/cpu/ppc4xx/kgdb.o (.text) - arch/powerpc/cpu/ppc4xx/traps.o (.text) - arch/powerpc/cpu/ppc4xx/interrupts.o (.text) - arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text) - arch/powerpc/cpu/ppc4xx/cpu_init.o (.text) - arch/powerpc/cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - lib/zlib.o (.text) - -/* common/env_embedded.o(.text) */ - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c deleted file mode 100644 index ef646fa..0000000 --- a/board/xes/xpedite1000/xpedite1000.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <console.h> -#include <asm/processor.h> -#include <spd_sdram.h> -#include <i2c.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - unsigned long sdrreg; - - /* - * Enable GPIO for pins 18 - 24 - * 18 = SEEPROM_WP - * 19 = #M_RST - * 20 = #MONARCH - * 21 = #LED_ALARM - * 22 = #LED_ACT - * 23 = #LED_STATUS1 - * 24 = #LED_STATUS2 - */ - mfsdr(SDR0_PFC0, sdrreg); - mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); - out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); - LED0_OFF(); - LED1_OFF(); - LED2_OFF(); - LED3_OFF(); - - /* Setup the external bus controller/chip selects */ - mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */ - mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ - mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */ - mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ - mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ - mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ - mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ - mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ - - /* - * Setup the interrupt controller polarities, triggers, etc. - * - * Because of the interrupt handling rework to handle 440GX interrupts - * with the common code, we needed to change names of the UIC registers. - * Here the new relationship: - * - * U-Boot name 440GX name - * ----------------------- - * UIC0 UICB0 - * UIC1 UIC0 - * UIC2 UIC1 - * UIC3 UIC2 - */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - mtdcr(UIC1ER, 0x00000000); /* disable all */ - mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */ - mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */ - mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */ - mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC1SR, 0xffffffff); /* clear all */ - - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - mtdcr(UIC2ER, 0x00000000); /* disable all */ - mtdcr(UIC2CR, 0x00000000); /* all non-critical */ - mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */ - mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */ - mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC2SR, 0xffffffff); /* clear all */ - - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - mtdcr(UIC3ER, 0x00000000); /* disable all */ - mtdcr(UIC3CR, 0x00000000); /* all non-critical */ - mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ - mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */ - mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr(UIC3SR, 0xffffffff); /* clear all */ - - mtdcr(UIC0SR, 0xfc000000); /* clear all */ - mtdcr(UIC0ER, 0x00000000); /* disable all */ - mtdcr(UIC0CR, 0x00000000); /* all non-critical */ - mtdcr(UIC0PR, 0xfc000000); /* */ - mtdcr(UIC0TR, 0x00000000); /* */ - mtdcr(UIC0VR, 0x00000001); /* */ - - LED0_ON(); - - return 0; -} - -int checkboard(void) -{ - char buf[64]; - int i; - - printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME); - printf(" "); - i = getenv_f("board_rev", buf, sizeof(buf)); - if (i > 0) - printf("Rev %s, ", buf); - i = getenv_f("serial#", buf, sizeof(buf)); - if (i > 0) - printf("Serial# %s, ", buf); - i = getenv_f("board_cfg", buf, sizeof(buf)); - if (i > 0) - printf("Cfg %s", buf); - printf("\n"); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = spd_sdram(); - - return 0; -} - -/* - * Override weak pci_pre_init() - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose) -{ - unsigned long strap; - - /* See if we're supposed to setup the pci */ - mfsdr(SDR0_SDSTP1, strap); - if ((strap & 0x00010000) == 0) - return 0; - -#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) - /* Setup System Device Register PCIL0_XCR */ - mfsdr(SDR0_XCR, strap); - strap &= 0x0f000000; - mtsdr(SDR0_XCR, strap); -#endif - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -#if defined(CONFIG_PCI) -/* - * Override weak is_pci_host() - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - */ -int is_pci_host(struct pci_controller *hose) -{ - return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0); -} -#endif /* defined(CONFIG_PCI) */ - -#ifdef CONFIG_POST -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return ctrlc(); -} -#endif diff --git a/board/xilinx/ppc405-generic/Kconfig b/board/xilinx/ppc405-generic/Kconfig deleted file mode 100644 index dfbc07b..0000000 --- a/board/xilinx/ppc405-generic/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_XILINX_PPC405_GENERIC - -config SYS_BOARD - default "ppc405-generic" - -config SYS_VENDOR - default "xilinx" - -config SYS_CONFIG_NAME - default "xilinx-ppc405-generic" - -endif diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS deleted file mode 100644 index ba48f50..0000000 --- a/board/xilinx/ppc405-generic/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -PPC405-GENERIC BOARD -M: Ricardo Ribalda <ricardo.ribalda@gmail.com> -S: Maintained -F: board/xilinx/ppc405-generic/ -F: include/configs/xilinx-ppc405-generic.h -F: configs/xilinx-ppc405-generic_defconfig -F: configs/xilinx-ppc405-generic_flash_defconfig diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile deleted file mode 100644 index 2800f68..0000000 --- a/board/xilinx/ppc405-generic/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com -# Work supported by Qtechnology http://www.qtec.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += xilinx_ppc405_generic.o diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c deleted file mode 100644 index be6b4dc..0000000 --- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com - * This work has been supported by: QTechnology http://qtec.com/ - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <config.h> -#include <common.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -ulong get_PCI_freq(void) -{ - return 0; -} - -int checkboard(void) -{ - puts("Xilinx PPC405 Generic Board\n"); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, - CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); - - return 0; -} - -void get_sys_info(sys_info_t *sys_info) -{ - sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sys_info->freqPCI = 0; - - return; -} - -int get_serial_clock(void){ - return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; -} diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h deleted file mode 100644 index c3df9e5..0000000 --- a/board/xilinx/ppc405-generic/xparameters.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters-ml507.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_SPI_0_BASEADDR 0x83400000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 -#define XPAR_SPI_0_NUM_TRANSFER_BITS 8 -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 - -#endif diff --git a/board/xilinx/ppc440-generic/Kconfig b/board/xilinx/ppc440-generic/Kconfig deleted file mode 100644 index d40783a..0000000 --- a/board/xilinx/ppc440-generic/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_XILINX_PPC440_GENERIC - -config SYS_BOARD - default "ppc440-generic" - -config SYS_VENDOR - default "xilinx" - -config SYS_CONFIG_NAME - default "xilinx-ppc440-generic" - -endif diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS deleted file mode 100644 index 0258c82..0000000 --- a/board/xilinx/ppc440-generic/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -PPC440-GENERIC BOARD -M: Ricardo Ribalda <ricardo.ribalda@gmail.com> -S: Maintained -F: board/xilinx/ppc440-generic/ -F: include/configs/xilinx-ppc440-generic.h -F: configs/xilinx-ppc440-generic_defconfig -F: configs/xilinx-ppc440-generic_flash_defconfig diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile deleted file mode 100644 index 4d5f410..0000000 --- a/board/xilinx/ppc440-generic/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com -# Work supported by Qtechnology http://www.qtec.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += xilinx_ppc440_generic.o -extra-y += init.o diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S deleted file mode 100644 index f9ff35f..0000000 --- a/board/xilinx/ppc440-generic/init.S +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com - * This work has been supported by: QTechnology http://qtec.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm/mmu.h> - -.section .bootpg,"ax" -.globl tlbtab - -tlbtab: -tlbtab_start -tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) -tlbtab_end diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c deleted file mode 100644 index 07a3ab7..0000000 --- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com - * This work has been supported by: QTechnology http://qtec.com/ - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#include <config.h> -#include <common.h> -#include <netdev.h> -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - puts("Xilinx PPC440 Generic Board\n"); - return 0; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, - CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); - - return 0; -} - -void get_sys_info(sys_info_t *sys_info) -{ - sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sys_info->freqPCI = 0; - - return; -} - -int get_serial_clock(void){ - return XPAR_UARTNS550_0_CLOCK_FREQ_HZ; -} - -int board_eth_init(bd_t *bis) -{ - int ret = 0; - - puts("Init xilinx temac\n"); -#ifdef XPAR_LLTEMAC_0_BASEADDR - ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR, - XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, - XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR); - -#endif - -#ifdef XPAR_LLTEMAC_1_BASEADDR - ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR, - XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB, - XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR); -#endif - - return ret; -} diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h deleted file mode 100644 index b45a6a1..0000000 --- a/board/xilinx/ppc440-generic/xparameters.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com - * This work has been supported by: QTechnology http://qtec.com/ - * based on xparameters-ml507.h by Xilinx - * - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef XPARAMETER_H -#define XPARAMETER_H - -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x87000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 -#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80 -#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98 -#define XPAR_LLTEMAC_0_BASEADDR 0x83000000 -#define XPAR_LLTEMAC_1_BASEADDR 0x83000040 - -#endif |