diff options
Diffstat (limited to 'board/liebherr/lwmon5/sdram.c')
| -rw-r--r-- | board/liebherr/lwmon5/sdram.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/board/liebherr/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c index 1932e06..f7251e5 100644 --- a/board/liebherr/lwmon5/sdram.c +++ b/board/liebherr/lwmon5/sdram.c @@ -25,6 +25,8 @@ #include <asm/ppc440.h> #include <watchdog.h> +DECLARE_GLOBAL_DATA_PTR; + /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory * region. Right now the cache should still be disabled in U-Boot because of the @@ -145,7 +147,7 @@ static void program_ecc(u32 start_address, * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ -phys_size_t initdram(void) +int initdram(void) { /* CL=4 */ mtsdram(DDR0_02, 0x00000000); @@ -241,5 +243,7 @@ phys_size_t initdram(void) */ set_mcsr(get_mcsr()); - return (CONFIG_SYS_MBYTES_SDRAM << 20); + gd->ram_size = CONFIG_SYS_MBYTES_SDRAM << 20; + + return 0; } |