diff options
Diffstat (limited to 'board/freescale/bsc9132qds')
| -rw-r--r-- | board/freescale/bsc9132qds/Kconfig | 14 | ||||
| -rw-r--r-- | board/freescale/bsc9132qds/MAINTAINERS | 25 | ||||
| -rw-r--r-- | board/freescale/bsc9132qds/Makefile | 21 | ||||
| -rw-r--r-- | board/freescale/bsc9132qds/README | 150 | ||||
| -rw-r--r-- | board/freescale/bsc9132qds/bsc9132qds.c | 432 | ||||
| -rw-r--r-- | board/freescale/bsc9132qds/ddr.c | 191 | ||||
| -rw-r--r-- | board/freescale/bsc9132qds/law.c | 28 | ||||
| -rw-r--r-- | board/freescale/bsc9132qds/spl_minimal.c | 117 | ||||
| -rw-r--r-- | board/freescale/bsc9132qds/tlb.c | 91 |
9 files changed, 0 insertions, 1069 deletions
diff --git a/board/freescale/bsc9132qds/Kconfig b/board/freescale/bsc9132qds/Kconfig deleted file mode 100644 index e5499e6..0000000 --- a/board/freescale/bsc9132qds/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_BSC9132QDS - -config SYS_BOARD - default "bsc9132qds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "BSC9132QDS" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/bsc9132qds/MAINTAINERS b/board/freescale/bsc9132qds/MAINTAINERS deleted file mode 100644 index 95abe3d..0000000 --- a/board/freescale/bsc9132qds/MAINTAINERS +++ /dev/null @@ -1,25 +0,0 @@ -BSC9132QDS BOARD -M: Naveen Burmi <naveen.burmi@nxp.com> -S: Maintained -F: board/freescale/bsc9132qds/ -F: include/configs/BSC9132QDS.h -F: configs/BSC9132QDS_NAND_DDRCLK100_defconfig -F: configs/BSC9132QDS_NAND_DDRCLK133_defconfig -F: configs/BSC9132QDS_NOR_DDRCLK100_defconfig -F: configs/BSC9132QDS_NOR_DDRCLK133_defconfig -F: configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig -F: configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig -F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig -F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig - -BSC9132QDS_NAND_DDRCLK100_SECURE BOARD -M: Ruchika Gupta <ruchika.gupta@nxp.com> -S: Maintained -F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig -F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig -F: configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig -F: configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig -F: configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig -F: configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig -F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig -F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile deleted file mode 100644 index dcbdf42..0000000 --- a/board/freescale/bsc9132qds/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL -obj-y += spl_minimal.o -else -obj-y += bsc9132qds.o -obj-y += ddr.o -endif - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README deleted file mode 100644 index ede95d4..0000000 --- a/board/freescale/bsc9132qds/README +++ /dev/null @@ -1,150 +0,0 @@ -Overview --------- - The BSC9132 is a highly integrated device that targets the evolving - Microcell, Picocell, and Enterprise-Femto base station market subsegments. - - The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 - core technologies with MAPLE-B2P baseband acceleration processing elements - to address the need for a high performance, low cost, integrated solution - that handles all required processing layers without the need for an - external device except for an RF transceiver or, in a Micro base station - configuration, a host device that handles the L3/L4 and handover between - sectors. - - The BSC9132 SoC includes the following function and features: - - Power Architecture subsystem including two e500 processors with - 512-Kbyte shared L2 cache - - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 - cache - - 32 Kbyte of shared M3 memory - - The Multi Accelerator Platform Engine for Pico BaseStation Baseband - Processing (MAPLE-B2P) - - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including - ECC), up to 1333 MHz data rate - - Dedicated security engine featuring trusted boot - - Two DMA controllers - - OCNDMA with four bidirectional channels - - SysDMA with sixteen bidirectional channels - - Interfaces - - Four-lane SerDes PHY - - PCI Express controller complies with the PEX Specification-Rev 2.0 - - Two Common Public Radio Interface (CPRI) controller lanes - - High-speed USB 2.0 host and device controller with ULPI interface - - Enhanced secure digital (SD/MMC) host controller (eSDHC) - - Antenna interface controller (AIC), supporting four industry - standard JESD207/four custom ADI RF interfaces - - ADI lanes support both full duplex FDD support & half duplex TDD - - Universal Subscriber Identity Module (USIM) interface that - facilitates communication to SIM cards or Eurochip pre-paid phone - cards - - Two DUART, two eSPI, and two I2C controllers - - Integrated Flash memory controller (IFC) - - GPIO - - Sixteen 32-bit timers - -The SC3850 core subsystem consists of the following: - - 32 KB, 8-way, level 1 instruction cache (L1 ICache) - - 32 KB, 8-way, level 1 data cache (L1 DCache) - - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory) - - Memory management unit (MMU) - - Global interrupt controller ( GIC) - - Debug and profiling unit (DPU) - - Two 32-bit quad timers - -BSC9132QDS board Overview -------------------------- - 2Gbyte DDR3 (on board DDR), Dual Ranki - 32Mbyte 16bit NOR flash - 128Mbyte 2K page size NAND Flash - 256 Kbit M24256 I2C EEPROM - 128 Mbit SPI Flash memory - SD slot - USB-ULPI - eTSEC1: Connected to SGMII PHY - eTSEC2: Connected to SGMII PHY - PCIe - CPRI - SerDes - I2C RTC - DUART interface: supports one UARTs up to 115200 bps for console display - -Frequency Combinations Supported --------------------------------- -Core MHz/CCB MHz/DDR(MT/s) -1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz - (SYSCLK = 100MHz, DDRCLK = 100MHz) -2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz - (SYSCLK = 100MHz, DDRCLK = 133MHz) - -Boot Methods Supported ------------------------ -1. NOR Flash -2. NAND Flash -3. SD Card -4. SPI flash - -Default Boot Method --------------------- -NOR boot - -Building U-Boot --------------- -To build the U-Boot for BSC9132QDS: -1. NOR Flash - make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK -2. NAND Flash : It is currently not supported -3. SPI Flash - make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK -4. SD Card - make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK - -Memory map ------------ - 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable - 0x8000_0000 0x8FFF_FFFF NOR Flash 256M - 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M - 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M - 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M - 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M - 0xC000_0000 0xC000_7FFF M3 Memory 32K - 0xC001_0000 0xC001_FFFF PCI Express I/O 64K - 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M - 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K - 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K - 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K - 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K - 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M - 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M - 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M - -Flashing Images ---------------- -To place a new U-Boot image in the NAND flash and then boot -with that new image temporarily, use this: - tftp 1000000 u-boot-nand.bin - nand erase 0 100000 - nand write 1000000 0 100000 - reset - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts - -Booting Linux -------------- -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp c00000 bsc9132qds.dtb - bootm 1000000 2000000 c00000 diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c deleted file mode 100644 index 6870674..0000000 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ /dev/null @@ -1,432 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <image.h> -#include <init.h> -#include <net.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/io.h> -#include <env.h> -#include <miiphy.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <mmc.h> -#include <netdev.h> -#include <fsl_ifc.h> -#include <hwconfig.h> -#include <i2c.h> -#include <fsl_ddr_sdram.h> -#include <jffs2/load_kernel.h> -#include <mtd_node.h> -#include <flash.h> - -#ifdef CONFIG_PCI -#include <pci.h> -#include <asm/fsl_pci.h> -#endif - -#include "../common/qixis.h" -DECLARE_GLOBAL_DATA_PTR; - - -int board_early_init_f(void) -{ - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - - setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - - return 0; -} - -void board_config_serdes_mux(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; - - switch (srds_cfg) { - /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ - case 1: - case 2: - case 3: - case 4: - case 5: - case 22: - case 23: - case 24: - case 25: - case 26: - QIXIS_WRITE_I2C(brdcfg[4], 0x03); - break; - - /* PEX(1) PEX(2) SGMII1 CPRI 1 */ - case 6: - case 7: - case 8: - case 9: - case 10: - case 27: - case 28: - case 29: - case 30: - case 31: - QIXIS_WRITE_I2C(brdcfg[4], 0x01); - break; - - /* PEX(1) PEX(2) SGMII1 SGMII2 */ - case 11: - case 32: - QIXIS_WRITE_I2C(brdcfg[4], 0x00); - break; - - /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ - case 12: - case 13: - case 14: - case 15: - case 16: - case 33: - case 34: - case 35: - case 36: - case 37: - QIXIS_WRITE_I2C(brdcfg[4], 0x07); - break; - - /* PEX(1) SGMII2 SGMII1 CPRI 1 */ - case 17: - case 18: - case 19: - case 20: - case 21: - case 38: - case 39: - case 40: - case 41: - case 42: - QIXIS_WRITE_I2C(brdcfg[4], 0x05); - break; - - /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ - case 43: - case 44: - case 45: - case 46: - case 47: - QIXIS_WRITE_I2C(brdcfg[4], 0x0F); - break; - - - default: - break; - } -} - -/* Configure DSP DDR controller */ -void dsp_ddr_configure(void) -{ - /* - *There are separate DDR-controllers for DSP and PowerPC side DDR. - *copy the ddr controller settings from PowerPC side DDR controller - *to the DSP DDR controller as connected DDR memories are similar. - */ - struct ccsr_ddr __iomem *pa_ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - struct ccsr_ddr temp_ddr; - struct ccsr_ddr __iomem *dsp_ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; - - memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr)); - temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; - temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; - memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr)); - dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; -} - -int board_early_init_r(void) -{ -#ifdef CONFIG_MTD_NOR_FLASH - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_64M, 1); - - set_tlb(1, flashbase + 0x4000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); -#endif - board_config_serdes_mux(); - dsp_ddr_configure(); - return 0; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif /* ifdef CONFIG_PCI */ - -int checkboard(void) -{ - struct cpu_type *cpu; - u8 sw; - - cpu = gd->arch.cpu; - printf("Board: %sQDS\n", cpu->name); - - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", - QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - printf("IFC chip select:"); - switch (sw) { - case 0: - printf("NOR\n"); - break; - case 2: - printf("Promjet\n"); - break; - case 4: - printf("NAND\n"); - break; - default: - printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - break; - } - - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; - -#endif - -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - tsec_eth_init(bis, tsec_info, num); -#endif - - #ifdef CONFIG_PCI - pci_eth_init(bis); - #endif - - return 0; -} - -#define USBMUX_SEL_MASK 0xc0 -#define USBMUX_SEL_UART2 0xc0 -#define USBMUX_SEL_USB 0x40 -#define SPIMUX_SEL_UART3 0x80 -#define GPS_MUX_SEL_GPS 0x40 - -#define TSEC_1588_CLKIN_MASK 0x03 -#define CON_XCVR_REF_CLK 0x00 - -int misc_init_r(void) -{ - u8 val; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 porbmsr = in_be32(&gur->porbmsr); - u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; - - /*Configure 1588 clock-in source from RF Card*/ - val = QIXIS_READ_I2C(brdcfg[5]); - QIXIS_WRITE_I2C(brdcfg[5], - (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); - - if (hwconfig("uart2") && hwconfig("usb1")) { - printf("UART2 and USB cannot work together on the board\n"); - printf("Remove one from hwconfig and reset\n"); - } else { - if (hwconfig("uart2")) { - val = QIXIS_READ_I2C(brdcfg[5]); - QIXIS_WRITE_I2C(brdcfg[5], - (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); - clrbits_be32(&gur->pmuxcr3, - MPC85xx_PMUXCR3_USB_SEL_MASK); - setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); - } else { - /* By default USB should be selected. - * Programming FPGA to select USB. */ - val = QIXIS_READ_I2C(brdcfg[5]); - QIXIS_WRITE_I2C(brdcfg[5], - (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); - } - - } - - if (hwconfig("sim")) { - if (romloc == PORBMSR_ROMLOC_NAND_2K || - romloc == PORBMSR_ROMLOC_NOR || - romloc == PORBMSR_ROMLOC_SPI) { - - val = QIXIS_READ_I2C(brdcfg[3]); - QIXIS_WRITE_I2C(brdcfg[3], val|0x10); - clrbits_be32(&gur->pmuxcr, - MPC85xx_PMUXCR0_SIM_SEL_MASK); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); - } - } - - if (hwconfig("uart3")) { - if (romloc == PORBMSR_ROMLOC_NAND_2K || - romloc == PORBMSR_ROMLOC_NOR || - romloc == PORBMSR_ROMLOC_SDHC) { - - /* UART3 and SPI1 (Flashes) are muxed together */ - val = QIXIS_READ_I2C(brdcfg[3]); - QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); - clrbits_be32(&gur->pmuxcr3, - MPC85xx_PMUXCR3_UART3_SEL_MASK); - setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); - - /* MUX to select UART3 connection to J24 header - * or to GPS */ - val = QIXIS_READ_I2C(brdcfg[6]); - if (hwconfig("gps")) - QIXIS_WRITE_I2C(brdcfg[6], - (val | GPS_MUX_SEL_GPS)); - else - QIXIS_WRITE_I2C(brdcfg[6], - (val & ~(GPS_MUX_SEL_GPS))); - } - } - return 0; -} - -void fdt_del_node_compat(void *blob, const char *compatible) -{ - int err; - int off = fdt_node_offset_by_compatible(blob, -1, compatible); - if (off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - compatible, fdt_strerror(off)); - return; - } - err = fdt_del_node(blob, off); - if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - compatible, fdt_strerror(err)); - } -} - -#if defined(CONFIG_OF_BOARD_SETUP) -#ifdef CONFIG_FDT_FIXUP_PARTITIONS -static const struct node_info nodes[] = { - { "cfi-flash", MTD_DEV_TYPE_NOR, }, - { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, -}; -#endif -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - #if defined(CONFIG_PCI) - FT_FSL_PCI_SETUP; - #endif - - fdt_fixup_memory(blob, (u64)base, (u64)size); -#ifdef CONFIG_FDT_FIXUP_PARTITIONS - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -#endif - - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 porbmsr = in_be32(&gur->porbmsr); - u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; - - if (!(hwconfig("uart2") && hwconfig("usb1"))) { - /* If uart2 is there in hwconfig remove usb node from - * device tree */ - - if (hwconfig("uart2")) { - /* remove dts usb node */ - fdt_del_node_compat(blob, "fsl-usb2-dr"); - } else { - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_del_node_and_alias(blob, "serial2"); - } - } - - if (hwconfig("uart3")) { - if (romloc == PORBMSR_ROMLOC_NAND_2K || - romloc == PORBMSR_ROMLOC_NOR || - romloc == PORBMSR_ROMLOC_SDHC) - /* Delete SPI node from the device tree */ - fdt_del_node_and_alias(blob, "spi1"); - } else - fdt_del_node_and_alias(blob, "serial3"); - - if (hwconfig("sim")) { - if (romloc == PORBMSR_ROMLOC_NAND_2K || - romloc == PORBMSR_ROMLOC_NOR || - romloc == PORBMSR_ROMLOC_SPI) { - - /* remove dts sdhc node */ - fdt_del_node_compat(blob, "fsl,esdhc"); - } else if (romloc == PORBMSR_ROMLOC_SDHC) { - - /* remove dts sim node */ - fdt_del_node_compat(blob, "fsl,sim-v1.0"); - printf("SIM & SDHC can't work together on the board"); - printf("\nRemove sim from hwconfig and reset\n"); - } - } - - return 0; -} -#endif diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c deleted file mode 100644 index f4effe5..0000000 --- a/board/freescale/bsc9132qds/ddr.c +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <vsprintf.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> -#include <asm/io.h> -#include <asm/fsl_law.h> - -#ifndef CONFIG_SYS_DDR_RAW_TIMING - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {1060, 1333, &ddr_cfg_regs_1333}, - {0, 0, NULL} -}; - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, - LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - - return ddr_size; -} - -#else /* CONFIG_SYS_DDR_RAW_TIMING */ -/* Micron MT41J512M8_187E */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1870, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - int i; - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} - -#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c deleted file mode 100644 index 6dca3d1..0000000 --- a/board/freescale/bsc9132qds/law.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_FPGA_BASE_PHYS - SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), -#endif - SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, - LAW_TRGT_IF_DSP_CCSR), - SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, - LAW_TRGT_IF_OCN_DSP), - SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, - LAW_TRGT_IF_CLASS_DSP), - SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, - LAW_TRGT_IF_CLASS_DSP) -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c deleted file mode 100644 index dd56ad6..0000000 --- a/board/freescale/bsc9132qds/spl_minimal.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <ns16550.h> -#include <asm/io.h> -#include <nand.h> -#include <linux/compiler.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/global_data.h> -#include <linux/delay.h> - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_init(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; -#if CONFIG_DDR_CLK_FREQ == 100000000 - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); - __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); - __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - - __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); -#elif CONFIG_DDR_CLK_FREQ == 133000000 - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); - __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); - __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - - __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); -#else - puts("Not a valid DDR Freq Found! Please Reset\n"); -#endif - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - - set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* Initialize the DDR3 */ - sdram_init(); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c deleted file mode 100644 index 9466814..0000000 --- a/board/freescale/bsc9132qds/tlb.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_BOOT - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR (PA) */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* CCSRBAR (DSP) */ - SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, - CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, - MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 3, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_64K, 1), -#endif -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), -#endif - -#ifdef CONFIG_SYS_FPGA_BASE - /* *I*G - Board FPGA */ - SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_256K, 1), -#endif - -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); |