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-rw-r--r--arch/arm/dts/stm32mp135f-dk-u-boot.dtsi19
-rw-r--r--arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi32
-rw-r--r--arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi32
-rw-r--r--arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi34
-rw-r--r--arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi34
-rw-r--r--arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi8
-rw-r--r--arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi6
-rw-r--r--arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi6
-rw-r--r--arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig1
-rw-r--r--arch/arm/mach-stm32mp/stm32mp1/Makefile1
-rw-r--r--arch/arm/mach-stm32mp/stm32mp1/psci.c14
-rw-r--r--arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c35
12 files changed, 175 insertions, 47 deletions
diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
index ba0c024..f004e98 100644
--- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
@@ -16,11 +16,26 @@
u-boot,mmc-env-partition = "u-boot-env";
};
+ gpio-keys {
+ button-user-1 {
+ label = "User-1";
+ linux,code = <BTN_2>;
+ gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ button-user {
+ /* update label to match the label requested in board_key_check() */
+ label = "User-2";
+ };
+ };
+
leds {
+ led-blue {
+ /delete-property/default-state;
+ };
+
led-red {
- color = <LED_COLOR_ID_RED>;
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- default-state = "off";
};
};
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
index 20728f2..a5158fe 100644
--- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
@@ -3,6 +3,7 @@
* Copyright : STMicroelectronics 2022
*/
+#include <dt-bindings/input/linux-event-codes.h>
#include "stm32mp15-scmi-u-boot.dtsi"
/ {
@@ -12,20 +13,35 @@
};
config {
- u-boot,boot-led = "heartbeat";
- u-boot,error-led = "error";
+ u-boot,boot-led = "led-blue";
+ u-boot,error-led = "led-red";
u-boot,mmc-env-partition = "u-boot-env";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
- st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-user-1 {
+ label = "User-1";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ button-user-2 {
+ label = "User-2";
+ linux,code = <BTN_2>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
};
led {
- red {
- label = "error";
+ led-blue {
+ /delete-property/label;
+ };
+
+ led-red {
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- default-state = "off";
- status = "okay";
};
};
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index a163582..f97deba 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include <dt-bindings/input/linux-event-codes.h>
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
@@ -14,12 +15,10 @@
};
config {
- u-boot,boot-led = "heartbeat";
- u-boot,error-led = "error";
+ u-boot,boot-led = "led-blue";
+ u-boot,error-led = "led-red";
u-boot,mmc-env-partition = "fip";
st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
- st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
#if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL)
@@ -48,12 +47,29 @@
};
#endif
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-user-1 {
+ label = "User-1";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ button-user-2 {
+ label = "User-2";
+ linux,code = <BTN_2>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
led {
- red {
- label = "error";
+ led-blue {
+ /delete-property/label;
+ };
+
+ led-red {
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- default-state = "off";
- status = "okay";
};
};
};
diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
index 4d763bd..7c0d1ba 100644
--- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
@@ -3,6 +3,7 @@
* Copyright : STMicroelectronics 2022
*/
+#include <dt-bindings/input/linux-event-codes.h>
#include "stm32mp15-scmi-u-boot.dtsi"
/ {
@@ -11,19 +12,36 @@
};
config {
- u-boot,boot-led = "heartbeat";
- u-boot,error-led = "error";
+ u-boot,boot-led = "led-blue";
+ u-boot,error-led = "led-red";
u-boot,mmc-env-partition = "u-boot-env";
- st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-user-1 {
+ label = "User-1";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ button-user-2 {
+ label = "User-2";
+ linux,code = <BTN_2>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
};
led {
- red {
- label = "error";
+ compatible = "gpio-leds";
+
+ led-blue {
+ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-red {
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- default-state = "off";
- status = "okay";
};
};
};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index ef91088..d93359f 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include <dt-bindings/input/linux-event-codes.h>
#include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
@@ -13,11 +14,9 @@
};
config {
- u-boot,boot-led = "heartbeat";
- u-boot,error-led = "error";
+ u-boot,boot-led = "led-blue";
+ u-boot,error-led = "led-red";
u-boot,mmc-env-partition = "fip";
- st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
#if defined(CONFIG_STM32MP15X_STM32IMAGE) || defined(CONFIG_SPL)
@@ -43,12 +42,31 @@
};
#endif
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-user-1 {
+ label = "User-1";
+ linux,code = <BTN_1>;
+ gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+
+ button-user-2 {
+ label = "User-2";
+ linux,code = <BTN_2>;
+ gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ };
+ };
+
led {
- red {
- label = "error";
+ compatible = "gpio-leds";
+
+ led-blue {
+ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-red {
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
- default-state = "off";
- status = "okay";
};
};
};
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 139940b..3515347 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -33,11 +33,11 @@
label = "fsbl1";
reg = <0x00000000 0x00040000>;
};
- partition@80000 {
+ partition@40000 {
label = "fsbl2";
reg = <0x00040000 0x00040000>;
};
- partition@100000 {
+ partition@80000 {
label = "ssbl";
reg = <0x00080000 0x00200000>;
};
@@ -58,7 +58,7 @@
label = "fsbl2";
reg = <0x00040000 0x00040000>;
};
- partition@100000 {
+ partition@80000 {
label = "fip";
reg = <0x00080000 0x00400000>;
};
@@ -112,7 +112,7 @@
label = "fip2";
reg = <0x00600000 0x00400000>;
};
- partition@1200000 {
+ partition@a00000 {
label = "UBI";
reg = <0x00a00000 0x3f600000>;
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index 2f70b06..1b44561 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -106,15 +106,15 @@
label = "fsbl2";
reg = <0x00040000 0x00040000>;
};
- partition@500000 {
+ partition@80000 {
label = "uboot";
reg = <0x00080000 0x00160000>;
};
- partition@900000 {
+ partition@1e0000 {
label = "env1";
reg = <0x001E0000 0x00010000>;
};
- partition@980000 {
+ partition@1f0000 {
label = "env2";
reg = <0x001F0000 0x00010000>;
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 552b35d..ba84db6 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -42,15 +42,15 @@
label = "fsbl2";
reg = <0x00040000 0x00040000>;
};
- partition@500000 {
+ partition@80000 {
label = "uboot";
reg = <0x00080000 0x00160000>;
};
- partition@900000 {
+ partition@1e0000 {
label = "env1";
reg = <0x001E0000 0x00010000>;
};
- partition@980000 {
+ partition@1f0000 {
label = "env2";
reg = <0x001F0000 0x00010000>;
};
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
index 8f91db4..5892762 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
@@ -17,6 +17,7 @@ config CMD_STM32PROG
config CMD_STM32PROG_USB
bool "support stm32prog over USB"
depends on CMD_STM32PROG
+ depends on USB_GADGET_DOWNLOAD
default y
help
activate the command "stm32prog usb" for STM32MP soc family
diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile
index 8571487..ebae50f 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/Makefile
+++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile
@@ -8,7 +8,6 @@ obj-y += cpu.o
obj-$(CONFIG_STM32MP13X) += stm32mp13x.o
obj-$(CONFIG_STM32MP15X) += stm32mp15x.o
-obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += tzc400.o
diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c
index 8cdeb0a..4f2379d 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/psci.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c
@@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
{
u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr;
u32 gicd_addr = stm32mp_get_gicd_base_address();
+ u32 cpu = psci_get_cpu_id();
+ u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT);
bool iwdg1_wake = false;
bool iwdg2_wake = false;
bool other_wake = false;
@@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+
+ /*
+ * The system has resumed successfully. Rewrite LR register stored
+ * on stack with 'ep' value, so that on return from this PSCI call,
+ * the code would jump to that 'ep' resume entry point code path
+ * instead of the previous 'lr' register content which (e.g. with
+ * Linux) points to resume failure code path.
+ *
+ * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout
+ * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on.
+ */
+ writel(ep, sp - 8);
}
diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
index afc56b0..d75ec99 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c
@@ -14,6 +14,7 @@
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
+#include <linux/bitfield.h>
/* RCC register */
#define RCC_TZCR (STM32_RCC_BASE + 0x00)
@@ -41,6 +42,9 @@
#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
+#define TAMP_SMCR (STM32_TAMP_BASE + 0x20)
+#define TAMP_SMCR_BKPRWDPROT GENMASK(7, 0)
+#define TAMP_SMCR_BKPWDPROT GENMASK(23, 16)
#define PWR_CR1 (STM32_PWR_BASE + 0x00)
#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
@@ -136,6 +140,18 @@ static void security_init(void)
*/
writel(0x0, TAMP_CR1);
+ /*
+ * TAMP: Configure non-zero secure protection settings. This is
+ * checked by BootROM function 35ac on OTP-CLOSED device during
+ * CPU core 1 release from endless loop. If secure protection
+ * fields are zero, the core 1 is not released from endless
+ * loop on second SGI0.
+ */
+ clrsetbits_le32(TAMP_SMCR,
+ TAMP_SMCR_BKPRWDPROT | TAMP_SMCR_BKPWDPROT,
+ FIELD_PREP(TAMP_SMCR_BKPRWDPROT, 0x20) |
+ FIELD_PREP(TAMP_SMCR_BKPWDPROT, 0x20));
+
/* GPIOZ: deactivate the security */
writel(BIT(0), RCC_MP_AHB5ENSETR);
writel(0x0, GPIOZ_SECCFGR);
@@ -322,8 +338,23 @@ void get_soc_name(char name[SOC_NAME_SIZE])
get_cpu_string_offsets(&type, &pkg, &rev);
- snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
- soc_type[type], soc_pkg[pkg], soc_rev[rev]);
+ if (bsec_dbgswenable()) {
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
+ soc_type[type], soc_pkg[pkg], soc_rev[rev]);
+ } else {
+ /*
+ * SoC revision is only accessible via DBUMCU IDC register,
+ * which requires BSEC.DENABLE DBGSWENABLE bit to be set to
+ * make the register accessible, otherwise an access to the
+ * register triggers bus fault. As BSEC.DBGSWENABLE is zero
+ * in case of an OTP-CLOSED system, do NOT set DBGSWENABLE
+ * bit as this might open a brief window for timing attacks.
+ * Instead, report that this system is OTP-CLOSED and do not
+ * report any SoC revision to avoid confusing users.
+ */
+ snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s SEC/C",
+ soc_type[type], soc_pkg[pkg]);
+ }
}
static void setup_soc_type_pkg_rev(void)
generated by cgit v1.1 at 2024-08-05 20:12:48 +0000