8 files changed, 22 insertions, 21 deletions

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7e20ef6..fa3b016 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -80,7 +80,7 @@ config SPL_ZERO_MEM_BEFORE_USE
 	  Sifive core devices that uses L2 cache to store SPL.
 
 # board-specific options below
-source "board/AndesTech/ae350/Kconfig"
+source "board/andestech/ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/openpiton/riscv64/Kconfig"
@@ -93,7 +93,7 @@ source "board/thead/th1520_lpi4a/Kconfig"
 source "board/xilinx/mbv/Kconfig"
 
 # platform-specific options below
-source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/andes/Kconfig"
 source "arch/riscv/cpu/cv1800b/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andes/Kconfig
index e3efb0d..120fec5 100644
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andes/Kconfig
@@ -1,4 +1,4 @@
-config RISCV_NDS
+config RISCV_ANDES
 	bool
 	select ARCH_EARLY_INIT_R
 	select SYS_CACHE_SHIFT_6
@@ -8,7 +8,7 @@ config RISCV_NDS
 	imply ANDES_PLMT_TIMER
 	imply SPL_ANDES_PLMT_TIMER
 	imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
-	imply V5L2_CACHE
+	imply ANDES_L2_CACHE
 	imply SPL_CPU
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andes/Makefile
index 35a1a2f..35a1a2f 100644
--- a/arch/riscv/cpu/andesv5/Makefile
+++ b/arch/riscv/cpu/andes/Makefile
diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andes/cache.c
index 269bb27..7d3df87 100644
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -12,21 +12,21 @@
 #include <dm/uclass-internal.h>
 #include <asm/arch-andes/csr.h>
 
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
 void enable_caches(void)
 {
 	struct udevice *dev;
 	int ret;
 
 	ret = uclass_get_device_by_driver(UCLASS_CACHE,
-					  DM_DRIVER_GET(v5l2_cache),
+					  DM_DRIVER_GET(andes_l2_cache),
 					  &dev);
 	if (ret) {
-		log_debug("Cannot enable v5l2 cache\n");
+		log_debug("Cannot enable Andes L2 cache\n");
 	} else {
 		ret = cache_enable(dev);
 		if (ret)
-			log_debug("v5l2 cache enable failed\n");
+			log_debug("Failed to enable Andes L2 cache\n");
 	}
 }
 
@@ -78,7 +78,7 @@ void dcache_enable(void)
 	asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
 #endif
 
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
 	cache_ops(cache_enable);
 #endif
 }
@@ -89,7 +89,7 @@ void dcache_disable(void)
 	asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
 #endif
 
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
 	cache_ops(cache_disable);
 #endif
 }
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andes/cpu.c
index d25ecba..d25ecba 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andes/cpu.c
diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andes/spl.c
index a13dc40..a13dc40 100644
--- a/arch/riscv/cpu/andesv5/spl.c
+++ b/arch/riscv/cpu/andes/spl.c
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h
index 62d184a..45ad2a5 100644
--- a/arch/riscv/include/asm/arch-jh7110/eeprom.h
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -13,6 +13,13 @@ u8 get_pcb_revision_from_eeprom(void);
 u32 get_ddr_size_from_eeprom(void);
 
 /**
+ * get_mmc_size_from_eeprom() - read eMMC size from EEPROM
+ *
+ * @return: size in GiB or 0 on error.
+ */
+u32 get_mmc_size_from_eeprom(void);
+
+/**
  * get_product_id_from_eeprom - get product ID string
  *
  * A string like "VF7110A1-2228-D008E000-00000001" is returned.
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 7350e2c..f9a1428 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -60,21 +60,20 @@ static void show_regs(struct pt_regs *regs)
 #endif
 }
 
-#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER)
-static void show_backtrace(struct pt_regs *regs)
+static void __maybe_unused show_backtrace(struct pt_regs *regs)
 {
 	uintptr_t *fp = (uintptr_t *)regs->s0;
 	unsigned count = 0;
 	ulong ra;
 
-	printf("backtrace:\n");
+	printf("\nbacktrace:\n");
 
 	/* there are a few entry points where the s0 register is
 	 * set to gd, so to avoid changing those, just abort if
 	 * the value is the same */
 	while (fp != NULL && fp != (uintptr_t *)gd) {
 		ra = fp[-1];
-		printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT,
+		printf("%3d: FP: " REG_FMT " RA: " REG_FMT,
 		       count, (ulong)fp, ra);
 
 		if (gd && gd->flags & GD_FLG_RELOC)
@@ -87,12 +86,6 @@ static void show_backtrace(struct pt_regs *regs)
 		count++;
 	}
 }
-#else
-static void show_backtrace(struct pt_regs *regs)
-{
-	printf("No backtrace support enabled\n");
-}
-#endif
 
 /**
  * instr_len() - get instruction length
@@ -165,7 +158,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
 		       epc - gd->reloc_off, regs->ra - gd->reloc_off);
 
 	show_regs(regs);
-	show_backtrace(regs);
+	if (CONFIG_IS_ENABLED(FRAMEPOINTER))
+		show_backtrace(regs);
 	show_code(epc);
 	show_efi_loaded_images(epc);
 	panic("\n");