diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/pl310.h | 9 | ||||
| -rw-r--r-- | arch/arm/mach-kirkwood/cpu.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-kirkwood/include/mach/cpu.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 39 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/include/mach/cpu.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/lowlevel.S | 30 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/mbus.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/system-controller.c | 2 |
9 files changed, 59 insertions, 31 deletions
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index f69e9e4..9d4cd68 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -7,13 +7,12 @@ #ifndef _PL310_H_ #define _PL310_H_ -#include <linux/types.h> - /* Register bit fields */ #define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) #define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1) #define L2X0_STNDBY_MODE_EN (1 << 0) #define L2X0_CTRL_EN 1 +#define L2X0_CTRL_OFF 0x100 #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) @@ -27,6 +26,10 @@ #define L2X0_CACHE_ID_RTL_MASK 0x3f #define L2X0_CACHE_ID_RTL_R3P2 0x8 +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + struct pl310_regs { u32 pl310_cache_id; u32 pl310_cache_type; @@ -87,3 +90,5 @@ void pl310_inval_range(u32 start, u32 end); void pl310_clean_inval_range(u32 start, u32 end); #endif + +#endif diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 80f893a..df3e8f1 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -52,7 +52,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) return (0x0000ffff & j); } -static struct mbus_win windows[] = { +static const struct mbus_win windows[] = { /* Window 0: PCIE MEM address space */ { KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE, KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index d8639c6..9eec786 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -150,7 +150,7 @@ struct kwgpio_registers { unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int mvebu_mbus_probe(struct mbus_win windows[], int count); +int mvebu_mbus_probe(const struct mbus_win windows[], int count); void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1457af1..1f8cdf8 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -20,7 +20,7 @@ #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) -static struct mbus_win windows[] = { +static const struct mbus_win windows[] = { /* SPI */ { MBUS_SPI_BASE, MBUS_SPI_SIZE, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, @@ -445,19 +445,6 @@ static void setup_usb_phys(void) */ int arch_cpu_init(void) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - - if (IS_ENABLED(CONFIG_ARMADA_38X)) { - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - } - /* * We need to call mvebu_mbus_probe() before calling * update_sdram_window_sizes() as it disables all previously @@ -663,7 +650,7 @@ void enable_caches(void) * ethernet driver (mvpp2). So lets keep the d-cache disabled * until this is solved. */ - if (IS_ENABLED(CONFIG_ARMADA_375)) { + if (!IS_ENABLED(CONFIG_ARMADA_375)) { /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } @@ -671,13 +658,21 @@ void enable_caches(void) void v7_outer_cache_enable(void) { + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + /* The L2 cache is already disabled at this point */ + + /* + * For now L2 cache will be enabled only for Armada XP and Armada 38x. + * It can be enabled also for other SoCs after testing that it works fine. + */ + if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X)) + return; + if (IS_ENABLED(CONFIG_ARMADA_XP)) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; u32 u; - /* The L2 cache is already disabled at this point */ - /* * For Aurora cache in no outer mode, enable via the CP15 * coprocessor broadcasting of cache commands to L2. @@ -687,10 +682,10 @@ void v7_outer_cache_enable(void) asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); isb(); - - /* Enable the L2 cache */ - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } void v7_outer_cache_disable(void) diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index d9fa1f3..b127fce 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -128,7 +128,7 @@ struct sar_freq_modes { unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); -int mvebu_mbus_probe(struct mbus_win windows[], int count); +int mvebu_mbus_probe(const struct mbus_win windows[], int count); u32 mvebu_get_nand_clock(void); void __noreturn return_to_bootrom(void); diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S index 2491310..60c2072 100644 --- a/arch/arm/mach-mvebu/lowlevel.S +++ b/arch/arm/mach-mvebu/lowlevel.S @@ -2,6 +2,8 @@ #include <config.h> #include <linux/linkage.h> +#include <asm/system.h> +#include <asm/pl310.h> ENTRY(arch_very_early_init) #ifdef CONFIG_ARMADA_38X @@ -10,10 +12,36 @@ ENTRY(arch_very_early_init) * register address on Armada 38x. Without this the SDRAM * located at >= 0x4000.0000 is also not accessible, as its * still locked to cache. + * + * So to fully release / unlock this area from cache, we need + * to first flush all caches, then disable the MMU and + * disable the L2 cache. */ + + /* Invalidate L1 I/D */ + mov r0, #0 @ set up for MCR + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array + mcr p15, 0, r0, c7, c10, 4 @ DSB + mcr p15, 0, r0, c7, c5, 4 @ ISB + + /* Disable MMU */ mrc p15, 0, r0, c1, c0, 0 - bic r0, #1 + bic r0, #CR_M mcr p15, 0, r0, c1, c0, 0 + + /* + * Disable L2 cache + * + * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG + * but CONFIG_SYS_PL310_BASE is already calculated from base + * address SOC_REGS_PHY_BASE. + */ + ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) + ldr r0, [r1, #L2X0_CTRL_OFF] + bic r0, #L2X0_CTRL_EN + str r0, [r1, #L2X0_CTRL_OFF] #endif /* Move internal registers from INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE */ diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 7092f6c..959ca8e 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -469,7 +469,7 @@ int mbus_dt_setup_win(u32 base, u32 size, u8 target, u8 attr) return 0; } -int mvebu_mbus_probe(struct mbus_win windows[], int count) +int mvebu_mbus_probe(const struct mbus_win windows[], int count) { int win; int ret; diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 2e467b5..943ae01 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -105,7 +105,7 @@ struct serdes_unit_data { u8 serdes_unit_num; }; -static struct serdes_unit_data serdes_type_to_unit_info[] = { +static const struct serdes_unit_data serdes_type_to_unit_info[] = { {PEX_UNIT_ID, 0,}, {PEX_UNIT_ID, 1,}, {PEX_UNIT_ID, 2,}, diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index ea858b2..e90aff0 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -86,7 +86,7 @@ static const struct udevice_id mvebu_reset_of_match[] = { { }, }; -static struct reset_ops mvebu_reset_ops = { +static const struct reset_ops mvebu_reset_ops = { .of_xlate = mvebu_reset_of_xlate, .request = mvebu_reset_request, .rfree = mvebu_reset_free, |