diff options
Diffstat (limited to 'arch')
63 files changed, 1272 insertions, 349 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 50f35e3..0fcae77 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -181,6 +181,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ rk3566-soquartz-model-a.dtb \ rk3568-bpi-r2-pro.dtb \ rk3568-evb.dtb \ + rk3568-generic.dtb \ rk3568-lubancat-2.dtb \ rk3568-nanopi-r5c.dtb \ rk3568-nanopi-r5s.dtb \ diff --git a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi index 732727d..0897325 100644 --- a/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rockpro64-u-boot.dtsi @@ -9,6 +9,28 @@ chosen { u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci; }; + + smbios { + compatible = "u-boot,sysinfo-smbios"; + smbios { + system { + manufacturer = "Pine64"; + product = "RockPro64"; + }; + + baseboard { + manufacturer = "Pine64"; + product = "RockPro64"; + }; + + chassis { + manufacturer = "Pine64"; + product = "RockPro64"; + }; + }; + }; + + }; &sdhci { diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi index f986e19..fa3df73 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi @@ -4,7 +4,6 @@ / { chosen { - stdout-path = &uart2; u-boot,spl-boot-order = "same-as-spl", &sdmmc1, &sdmmc0; }; @@ -88,9 +87,3 @@ vqmmc-supply = <&vcc_1v8>; status = "okay"; }; - -&uart2 { - clock-frequency = <24000000>; - bootph-all; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi index ad43fa1..8cbf3d9 100644 --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dtsi @@ -191,30 +191,30 @@ }; }; - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; + leds: pwm-leds { + compatible = "pwm-leds"; green_led: led-0 { color = <LED_COLOR_ID_GREEN>; default-state = "on"; function = LED_FUNCTION_POWER; - gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; }; amber_led: led-1 { color = <LED_COLOR_ID_AMBER>; function = LED_FUNCTION_CHARGING; - gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; - retain-state-suspended; + max-brightness = <255>; + pwms = <&pwm7 0 25000 0>; }; red_led: led-2 { color = <LED_COLOR_ID_RED>; default-state = "off"; function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + max-brightness = <255>; + pwms = <&pwm0 0 25000 0>; }; }; @@ -356,7 +356,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -371,7 +370,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_gpu"; @@ -533,7 +531,6 @@ regulator-boot-on; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1390000>; - regulator-init-microvolt = <900000>; regulator-name = "vdd_cpu"; regulator-ramp-delay = <2300>; vin-supply = <&vcc_sys>; @@ -597,15 +594,6 @@ }; }; - gpio-led { - led_pins: led-pins { - rockchip,pins = - <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - joy-mux { joy_mux_en: joy-mux-en { rockchip,pins = @@ -654,10 +642,24 @@ vccio7-supply = <&vcc_3v3>; }; +&pwm0 { + pinctrl-0 = <&pwm0m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pwm5 { status = "okay"; }; +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8>; status = "okay"; diff --git a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi index 06cc15e..930d660 100644 --- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi +++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi @@ -2,19 +2,12 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &gpio0 { bootph-all; }; &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; @@ -28,12 +21,6 @@ }; }; -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - /* * U-Boot does not support multiple regulators using the same gpio, * use vcc5v0_usb20_host to fix use of USB 2.0 port diff --git a/arch/arm/dts/rk3566-quartz64-a.dts b/arch/arm/dts/rk3566-quartz64-a.dts index 25a8c78..59843a7 100644 --- a/arch/arm/dts/rk3566-quartz64-a.dts +++ b/arch/arm/dts/rk3566-quartz64-a.dts @@ -31,8 +31,9 @@ fan: gpio_fan { compatible = "gpio-fan"; gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0 - 4500 1>; + gpio-fan,speed-map = + < 0 0>, + <4500 1>; pinctrl-names = "default"; pinctrl-0 = <&fan_en_h>; #cooling-cells = <2>; @@ -366,7 +367,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_logic"; @@ -381,7 +381,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-name = "vdd_gpu"; diff --git a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi index 3c2c54e..c235b43 100644 --- a/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi +++ b/arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi @@ -2,15 +2,8 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; @@ -24,12 +17,6 @@ }; }; -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3566-quartz64-b.dts b/arch/arm/dts/rk3566-quartz64-b.dts index b276eb0..2d92713 100644 --- a/arch/arm/dts/rk3566-quartz64-b.dts +++ b/arch/arm/dts/rk3566-quartz64-b.dts @@ -277,7 +277,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-state-mem { @@ -292,7 +291,6 @@ regulator-boot-on; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-state-mem { diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi index c925439..e0e501d 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi @@ -5,19 +5,6 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; -}; - -&uart2 { - clock-frequency = <24000000>; - bootph-all; - status = "okay"; }; diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts b/arch/arm/dts/rk3566-radxa-cm3-io.dts index 5e4236a..3ae24e3 100644 --- a/arch/arm/dts/rk3566-radxa-cm3-io.dts +++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts @@ -14,6 +14,7 @@ compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; aliases { + ethernet0 = &gmac1; mmc1 = &sdmmc0; }; @@ -137,8 +138,8 @@ &mdio1 { rgmii_phy1: ethernet-phy@0 { - compatible="ethernet-phy-ieee802.3-c22"; - reg= <0x0>; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; }; }; diff --git a/arch/arm/dts/rk3566-soquartz-blade.dts b/arch/arm/dts/rk3566-soquartz-blade.dts index 4e49beb..fdbf1c7 100644 --- a/arch/arm/dts/rk3566-soquartz-blade.dts +++ b/arch/arm/dts/rk3566-soquartz-blade.dts @@ -13,6 +13,10 @@ model = "PINE64 RK3566 SOQuartz on Blade carrier board"; compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; + aliases { + ethernet0 = &gmac1; + }; + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ vcc3v0_sd: vcc3v0-sd-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/dts/rk3566-soquartz-cm4.dts b/arch/arm/dts/rk3566-soquartz-cm4.dts index cddf6cd..6ed3fa4 100644 --- a/arch/arm/dts/rk3566-soquartz-cm4.dts +++ b/arch/arm/dts/rk3566-soquartz-cm4.dts @@ -8,6 +8,10 @@ model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566"; + aliases { + ethernet0 = &gmac1; + }; + /* labeled +12v in schematic */ vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/dts/rk3566-soquartz-model-a.dts b/arch/arm/dts/rk3566-soquartz-model-a.dts index 2208dbf..f2095df 100644 --- a/arch/arm/dts/rk3566-soquartz-model-a.dts +++ b/arch/arm/dts/rk3566-soquartz-model-a.dts @@ -8,6 +8,10 @@ model = "PINE64 RK3566 SOQuartz on Model A carrier board"; compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; + aliases { + ethernet0 = &gmac1; + }; + /* labeled DCIN_12V in schematic */ vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi index 793cca2..5e46a24 100644 --- a/arch/arm/dts/rk3566-soquartz-u-boot.dtsi +++ b/arch/arm/dts/rk3566-soquartz-u-boot.dtsi @@ -2,25 +2,12 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3566-soquartz.dtsi b/arch/arm/dts/rk3566-soquartz.dtsi index 31aa2b8..bfb7b95 100644 --- a/arch/arm/dts/rk3566-soquartz.dtsi +++ b/arch/arm/dts/rk3566-soquartz.dtsi @@ -12,7 +12,6 @@ compatible = "pine64,soquartz", "rockchip,rk3566"; aliases { - ethernet0 = &gmac1; mmc0 = &sdmmc0; mmc1 = &sdhci; mmc2 = &sdmmc1; @@ -234,7 +233,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-state-mem { @@ -249,7 +247,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; regulator-state-mem { @@ -272,7 +269,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-name = "vdd_npu"; regulator-state-mem { diff --git a/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi index 60a3b21..5f4f14b 100644 --- a/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi +++ b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi @@ -4,16 +4,3 @@ */ #include "rk356x-u-boot.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; -}; - -&uart2 { - clock-frequency = <24000000>; - bootph-pre-ram; - status = "okay"; -}; - diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb-u-boot.dtsi index 382a52a..5f4f14b 100644 --- a/arch/arm/dts/rk3568-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi @@ -4,20 +4,3 @@ */ #include "rk356x-u-boot.dtsi" - -/ { - chosen { - stdout-path = &uart2; - u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; - }; -}; - -&sdmmc0 { - status = "okay"; -}; - -&uart2 { - clock-frequency = <24000000>; - bootph-pre-ram; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts index 6747925..19f8fc3 100644 --- a/arch/arm/dts/rk3568-evb.dts +++ b/arch/arm/dts/rk3568-evb.dts @@ -293,7 +293,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -307,7 +306,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -331,7 +329,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; diff --git a/arch/arm/dts/rk3568-generic-u-boot.dtsi b/arch/arm/dts/rk3568-generic-u-boot.dtsi index 9002258..6e8307e 100644 --- a/arch/arm/dts/rk3568-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3568-generic-u-boot.dtsi @@ -1,14 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk356x-u-boot.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; -}; - -&uart2 { - bootph-pre-ram; - clock-frequency = <24000000>; -}; diff --git a/arch/arm/dts/rk3568-generic.dts b/arch/arm/dts/rk3568-generic.dts index 1006ea5..88eb1bf 100644 --- a/arch/arm/dts/rk3568-generic.dts +++ b/arch/arm/dts/rk3568-generic.dts @@ -10,7 +10,12 @@ model = "Generic RK3566/RK3568"; compatible = "rockchip,rk3568"; - chosen: chosen { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { stdout-path = "serial2:1500000n8"; }; }; @@ -18,6 +23,9 @@ &sdhci { bus-width = <8>; cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; non-removable; pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; @@ -28,6 +36,8 @@ bus-width = <4>; cap-sd-highspeed; disable-wp; + no-mmc; + no-sdio; pinctrl-names = "default"; pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; status = "okay"; diff --git a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi index 27c6277..1597473 100644 --- a/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi +++ b/arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi @@ -6,22 +6,9 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; - -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-lubancat-2.dts b/arch/arm/dts/rk3568-lubancat-2.dts index e653b06..a8a4cc1 100644 --- a/arch/arm/dts/rk3568-lubancat-2.dts +++ b/arch/arm/dts/rk3568-lubancat-2.dts @@ -243,7 +243,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; @@ -258,7 +257,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; @@ -284,7 +282,6 @@ regulator-boot-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-initial-mode = <0x2>; diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi index 880f8ff..64c4337 100644 --- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -8,31 +8,18 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &pcie3x1 { /delete-property/ vpcie3v3-supply; }; &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; }; -&uart2 { - clock-frequency = <24000000>; - bootph-all; - status = "okay"; -}; - &vcc5v0_usb_host { /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; diff --git a/arch/arm/dts/rk3568-nanopi-r5s.dtsi b/arch/arm/dts/rk3568-nanopi-r5s.dtsi index 58ba328..93189f8 100644 --- a/arch/arm/dts/rk3568-nanopi-r5s.dtsi +++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi @@ -232,7 +232,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -246,7 +245,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -270,7 +268,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; diff --git a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi index 0fc360b..1fc71fa 100644 --- a/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi +++ b/arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi @@ -2,19 +2,12 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &fspi_dual_io_pins { bootph-all; }; &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; @@ -29,9 +22,3 @@ bootph-pre-ram; }; }; - -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-odroid-m1.dts b/arch/arm/dts/rk3568-odroid-m1.dts index 59ecf86..a337f54 100644 --- a/arch/arm/dts/rk3568-odroid-m1.dts +++ b/arch/arm/dts/rk3568-odroid-m1.dts @@ -291,7 +291,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -305,7 +304,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -329,7 +327,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; diff --git a/arch/arm/dts/rk3568-radxa-cm3i.dtsi b/arch/arm/dts/rk3568-radxa-cm3i.dtsi index c50fbdd..45b03dc 100644 --- a/arch/arm/dts/rk3568-radxa-cm3i.dtsi +++ b/arch/arm/dts/rk3568-radxa-cm3i.dtsi @@ -163,7 +163,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -177,7 +176,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -201,7 +199,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi index 1136f0b..74755a4 100644 --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -2,12 +2,6 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &pcie3x1 { pinctrl-0 = <&pcie30x1_reset_h>; }; @@ -22,18 +16,11 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; }; -&uart2 { - bootph-all; - clock-frequency = <24000000>; - status = "okay"; -}; - &usb_host0_xhci { dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index b05b715..5b823fc 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk356x-u-boot.dtsi" -/ { - chosen { - stdout-path = &uart2; - }; -}; - &pcie3x2 { pinctrl-0 = <&pcie3x2_reset_h>; }; @@ -26,7 +20,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; @@ -48,9 +41,3 @@ spi-tx-bus-width = <1>; }; }; - -&uart2 { - clock-frequency = <24000000>; - bootph-all; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3568-rock-3a.dts b/arch/arm/dts/rk3568-rock-3a.dts index 917f5b2..a5e974e 100644 --- a/arch/arm/dts/rk3568-rock-3a.dts +++ b/arch/arm/dts/rk3568-rock-3a.dts @@ -15,6 +15,7 @@ ethernet0 = &gmac1; mmc0 = &sdhci; mmc1 = &sdmmc0; + mmc2 = &sdmmc2; }; chosen: chosen { @@ -350,7 +351,6 @@ regulator-name = "vdd_logic"; regulator-always-on; regulator-boot-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -364,7 +364,6 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; regulator-always-on; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -388,7 +387,6 @@ vdd_npu: DCDC_REG4 { regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1350000>; @@ -750,6 +748,9 @@ non-removable; pinctrl-names = "default"; pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; sd-uhs-sdr104; vmmc-supply = <&vcc3v3_sys>; vqmmc-supply = <&vcc_1v8>; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 354b695..d347080 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -19,7 +19,6 @@ dmc: dmc { compatible = "rockchip,rk3568-dmc"; bootph-all; - status = "okay"; }; otp: nvmem@fe38c000 { @@ -27,7 +26,6 @@ reg = <0x0 0xfe38c000 0x0 0x4000>; #address-cells = <1>; #size-cells = <1>; - status = "okay"; cpu_id: id@a { reg = <0x0a 0x10>; @@ -37,27 +35,22 @@ &xin24m { bootph-all; - status = "okay"; }; &cru { bootph-all; - status = "okay"; }; &pmucru { bootph-all; - status = "okay"; }; &grf { bootph-all; - status = "okay"; }; &pmugrf { bootph-all; - status = "okay"; }; &pinctrl { @@ -141,6 +134,11 @@ bootph-pre-ram; }; +&uart2 { + bootph-pre-ram; + clock-frequency = <24000000>; +}; + #ifdef CONFIG_ROCKCHIP_SPI_IMAGE &binman { simple-bin-spi { diff --git a/arch/arm/dts/rk356x.dtsi b/arch/arm/dts/rk356x.dtsi index 61680c7..c19c0f1 100644 --- a/arch/arm/dts/rk356x.dtsi +++ b/arch/arm/dts/rk356x.dtsi @@ -613,6 +613,17 @@ #iommu-cells = <0>; }; + rga: rga@fdeb0000 { + compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; + reg = <0x0 0xfdeb0000 0x0 0x180>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3568_PD_RGA>; + }; + vepu: video-codec@fdee0000 { compatible = "rockchip,rk3568-vepu"; reg = <0x0 0xfdee0000 0x0 0x800>; @@ -948,6 +959,13 @@ reg = <0x0 0xfe1a8100 0x0 0x20>; }; + dfi: dfi@fe230000 { + compatible = "rockchip,rk3568-dfi"; + reg = <0x00 0xfe230000 0x00 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + rockchip,pmu = <&pmugrf>; + }; + pcie2x1: pcie@fe260000 { compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0000000 0x0 0x00400000>, @@ -959,7 +977,7 @@ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "sys", "pmc", "msi", "legacy", "err"; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; bus-range = <0x0 0xf>; clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, diff --git a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts index b515438..be6a4f4 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a-io.dts +++ b/arch/arm/dts/rk3588-edgeble-neu6a-io.dts @@ -12,10 +12,6 @@ compatible = "edgeble,neural-compute-module-6a-io", "edgeble,neural-compute-module-6a", "rockchip,rk3588"; - aliases { - serial2 = &uart2; - }; - chosen { stdout-path = "serial2:1500000n8"; }; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts index 9933765..070baeb 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts @@ -9,13 +9,9 @@ / { model = "Edgeble Neu6B IO Board"; - compatible = "edgeble,neural-compute-module-6b-io", + compatible = "edgeble,neural-compute-module-6a-io", "edgeble,neural-compute-module-6b", "rockchip,rk3588"; - aliases { - serial2 = &uart2; - }; - chosen { stdout-path = "serial2:1500000n8"; }; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts index b9d789d..ac7c677 100644 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -16,8 +16,8 @@ compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588"; aliases { + ethernet0 = &gmac0; mmc0 = &sdhci; - serial2 = &uart2; }; chosen { @@ -56,6 +56,63 @@ }; }; + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,name = "RK3588 EVB1 Audio"; + simple-audio-card,aux-devs = <&_headphone>, <&_speaker>; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&masterdai>; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,pin-switches = "Headphones", "Speaker"; + simple-audio-card,routing = + "Speaker Amplifier INL", "LOUT2", + "Speaker Amplifier INR", "ROUT2", + "Speaker", "Speaker Amplifier OUTL", + "Speaker", "Speaker Amplifier OUTR", + "Headphones Amplifier INL", "LOUT1", + "Headphones Amplifier INR", "ROUT1", + "Headphones", "Headphones Amplifier OUTL", + "Headphones", "Headphones Amplifier OUTR", + "LINPUT1", "Onboard Microphone", + "RINPUT1", "Onboard Microphone", + "LINPUT2", "Microphone Jack", + "RINPUT2", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + amp_headphone: headphone-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&headphone_amplifier_en>; + sound-name-prefix = "Headphones Amplifier"; + }; + + amp_speaker: speaker-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&speaker_amplifier_en>; + sound-name-prefix = "Speaker Amplifier"; + }; + backlight: backlight { compatible = "pwm-backlight"; power-supply = <&vcc12v_dcin>; @@ -240,6 +297,32 @@ }; }; +&i2c7 { + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + AVDD-supply = <&avcc_1v8_codec_s0>; + DVDD-supply = <&avcc_1v8_codec_s0>; + HPVDD-supply = <&vcc_3v3_s0>; + PVDD-supply = <&vcc_3v3_s0>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + &mdio0 { rgmii_phy: ethernet-phy@1 { /* RTL8211F */ @@ -273,6 +356,20 @@ }; &pinctrl { + audio { + hp_detect: headphone-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + headphone_amplifier_en: headphone-amplifier-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + speaker_amplifier_en: speaker-amplifier-en { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + rtl8111 { rtl8111_isolate: rtl8111-isolate { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi index 87831c9..60494bb 100644 --- a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi +++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi @@ -6,12 +6,6 @@ #include "rk3588-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; - &fspim1_pins { bootph-all; }; diff --git a/arch/arm/dts/rk3588-nanopc-t6.dts b/arch/arm/dts/rk3588-nanopc-t6.dts index 97af4f9..d772277 100644 --- a/arch/arm/dts/rk3588-nanopc-t6.dts +++ b/arch/arm/dts/rk3588-nanopc-t6.dts @@ -19,7 +19,6 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc; - serial2 = &uart2; }; chosen { @@ -537,13 +536,12 @@ }; &sdmmc { - max-frequency = <200000000>; - no-sdio; - no-mmc; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; disable-wp; + no-mmc; + no-sdio; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s3>; vqmmc-supply = <&vccio_sd_s0>; @@ -570,6 +568,8 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc4v0_sys>; vcc2-supply = <&vcc4v0_sys>; vcc3-supply = <&vcc4v0_sys>; @@ -590,7 +590,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi index b0f5c66..5d5fa6f 100644 --- a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi +++ b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi @@ -2,12 +2,6 @@ #include "rk3588-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; - &fspim1_pins { bootph-all; }; diff --git a/arch/arm/dts/rk3588-orangepi-5-plus.dts b/arch/arm/dts/rk3588-orangepi-5-plus.dts index 298c183..3e660ff 100644 --- a/arch/arm/dts/rk3588-orangepi-5-plus.dts +++ b/arch/arm/dts/rk3588-orangepi-5-plus.dts @@ -19,7 +19,6 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc; - serial2 = &uart2; }; chosen { diff --git a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi index 191ec98..7b93794 100644 --- a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi +++ b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi @@ -4,9 +4,3 @@ */ #include "rk3588-u-boot.dtsi" - -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; diff --git a/arch/arm/dts/rk3588-quartzpro64.dts b/arch/arm/dts/rk3588-quartzpro64.dts index 5c59f95..87a0abf 100644 --- a/arch/arm/dts/rk3588-quartzpro64.dts +++ b/arch/arm/dts/rk3588-quartzpro64.dts @@ -17,9 +17,9 @@ compatible = "pine64,quartzpro64", "rockchip,rk3588"; aliases { + ethernet0 = &gmac0; mmc0 = &sdhci; mmc1 = &sdmmc; - serial2 = &uart2; }; chosen { diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index b595dde..9ee9dd0 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -7,10 +7,6 @@ #include <dt-bindings/usb/pd.h> / { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; - vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -21,10 +17,6 @@ }; }; -&combphy2_psu { - status = "okay"; -}; - &fspim2_pins { bootph-all; }; @@ -39,7 +31,6 @@ &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; @@ -129,10 +120,6 @@ status = "okay"; }; -&usb_host2_xhci { - status = "okay"; -}; - &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4m1_xfer>; diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 741f631..a0e303c 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -14,7 +14,6 @@ mmc0 = &sdhci; mmc1 = &sdmmc; mmc2 = &sdio; - serial2 = &uart2; }; chosen { @@ -138,6 +137,10 @@ status = "okay"; }; +&combphy2_psu { + status = "okay"; +}; + &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; }; @@ -423,6 +426,8 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; vcc3-supply = <&vcc5v0_sys>; @@ -443,7 +448,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; @@ -765,3 +770,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi index 06c6f32..ca2a684 100644 --- a/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi +++ b/arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi @@ -6,20 +6,12 @@ #include "rk3588-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; &uart9 { bootph-pre-ram; clock-frequency = <24000000>; - status = "okay"; }; diff --git a/arch/arm/dts/rk3588-turing-rk1.dtsi b/arch/arm/dts/rk3588-turing-rk1.dtsi index 9570b34..dc08da5 100644 --- a/arch/arm/dts/rk3588-turing-rk1.dtsi +++ b/arch/arm/dts/rk3588-turing-rk1.dtsi @@ -19,8 +19,6 @@ aliases { ethernet0 = &gmac1; mmc0 = &sdhci; - serial2 = &uart2; - serial9 = &uart9; }; fan: pwm-fan { @@ -235,13 +233,13 @@ &pinctrl { fan { fan_int: fan-int { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; hym8563 { hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 31046fc..992f7b5 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -7,7 +7,7 @@ / { usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, diff --git a/arch/arm/dts/rk3588s-orangepi-5.dts b/arch/arm/dts/rk3588s-orangepi-5.dts index 8f399c4..25de436 100644 --- a/arch/arm/dts/rk3588s-orangepi-5.dts +++ b/arch/arm/dts/rk3588s-orangepi-5.dts @@ -13,8 +13,8 @@ compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; aliases { + ethernet0 = &gmac1; mmc0 = &sdmmc; - serial2 = &uart2; }; chosen { @@ -38,7 +38,7 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 =<&leds_gpio>; + pinctrl-0 = <&leds_gpio>; led-1 { gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; @@ -314,6 +314,7 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; spi-max-frequency = <1000000>; + system-power-controller; vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; @@ -660,3 +661,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi index 63151d9..30db12c 100644 --- a/arch/arm/dts/rk3588s-pinctrl.dtsi +++ b/arch/arm/dts/rk3588s-pinctrl.dtsi @@ -369,7 +369,7 @@ emmc_data_strobe: emmc-data-strobe { rockchip,pins = /* emmc_data_strobe */ - <2 RK_PA2 1 &pcfg_pull_none>; + <2 RK_PA2 1 &pcfg_pull_down>; }; }; diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index 584476f..efba0c3 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -5,14 +5,7 @@ #include "rk3588s-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; - }; -}; - &sdhci { cap-mmc-highspeed; - mmc-ddr-1_8v; mmc-hs200-1_8v; }; diff --git a/arch/arm/dts/rk3588s-rock-5a.dts b/arch/arm/dts/rk3588s-rock-5a.dts index 8347adc..2002fd0 100644 --- a/arch/arm/dts/rk3588s-rock-5a.dts +++ b/arch/arm/dts/rk3588s-rock-5a.dts @@ -12,9 +12,9 @@ compatible = "radxa,rock-5a", "rockchip,rk3588s"; aliases { + ethernet0 = &gmac1; mmc0 = &sdhci; mmc1 = &sdmmc; - serial2 = &uart2; }; analog-sound { @@ -114,6 +114,10 @@ }; }; +&combphy2_psu { + status = "okay"; +}; + &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; }; @@ -734,3 +738,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index c0fd16c..bf3b1ea8 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -7,22 +7,20 @@ / { aliases { - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; spi5 = &sfc; }; + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; + dmc { compatible = "rockchip,rk3588-dmc"; bootph-all; - status = "okay"; }; usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc000000 0x0 0x400000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, @@ -43,33 +41,6 @@ status = "disabled"; }; - usb_host2_xhci: usb@fcd00000 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; - reg = <0x0 0xfcd00000 0x0 0x400000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, - <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, - <&cru CLK_PIPEPHY2_PIPE_U3_G>; - clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; - dr_mode = "host"; - phys = <&combphy2_psu PHY_TYPE_USB3>; - phy-names = "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_A_USB3OTG2>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - pmu1_grf: syscon@fd58a000 { - bootph-all; - compatible = "rockchip,rk3588-pmu1-grf", "syscon"; - reg = <0x0 0xfd58a000 0x0 0x2000>; - }; - usbdpphy0_grf: syscon@fd5c8000 { compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; reg = <0x0 0xfd5c8000 0x0 0x4000>; @@ -193,17 +164,18 @@ &xin24m { bootph-all; - status = "okay"; }; &cru { bootph-pre-ram; - status = "okay"; }; &sys_grf { bootph-pre-ram; - status = "okay"; +}; + +&pmu1grf { + bootph-all; }; &scmi { @@ -241,9 +213,8 @@ }; &uart2 { - clock-frequency = <24000000>; bootph-pre-ram; - status = "okay"; + clock-frequency = <24000000>; }; &uart2m0_xfer { diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 61a9a11..36b1b7a 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -18,6 +18,38 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -362,6 +394,11 @@ #clock-cells = <0>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, @@ -443,11 +480,47 @@ status = "disabled"; }; + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; }; + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + }; + php_grf: syscon@fd5b0000 { compatible = "rockchip,rk3588-php-grf", "syscon"; reg = <0x0 0xfd5b0000 0x0 0x1000>; @@ -567,6 +640,74 @@ status = "disabled"; }; + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + uart0: serial@fd890000 { compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; reg = <0x0 0xfd890000 0x0 0x100>; @@ -890,6 +1031,7 @@ reg = <RK3588_PD_USB>; clocks = <&cru PCLK_PHP_ROOT>, <&cru ACLK_USB_ROOT>, + <&cru ACLK_USB>, <&cru HCLK_USB_ROOT>, <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, @@ -1329,6 +1471,16 @@ }; }; + dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; + rockchip,pmu = <&pmu1grf>; + }; + gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts index dded0a1..0c2396b 100644 --- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts @@ -20,6 +20,76 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + v3v3_sys: v3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_ETHERNET_OUT>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; + assigned-clock-rates = <125000000>, <0>, <25000000>; + clock_in_out = "input"; + phy-handle = <&phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>; + tx_delay = <0x2a>; + rx_delay = <0x1a>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm11 { + status = "okay"; }; &sdmmc { diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/dts/rv1126-edgeble-neu2.dtsi index cc64ba4..7ea8d7d 100644 --- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi +++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi @@ -11,15 +11,6 @@ mmc0 = &emmc; }; - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - vccio_flash: vccio-flash-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -52,7 +43,7 @@ bus-width = <8>; non-removable; pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>; rockchip,default-sample-phase = <90>; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&vccio_flash>; @@ -301,6 +292,22 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &sdio { bus-width = <4>; cap-sd-highspeed; diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi index 28d8d29..f84f5f2 100644 --- a/arch/arm/dts/rv1126-pinctrl.dtsi +++ b/arch/arm/dts/rv1126-pinctrl.dtsi @@ -11,6 +11,14 @@ * by adding changes at end of this file. */ &pinctrl { + clk_out_ethernet { + /omit-if-no-ref/ + clk_out_ethernetm1_pins: clk-out-ethernetm1-pins { + rockchip,pins = + /* clk_out_ethernet_m1 */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + }; emmc { /omit-if-no-ref/ emmc_rstnout: emmc-rstnout { @@ -51,6 +59,24 @@ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; }; }; + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PA3 3 &pcfg_pull_down>, + /* fspi_cs0n */ + <0 RK_PD4 3 &pcfg_pull_up>, + /* fspi_d0 */ + <1 RK_PA0 3 &pcfg_pull_up>, + /* fspi_d1 */ + <1 RK_PA1 3 &pcfg_pull_up>, + /* fspi_d2 */ + <0 RK_PD6 3 &pcfg_pull_up>, + /* fspi_d3 */ + <1 RK_PA2 3 &pcfg_pull_up>; + }; + }; i2c0 { /omit-if-no-ref/ i2c0_xfer: i2c0-xfer { @@ -61,6 +87,86 @@ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; }; }; + i2c2 { + /omit-if-no-ref/ + i2c2_xfer: i2c2-xfer { + rockchip,pins = + /* i2c2_scl */ + <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c2_sda */ + <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_pin_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_pin_m0 */ + <3 RK_PA7 6 &pcfg_pull_none>; + }; + }; + rgmii { + /omit-if-no-ref/ + rgmiim1_miim: rgmiim1-miim { + rockchip,pins = + /* rgmii_mdc_m1 */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_rxer: rgmiim1-rxer { + rockchip,pins = + /* rgmii_rxer_m1 */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_bus2: rgmiim1-bus2 { + rockchip,pins = + /* rgmii_rxd0_m1 */ + <2 RK_PB5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <2 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <2 RK_PB4 2 &pcfg_pull_none>, + /* rgmii_txd0_m1 */ + <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd1_m1 */ + <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_bus4: rgmiim1-bus4 { + rockchip,pins = + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd2_m1 */ + <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd3_m1 */ + <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_mclkinout: rgmiim1-mclkinout { + rockchip,pins = + /* rgmii_clk_m1 */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + }; sdmmc0 { /omit-if-no-ref/ sdmmc0_bus4: sdmmc0-bus4 { @@ -187,6 +293,14 @@ /* uart3_tx_m0 */ <3 RK_PC6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <3 RK_PA1 4 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <3 RK_PA0 4 &pcfg_pull_up>; + }; }; uart4 { /omit-if-no-ref/ @@ -197,6 +311,14 @@ /* uart4_tx_m0 */ <3 RK_PA4 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PD4 3 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; }; uart5 { /omit-if-no-ref/ @@ -207,5 +329,13 @@ /* uart5_tx_m0 */ <3 RK_PA6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PA0 3 &pcfg_pull_up>; + }; }; }; diff --git a/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi new file mode 100644 index 0000000..a625660 --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rv1126-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; + }; +}; + +&sdio { + status = "disabled"; +}; diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dts b/arch/arm/dts/rv1126-sonoff-ihost.dts new file mode 100644 index 0000000..77386a4 --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-sonoff-ihost.dtsi" + +/ { + model = "Sonoff iHost 4G"; + compatible = "itead,sonoff-ihost", "rockchip,rv1126"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dtsi b/arch/arm/dts/rv1126-sonoff-ihost.dtsi new file mode 100644 index 0000000..32b329e --- /dev/null +++ b/arch/arm/dts/rv1126-sonoff-ihost.dtsi @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-name = "vdd_npu_vepu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-name = "vcc_0v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-name = "vcc0v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-name = "vcc_dovdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-name = "vcc_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-name = "vcc_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "xin32k"; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>, + <&cru CLK_GMAC_TX_RX>; + assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>, + <&cru RMII_MODE_CLK>; + assigned-clock-rates = <0>, <50000000>; + clock_in_out = "output"; + phy-handle = <&phy>; + phy-mode = "rmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-active-low; + reset-assert-us = <50000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + bt { + bt_enable: bt-enable { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc1v8_pmu>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vcc_1v8>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_dovdd>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_dovdd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723ds-bt"; + device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */ + enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */ + host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */ + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; + status = "okay"; +}; diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi index 1cb4314..bb603ca 100644 --- a/arch/arm/dts/rv1126.dtsi +++ b/arch/arm/dts/rv1126.dtsi @@ -21,6 +21,13 @@ aliases { i2c0 = &i2c0; + i2c2 = &i2c2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; }; cpus { @@ -83,6 +90,11 @@ clock-frequency = <24000000>; }; + display_subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -125,6 +137,26 @@ reg = <0xfe86c000 0x20>; }; + qos_iep: qos@fe8a0000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0000 0x20>; + }; + + qos_rga_rd: qos@fe8a0080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0080 0x20>; + }; + + qos_rga_wr: qos@fe8a0100 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0100 0x20>; + }; + + qos_vop: qos@fe8a0180 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0180 0x20>; + }; + gic: interrupt-controller@feff0000 { compatible = "arm,gic-400"; interrupt-controller; @@ -170,6 +202,25 @@ pm_qos = <&qos_sdio>; #power-domain-cells = <0>; }; + + power-domain@RV1126_PD_VO { + reg = <RV1126_PD_VO>; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru CLK_RGA_CORE>, + <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP>, + <&cru PCLK_DSIHOST>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru CLK_IEP_CORE>; + pm_qos = <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_vop>, + <&qos_iep>; + #power-domain-cells = <0>; + }; }; }; @@ -187,6 +238,20 @@ status = "disabled"; }; + i2c2: i2c@ff400000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff400000 0x1000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@ff410000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff410000 0x100>; @@ -203,6 +268,17 @@ status = "disabled"; }; + pwm2: pwm@ff430020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430020 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + pmucru: clock-controller@ff480000 { compatible = "rockchip,rv1126-pmucru"; reg = <0xff480000 0x1000>; @@ -232,6 +308,17 @@ clock-names = "apb_pclk"; }; + pwm11: pwm@ff550030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550030 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@ff560000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff560000 0x100>; @@ -332,6 +419,92 @@ clock-names = "pclk", "timer"; }; + vop: vop@ffb00000 { + compatible = "rockchip,rv1126-vop"; + reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + reset-names = "axi", "ahb", "dclk"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + iommus = <&vop_mmu>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + }; + }; + }; + + vop_mmu: iommu@ffb00f00 { + compatible = "rockchip,iommu"; + reg = <0xffb00f00 0x100>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + #iommu-cells = <0>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + }; + + gmac: ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x4000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_GMAC_A>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + emmc: mmc@ffc50000 { compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0xffc50000 0x4000>; @@ -370,6 +543,18 @@ status = "disabled"; }; + sfc: spi@ffc90000 { + compatible = "rockchip,sfc"; + reg = <0xffc90000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <80000000>; + clock-names = "clk_sfc", "hclk_sfc"; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rv1126-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6ff0aa6..1bc7ee9 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -265,6 +265,7 @@ config ROCKCHIP_RK3399 imply TPL_TINY_MEMSET imply TPL_ROCKCHIP_COMMON_BOARD imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT + imply BOOTSTD_FULL imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 @@ -292,6 +293,8 @@ config ROCKCHIP_RK3568 imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT help The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55, including NEON and GPU, 512K L3 cache, Mali-G52 based graphics, @@ -317,8 +320,11 @@ config ROCKCHIP_RK3588 imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT imply CLK_SCMI imply SCMI_FIRMWARE + imply BOOTSTD_FULL help The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4, @@ -359,6 +365,7 @@ config ROCKCHIP_RV1126 select PMIC_RK8XX select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD + select SPL_OPTEE_IMAGE if SPL_FIT imply OF_LIBFDT_OVERLAY imply ROCKCHIP_OTP imply MISC_INIT_R diff --git a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c index e8772d3..7b2cf37 100644 --- a/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/syscon_rk3588.c @@ -10,7 +10,7 @@ static const struct udevice_id rk3588_syscon_ids[] = { { .compatible = "rockchip,rk3588-sys-grf", .data = ROCKCHIP_SYSCON_GRF }, - { .compatible = "rockchip,rk3588-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { .compatible = "rockchip,rk3588-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, { .compatible = "rockchip,rk3588-vop-grf", .data = ROCKCHIP_SYSCON_VOP_GRF }, { .compatible = "rockchip,rk3588-vo-grf", .data = ROCKCHIP_SYSCON_VO_GRF }, { .compatible = "rockchip,pcie30-phy-grf", .data = ROCKCHIP_SYSCON_PCIE30_PHY_GRF }, diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index a6e2b59..55b1112 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -14,6 +14,13 @@ config TARGET_RV1126_NEU2 IO board and Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. +config TARGET_RV1126_SONOFF_IHOST + bool "Sonoff iHost smart home hub" + help + Sonoff iHost is a smart home gateway based on Rockchip RV1126 SoC. + It features Wifi, Bluetooth and Zigbee radios that are used by many + smart home devices. + config SOC_SPECIFIC_OPTIONS # dummy def_bool y select HAS_CUSTOM_SYS_INIT_SP_ADDR @@ -58,5 +65,6 @@ config TEXT_BASE default 0x600000 source board/edgeble/neural-compute-module-2/Kconfig +source board/itead/sonoff-ihost/Kconfig endif diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 99ecbdc..0d9a0ae 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -109,7 +109,14 @@ size_t rockchip_sdram_size(phys_addr_t reg) cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); cs1_col = cs0_col; - bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + if (dram_type == LPDDR5) + /* LPDDR5: 0:8bank(bk=3), 1:16bank(bk=4) */ + bk = 3 + ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & + SYS_REG_BK_MASK); + else + /* Other: 0:8bank(bk=3), 1:4bank(bk=2) */ + bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & + SYS_REG_BK_MASK); if (version >= 2) { cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) & SYS_REG_CS1_COL_MASK); |