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-rw-r--r--arch/x86/cpu/apollolake/cpu.c14
-rw-r--r--arch/x86/cpu/apollolake/cpu_common.c60
-rw-r--r--arch/x86/cpu/apollolake/cpu_spl.c58
-rw-r--r--arch/x86/cpu/coreboot/Makefile1
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c2
-rw-r--r--arch/x86/cpu/coreboot/sdram.c29
-rw-r--r--arch/x86/cpu/coreboot/tables.c255
-rw-r--r--arch/x86/cpu/coreboot/timestamp.c14
-rw-r--r--arch/x86/cpu/start_from_spl.S4
9 files changed, 77 insertions, 360 deletions
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
index fbc016d..647c9df 100644
--- a/arch/x86/cpu/apollolake/cpu.c
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -19,6 +19,7 @@
#include <asm/arch/iomap.h>
#include <dm/acpi.h>
+#ifdef CONFIG_ACPIGEN
#define CSTATE_RES(address_space, width, offset, address) \
{ \
.space_id = address_space, \
@@ -57,11 +58,6 @@ static struct acpi_cstate cstate_map[] = {
},
};
-static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
-{
- return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
-}
-
static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
{
uint core_id = dev_seq(dev);
@@ -89,6 +85,12 @@ static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
return 0;
}
+#endif /* CONFIG_ACPIGEN */
+
+static int apl_get_info(const struct udevice *dev, struct cpu_info *info)
+{
+ return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
+}
static void update_fixed_mtrrs(void)
{
@@ -170,9 +172,11 @@ static int cpu_apl_probe(struct udevice *dev)
return 0;
}
+#ifdef CONFIG_ACPIGEN
struct acpi_ops apl_cpu_acpi_ops = {
.fill_ssdt = acpi_cpu_fill_ssdt,
};
+#endif
static const struct cpu_ops cpu_x86_apl_ops = {
.get_desc = cpu_x86_get_desc,
diff --git a/arch/x86/cpu/apollolake/cpu_common.c b/arch/x86/cpu/apollolake/cpu_common.c
index 63f6999..5d7d26b 100644
--- a/arch/x86/cpu/apollolake/cpu_common.c
+++ b/arch/x86/cpu/apollolake/cpu_common.c
@@ -7,11 +7,17 @@
#include <dm.h>
#include <log.h>
#include <asm/cpu_common.h>
+#include <asm/io.h>
#include <asm/msr.h>
+#include <asm/pci.h>
#include <asm/arch/cpu.h>
#include <asm/arch/iomap.h>
+#include <asm/arch/uart.h>
#include <power/acpi_pmc.h>
+/* Define this here to avoid referencing any drivers for the debug UART 1 */
+#define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
+
void cpu_flush_l1d_to_l2(void)
{
struct msr_t msr;
@@ -40,3 +46,57 @@ void enable_pm_timer_emulation(const struct udevice *pmc)
debug("PM timer %x %x\n", msr.hi, msr.lo);
msr_write(MSR_EMULATE_PM_TIMER, msr);
}
+
+static void pch_uart_init(void)
+{
+ /*
+ * Set up the pinmux so that the UART rx/tx signals are connected
+ * outside the SoC.
+ *
+ * There are about 500 lines of code required to program the GPIO
+ * configuration for the UARTs. But it boils down to four writes, and
+ * for the debug UART we want the minimum possible amount of code before
+ * the UART is running. So just add the magic writes here. See
+ * apl_hostbridge_early_init_pinctrl() for the full horror.
+ */
+ if (PCI_FUNC(PCH_DEV_UART) == 1) {
+ writel(0x40000402, 0xd0c50650);
+ writel(0x3c47, 0xd0c50654);
+ writel(0x40000400, 0xd0c50658);
+ writel(0x3c48, 0xd0c5065c);
+ } else { /* UART2 */
+ writel(0x40000402, 0xd0c50670);
+ writel(0x3c4b, 0xd0c50674);
+ writel(0x40000400, 0xd0c50678);
+ writel(0x3c4c, 0xd0c5067c);
+ }
+
+#ifdef CONFIG_DEBUG_UART
+ apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
+#endif
+}
+
+static void p2sb_enable_bar(ulong bar)
+{
+ /* Enable PCR Base address in PCH */
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
+ PCI_SIZE_32);
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
+
+ /* Enable P2SB MSE */
+ pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
+ PCI_SIZE_8);
+}
+
+/*
+ * board_debug_uart_init() - Init the debug UART ready for use
+ *
+ * This is the minimum init needed to get the UART running. It avoids any
+ * drivers or complex code, so that the UART is running as soon as possible.
+ */
+void board_debug_uart_init(void)
+{
+ p2sb_enable_bar(IOMAP_P2SB_BAR);
+ pch_uart_init();
+}
diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c
index 9a18476..8f48457 100644
--- a/arch/x86/cpu/apollolake/cpu_spl.c
+++ b/arch/x86/cpu/apollolake/cpu_spl.c
@@ -31,68 +31,10 @@
#include <asm/arch/lpc.h>
#include <asm/arch/pch.h>
#include <asm/arch/systemagent.h>
-#include <asm/arch/uart.h>
#include <asm/fsp2/fsp_api.h>
#include <linux/sizes.h>
#include <power/acpi_pmc.h>
-/* Define this here to avoid referencing any drivers for the debug UART 1 */
-#define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
-
-static void pch_uart_init(void)
-{
- /*
- * Set up the pinmux so that the UART rx/tx signals are connected
- * outside the SoC.
- *
- * There are about 500 lines of code required to program the GPIO
- * configuration for the UARTs. But it boils down to four writes, and
- * for the debug UART we want the minimum possible amount of code before
- * the UART is running. So just add the magic writes here. See
- * apl_hostbridge_early_init_pinctrl() for the full horror.
- */
- if (PCI_FUNC(PCH_DEV_UART) == 1) {
- writel(0x40000402, 0xd0c50650);
- writel(0x3c47, 0xd0c50654);
- writel(0x40000400, 0xd0c50658);
- writel(0x3c48, 0xd0c5065c);
- } else { /* UART2 */
- writel(0x40000402, 0xd0c50670);
- writel(0x3c4b, 0xd0c50674);
- writel(0x40000400, 0xd0c50678);
- writel(0x3c4c, 0xd0c5067c);
- }
-
-#ifdef CONFIG_DEBUG_UART
- apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
-#endif
-}
-
-static void p2sb_enable_bar(ulong bar)
-{
- /* Enable PCR Base address in PCH */
- pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
- PCI_SIZE_32);
- pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
-
- /* Enable P2SB MSE */
- pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
- PCI_SIZE_8);
-}
-
-/*
- * board_debug_uart_init() - Init the debug UART ready for use
- *
- * This is the minimum init needed to get the UART running. It avoids any
- * drivers or complex code, so that the UART is running as soon as possible.
- */
-void board_debug_uart_init(void)
-{
- p2sb_enable_bar(IOMAP_P2SB_BAR);
- pch_uart_init();
-}
-
static int fast_spi_cache_bios_region(void)
{
uint map_size, offset;
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index 605f903..a6cdb9a 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -20,5 +20,4 @@ else
obj-y += sdram.o
endif
obj-y += coreboot.o
-obj-y += tables.o
obj-y += timestamp.o
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 15c3ad8..69cf8f4 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -14,7 +14,7 @@
#include <asm/io.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
-#include <asm/arch/sysinfo.h>
+#include <asm/cb_sysinfo.h>
#include <asm/arch/timestamp.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index a2e47d1..4a256ba 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <init.h>
#include <asm/e820.h>
-#include <asm/arch/sysinfo.h>
+#include <asm/cb_sysinfo.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -16,32 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
unsigned int install_e820_map(unsigned int max_entries,
struct e820_entry *entries)
{
- unsigned int num_entries;
- int i;
-
- num_entries = min((unsigned int)lib_sysinfo.n_memranges, max_entries);
- if (num_entries < lib_sysinfo.n_memranges) {
- printf("Warning: Limiting e820 map to %d entries.\n",
- num_entries);
- }
- for (i = 0; i < num_entries; i++) {
- struct memrange *memrange = &lib_sysinfo.memrange[i];
-
- entries[i].addr = memrange->base;
- entries[i].size = memrange->size;
-
- /*
- * coreboot has some extensions (type 6 & 16) to the E820 types.
- * When we detect this, mark it as E820_RESERVED.
- */
- if (memrange->type == CB_MEM_VENDOR_RSVD ||
- memrange->type == CB_MEM_TABLE)
- entries[i].type = E820_RESERVED;
- else
- entries[i].type = memrange->type;
- }
-
- return num_entries;
+ return cb_install_e820_map(max_entries, entries);
}
/*
diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c
deleted file mode 100644
index c52741a..0000000
--- a/arch/x86/cpu/coreboot/tables.c
+++ /dev/null
@@ -1,255 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * This file is part of the libpayload project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2009 coresystems GmbH
- */
-
-#include <common.h>
-#include <net.h>
-#include <asm/arch/sysinfo.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * This needs to be in the .data section so that it's copied over during
- * relocation. By default it's put in the .bss section which is simply filled
- * with zeroes when transitioning from "ROM", which is really RAM, to other
- * RAM.
- */
-struct sysinfo_t lib_sysinfo __attribute__((section(".data")));
-
-/*
- * Some of this is x86 specific, and the rest of it is generic. Right now,
- * since we only support x86, we'll avoid trying to make lots of infrastructure
- * we don't need. If in the future, we want to use coreboot on some other
- * architecture, then take out the generic parsing code and move it elsewhere.
- */
-
-/* === Parsing code === */
-/* This is the generic parsing code. */
-
-static void cb_parse_memory(unsigned char *ptr, struct sysinfo_t *info)
-{
- struct cb_memory *mem = (struct cb_memory *)ptr;
- int count = MEM_RANGE_COUNT(mem);
- int i;
-
- if (count > SYSINFO_MAX_MEM_RANGES)
- count = SYSINFO_MAX_MEM_RANGES;
-
- info->n_memranges = 0;
-
- for (i = 0; i < count; i++) {
- struct cb_memory_range *range =
- (struct cb_memory_range *)MEM_RANGE_PTR(mem, i);
-
- info->memrange[info->n_memranges].base =
- UNPACK_CB64(range->start);
-
- info->memrange[info->n_memranges].size =
- UNPACK_CB64(range->size);
-
- info->memrange[info->n_memranges].type = range->type;
-
- info->n_memranges++;
- }
-}
-
-static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
-{
- struct cb_serial *ser = (struct cb_serial *)ptr;
- info->serial = ser;
-}
-
-static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info)
-{
- struct cb_vbnv *vbnv = (struct cb_vbnv *)ptr;
-
- info->vbnv_start = vbnv->vbnv_start;
- info->vbnv_size = vbnv->vbnv_size;
-}
-
-static void cb_parse_cbmem_entry(unsigned char *ptr, struct sysinfo_t *info)
-{
- struct cb_cbmem_entry *entry = (struct cb_cbmem_entry *)ptr;
-
- if (entry->id != CBMEM_ID_SMBIOS)
- return;
-
- info->smbios_start = entry->address;
- info->smbios_size = entry->entry_size;
-}
-
-static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
-{
- int i;
- struct cb_gpios *gpios = (struct cb_gpios *)ptr;
-
- info->num_gpios = (gpios->count < SYSINFO_MAX_GPIOS) ?
- (gpios->count) : SYSINFO_MAX_GPIOS;
-
- for (i = 0; i < info->num_gpios; i++)
- info->gpios[i] = gpios->gpios[i];
-}
-
-static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info)
-{
- struct cb_vdat *vdat = (struct cb_vdat *) ptr;
-
- info->vdat_addr = vdat->vdat_addr;
- info->vdat_size = vdat->vdat_size;
-}
-
-static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info)
-{
- info->tstamp_table = ((struct cb_cbmem_tab *)ptr)->cbmem_tab;
-}
-
-static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info)
-{
- info->cbmem_cons = ((struct cb_cbmem_tab *)ptr)->cbmem_tab;
-}
-
-static void cb_parse_framebuffer(unsigned char *ptr, struct sysinfo_t *info)
-{
- info->framebuffer = (struct cb_framebuffer *)ptr;
-}
-
-static void cb_parse_string(unsigned char *ptr, char **info)
-{
- *info = (char *)((struct cb_string *)ptr)->string;
-}
-
-__weak void cb_parse_unhandled(u32 tag, unsigned char *ptr)
-{
-}
-
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
-{
- unsigned char *ptr = addr;
- struct cb_header *header;
- int i;
-
- header = (struct cb_header *)ptr;
- if (!header->table_bytes)
- return 0;
-
- /* Make sure the checksums match. */
- if (!ip_checksum_ok(header, sizeof(*header)))
- return -1;
-
- if (compute_ip_checksum(ptr + sizeof(*header), header->table_bytes) !=
- header->table_checksum)
- return -1;
-
- /* Now, walk the tables. */
- ptr += header->header_bytes;
-
- /* Inintialize some fields to sentinel values. */
- info->vbnv_start = info->vbnv_size = (uint32_t)(-1);
-
- for (i = 0; i < header->table_entries; i++) {
- struct cb_record *rec = (struct cb_record *)ptr;
-
- /* We only care about a few tags here (maybe more later). */
- switch (rec->tag) {
- case CB_TAG_FORWARD:
- return cb_parse_header(
- (void *)(unsigned long)
- ((struct cb_forward *)rec)->forward,
- len, info);
- continue;
- case CB_TAG_MEMORY:
- cb_parse_memory(ptr, info);
- break;
- case CB_TAG_SERIAL:
- cb_parse_serial(ptr, info);
- break;
- case CB_TAG_VERSION:
- cb_parse_string(ptr, &info->version);
- break;
- case CB_TAG_EXTRA_VERSION:
- cb_parse_string(ptr, &info->extra_version);
- break;
- case CB_TAG_BUILD:
- cb_parse_string(ptr, &info->build);
- break;
- case CB_TAG_COMPILE_TIME:
- cb_parse_string(ptr, &info->compile_time);
- break;
- case CB_TAG_COMPILE_BY:
- cb_parse_string(ptr, &info->compile_by);
- break;
- case CB_TAG_COMPILE_HOST:
- cb_parse_string(ptr, &info->compile_host);
- break;
- case CB_TAG_COMPILE_DOMAIN:
- cb_parse_string(ptr, &info->compile_domain);
- break;
- case CB_TAG_COMPILER:
- cb_parse_string(ptr, &info->compiler);
- break;
- case CB_TAG_LINKER:
- cb_parse_string(ptr, &info->linker);
- break;
- case CB_TAG_ASSEMBLER:
- cb_parse_string(ptr, &info->assembler);
- break;
- /*
- * FIXME we should warn on serial if coreboot set up a
- * framebuffer buf the payload does not know about it.
- */
- case CB_TAG_FRAMEBUFFER:
- cb_parse_framebuffer(ptr, info);
- break;
- case CB_TAG_GPIO:
- cb_parse_gpios(ptr, info);
- break;
- case CB_TAG_VDAT:
- cb_parse_vdat(ptr, info);
- break;
- case CB_TAG_TIMESTAMPS:
- cb_parse_tstamp(ptr, info);
- break;
- case CB_TAG_CBMEM_CONSOLE:
- cb_parse_cbmem_cons(ptr, info);
- break;
- case CB_TAG_VBNV:
- cb_parse_vbnv(ptr, info);
- break;
- case CB_TAG_CBMEM_ENTRY:
- cb_parse_cbmem_entry(ptr, info);
- break;
- default:
- cb_parse_unhandled(rec->tag, ptr);
- break;
- }
-
- ptr += rec->size;
- }
-
- return 1;
-}
-
-/* == Architecture specific == */
-/* This is the x86 specific stuff. */
-
-int get_coreboot_info(struct sysinfo_t *info)
-{
- long addr;
- int ret;
-
- addr = locate_coreboot_table();
- if (addr < 0)
- return addr;
- ret = cb_parse_header((void *)addr, 0x1000, info);
- if (!ret)
- return -ENOENT;
- gd->arch.coreboot_table = addr;
- gd->flags |= GD_FLG_SKIP_LL_INIT;
-
- return 0;
-}
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index 0162597..7f133ce 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -8,21 +8,9 @@
#include <common.h>
#include <bootstage.h>
#include <asm/arch/timestamp.h>
-#include <asm/arch/sysinfo.h>
+#include <asm/cb_sysinfo.h>
#include <linux/compiler.h>
-struct timestamp_entry {
- uint32_t entry_id;
- uint64_t entry_stamp;
-} __packed;
-
-struct timestamp_table {
- uint64_t base_time;
- uint32_t max_entries;
- uint32_t num_entries;
- struct timestamp_entry entries[0]; /* Variable number of entries */
-} __packed;
-
static struct timestamp_table *ts_table __attribute__((section(".data")));
void timestamp_init(void)
diff --git a/arch/x86/cpu/start_from_spl.S b/arch/x86/cpu/start_from_spl.S
index 905c825..abfd4ab 100644
--- a/arch/x86/cpu/start_from_spl.S
+++ b/arch/x86/cpu/start_from_spl.S
@@ -43,6 +43,10 @@ use_existing_stack:
call board_init_f_init_reserve
+#ifdef CONFIG_DEBUG_UART
+ call debug_uart_init
+#endif
+
call x86_cpu_reinit_f
xorl %eax, %eax
call board_init_f