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Diffstat (limited to 'arch/riscv/cpu/fu740/spl.c')
-rw-r--r--arch/riscv/cpu/fu740/spl.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
index ea0b228..55e3034 100644
--- a/arch/riscv/cpu/fu740/spl.c
+++ b/arch/riscv/cpu/fu740/spl.c
@@ -6,6 +6,9 @@
#include <dm.h>
#include <log.h>
+#include <asm/csr.h>
+
+#define CSR_U74_FEATURE_DISABLE 0x7c1
int spl_soc_init(void)
{
@@ -21,3 +24,15 @@ int spl_soc_init(void)
return 0;
}
+
+void harts_early_init(void)
+{
+ /*
+ * Feature Disable CSR
+ *
+ * Clear feature disable CSR to '0' to turn on all features for
+ * each core. This operation must be in M-mode.
+ */
+ if (CONFIG_IS_ENABLED(RISCV_MMODE))
+ csr_write(CSR_U74_FEATURE_DISABLE, 0);
+}