diff options
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 36 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 5 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 3 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 202 | ||||
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 5 | ||||
-rw-r--r-- | arch/powerpc/include/asm/fsl_secure_boot.h | 1 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 4 |
9 files changed, 8 insertions, 252 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 876f768..3954235 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -161,13 +161,6 @@ config TARGET_T2080RDB imply CMD_SATA imply PANIC_HANG -config TARGET_T4160RDB - bool "Support T4160RDB" - select ARCH_T4160 - select SUPPORT_SPL - select PHYS_64BIT - imply PANIC_HANG - config TARGET_T4240RDB bool "Support T4240RDB" select ARCH_T4240 @@ -732,29 +725,6 @@ config ARCH_T2080 imply CMD_REGINFO imply FSL_SATA -config ARCH_T4160 - bool - select E500MC - select E6500 - select FSL_LAW - select SYS_FSL_DDR_VER_47 - select SYS_FSL_ERRATUM_A004468 - select SYS_FSL_ERRATUM_A005871 - select SYS_FSL_ERRATUM_A006379 - select SYS_FSL_ERRATUM_A006593 - select SYS_FSL_ERRATUM_A007186 - select SYS_FSL_ERRATUM_A007798 - select SYS_FSL_ERRATUM_A009942 - select SYS_FSL_HAS_DDR3 - select SYS_FSL_HAS_SEC - select SYS_FSL_QORIQ_CHASSIS2 - select SYS_FSL_SEC_BE - select SYS_FSL_SEC_COMPAT_4 - select SYS_PPC64 - select FSL_IFC - imply CMD_NAND - imply CMD_REGINFO - config ARCH_T4240 bool select E500MC @@ -823,8 +793,7 @@ config NXP_ESBC config MAX_CPUS int "Maximum number of CPUs permitted for MPC85xx" default 12 if ARCH_T4240 - default 8 if ARCH_P4080 || \ - ARCH_T4160 + default 8 if ARCH_P4080 default 4 if ARCH_B4860 || \ ARCH_P2041 || \ ARCH_P3041 || \ @@ -877,7 +846,6 @@ config SYS_CCSRBAR_DEFAULT ARCH_T1040 || \ ARCH_T1042 || \ ARCH_T2080 || \ - ARCH_T4160 || \ ARCH_T4240 default 0xe0000000 if ARCH_QEMU_E500 help @@ -1062,7 +1030,6 @@ config SYS_FSL_NUM_LAWS ARCH_P4080 || \ ARCH_P5040 || \ ARCH_T2080 || \ - ARCH_T4160 || \ ARCH_T4240 default 16 if ARCH_T1024 || \ ARCH_T1040 || \ @@ -1142,7 +1109,6 @@ config SYS_FSL_IFC_CLK_DIV ARCH_T1024 || \ ARCH_T1040 || \ ARCH_T1042 || \ - ARCH_T4160 || \ ARCH_T4240 default 1 help diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index bbaae0d..993e487 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -42,7 +42,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o obj-$(CONFIG_ARCH_P4080) += p4080_ids.o obj-$(CONFIG_ARCH_P5040) += p5040_ids.o obj-$(CONFIG_ARCH_T4240) += t4240_ids.o -obj-$(CONFIG_ARCH_T4160) += t4240_ids.o obj-$(CONFIG_ARCH_B4420) += b4860_ids.o obj-$(CONFIG_ARCH_B4860) += b4860_ids.o obj-$(CONFIG_ARCH_T1040) += t1040_ids.o @@ -74,7 +73,6 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o -obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 7d168e3..3f2fc06 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -527,8 +527,7 @@ static void fdt_fixup_usb(void *fdt) #define fdt_fixup_usb(x) #endif -#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \ - defined(CONFIG_ARCH_T4160) +#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) void fdt_fixup_dma3(void *blob) { /* the 3rd DMA is not functional if SRIO2 is chosen */ @@ -545,7 +544,7 @@ void fdt_fixup_dma3(void *blob) case 0x29: case 0x2d: case 0x2e: -#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) +#elif defined(CONFIG_ARCH_T4240) u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS4_PRTCL; srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index ee5015e..5bf0047 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -392,7 +392,7 @@ const char *serdes_clock_to_string(u32 clock) case SRDS_PLLCR0_RFCK_SEL_161_13: return "161.1328123"; default: -#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS) +#if defined(CONFIG_TARGET_T4240QDS) return "???"; #else return "122.88"; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e6e3f17..e229a5c 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -126,8 +126,7 @@ void get_sys_info(sys_info_t *sys_info) * it uses 6. * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ -#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \ - defined(CONFIG_ARCH_T2080) +#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T2080) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index a8c0c47..61402e8 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -262,208 +262,6 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_ARCH_T4160) -static const struct serdes_config serdes1_cfg_tbl[] = { - /* SerDes 1 */ - {1, {NONE, NONE, NONE, NONE, - XAUI_FM1_MAC10, XAUI_FM1_MAC10, - XAUI_FM1_MAC10, XAUI_FM1_MAC10} }, - {2, {NONE, NONE, NONE, NONE, - HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, - HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, - {4, {NONE, NONE, NONE, NONE, - HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, - HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} }, - {27, {NONE, NONE, NONE, NONE, - SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, - {28, {NONE, NONE, NONE, NONE, - SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, - {35, {NONE, NONE, NONE, NONE, - SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, - {36, {NONE, NONE, NONE, NONE, - SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, - SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} }, - {37, {NONE, NONE, NONE, NONE, - NONE, NONE, QSGMII_FM1_A, NONE} }, - {38, {NONE, NONE, NONE, NONE, - NONE, NONE, QSGMII_FM1_A, NONE} }, - {} -}; -static const struct serdes_config serdes2_cfg_tbl[] = { - /* SerDes 2 */ - {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, - XAUI_FM2_MAC9, XAUI_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, - XAUI_FM2_MAC9, XAUI_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, - XAUI_FM2_MAC9, XAUI_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, - XAUI_FM2_MAC9, XAUI_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - NONE, NONE} }, - {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {37, {NONE, NONE, QSGMII_FM2_B, NONE, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {38, {NONE, NONE, QSGMII_FM2_B, NONE, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, - SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, - XAUI_FM2_MAC9, XAUI_FM2_MAC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, - XAUI_FM2_MAC9, XAUI_FM2_MAC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, QSGMII_FM2_A, NONE} }, - {55, {NONE, XFI_FM1_MAC10, - XFI_FM2_MAC10, NONE, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {56, {NONE, XFI_FM1_MAC10, - XFI_FM2_MAC10, NONE, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, - {57, {NONE, XFI_FM1_MAC10, - XFI_FM2_MAC10, NONE, - SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, - NONE, NONE} }, - {} -}; -static const struct serdes_config serdes3_cfg_tbl[] = { - /* SerDes 3 */ - {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, - {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, - {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, - {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, - {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, - {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, - {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, - {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} }, - {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, - INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, - {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, - INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} }, - {11, {NONE, NONE, NONE, NONE, - PCIE2, PCIE2, PCIE2, PCIE2} }, - {12, {NONE, NONE, NONE, NONE, - PCIE2, PCIE2, PCIE2, PCIE2} }, - {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, - PCIE2, PCIE2, PCIE2, PCIE2} }, - {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, - PCIE2, PCIE2, PCIE2, PCIE2} }, - {15, {NONE, NONE, NONE, NONE, - SRIO1, SRIO1, SRIO1, SRIO1} }, - {16, {NONE, NONE, NONE, NONE, - SRIO1, SRIO1, SRIO1, SRIO1} }, - {17, {NONE, NONE, NONE, NONE, - SRIO1, SRIO1, SRIO1, SRIO1} }, - {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, - SRIO1, SRIO1, SRIO1, SRIO1} }, - {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, - SRIO1, SRIO1, SRIO1, SRIO1} }, - {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, - SRIO1, SRIO1, SRIO1, SRIO1} }, - {} -}; -static const struct serdes_config serdes4_cfg_tbl[] = { - /* SerDes 4 */ - {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} }, - {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} }, - {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} }, - {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} }, - {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} }, - {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} }, - {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} }, - {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} }, - {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} }, - {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} }, - {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} }, - {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} }, - {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} }, - {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} }, - {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} }, - {} -} -; #else #error "Need to define SerDes protocol" #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 33a3b3a..cfe74bc 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -184,7 +184,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) +#elif defined(CONFIG_ARCH_T4240) #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ @@ -199,9 +199,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 -#if defined(CONFIG_ARCH_T4160) -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 991d753..3a1d858 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -21,7 +21,6 @@ #if defined(CONFIG_TARGET_B4860QDS) || \ defined(CONFIG_TARGET_B4420QDS) || \ - defined(CONFIG_TARGET_T4160QDS) || \ defined(CONFIG_TARGET_T4240QDS) || \ defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 70112c9..f539c0b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1757,7 +1757,7 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) +#if defined(CONFIG_ARCH_T4240) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1869,7 +1869,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) +#if defined(CONFIG_ARCH_T4240) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 |