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-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig14
-rw-r--r--arch/powerpc/cpu/mpc83xx/elbc/elbc.h170
-rw-r--r--arch/powerpc/cpu/mpc83xx/pcie.c3
-rw-r--r--arch/powerpc/cpu/mpc83xx/speed.c4
-rw-r--r--arch/powerpc/cpu/mpc83xx/spl_minimal.c2
-rw-r--r--arch/powerpc/cpu/mpc83xx/start.S5
-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig8
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c8
-rw-r--r--arch/powerpc/cpu/mpc8xx/Kconfig88
-rw-r--r--arch/powerpc/dts/Makefile1
-rw-r--r--arch/powerpc/dts/qemu-ppce500.dts10
-rw-r--r--arch/powerpc/include/asm/config.h3
13 files changed, 34 insertions, 286 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index cff98f7..bcd8375 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -179,13 +179,6 @@ config ARCH_MPC837X
select SYS_CACHE_SHIFT_5
select FSL_ELBC
-config SYS_IMMR
- hex "Value for IMMR"
- default 0xE0000000
- help
- Address for the Internal Memory-Mapped Registers (IMMR) window used
- to configure the features of the SoC.
-
source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
@@ -195,6 +188,13 @@ source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
+config 83XX_PCICLK
+ hex "PCI clock frequency"
+ default 0xDEADBEEF
+ help
+ If required, the PCI clock frequency to use when configuring
+ the host bridge.
+
config FSL_ELBC
bool
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
index 245fe7c..e795cd1 100644
--- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
+++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
@@ -1,173 +1,3 @@
-#ifdef CONFIG_ELBC_BR0_OR0
-#define CONFIG_SYS_BR0_PRELIM (\
- CONFIG_BR0_OR0_BASE |\
- CONFIG_BR0_PORTSIZE |\
- CONFIG_BR0_ERRORCHECKING |\
- CONFIG_BR0_WRITE_PROTECT_BIT |\
- CONFIG_BR0_MACHINE |\
- CONFIG_BR0_ATOMIC |\
- CONFIG_BR0_VALID_BIT \
-)
-#define CONFIG_SYS_OR0_PRELIM (\
- CONFIG_OR0_AM |\
- CONFIG_OR0_XAM |\
- CONFIG_OR0_BCTLD |\
- CONFIG_OR0_BI |\
- CONFIG_OR0_COLS |\
- CONFIG_OR0_ROWS |\
- CONFIG_OR0_PMSEL |\
- CONFIG_OR0_SCY |\
- CONFIG_OR0_PGS |\
- CONFIG_OR0_CSCT |\
- CONFIG_OR0_CST |\
- CONFIG_OR0_CHT |\
- CONFIG_OR0_RST |\
- CONFIG_OR0_CSNT |\
- CONFIG_OR0_ACS |\
- CONFIG_OR0_XACS |\
- CONFIG_OR0_SETA |\
- CONFIG_OR0_TRLX |\
- CONFIG_OR0_EHTR |\
- CONFIG_OR0_EAD \
-)
-#endif /* CONFIG_ELBC_BR0_OR0 */
-
-#ifdef CONFIG_ELBC_BR1_OR1
-#define CONFIG_SYS_BR1_PRELIM (\
- CONFIG_BR1_OR1_BASE |\
- CONFIG_BR1_PORTSIZE |\
- CONFIG_BR1_ERRORCHECKING |\
- CONFIG_BR1_WRITE_PROTECT_BIT |\
- CONFIG_BR1_MACHINE |\
- CONFIG_BR1_ATOMIC |\
- CONFIG_BR1_VALID_BIT \
-)
-#define CONFIG_SYS_OR1_PRELIM (\
- CONFIG_OR1_AM |\
- CONFIG_OR1_XAM |\
- CONFIG_OR1_BCTLD |\
- CONFIG_OR1_BI |\
- CONFIG_OR1_COLS |\
- CONFIG_OR1_ROWS |\
- CONFIG_OR1_PMSEL |\
- CONFIG_OR1_SCY |\
- CONFIG_OR1_PGS |\
- CONFIG_OR1_CSCT |\
- CONFIG_OR1_CST |\
- CONFIG_OR1_CHT |\
- CONFIG_OR1_RST |\
- CONFIG_OR1_CSNT |\
- CONFIG_OR1_ACS |\
- CONFIG_OR1_XACS |\
- CONFIG_OR1_SETA |\
- CONFIG_OR1_TRLX |\
- CONFIG_OR1_EHTR |\
- CONFIG_OR1_EAD \
-)
-#endif /* CONFIG_ELBC_BR1_OR1 */
-
-#ifdef CONFIG_ELBC_BR2_OR2
-#define CONFIG_SYS_BR2_PRELIM (\
- CONFIG_BR2_OR2_BASE |\
- CONFIG_BR2_PORTSIZE |\
- CONFIG_BR2_ERRORCHECKING |\
- CONFIG_BR2_WRITE_PROTECT_BIT |\
- CONFIG_BR2_MACHINE |\
- CONFIG_BR2_ATOMIC |\
- CONFIG_BR2_VALID_BIT \
-)
-#define CONFIG_SYS_OR2_PRELIM (\
- CONFIG_OR2_AM |\
- CONFIG_OR2_XAM |\
- CONFIG_OR2_BCTLD |\
- CONFIG_OR2_BI |\
- CONFIG_OR2_COLS |\
- CONFIG_OR2_ROWS |\
- CONFIG_OR2_PMSEL |\
- CONFIG_OR2_SCY |\
- CONFIG_OR2_PGS |\
- CONFIG_OR2_CSCT |\
- CONFIG_OR2_CST |\
- CONFIG_OR2_CHT |\
- CONFIG_OR2_RST |\
- CONFIG_OR2_CSNT |\
- CONFIG_OR2_ACS |\
- CONFIG_OR2_XACS |\
- CONFIG_OR2_SETA |\
- CONFIG_OR2_TRLX |\
- CONFIG_OR2_EHTR |\
- CONFIG_OR2_EAD \
-)
-#endif /* CONFIG_ELBC_BR2_OR2 */
-
-#ifdef CONFIG_ELBC_BR3_OR3
-#define CONFIG_SYS_BR3_PRELIM (\
- CONFIG_BR3_OR3_BASE |\
- CONFIG_BR3_PORTSIZE |\
- CONFIG_BR3_ERRORCHECKING |\
- CONFIG_BR3_WRITE_PROTECT_BIT |\
- CONFIG_BR3_MACHINE |\
- CONFIG_BR3_ATOMIC |\
- CONFIG_BR3_VALID_BIT \
-)
-#define CONFIG_SYS_OR3_PRELIM (\
- CONFIG_OR3_AM |\
- CONFIG_OR3_XAM |\
- CONFIG_OR3_BCTLD |\
- CONFIG_OR3_BI |\
- CONFIG_OR3_COLS |\
- CONFIG_OR3_ROWS |\
- CONFIG_OR3_PMSEL |\
- CONFIG_OR3_SCY |\
- CONFIG_OR3_PGS |\
- CONFIG_OR3_CSCT |\
- CONFIG_OR3_CST |\
- CONFIG_OR3_CHT |\
- CONFIG_OR3_RST |\
- CONFIG_OR3_CSNT |\
- CONFIG_OR3_ACS |\
- CONFIG_OR3_XACS |\
- CONFIG_OR3_SETA |\
- CONFIG_OR3_TRLX |\
- CONFIG_OR3_EHTR |\
- CONFIG_OR3_EAD \
-)
-#endif /* CONFIG_ELBC_BR3_OR3 */
-
-#ifdef CONFIG_ELBC_BR4_OR4
-#define CONFIG_SYS_BR4_PRELIM (\
- CONFIG_BR4_OR4_BASE |\
- CONFIG_BR4_PORTSIZE |\
- CONFIG_BR4_ERRORCHECKING |\
- CONFIG_BR4_WRITE_PROTECT_BIT |\
- CONFIG_BR4_MACHINE |\
- CONFIG_BR4_ATOMIC |\
- CONFIG_BR4_VALID_BIT \
-)
-#define CONFIG_SYS_OR4_PRELIM (\
- CONFIG_OR4_AM |\
- CONFIG_OR4_XAM |\
- CONFIG_OR4_BCTLD |\
- CONFIG_OR4_BI |\
- CONFIG_OR4_COLS |\
- CONFIG_OR4_ROWS |\
- CONFIG_OR4_PMSEL |\
- CONFIG_OR4_SCY |\
- CONFIG_OR4_PGS |\
- CONFIG_OR4_CSCT |\
- CONFIG_OR4_CST |\
- CONFIG_OR4_CHT |\
- CONFIG_OR4_RST |\
- CONFIG_OR4_CSNT |\
- CONFIG_OR4_ACS |\
- CONFIG_OR4_XACS |\
- CONFIG_OR4_SETA |\
- CONFIG_OR4_TRLX |\
- CONFIG_OR4_EHTR |\
- CONFIG_OR4_EAD \
-)
-#endif /* CONFIG_ELBC_BR4_OR4 */
-
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index c386e4e..d2b6b05 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -8,6 +8,7 @@
*/
#include <common.h>
+#include <clock_legacy.h>
#include <pci.h>
#include <mpc83xx.h>
#include <asm/global_data.h>
@@ -46,7 +47,7 @@ int get_pcie_clk(int index)
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
sccr = im->clk.sccr;
- pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+ pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index e5db96b..f835263 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -137,8 +137,8 @@ int get_clocks(void)
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if (im->reset.rcwh & HRCWH_PCI_HOST) {
-#if defined(CONFIG_SYS_CLK_FREQ)
- pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
+#if CONFIG_SYS_CLK_FREQ != 0
+ pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
#else
pci_sync_in = 0xDEADBEEF;
#endif
diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
index 00cb2bd..11b1e61 100644
--- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c
@@ -102,5 +102,5 @@ ulong get_bus_freq(ulong dummy)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
- return CONFIG_SYS_CLK_FREQ * spmf;
+ return get_board_sys_clk() * spmf;
}
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index c4953df..0944d19 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -14,8 +14,6 @@
#include <config.h>
#include <mpc83xx.h>
-#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
-
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
@@ -115,9 +113,6 @@ disable_addr_trans:
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
#endif /* CONFIG_DEFAULT_IMMR */
-#ifndef CONFIG_SYS_IMMR
-#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
-#endif /* CONFIG_SYS_IMMR */
/*
* After configuration, a system reset exception is executed using the
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 836aedd..4471754 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -109,6 +109,7 @@ config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
select ARCH_QEMU_E500
select PHYS_64BIT
+ imply OF_HAS_PRIOR_STAGE
config TARGET_T1024RDB
bool "Support T1024RDB"
@@ -353,6 +354,7 @@ config ARCH_P1010
bool
select FSL_LAW
select SYS_CACHE_SHIFT_5
+ select SYS_HAS_SERDES
select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125
@@ -1000,6 +1002,9 @@ config SYS_FSL_ERRATUM_SRIO_A004034
config SYS_FSL_ERRATUM_USB14
bool
+config SYS_HAS_SERDES
+ bool
+
config SYS_P4080_ERRATUM_CPU22
bool
@@ -1083,9 +1088,6 @@ config SYS_PPC64
config SYS_PPC_E500_USE_DEBUG_TLB
bool
-config FSL_IFC
- bool
-
config FSL_ELBC
bool
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 3f2fc06..d4b828e 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -662,9 +662,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0)/2, 1);
#else
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 1fe914a..5a9cd28 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -75,7 +75,7 @@ void get_sys_info(sys_info_t *sys_info)
uint rcw_tmp;
#endif
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
- unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ unsigned long sysclk = get_board_sys_clk();
uint mem_pll_rat;
sys_info->freq_systembus = sysclk;
@@ -102,7 +102,7 @@ void get_sys_info(sys_info_t *sys_info)
* are driven by differential sysclock.
*/
if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
- sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_ddrbus = get_board_sys_clk();
else
#endif
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
@@ -526,7 +526,7 @@ void get_sys_info(sys_info_t *sys_info)
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
- sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_systembus = plat_ratio * get_board_sys_clk();
/* Divide before multiply to avoid integer
* overflow for processor speeds above 2GHz */
@@ -554,7 +554,7 @@ void get_sys_info(sys_info_t *sys_info)
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
- sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
+ sys_info->freq_qe = qe_ratio * get_board_sys_clk();
#endif
#endif
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 936cbda..d630711 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -84,94 +84,6 @@ config SYS_DER
help
Debug Event Register (37-47)
-comment "Memory mapping"
-
-config SYS_BR0_PRELIM
- hex "Preliminary value for BR0"
-
-config SYS_OR0_PRELIM
- hex "Preliminary value for OR0"
-
-config SYS_BR1_PRELIM_BOOL
- bool "Define Bank 1"
-
-config SYS_BR1_PRELIM
- hex "Preliminary value for BR1"
- depends on SYS_BR1_PRELIM_BOOL
-
-config SYS_OR1_PRELIM
- hex "Preliminary value for OR1"
- depends on SYS_BR1_PRELIM_BOOL
-
-config SYS_BR2_PRELIM_BOOL
- bool "Define Bank 2"
-
-config SYS_BR2_PRELIM
- hex "Preliminary value for BR2"
- depends on SYS_BR2_PRELIM_BOOL
-
-config SYS_OR2_PRELIM
- hex "Preliminary value for OR2"
- depends on SYS_BR2_PRELIM_BOOL
-
-config SYS_BR3_PRELIM_BOOL
- bool "Define Bank 3"
-
-config SYS_BR3_PRELIM
- hex "Preliminary value for BR3"
- depends on SYS_BR3_PRELIM_BOOL
-
-config SYS_OR3_PRELIM
- hex "Preliminary value for OR3"
- depends on SYS_BR3_PRELIM_BOOL
-
-config SYS_BR4_PRELIM_BOOL
- bool "Define Bank 4"
-
-config SYS_BR4_PRELIM
- hex "Preliminary value for BR4"
- depends on SYS_BR4_PRELIM_BOOL
-
-config SYS_OR4_PRELIM
- hex "Preliminary value for OR4"
- depends on SYS_BR4_PRELIM_BOOL
-
-config SYS_BR5_PRELIM_BOOL
- bool "Define Bank 5"
-
-config SYS_BR5_PRELIM
- hex "Preliminary value for BR5"
- depends on SYS_BR5_PRELIM_BOOL
-
-config SYS_OR5_PRELIM
- hex "Preliminary value for OR5"
- depends on SYS_BR5_PRELIM_BOOL
-
-config SYS_BR6_PRELIM_BOOL
- bool "Define Bank 6"
-
-config SYS_BR6_PRELIM
- hex "Preliminary value for BR6"
- depends on SYS_BR6_PRELIM_BOOL
-
-config SYS_OR6_PRELIM
- hex "Preliminary value for OR6"
- depends on SYS_BR6_PRELIM_BOOL
-
-config SYS_BR7_PRELIM_BOOL
- bool "Define Bank 7"
-
-config SYS_BR7_PRELIM
- hex "Preliminary value for BR7"
- depends on SYS_BR7_PRELIM_BOOL
-
-config SYS_OR7_PRELIM
- hex "Preliminary value for OR7"
- depends on SYS_BR7_PRELIM_BOOL
-
-config SYS_IMMR
- hex "Value for IMMR"
-
source "board/cssi/MCR3000/Kconfig"
endmenu
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index ceaa8ce..66d22ae 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -18,6 +18,7 @@ dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
+dtb-$(CONFIG_TARGET_QEMU_PPCE500) += qemu-ppce500.dtb
dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
diff --git a/arch/powerpc/dts/qemu-ppce500.dts b/arch/powerpc/dts/qemu-ppce500.dts
new file mode 100644
index 0000000..e88e09e
--- /dev/null
+++ b/arch/powerpc/dts/qemu-ppce500.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Empty device tree for qemu-ppce400
+ *
+ * Copyright 2021 Google LLC
+ */
+/dts-v1/;
+
+/ {
+};
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index a97b72d..3541371 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -51,9 +51,6 @@
/* The FMAN driver uses the PHYLIB infrastructure */
-/* All PPC boards must swap IDE bytes */
-#define CONFIG_IDE_SWAP_IO
-
#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
/*
* TODO: Convert this to a clock driver exists that can give us the UART
generated by cgit v1.1 at 2024-10-18 09:02:22 +0000