diff options
Diffstat (limited to 'arch/powerpc')
33 files changed, 93 insertions, 909 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 083febe..cff98f7 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -8,22 +8,6 @@ choice prompt "Target select" optional -config TARGET_MPC8349EMDS - bool "Support MPC8349EMDS" - select ARCH_MPC8349 - select BOARD_EARLY_INIT_F - select SYS_FSL_DDR - select SYS_FSL_DDR_BE - select SYS_FSL_HAS_DDR2 - -config TARGET_MPC8349EMDS_SDRAM - bool "Support MPC8349EMDS_SDRAM" - select ARCH_MPC8349 - select BOARD_EARLY_INIT_F - select SYS_FSL_DDR - select SYS_FSL_DDR_BE - select SYS_FSL_HAS_DDR2 - config TARGET_MPC837XERDB bool "Support MPC837XERDB" select ARCH_MPC837X @@ -119,7 +103,7 @@ config MPC83XX_PCIE2_SUPPORT config MPC83XX_SDHC_SUPPORT bool -config MPC83XX_SATA_SUPPORT +config MPC83XX_SATA bool config MPC83XX_SECOND_I2C @@ -131,6 +115,7 @@ config MPC83XX_LDP_PIN config ARCH_MPC830X bool select MPC83XX_SDHC_SUPPORT + select SYS_CACHE_SHIFT_5 config ARCH_MPC8308 bool @@ -154,6 +139,7 @@ config ARCH_MPC831X select MPC83XX_PCI_SUPPORT select MPC83XX_TSEC1_SUPPORT select MPC83XX_TSEC2_SUPPORT + select SYS_CACHE_SHIFT_5 config ARCH_MPC8313 bool @@ -165,18 +151,11 @@ config ARCH_MPC832X bool select MPC83XX_QUICC_ENGINE select MPC83XX_PCI_SUPPORT + select SYS_CACHE_SHIFT_5 config ARCH_MPC834X bool - -config ARCH_MPC8349 - bool - select ARCH_MPC834X - select MPC83XX_PCI_SUPPORT - select MPC83XX_TSEC1_SUPPORT - select MPC83XX_TSEC2_SUPPORT - select MPC83XX_LDP_PIN - select MPC83XX_SECOND_I2C + select SYS_CACHE_SHIFT_5 config ARCH_MPC8360 bool @@ -184,6 +163,7 @@ config ARCH_MPC8360 select MPC83XX_PCI_SUPPORT select MPC83XX_LDP_PIN select MPC83XX_SECOND_I2C + select SYS_CACHE_SHIFT_5 config ARCH_MPC837X bool @@ -193,9 +173,10 @@ config ARCH_MPC837X select MPC83XX_PCIE1_SUPPORT select MPC83XX_PCIE2_SUPPORT select MPC83XX_SDHC_SUPPORT - select MPC83XX_SATA_SUPPORT + select MPC83XX_SATA select MPC83XX_LDP_PIN select MPC83XX_SECOND_I2C + select SYS_CACHE_SHIFT_5 select FSL_ELBC config SYS_IMMR @@ -214,36 +195,9 @@ source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig" source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig" source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig" -menu "Legacy options" - -if ARCH_MPC8349 - -#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT -choice - prompt "PMC slot configuration" - -config PCI_ALL_PCI1 - bool "All PMC slots on PCI1" - -config PCI_ONE_PCI1 - bool "First PMC1 on PCI1" - -config PCI_TWO_PCI1 - bool "First two PMC1 on PCI1" - -endchoice - -config PCI_64BIT - bool "PMC2 is 64bit" - -endif - -endmenu - config FSL_ELBC bool -source "board/freescale/mpc8349emds/Kconfig" source "board/freescale/mpc837xerdb/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index aeb42b1..7c4ef76 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -26,7 +26,7 @@ obj-y += cpu.o obj-y += cpu_init.o obj-y += speed.o obj-y += interrupts.o -obj-y += ecc.o +obj-$(CONFIG_DDR_ECC_CMD) += ecc.o ifndef CONFIG_PINCTRL obj-$(CONFIG_QE) += qe_io.o endif diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 7a8ec7f..3e24752 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -11,7 +11,6 @@ #include <mpc83xx.h> #include <command.h> -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) void ecc_print_status(void) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; @@ -386,4 +385,3 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc, " - writes pattern injecting errors with word access\n" " - writes pattern with word access, generates error\n" " - disables injects\n" " - re-inits memory"); -#endif diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 index 23e81ab..208eed0 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0 @@ -22,7 +22,7 @@ config BR0_PORTSIZE_16BIT config BR0_PORTSIZE_32BIT depends on !BR0_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR0_MACHINE_GPCM bool "GPCM" config BR0_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR0_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR0_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 index 08dcc7d..1dc3e75 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1 @@ -22,7 +22,7 @@ config BR1_PORTSIZE_16BIT config BR1_PORTSIZE_32BIT depends on !BR1_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR1_MACHINE_GPCM bool "GPCM" config BR1_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR1_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR1_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 index 298d87f..a9b2546 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2 @@ -22,7 +22,7 @@ config BR2_PORTSIZE_16BIT config BR2_PORTSIZE_32BIT depends on !BR2_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR2_MACHINE_GPCM bool "GPCM" config BR2_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR2_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR2_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 index 963831b..94442cd 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3 @@ -22,7 +22,7 @@ config BR3_PORTSIZE_16BIT config BR3_PORTSIZE_32BIT depends on !BR3_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR3_MACHINE_GPCM bool "GPCM" config BR3_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR3_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR3_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 index 0063dab..5d69385 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 +++ b/arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4 @@ -22,7 +22,7 @@ config BR4_PORTSIZE_16BIT config BR4_PORTSIZE_32BIT depends on !BR4_MACHINE_FCM - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 + depends on ARCH_MPC8360 || ARCH_MPC8379 bool "32-bit" endchoice @@ -58,11 +58,11 @@ config BR4_MACHINE_GPCM bool "GPCM" config BR4_MACHINE_FCM - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "FCM" config BR4_MACHINE_SDRAM - depends on ARCH_MPC8349 || ARCH_MPC8360 + depends on ARCH_MPC8360 bool "SDRAM" config BR4_MACHINE_UPMA diff --git a/arch/powerpc/cpu/mpc83xx/hid/Kconfig b/arch/powerpc/cpu/mpc83xx/hid/Kconfig index c367ad2..1f61108 100644 --- a/arch/powerpc/cpu/mpc83xx/hid/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hid/Kconfig @@ -434,7 +434,7 @@ config HID2_IWLCK_1 config HID2_IWLCK_2 bool "Way 0 through 2 locked" -if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 +if ARCH_MPC8360 || ARCH_MPC8379 config HID2_IWLCK_3 bool "Way 0 through 3 locked" @@ -470,7 +470,7 @@ config HID2_DWLCK_1 config HID2_DWLCK_2 bool "Way 0 through 2 locked" -if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 +if ARCH_MPC8360 || ARCH_MPC8379 config HID2_DWLCK_3 bool "Way 0 through 3 locked" diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig index 75ec9c9..71fa738 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -7,7 +7,7 @@ config LBMC_CLOCK_MODE_1_1 bool "1 : 1" config LBMC_CLOCK_MODE_1_2 - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "1 : 2" endchoice @@ -19,12 +19,12 @@ config DDR_MC_CLOCK_MODE_1_2 bool "1 : 2" config DDR_MC_CLOCK_MODE_1_1 - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "1 : 1" endchoice -if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349 +if !ARCH_MPC8313 && !ARCH_MPC832X choice prompt "System PLL VCO division" @@ -67,43 +67,43 @@ config SYSTEM_PLL_FACTOR_6_1 bool "6 : 1" config SYSTEM_PLL_FACTOR_7_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "7 : 1" config SYSTEM_PLL_FACTOR_8_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "8 : 1" config SYSTEM_PLL_FACTOR_9_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "9 : 1" config SYSTEM_PLL_FACTOR_10_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "10 : 1" config SYSTEM_PLL_FACTOR_11_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "11 : 1" config SYSTEM_PLL_FACTOR_12_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "12 : 1" config SYSTEM_PLL_FACTOR_13_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "13 : 1" config SYSTEM_PLL_FACTOR_14_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "14 : 1" config SYSTEM_PLL_FACTOR_15_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPV8360 || ARCH_MPC837X bool "15 : 1" config SYSTEM_PLL_FACTOR_16_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 + depends on ARCH_MPV8360 bool "16 : 1" endchoice @@ -310,21 +310,6 @@ config PCI_HOST_MODE_ENABLE endchoice -if ARCH_MPC8349 - -choice - prompt "PCI 64-bit mode" - -config PCI_64BIT_MODE_DISABLE - bool "Disabled" - -config PCI_64BIT_MODE_ENABLE - bool "Enabled" - -endchoice - -endif - choice prompt "PCI internal arbiter 1 mode" @@ -336,21 +321,6 @@ config PCI_INT_ARBITER1_ENABLE endchoice -if ARCH_MPC8349 - -choice - prompt "PCI internal arbiter 2 mode" - -config PCI_INT_ARBITER2_DISABLE - bool "Disabled" - -config PCI_INT_ARBITER2_ENABLE - bool "Enabled" - -endchoice - -endif - if ARCH_MPC8360 choice @@ -425,10 +395,6 @@ config BOOT_ROM_INTERFACE_PCI1 depends on MPC83XX_PCI_SUPPORT bool "PCI1" -config BOOT_ROM_INTERFACE_PCI2 - depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349 - bool "PCI2" - config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM depends on ARCH_MPC837X bool "PCI2" @@ -448,15 +414,15 @@ config BOOT_ROM_INTERFACE_GPCM_16BIT bool "Local bus GPCM - 16-bit ROM" config BOOT_ROM_INTERFACE_GPCM_32BIT - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8360 || ARCH_MPC837X bool "Local bus GPCM - 32-bit ROM" config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "Local bus NAND Flash- 8-bit small page ROM" config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE - depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + depends on !ARCH_MPC832X && !ARCH_MPC8360 bool "Local bus NAND Flash- 8-bit large page ROM" endchoice @@ -467,11 +433,10 @@ choice prompt "TSEC1 mode" config TSEC1_MODE_MII - depends on !ARCH_MPC8349 bool "MII" config TSEC1_MODE_RMII - depends on ARCH_MPC831X && !ARCH_MPC8349 + depends on ARCH_MPC831X bool "RMII" config TSEC1_MODE_RGMII @@ -481,14 +446,6 @@ config TSEC1_MODE_RTBI depends on ARCH_MPC831X || ARCH_MPC837X bool "RTBI" -config TSEC1_MODE_GMII - depends on ARCH_MPC8349 - bool "GMII" - -config TSEC1_MODE_TBI - depends on ARCH_MPC8349 - bool "TBI" - config TSEC1_MODE_SGMII depends on ARCH_MPC831X || ARCH_MPC837X bool "SGMII" @@ -503,11 +460,10 @@ choice prompt "TSEC2 mode" config TSEC2_MODE_MII - depends on !ARCH_MPC8349 bool "MII" config TSEC2_MODE_RMII - depends on ARCH_MPC831X && !ARCH_MPC8349 + depends on ARCH_MPC831X bool "RMII" config TSEC2_MODE_RGMII @@ -517,14 +473,6 @@ config TSEC2_MODE_RTBI depends on ARCH_MPC831X || ARCH_MPC837X bool "RTBI" -config TSEC2_MODE_GMII - depends on ARCH_MPC8349 - bool "GMII" - -config TSEC2_MODE_TBI - depends on ARCH_MPC8349 - bool "TBI" - config TSEC2_MODE_SGMII depends on ARCH_MPC831X || ARCH_MPC837X bool "SGMII" @@ -559,7 +507,7 @@ endchoice endif -if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360 +if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360 choice prompt "LALE timing" @@ -603,7 +551,7 @@ config DDR_MC_CLOCK_MODE config SYSTEM_PLL_VCO_DIV int - default 0 if ARCH_MPC8349 || ARCH_MPC832X + default 0 if ARCH_MPC832X default 2 if ARCH_MPC8313 default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X @@ -675,7 +623,6 @@ config BOOT_ROM_INTERFACE hex default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM default 0x4 if BOOT_ROM_INTERFACE_PCI1 - default 0x8 if BOOT_ROM_INTERFACE_PCI2 default 0x8 if BOOT_ROM_INTERFACE_ESDHC default 0xc if BOOT_ROM_INTERFACE_SPI default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM @@ -690,26 +637,18 @@ config TSEC1_MODE default 0x0 if !MPC83XX_TSEC1_SUPPORT default 0x0 if TSEC1_MODE_MII default 0x1 if TSEC1_MODE_RMII - default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349 - default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349 + default 0x3 if TSEC1_MODE_RGMII + default 0x5 if TSEC1_MODE_RTBI default 0x6 if TSEC1_MODE_SGMII - default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349 - default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349 - default 0x2 if TSEC1_MODE_GMII - default 0x3 if TSEC1_MODE_TBI config TSEC2_MODE hex default 0x0 if !MPC83XX_TSEC2_SUPPORT default 0x0 if TSEC2_MODE_MII default 0x1 if TSEC2_MODE_RMII - default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349 - default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349 + default 0x3 if TSEC2_MODE_RGMII + default 0x5 if TSEC2_MODE_RTBI default 0x6 if TSEC2_MODE_SGMII - default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349 - default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349 - default 0x2 if TSEC2_MODE_GMII - default 0x3 if TSEC2_MODE_TBI config SECONDARY_DDR_IO int @@ -792,9 +731,7 @@ config PCI_HOST_MODE config PCI_64BIT_MODE int - default 0 if !ARCH_MPC8349 - default 0 if PCI_64BIT_MODE_DISABLE - default 1 if PCI_64BIT_MODE_ENABLE + default 0 config PCI_INT_ARBITER1 int @@ -804,9 +741,7 @@ config PCI_INT_ARBITER1 config PCI_INT_ARBITER2 int - default 0 if !ARCH_MPC8349 - default 0 if PCI_INT_ARBITER2_DISABLE - default 1 if PCI_INT_ARBITER2_ENABLE + default 0 config PCI_CLOCK_OUTPUT_DRIVE int diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h index 7d66ba7..0f34267 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h +++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h @@ -1,11 +1,3 @@ -#ifdef CONFIG_ARCH_MPC8349 -#define TSEC1_MODE_SHIFT 17 -#define TSEC2_MODE_SHIFT 19 -#else -#define TSEC1_MODE_SHIFT 18 -#define TSEC2_MODE_SHIFT 21 -#endif - #define CONFIG_SYS_HRCW_LOW (\ (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ @@ -28,8 +20,8 @@ (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\ (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\ (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\ - (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\ - (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\ + (CONFIG_TSEC1_MODE << (31 - 18)) |\ + (CONFIG_TSEC2_MODE << (31 - 21)) |\ (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\ (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\ (CONFIG_LALE_TIMING << (31 - 29)) |\ diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr index f32309e..33e1295 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr @@ -38,50 +38,6 @@ endchoice endif -if ARCH_MPC8349 - -choice - prompt "TSEC1 emergency priority" - -config SPCR_TSEC1EP_UNSET - bool "Don't set value" - -config SPCR_TSEC1EP_0 - bool "Level 0 (lowest priority)" - -config SPCR_TSEC1EP_1 - bool "Level 1" - -config SPCR_TSEC1EP_2 - bool "Level 2" - -config SPCR_TSEC1EP_3 - bool "Level 3 (highest priority)" - -endchoice - -choice - prompt "TSEC2 emergency priority" - -config SPCR_TSEC2EP_UNSET - bool "Don't set value" - -config SPCR_TSEC2EP_0 - bool "Level 0 (lowest priority)" - -config SPCR_TSEC2EP_1 - bool "Level 1" - -config SPCR_TSEC2EP_2 - bool "Level 2" - -config SPCR_TSEC2EP_3 - bool "Level 3 (highest priority)" - -endchoice - -endif - config SPCR_OPT hex default 0x0 if SPCR_OPT_UNSET diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 84797c8..c386e4e 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -34,148 +34,6 @@ static struct { #endif }; -#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES - -/* private structure for mpc83xx pcie hose */ -static struct mpc83xx_pcie_priv { - u8 index; -} pcie_priv[PCIE_MAX_BUSES] = { - { - /* pcie controller 1 */ - .index = 0, - }, - { - /* pcie controller 2 */ - .index = 1, - }, -}; - -static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) -{ - int bus = PCI_BUS(dev) - hose->first_busno; - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data; - pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; - struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; - u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); - u32 dev_base = bus << 24 | devfn << 16; - - if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK) - return -1; - /* - * Workaround for the HW bug: for Type 0 configure transactions the - * PCI-E controller does not check the device number bits and just - * assumes that the device number bits are 0. - */ - if (devfn & 0xf8) - return -1; - - out_le32(&out_win->tarl, dev_base); - return 0; -} - -#define cfg_read(val, addr, type, op) \ - do { *val = op((type)(addr)); } while (0) -#define cfg_write(val, addr, type, op) \ - do { op((type *)(addr), (val)); } while (0) - -#define cfg_read_err(val) do { *val = -1; } while (0) -#define cfg_write_err(val) do { } while (0) - -#define PCIE_OP(rw, size, type, op) \ -static int pcie_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, \ - type val) \ -{ \ - int ret; \ - \ - ret = mpc83xx_pcie_remap_cfg(hose, dev); \ - if (ret) { \ - cfg_##rw##_err(val); \ - return ret; \ - } \ - cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \ - return 0; \ -} - -PCIE_OP(read, byte, u8 *, in_8) -PCIE_OP(read, word, u16 *, in_le16) -PCIE_OP(read, dword, u32 *, in_le32) -PCIE_OP(write, byte, u8, out_8) -PCIE_OP(write, word, u16, out_le16) -PCIE_OP(write, dword, u32, out_le32) - -static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, - u8 link) -{ - extern void disable_addr_trans(void); /* start.S */ - static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; - struct pci_controller *hose = &pcie_hose[bus]; - int i; - - /* - * There are no spare BATs to remap all PCI-E windows for U-Boot, so - * disable translations. In general, this is not great solution, and - * that's why we don't register PCI-E hoses by default. - */ - disable_addr_trans(); - - for (i = 0; i < 2; i++, reg++) { - if (reg->size == 0) - break; - - hose->regions[i] = *reg; - hose->region_count++; - } - - i = hose->region_count++; - hose->regions[i].bus_start = 0; - hose->regions[i].phys_start = 0; - hose->regions[i].size = gd->ram_size; - hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; - - i = hose->region_count++; - hose->regions[i].bus_start = CONFIG_SYS_IMMR; - hose->regions[i].phys_start = CONFIG_SYS_IMMR; - hose->regions[i].size = 0x100000; - hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; - - hose->first_busno = pci_last_busno() + 1; - hose->last_busno = 0xff; - - hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; - - hose->priv_data = &pcie_priv[bus]; - - pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); - - if (!link) - hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK; - - pci_register_hose(hose); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -} - -#else - -static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, - u8 link) {} - -#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */ - int get_pcie_clk(int index) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; @@ -340,8 +198,6 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) printf("link\n"); else printf("No link\n"); - - mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0); } /* diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index a861e8d..e12043b 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -834,12 +834,6 @@ long int spd_sdram() #endif debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); -#if defined(CONFIG_DDR_2T_TIMING) - /* - * Enable 2T timing by setting sdram_cfg[16]. - */ - sdram_cfg |= SDRAM_CFG_2T_EN; -#endif /* Enable controller, and GO! */ ddr->sdram_cfg = sdram_cfg; sync(); @@ -914,16 +908,12 @@ void ddr_enable_ecc(unsigned int dram_size) pattern[0] = 0xdeadbeef; pattern[1] = 0xdeadbeef; -#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) - dma_meminit(pattern[0], dram_size); -#else debug("ddr init: CPU FP write method\n"); size = dram_size; for (p = 0; p < (u64*)(size); p++) { ppcDWstore((u32*)p, pattern); } sync(); -#endif t_end = get_tbms(); icache_disable(); diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 9da22ce..c4953df 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -13,7 +13,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc83xx.h> -#include <version.h> #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ @@ -92,12 +91,6 @@ */ .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - - .align 2 - .globl enable_addr_trans enable_addr_trans: /* enable address translation */ diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 66ebaf5..836aedd 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -48,6 +48,7 @@ config TARGET_MPC8548CDS bool "Support MPC8548CDS" select ARCH_MPC8548 select FSL_VIA + select SYS_CACHE_SHIFT_5 config TARGET_P1010RDB_PA bool "Support P1010RDB_PA" @@ -316,6 +317,7 @@ config ARCH_MPC8540 config ARCH_MPC8544 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A005125 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR2 @@ -350,6 +352,7 @@ config ARCH_MPC8560 config ARCH_P1010 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 @@ -395,6 +398,7 @@ config ARCH_P1011 config ARCH_P1020 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_ELBC_A001 @@ -490,6 +494,7 @@ config ARCH_P1025 config ARCH_P2020 bool select FSL_LAW + select SYS_CACHE_SHIFT_5 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 @@ -510,6 +515,7 @@ config ARCH_P2041 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A005275 @@ -534,6 +540,7 @@ config ARCH_P3041 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 @@ -563,6 +570,7 @@ config ARCH_P4080 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004580 @@ -601,6 +609,7 @@ config ARCH_P5040 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004699 @@ -624,11 +633,13 @@ config ARCH_P5040 config ARCH_QEMU_E500 bool + select SYS_CACHE_SHIFT_5 config ARCH_T1024 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008109 @@ -651,6 +662,7 @@ config ARCH_T1040 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -673,6 +685,7 @@ config ARCH_T1042 bool select E500MC select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -696,6 +709,7 @@ config ARCH_T2080 select E500MC select E6500 select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 @@ -718,12 +732,14 @@ config ARCH_T2080 imply CMD_NAND imply CMD_REGINFO imply FSL_SATA + imply ID_EEPROM config ARCH_T4240 bool select E500MC select E6500 select FSL_LAW + select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 15248a4..6f4ad1f 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o endif obj-$(CONFIG_CPM2) += commproc.o -obj-$(CONFIG_CPM2) += ether_fcc.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_FSL_CORENET) += liodn.o obj-$(CONFIG_MP) += mp.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 610a8ec..cd32290 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -11,6 +11,7 @@ #include <config.h> #include <common.h> #include <cpu_func.h> +#include <clock_legacy.h> #include <init.h> #include <irq_func.h> #include <log.h> @@ -52,7 +53,8 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \ + defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif @@ -70,12 +72,12 @@ int checkcpu (void) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ -#ifdef CONFIG_DDR_CLK_FREQ +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; -#endif /* CONFIG_DDR_CLK_FREQ */ +#endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c deleted file mode 100644 index 3c4eb1a..0000000 --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * MPC8560 FCC Fast Ethernet - * Copyright (c) 2003 Motorola,Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - */ - -/* - * MPC8560 FCC Fast Ethernet - * Basic ET HW initialization and packet RX/TX routines - * - * This code will not perform the IO port configuration. This should be - * done in the iop_conf_t structure specific for the board. - * - * TODO: - * add a PHY driver to do the negotiation - * reflect negotiation results in FPSMR - * look for ways to configure the board specific stuff elsewhere, eg. - * config_xxx.h or the board directory - */ - -#include <common.h> -#include <malloc.h> -#include <asm/cpm_85xx.h> -#include <command.h> -#include <config.h> -#include <net.h> - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -#include <miiphy.h> -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) - -static struct ether_fcc_info_s -{ - int ether_index; - int proff_enet; - ulong cpm_cr_enet_sblock; - ulong cpm_cr_enet_page; - ulong cmxfcr_mask; - ulong cmxfcr_value; -} - ether_fcc_info[] = -{ -#ifdef CONFIG_ETHER_ON_FCC1 -{ - 0, - PROFF_FCC1, - CPM_CR_FCC1_SBLOCK, - CPM_CR_FCC1_PAGE, - CONFIG_SYS_CMXFCR_MASK1, - CONFIG_SYS_CMXFCR_VALUE1 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC2 -{ - 1, - PROFF_FCC2, - CPM_CR_FCC2_SBLOCK, - CPM_CR_FCC2_PAGE, - CONFIG_SYS_CMXFCR_MASK2, - CONFIG_SYS_CMXFCR_VALUE2 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC3 -{ - 2, - PROFF_FCC3, - CPM_CR_FCC3_SBLOCK, - CPM_CR_FCC3_PAGE, - CONFIG_SYS_CMXFCR_MASK3, - CONFIG_SYS_CMXFCR_VALUE3 -}, -#endif -}; - -/*---------------------------------------------------------------------*/ - -/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ -#define PKT_MAXDMA_SIZE 1520 - -/* The FCC stores dest/src/type, data, and checksum for receive packets. */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 - -/* Maximum input buffer size. Must be a multiple of 32. */ -#define PKT_MAXBLR_SIZE 1536 - -#define TOUT_LOOP 1000000 - -#define TX_BUF_CNT 2 - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FCC Ethernet Tx and Rx buffer descriptors. - * Provide for Double Buffering - * Note: PKTBUFSRX is defined in net.h - */ - -typedef volatile struct rtxbd { - cbd_t rxbd[PKTBUFSRX]; - cbd_t txbd[TX_BUF_CNT]; -} RTXBD; - -/* Good news: the FCC supports external BDs! */ -#ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); -#else -#error "rtx must be 64-bit aligned" -#endif - -#undef ET_DEBUG - -static int fec_send(struct eth_device *dev, void *packet, int length) -{ - int i = 0; - int result = 0; - - if (length <= 0) { - printf("fec: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - printf("fec: tx buffer not ready\n"); - goto out; - } - } - - rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx.txbd[txIdx].cbd_datlen = length; - rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \ - BD_ENET_TX_TC | BD_ENET_TX_PAD); - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - printf("fec: tx error\n"); - goto out; - } - } - -#ifdef ET_DEBUG - printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc); - printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length); - for(i=0;i<(length/16 + 1);i++) { - printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\ - *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \ - *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3)); - } -#endif - - /* return only status bits */ - result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - txIdx = (txIdx + 1) % TX_BUF_CNT; - -out: - return result; -} - -static int fec_recv(struct eth_device* dev) -{ - int length; - - for (;;) - { - if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - length = rtx.rxbd[rxIdx].cbd_datlen; - - if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { - printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); - } - else { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], length - 4); - } - - - /* Give the buffer back to the FCC. */ - rtx.rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - - -static int fec_init(struct eth_device* dev, struct bd_info *bis) -{ - struct ether_fcc_info_s * info = dev->priv; - int i; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); - fcc_enet_t *pram_ptr; - unsigned long mem_addr; - -#if 0 - mii_discover_phy(); -#endif - - /* 28.9 - (1-2): ioports have been set up already */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - cpm->im_cpm_mux.cmxuar = 0; /* ATM */ - cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | - info->cmxfcr_value; - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } - - /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } else if (info->ether_index == 1){ - cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } else if (info->ether_index == 2){ - cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } - - /* 28.9 - (6): FDSR: Ethernet Syn */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fdsr = 0xD555; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.fdsr = 0xD555; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.fdsr = 0xD555; - } - - /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ - rxIdx = 0; - txIdx = 0; - - /* Setup Receiver Buffer Descriptors */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; - } - rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx.txbd[i].cbd_sc = 0; - rtx.txbd[i].cbd_datlen = 0; - rtx.txbd[i].cbd_bufaddr = 0; - } - rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 28.9 - (7): initialize parameter ram */ - pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); - - /* clear whole structure to make sure all reserved fields are zero */ - memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 - * 0x9000 for MPC8541, MPC8555 - */ - mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); - pram_ptr->fen_genfcc.fcc_riptr = mem_addr; - pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - */ - pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ - /* localbus SDRAM should be preferred */ - pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); - pram_ptr->fen_genfcc.fcc_rbdstat = 0; - pram_ptr->fen_genfcc.fcc_rbdlen = 0; - pram_ptr->fen_genfcc.fcc_rdptr = 0; - /* localbus SDRAM should be preferred */ - pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); - pram_ptr->fen_genfcc.fcc_tbdstat = 0; - pram_ptr->fen_genfcc.fcc_tbdlen = 0; - pram_ptr->fen_genfcc.fcc_tdptr = 0; - - /* protocol-specific area */ - pram_ptr->fen_statbuf = 0x0; - pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ - pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ - pram_ptr->fen_crcec = 0; - pram_ptr->fen_alec = 0; - pram_ptr->fen_disfc = 0; - pram_ptr->fen_retlim = 15; /* Retry limit threshold */ - pram_ptr->fen_retcnt = 0; - pram_ptr->fen_pper = 0; - pram_ptr->fen_boffcnt = 0; - pram_ptr->fen_gaddrh = 0; - pram_ptr->fen_gaddrl = 0; - pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So far we have only been given one Ethernet address. We make - * it unique by setting a few bits in the upper byte of the - * non-static part of the address. - */ -#define ea eth_get_ethaddr() - pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - pram_ptr->fen_ibdcount = 0; - pram_ptr->fen_ibdstart = 0; - pram_ptr->fen_ibdend = 0; - pram_ptr->fen_txlen = 0; - pram_ptr->fen_iaddrh = 0; /* disable hash */ - pram_ptr->fen_iaddrl = 0; - pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ - /* pad pointer. use tiptr since we don't need a specific padding char */ - pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; - pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ - pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ - -#if defined(ET_DEBUG) - printf("parm_ptr(0xff788500) = %p\n",pram_ptr); - printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", - pram_ptr->fen_genfcc.fcc_rbase); - printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", - pram_ptr->fen_genfcc.fcc_tbase); -#endif - - /* 28.9 - (8)(9): clear out events in FCCE */ - /* 28.9 - (9): FCCM: mask all events */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fcce = ~0x0; - cpm->im_cpm_fcc1.fccm = 0; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.fcce = ~0x0; - cpm->im_cpm_fcc2.fccm = 0; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.fcce = ~0x0; - cpm->im_cpm_fcc3.fccm = 0; - } - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, - info->cpm_cr_enet_sblock, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cpcr & CPM_CR_FLG); - - /* 28.9 - (14): enable tx/rx in gfmr */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } - - return 1; -} - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s * info = dev->priv; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - - /* write GFMR: disable tx/rx */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } else if(info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } else if(info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } -} - -int fec_initialize(struct bd_info *bis) -{ - struct eth_device* dev; - int i; - - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) - { - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "FCC%d", - ether_fcc_info[i].ether_index + 1); - dev->priv = ðer_fcc_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ - && defined(CONFIG_BITBANGMII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - } - - return 1; -} - -#endif diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 5bf0047..da8e0b6 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -399,4 +399,3 @@ const char *serdes_clock_to_string(u32 clock) #endif } } - diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index f5126e2..2b4912b 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -885,4 +885,3 @@ const char *serdes_clock_to_string(u32 clock) return "150"; } } - diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e229a5c..1fe914a 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -11,6 +11,7 @@ #include <common.h> #include <cpu_func.h> +#include <clock_legacy.h> #include <ppc_asm.tmpl> #include <asm/global_data.h> #include <linux/compiler.h> @@ -104,8 +105,8 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; else #endif -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + sys_info->freq_ddrbus = get_board_ddr_clk(); #else sys_info->freq_ddrbus = sysclk; #endif @@ -538,12 +539,12 @@ void get_sys_info(sys_info_t *sys_info) /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */ sys_info->freq_ddrbus = sys_info->freq_systembus; -#ifdef CONFIG_DDR_CLK_FREQ +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) { u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; if (ddr_ratio != 0x7) - sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus = ddr_ratio * get_board_ddr_clk(); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index f41e82a..656cc6e 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -14,7 +14,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc85xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> @@ -77,7 +76,7 @@ _start_e500: /* Enable debug exception */ li r1,MSR_DE - mtmsr r1 + mtmsr r1 /* * If we got an ePAPR device tree pointer passed in as r3, we need that @@ -1138,11 +1137,7 @@ switch_as: .globl _start _start: .long 0x27051956 /* U-BOOT Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - .align 4 .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ @@ -1164,9 +1159,9 @@ _start_cont: li r0,0 -1: subi r4,r4,4 - stw r0,0(r4) - cmplw r4,r3 +1: subi r4,r4,4 + stw r0,0(r4) + cmplw r4,r3 bne 1b #if CONFIG_VAL(SYS_MALLOC_F_LEN) diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index f112317..936cbda 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -19,9 +19,11 @@ choice config MPC866 bool "MPC866" + select SYS_CACHE_SHIFT_4 config MPC885 bool "MPC885" + select SYS_CACHE_SHIFT_4 endchoice diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index ed735cd..0ebb7b3 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc8xx.h> -#include <version.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> @@ -62,9 +61,6 @@ */ .text .long 0x27051956 /* U-Boot Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index eda6486..0985fb2 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -351,10 +351,6 @@ int fixup_cpu(void) */ int cpu_eth_init(struct bd_info *bis) { -#if defined(CONFIG_ETHER_ON_FCC) - fec_initialize(bis); -#endif - #if defined(CONFIG_UEC_ETH) uec_standard_init(bis); #endif diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index ac8eeb4..f753ddf 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -25,13 +25,6 @@ */ #define ARCH_DMA_MINALIGN L1_CACHE_BYTES -/* - * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too - */ -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES -#endif - #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 2c96378..a97b72d 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -26,15 +26,6 @@ #endif #endif -/* Check if boards need to enable FSL DMA engine for SDRAM init */ -#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) -#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ - ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ - !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) -#define CONFIG_FSL_DMA -#endif -#endif - /* * Provide a default boot page translation virtual address that lines up with * Freescale's default e500 reset page. diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 3b26451..5038cb9 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -294,8 +294,8 @@ void lbc_sdram_init(void); #define LBCR_EPAR_SHIFT 16 #define LBCR_BMT 0x0000FF00 #define LBCR_BMT_SHIFT 8 -#define LBCR_BMTPS 0x0000000F -#define LBCR_BMTPS_SHIFT 0 +#define LBCR_BMTPS 0x0000000F +#define LBCR_BMTPS_SHIFT 0 /* LCRR - Clock Ratio Register */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index f539c0b..770705a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1510,7 +1510,7 @@ typedef struct par_io { */ typedef struct cpc_corenet { - u32 cpccsr0; /* Config/status reg */ + u32 cpccsr0; /* Config/status reg */ u32 res1; u32 cpccfg0; /* Configuration register */ u32 res2; @@ -1573,7 +1573,7 @@ typedef struct cpc_corenet { #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a #define CPC_SRCR0_SRAMEN 0x00000001 -#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ +#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index e03ab21..19e63eb 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -46,11 +46,7 @@ #define MSR_RI (1<<1) /* Recoverable Exception */ #define MSR_LE (1<<0) /* Little Endian */ -#ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_ MSR_ME|MSR_IP|MSR_RI -#else #define MSR_ MSR_ME|MSR_RI -#endif #ifndef CONFIG_E500 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR #else @@ -752,7 +748,7 @@ #define MAS5 SPRN_MAS5 #define MAS6 SPRN_MAS6 #define MAS7 SPRN_MAS7 -#define MAS8 SPRN_MAS8 +#define MAS8 SPRN_MAS8 #if defined(CONFIG_MPC85xx) #define DAR_DEAR DEAR diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 31c17b5..8d65047 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -119,7 +119,7 @@ static void boot_jump_linux(bootm_headers_t *images) void arch_lmb_reserve(struct lmb *lmb) { phys_size_t bootm_size; - ulong size, sp, bootmap_base; + ulong size, bootmap_base; bootmap_base = env_get_bootm_low(); bootm_size = env_get_bootm_size(); @@ -141,21 +141,7 @@ void arch_lmb_reserve(struct lmb *lmb) lmb_reserve(lmb, base, bootm_size - size); } - /* - * Booting a (Linux) kernel image - * - * Allocate space for command line and board info - the - * address should be as high as possible within the reach of - * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused - * memory, which means far enough below the current stack - * pointer. - */ - sp = get_sp(); - debug("## Current stack ends at 0x%08lx\n", sp); - - /* adjust sp by 4K to be safe */ - sp -= 4096; - lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp)); + arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096); #ifdef CONFIG_MP cpu_mp_lmb_reserve(lmb); diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index dcef1ff..e550251 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -104,4 +104,3 @@ _GLOBAL(invalidate_dcache_range) sync /* wait for dcbi's to get to ram */ #endif blr - |