diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/Kconfig')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 12dc03c..2ac6b87 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -154,6 +154,7 @@ config TARGET_P2041RDB bool "Support P2041RDB" select ARCH_P2041 select BOARD_LATE_INIT if CHAIN_OF_TRUST + select FSL_CORENET select PHYS_64BIT imply CMD_SATA imply FSL_SATA @@ -233,6 +234,7 @@ config TARGET_KMP204X config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM + select FSL_CORENET endchoice @@ -240,6 +242,7 @@ config ARCH_B4420 bool select E500MC select E6500 + select FSL_CORENET select FSL_LAW select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 @@ -268,6 +271,7 @@ config ARCH_B4860 bool select E500MC select E6500 + select FSL_CORENET select FSL_LAW select HETROGENOUS_CLUSTERS select SYS_FSL_DDR_VER_47 @@ -607,6 +611,7 @@ config ARCH_P3041 bool select BACKSIDE_L2_CACHE select E500MC + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 @@ -638,6 +643,7 @@ config ARCH_P4080 bool select BACKSIDE_L2_CACHE select E500MC + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 @@ -678,6 +684,7 @@ config ARCH_P5040 bool select BACKSIDE_L2_CACHE select E500MC + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_44 @@ -710,6 +717,7 @@ config ARCH_T1024 select BACKSIDE_L2_CACHE select E500MC select E5500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 @@ -735,6 +743,7 @@ config ARCH_T1040 select BACKSIDE_L2_CACHE select E500MC select E5500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 @@ -760,6 +769,7 @@ config ARCH_T1042 select BACKSIDE_L2_CACHE select E500MC select E5500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_50 @@ -784,6 +794,7 @@ config ARCH_T2080 bool select E500MC select E6500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 @@ -814,6 +825,7 @@ config ARCH_T4240 bool select E500MC select E6500 + select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 select SYS_FSL_DDR_VER_47 @@ -1274,6 +1286,10 @@ config SYS_BOOK3E_HV bool "Category E.HV is supported" depends on BOOKE +config FSL_CORENET + bool + select SYS_FSL_CPC + config SYS_CPC_REINIT_F bool help @@ -1281,7 +1297,7 @@ config SYS_CPC_REINIT_F required to be re-initialized. config SYS_FSL_CPC - bool "Corenet Platform Cache support" + bool config SYS_CACHE_STASHING bool "Enable cache stashing" |