diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/dts/stm32429i-eval-u-boot.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/dts/stm32746g-eval-u-boot.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/dts/stm32f429-disco-u-boot.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/dts/stm32f469-disco-u-boot.dtsi | 6 | ||||
-rw-r--r-- | arch/arm/dts/stm32f7-u-boot.dtsi | 4 | ||||
-rw-r--r-- | arch/arm/dts/stm32f746-disco-u-boot.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/dts/stm32f769-disco-u-boot.dtsi | 6 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15-ddr.dtsi | 30 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi | 12 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 12 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi | 12 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi | 12 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi | 12 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 12 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15-u-boot.dtsi | 8 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 4 | ||||
-rw-r--r-- | arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 15 |
17 files changed, 35 insertions, 118 deletions
diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi index 09d9d9a..fcab9ae 100644 --- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi @@ -33,7 +33,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; + reg = <0xa0000000 0x1000>; clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; st,syscfg = <&syscfg>; pinctrl-0 = <&fmc_pins_d32>; diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi index f2195a6..8550ef7 100644 --- a/arch/arm/dts/stm32746g-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi @@ -177,7 +177,7 @@ }; &qspi { - reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>; qflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi index 297cc56..c993f86 100644 --- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi @@ -33,7 +33,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; + reg = <0xa0000000 0x1000>; clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; pinctrl-0 = <&fmc_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index 9eda8f5..cd17362 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -34,7 +34,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; + reg = <0xa0000000 0x1000>; clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; st,syscfg = <&syscfg>; pinctrl-0 = <&fmc_pins_d32>; @@ -70,7 +70,7 @@ compatible = "st,stm32f469-qspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <91>; spi-max-frequency = <108000000>; @@ -236,7 +236,7 @@ }; &qspi { - reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>; flash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 46bd110..c1b2ac2 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -7,7 +7,7 @@ fmc: fmc@A0000000 { compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; + reg = <0xa0000000 0x1000>; clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; pinctrl-0 = <&fmc_pins>; pinctrl-names = "default"; @@ -46,7 +46,7 @@ compatible = "st,stm32f469-qspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = <92>; spi-max-frequency = <108000000>; diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index 4f34fc9..f88466f 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -228,7 +228,7 @@ }; &qspi { - reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>; qflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 7dfe430..5589b41 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -53,9 +53,9 @@ soc { dsi: dsi@40016c00 { compatible = "st,stm32-dsi"; - reg = <0x40016C00 0x800>; + reg = <0x40016c00 0x800>; resets = <&rcc STM32F7_APB2_RESET(DSI)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, + clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>, <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>, <&clk_hse>; clock-names = "pclk", "px_clk", "ref"; @@ -227,7 +227,7 @@ }; &qspi { - reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>; + reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>; flash0: mx66l51235l@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 2a139c5..0aac913 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -116,24 +116,6 @@ DDR_MR3 >; -#ifdef DDR_PHY_CAL_SKIP - st,phy-cal = < - DDR_DX0DLLCR - DDR_DX0DQTR - DDR_DX0DQSTR - DDR_DX1DLLCR - DDR_DX1DQTR - DDR_DX1DQSTR - DDR_DX2DLLCR - DDR_DX2DQTR - DDR_DX2DQSTR - DDR_DX3DLLCR - DDR_DX3DQTR - DDR_DX3DQSTR - >; - -#endif - status = "okay"; }; }; @@ -224,18 +206,6 @@ #undef DDR_ODTCR #undef DDR_ZQ0CR1 #undef DDR_DX0GCR -#undef DDR_DX0DLLCR -#undef DDR_DX0DQTR -#undef DDR_DX0DQSTR #undef DDR_DX1GCR -#undef DDR_DX1DLLCR -#undef DDR_DX1DQTR -#undef DDR_DX1DQSTR #undef DDR_DX2GCR -#undef DDR_DX2DLLCR -#undef DDR_DX2DQTR -#undef DDR_DX2DQSTR #undef DDR_DX3GCR -#undef DDR_DX3DLLCR -#undef DDR_DX3DQTR -#undef DDR_DX3DQSTR diff --git a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi index 978331b..e60d0ae 100644 --- a/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi @@ -100,20 +100,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE80 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE80 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi index 426be21..1a6fa80 100644 --- a/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi @@ -100,20 +100,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi index b3eb280..0a277cd 100644 --- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi @@ -101,20 +101,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi index ed3a524..92774ff 100644 --- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi @@ -101,20 +101,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi index d5813d6..e53ab18 100644 --- a/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi @@ -101,20 +101,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi index 24c8126..ff582ac 100644 --- a/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi +++ b/arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi @@ -100,20 +100,8 @@ #define DDR_ODTCR 0x00010000 #define DDR_ZQ0CR1 0x00000038 #define DDR_DX0GCR 0x0000CE81 -#define DDR_DX0DLLCR 0x40000000 -#define DDR_DX0DQTR 0xFFFFFFFF -#define DDR_DX0DQSTR 0x3DB02000 #define DDR_DX1GCR 0x0000CE81 -#define DDR_DX1DLLCR 0x40000000 -#define DDR_DX1DQTR 0xFFFFFFFF -#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX2GCR 0x0000CE81 -#define DDR_DX2DLLCR 0x40000000 -#define DDR_DX2DQTR 0xFFFFFFFF -#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX3GCR 0x0000CE81 -#define DDR_DX3DLLCR 0x40000000 -#define DDR_DX3DQTR 0xFFFFFFFF -#define DDR_DX3DQSTR 0x3DB02000 #include "stm32mp15-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index db23d80..e23d6c7 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -50,8 +50,8 @@ compatible = "st,stm32mp1-ddr"; - reg = <0x5A003000 0x550 - 0x5A004000 0x234>; + reg = <0x5a003000 0x550 + 0x5a004000 0x234>; clocks = <&rcc AXIDCG>, <&rcc DDRC1>, @@ -237,7 +237,7 @@ u-boot-stm32 { filename = "u-boot.stm32"; mkimage { - args = "-T stm32image -a 0xC0100000 -e 0xC0100000"; + args = "-T stm32image -a 0xc0100000 -e 0xc0100000"; u-boot { }; }; @@ -250,7 +250,7 @@ spl-stm32 { filename = "u-boot-spl.stm32"; mkimage { - args = "-T stm32image -a 0x2FFC2500 -e 0x2FFC2500"; + args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500"; u-boot-spl { }; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index 71b0486..5b2b09b 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -216,6 +216,10 @@ &sdmmc1 { u-boot,dm-spl; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; }; &sdmmc1_b4_pins_a { diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index 8b275e4..c96eba9 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -19,8 +19,23 @@ }; }; + +ðernet0 { + mdio0 { + ethernet-phy@7 { + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <1000>; + }; + }; +}; + &sdmmc1 { u-boot,dm-spl; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; }; &sdmmc1_b4_pins_a { |