diff options
Diffstat (limited to 'arch/arm')
35 files changed, 4772 insertions, 9 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3baaf4..44256d9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -153,6 +153,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-nanopi-r4s.dtb \ rk3399-orangepi.dtb \ rk3399-pinebook-pro.dtb \ + rk3399-pinephone-pro.dtb \ rk3399-puma-haikou.dtb \ rk3399-roc-pc.dtb \ rk3399-roc-pc-mezzanine.dtb \ @@ -170,6 +171,9 @@ dtb-$(CONFIG_ROCKCHIP_RV1108) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb +dtb-$(CONFIG_ROCKCHIP_RV1126) += \ + rv1126-edgeble-neu2-io.dtb + dtb-$(CONFIG_ARCH_S5P4418) += \ s5p4418-nanopi2.dtb diff --git a/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi new file mode 100644 index 0000000..e8a34c7 --- /dev/null +++ b/arch/arm/dts/px30-ringneck-haikou-u-boot.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "px30-u-boot.dtsi" + +/ { + config { + u-boot,mmc-env-offset = <0x5000>; /* @ 20KB */ + u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */ + u-boot,boot-led = "module_led"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = "same-as-spl", &emmc, &sdmmc; + }; +}; + +&binman { + simple-bin { + blob { + offset = <((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512)>; + }; + }; +}; + +&emmc_clk { + u-boot,dm-pre-reloc; +}; + +&emmc_cmd { + u-boot,dm-pre-reloc; +}; + +&emmc_bus8 { + u-boot,dm-pre-reloc; +}; + +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&gpio2 { + u-boot,dm-pre-reloc; + + /* + * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module + * eMMC powered-down initially (in fact it keeps the reset signal + * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after + * the SPL has been booted from SD Card. + */ + bios-disable-override-hog { + u-boot,dm-pre-reloc; + }; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pcfg_pull_none_8ma { + u-boot,dm-pre-reloc; +}; + +&pcfg_pull_up_8ma { + u-boot,dm-pre-reloc; +}; + +&sdmmc_bus4 { + u-boot,dm-pre-reloc; +}; + +&sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_cmd { + u-boot,dm-pre-reloc; +}; + +&sdmmc_det { + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <24000000>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/px30-ringneck-haikou.dts b/arch/arm/dts/px30-ringneck-haikou.dts new file mode 100644 index 0000000..08a3ad3 --- /dev/null +++ b/arch/arm/dts/px30-ringneck-haikou.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "px30-ringneck.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit"; + compatible = "tsd,px30-ringneck-haikou", "rockchip,px30"; + + aliases { + mmc2 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&haikou_keys_pin>; + pinctrl-names = "default"; + + button-batlow-n { + label = "BATLOW#"; + linux,code = <KEY_BATTERY>; + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + }; + + button-slp-btn-n { + label = "SLP_BTN#"; + linux,code = <KEY_SLEEP>; + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; + }; + + button-wake-n { + label = "WAKE#"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-lid-btn-n { + label = "LID_BTN#"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; + + sd_card_led: led-1 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + function = LED_FUNCTION_SD; + color = <LED_COLOR_ID_BLUE>; + }; + }; + + i2s0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Haikou,I2S-codec"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { + clocks = <&sgtl5000_clk>; + sound-dai = <&sgtl5000>; + }; + + simple-audio-card,cpu { + bitclock-master; + frame-master; + sound-dai = <&i2s0_8ch>; + }; + }; + + sgtl5000_clk: sgtl5000-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_baseboard: vcc5v0-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdda_codec: vdda-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdda_codec"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_baseboard>; + }; + + vddd_codec: vddd-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vddd_codec"; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + vin-supply = <&vcc5v0_baseboard>; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_clk>; + #sound-dai-cells = <0>; + VDDA-supply = <&vdda_codec>; + VDDIO-supply = <&vcc3v3_baseboard>; + VDDD-supply = <&vddd_codec>; + }; +}; + +&i2c3 { + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&gmac { + status = "okay"; +}; + +&pinctrl { + haikou { + haikou_keys_pin: haikou-keys-pin { + rockchip,pins = + /* WAKE# */ + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + /* LID_BTN */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + /* BATLOW# */ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + /* BIOS_DISABLE# */ + <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sd_card_led_pin: sd-card-led-pin { + rockchip,pins = + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&sdmmc { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&uart5_xfer>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; diff --git a/arch/arm/dts/px30-ringneck.dtsi b/arch/arm/dts/px30-ringneck.dtsi new file mode 100644 index 0000000..1239775 --- /dev/null +++ b/arch/arm/dts/px30-ringneck.dtsi @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "px30.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdio; + rtc0 = &rtc_twi; + rtc1 = &rk809; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&module_led_pin>; + status = "okay"; + + module_led: led-0 { + gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + color = <LED_COLOR_ID_AMBER>; + }; + }; + + vcc5v0_sys: vccsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + supports-emmc; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_emmc>; + + status = "okay"; +}; + +/* On-module TI DP83825I PHY but no connector, enable in carrierboard */ +&gmac { + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + phy-supply = <&vcc_3v3>; + clock_in_out = "output"; +}; + +&gpio2 { + /* + * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module + * eMMC powered-down initially (in fact it keeps the reset signal + * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after + * the SPL has been booted from SD Card. + */ + bios-disable-override-hog { + gpios = <RK_PB5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "bios_disable_override"; + gpio-hog; + }; + + /* + * The BIOS_DISABLE hog is a feedback pin for the actual status of the + * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually + * represents the state of a switch on the baseboard. + */ + bios-disable-n-hog { + gpios = <RK_PC2 GPIO_ACTIVE_LOW>; + line-name = "bios_disable"; + input; + gpio-hog; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_int>; + pinctrl-names = "default"; + #clock-cells = <0>; + clock-output-names = "xin32k"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_3v3>; + vcc6-supply = <&vcc_3v3>; + vcc7-supply = <&vcc_3v3>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { + regulator-name = "vcc_3v0_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_3v3: DCDC_REG5 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v0: LDO_REG3 { + regulator-name = "vcc_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_lcd"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8_lcd: LDO_REG8 { + regulator-name = "vcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG9 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + /* SE05x is limited to Fast Mode */ + clock-frequency = <400000>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2s0_8ch { + rockchip,trcm-sync-tx-only; + + pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx + &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_emmc>; + vccio-oscgpi-supply = <&vcc_3v3>; + + status = "okay"; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + module_led_pin: module-led-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + vqmmc-supply = <&vccio_sd>; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +/* Mule UCAN */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index 00f50b0..bfa3580 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -365,6 +365,28 @@ status = "disabled"; }; + i2s0_8ch: i2s@ff060000 { + compatible = "rockchip,px30-i2s-tdm"; + reg = <0x0 0xff060000 0x0 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac 16>, <&dmac 17>; + dma-names = "tx", "rx"; + rockchip,grf = <&grf>; + resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; + reset-names = "tx-m", "rx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx + &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx + &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 + &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 + &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 + &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s1_2ch: i2s@ff070000 { compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff070000 0x0 0x1000>; @@ -528,7 +550,7 @@ i2c0: i2c@ff180000 { compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff180000 0x0 0x1000>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; @@ -711,7 +733,7 @@ clock-names = "pclk", "timer"; }; - dmac: dmac@ff240000 { + dmac: dma-controller@ff240000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff240000 0x0 0x4000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, @@ -1072,7 +1094,7 @@ }; dsi: dsi@ff450000 { - compatible = "rockchip,px30-mipi-dsi"; + compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff450000 0x0 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_MIPI_DSI>; diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi new file mode 100644 index 0000000..1dad283 --- /dev/null +++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Peter Robinson <pbrobinson at gmail.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr4-100.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; + + config { + u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */ + }; +}; + +&rng { + status = "okay"; +}; + +&sdhci { + max-frequency = <25000000>; + u-boot,dm-pre-reloc; +}; + +&sdmmc { + max-frequency = <20000000>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts new file mode 100644 index 0000000..04403a7 --- /dev/null +++ b/arch/arm/dts/rk3399-pinephone-pro.dts @@ -0,0 +1,474 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Martijn Braam <martijn@brixit.nl> + * Copyright (c) 2021 Kamil Trzciński <ayufan@ayufan.eu> + */ + +/* + * PinePhone Pro datasheet: + * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Pine64 PinePhonePro"; + compatible = "pine64,pinephone-pro", "rockchip,rk3399"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn_pin>; + + key-power { + debounce-interval = <20>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcca1v8_s3: vcc1v8-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcca1v8_s3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; + + vcc1v8_codec: vcc1v8-codec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc1v8_codec_en>; + regulator-name = "vcc1v8_codec"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + wifi_pwrseq: sdio-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h_pin>; + /* + * Wait between power-on and SDIO access for CYP43455 + * POR circuit. + */ + post-power-on-delay-ms = <110>; + /* + * Wait between consecutive toggles for CYP43455 CBUCK + * regulator discharge. + */ + power-off-delay-us = <10000>; + + /* WL_REG_ON on module */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_cpu_l: DCDC_REG1 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_center: DCDC_REG2 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca3v0_codec: LDO_REG1 { + regulator-name = "vcca3v0_codec"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vcca1v8_codec: LDO_REG3 { + regulator-name = "vcca1v8_codec"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + rk818_pwr_on: LDO_REG4 { + regulator-name = "rk818_pwr_on"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: LDO_REG5 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG7 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc3v3_s3: LDO_REG8 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG9 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vcc3v3_s0: SWITCH_REG { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&cluster0_opp { + opp04 { + status = "disabled"; + }; + + opp05 { + status = "disabled"; + }; +}; + +&cluster1_opp { + opp06 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1100000 1100000 1150000>; + }; + + opp07 { + status = "disabled"; + }; +}; + +&io_domains { + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn_pin: pwrbtn-pin { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h_pin: wifi-enable-h-pin { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + vcc1v8_codec_en: vcc1v8-codec-en { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + bt_wake_pin: bt-wake-pin { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_pin: bt-host-wake-pin { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_pin: bt-reset-pin { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk818 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-puma-haikou.dts b/arch/arm/dts/rk3399-puma-haikou.dts index 292bb7e..115c14c 100644 --- a/arch/arm/dts/rk3399-puma-haikou.dts +++ b/arch/arm/dts/rk3399-puma-haikou.dts @@ -49,7 +49,7 @@ sgtl5000_clk: sgtl5000-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <24576000>; + clock-frequency = <24576000>; }; dc_12v: dc-12v { @@ -207,7 +207,7 @@ cap-sd-highspeed; cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; - max-frequency = <150000000>; + max-frequency = <40000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; vmmc-supply = <&vcc3v3_baseboard>; @@ -232,6 +232,7 @@ &usbdrd_dwc3_0 { dr_mode = "otg"; + extcon = <&extcon_usb3>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index fb67db4..aa3e21b 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -25,6 +25,13 @@ }; }; + extcon_usb3: extcon-usb3 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_id>; + }; + clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -55,7 +62,6 @@ vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; - enable-active-low; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_host_en>; regulator-name = "vcc5v0_host"; @@ -71,6 +77,17 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; }; &cpu_b0 { @@ -422,9 +439,22 @@ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb3 { + usb3_id: usb3-id { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &sdhci { + /* + * Signal integrity isn't great at 200MHz but 100MHz has proven stable + * enough. + */ + max-frequency = <100000000>; + bus-width = <8>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io-u-boot.dtsi b/arch/arm/dts/rv1126-edgeble-neu2-io-u-boot.dtsi new file mode 100644 index 0000000..51a1617 --- /dev/null +++ b/arch/arm/dts/rv1126-edgeble-neu2-io-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rv1126-u-boot.dtsi" + +&sdio { + status = "disabled"; +}; diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts new file mode 100644 index 0000000..dded0a1 --- /dev/null +++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-edgeble-neu2.dtsi" + +/ { + model = "Edgeble Neu2 IO Board"; + compatible = "edgeble,neural-compute-module-2-io", + "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/dts/rv1126-edgeble-neu2.dtsi new file mode 100644 index 0000000..cc64ba4 --- /dev/null +++ b/arch/arm/dts/rv1126-edgeble-neu2.dtsi @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + aliases { + mmc0 = &emmc; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccio_flash: vccio-flash-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_vol_sel>; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-name = "vdd_npu_vepu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-name = "vcc_0v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-name = "vcc0v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-name = "vcc_dovdd"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-name = "vcc_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-name = "vcc_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&pinctrl { + bt { + bt_enable: bt-enable { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_vol_sel: flash-vol-sel { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc1v8_pmu>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vccio_flash>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_dovdd>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_dovdd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + status = "okay"; + + bluetooth { + compatible = "qcom,qca9377-bt"; + clocks = <&rk809 1>; + enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */ + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>; + vddxo-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi new file mode 100644 index 0000000..28d8d29 --- /dev/null +++ b/arch/arm/dts/rv1126-pinctrl.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clko */ + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c0_sda */ + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc0_pwr: sdmmc0-pwr { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc1_pwr: sdmmc1-pwr { + rockchip,pins = + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <1 RK_PC2 1 &pcfg_pull_up>, + /* uart0_tx */ + <1 RK_PC3 1 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn_gpio: uart0-rts-pin { + rockchip,pins = + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB6 2 &pcfg_pull_up>; + }; + }; + uart2 { + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA2 1 &pcfg_pull_up>; + }; + }; + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <3 RK_PC6 4 &pcfg_pull_up>; + }; + }; + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PA5 4 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PA4 4 &pcfg_pull_up>; + }; + }; + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi new file mode 100644 index 0000000..bc77037 --- /dev/null +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include "rockchip-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = \ + "same-as-spl", &emmc, &sdmmc; + }; + + dmc { + compatible = "rockchip,rv1126-dmc"; + u-boot,dm-pre-reloc; + }; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&grf { + u-boot,dm-spl; +}; + +&pmu { + u-boot,dm-spl; +}; + +&pmugrf { + u-boot,dm-spl; +}; + +&xin24m { + u-boot,dm-spl; +}; + +&cru { + u-boot,dm-spl; +}; + +&pmucru { + u-boot,dm-spl; +}; + +&sdmmc { + u-boot,dm-spl; +}; + +&emmc { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi new file mode 100644 index 0000000..1cb4314 --- /dev/null +++ b/arch/arm/dts/rv1126.dtsi @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rockchip,rv1126-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/power/rockchip,rv1126-power.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1126"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + grf: syscon@fe000000 { + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; + reg = <0xfe000000 0x20000>; + }; + + pmugrf: syscon@fe020000 { + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; + reg = <0xfe020000 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rv1126-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + qos_emmc: qos@fe860000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860000 0x20>; + }; + + qos_nandc: qos@fe860080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860080 0x20>; + }; + + qos_sfc: qos@fe860200 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860200 0x20>; + }; + + qos_sdio: qos@fe86c000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe86c000 0x20>; + }; + + gic: interrupt-controller@feff0000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0xfeff1000 0x1000>, + <0xfeff2000 0x2000>, + <0xfeff4000 0x2000>, + <0xfeff6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; + reg = <0xff3e0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rv1126-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RV1126_PD_NVM { + reg = <RV1126_PD_NVM>; + clocks = <&cru HCLK_EMMC>, + <&cru CLK_EMMC>, + <&cru HCLK_NANDC>, + <&cru CLK_NANDC>, + <&cru HCLK_SFC>, + <&cru HCLK_SFCXIP>, + <&cru SCLK_SFC>; + pm_qos = <&qos_emmc>, + <&qos_nandc>, + <&qos_sfc>; + #power-domain-cells = <0>; + }; + + power-domain@RV1126_PD_SDIO { + reg = <RV1126_PD_SDIO>; + clocks = <&cru HCLK_SDIO>, + <&cru CLK_SDIO>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + }; + }; + + i2c0: i2c@ff3f0000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff3f0000 0x1000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@ff410000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff410000 0x100>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 7>, <&dmac 6>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pmucru: clock-controller@ff480000 { + compatible = "rockchip,rv1126-pmucru"; + reg = <0xff480000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dmac: dma-controller@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff4e0000 0x4000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + + uart0: serial@ff560000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff560000 0x100>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 5>, <&dmac 4>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@ff570000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff570000 0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 9>, <&dmac 8>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff580000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff580000 0x100>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 11>, <&dmac 10>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@ff590000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff590000 0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 13>, <&dmac 12>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@ff5a0000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff5a0000 0x100>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 15>, <&dmac 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + saradc: adc@ff5e0000 { + compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; + reg = <0xff5e0000 0x100>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + timer0: timer@ff660000 { + compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; + reg = <0xff660000 0x20>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + emmc: mmc@ffc50000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc50000 0x4000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + + sdmmc: mmc@ffc60000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc60000 0x4000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdio: mmc@ffc70000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc70000 0x4000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_SDIO>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1126-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@ff460000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff460000 0x100>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff620000 0x100>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff630000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff640000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff640000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ff650000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff650000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rv1126-pinctrl.dtsi" diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h new file mode 100644 index 0000000..49a1f76 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h @@ -0,0 +1,459 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#ifndef _ASM_ARCH_CRU_RV1126_H +#define _ASM_ARCH_CRU_RV1126_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#define APLL_HZ (1008 * MHz) +#else +#define APLL_HZ (816 * MHz) +#endif +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (500 * MHz) +#define HPLL_HZ (1400 * MHz) +#define PCLK_PDPMU_HZ (100 * MHz) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#define ACLK_PDBUS_HZ (396 * MHz) +#else +#define ACLK_PDBUS_HZ (500 * MHz) +#endif +#define HCLK_PDBUS_HZ (200 * MHz) +#define PCLK_PDBUS_HZ (100 * MHz) +#define ACLK_PDPHP_HZ (300 * MHz) +#define HCLK_PDPHP_HZ (200 * MHz) +#define HCLK_PDCORE_HZ (200 * MHz) +#define HCLK_PDAUDIO_HZ (150 * MHz) +#define CLK_OSC0_DIV_HZ (32768) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#define ACLK_PDVI_HZ (297 * MHz) +#define CLK_ISP_HZ (297 * MHz) +#define ACLK_PDISPP_HZ (297 * MHz) +#define CLK_ISPP_HZ (237 * MHz) +#define ACLK_VOP_HZ (300 * MHz) +#define DCLK_VOP_HZ (65 * MHz) +#endif + +/* RV1126 pll id */ +enum rv1126_pll_id { + APLL, + DPLL, + CPLL, + HPLL, + GPLL, + PLL_COUNT, +}; + +struct rv1126_clk_info { + unsigned long id; + char *name; + bool is_cru; +}; + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rv1126_pmuclk_priv { + struct rv1126_pmucru *pmucru; + ulong gpll_hz; +}; + +struct rv1126_clk_priv { + struct rv1126_cru *cru; + struct rv1126_grf *grf; + ulong gpll_hz; + ulong cpll_hz; + ulong hpll_hz; + ulong armclk_hz; + ulong armclk_enter_hz; + ulong armclk_init_hz; + bool sync_kernel; + bool set_armclk_rate; +}; + +struct rv1126_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int con5; + unsigned int con6; + unsigned int reserved0[1]; +}; + +struct rv1126_pmucru { + unsigned int pmu_mode; + unsigned int reserved1[3]; + struct rv1126_pll pll; + unsigned int offsetcal_status; + unsigned int reserved2[51]; + unsigned int pmu_clksel_con[14]; + unsigned int reserved3[18]; + unsigned int pmu_clkgate_con[3]; + unsigned int reserved4[29]; + unsigned int pmu_softrst_con[2]; + unsigned int reserved5[14]; + unsigned int pmu_autocs_con[2]; +}; + +check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244); + +struct rv1126_cru { + struct rv1126_pll pll[4]; + unsigned int offsetcal_status[4]; + unsigned int mode; + unsigned int reserved1[27]; + unsigned int clksel_con[78]; + unsigned int reserved2[18]; + unsigned int clkgate_con[25]; + unsigned int reserved3[7]; + unsigned int softrst_con[15]; + unsigned int reserved4[17]; + unsigned int ssgtbl[32]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int reserved5[11]; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; + unsigned int reserved6[2]; + unsigned int gmac_con; + unsigned int misc[2]; + unsigned int reserved7[45]; + unsigned int autocs_con[26]; +}; + +check_member(rv1126_cru, autocs_con[25], 0x584); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +struct cpu_rate_table { + unsigned long rate; + unsigned int aclk_div; + unsigned int pclk_div; +}; + +#define RV1126_PMU_MODE 0x0 +#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) +#define RV1126_PLL_CON(x) ((x) * 0x4) +#define RV1126_MODE_CON 0x90 + +enum { + /* CRU_PMU_CLK_SEL0_CON */ + RTC32K_SEL_SHIFT = 7, + RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, + RTC32K_SEL_PMUPVTM = 0, + RTC32K_SEL_OSC1_32K, + RTC32K_SEL_OSC0_DIV32K, + + /* CRU_PMU_CLK_SEL1_CON */ + PCLK_PDPMU_DIV_SHIFT = 0, + PCLK_PDPMU_DIV_MASK = 0x1f, + + /* CRU_PMU_CLK_SEL2_CON */ + CLK_I2C0_DIV_SHIFT = 0, + CLK_I2C0_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL3_CON */ + CLK_I2C2_DIV_SHIFT = 0, + CLK_I2C2_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL6_CON */ + CLK_PWM1_SEL_SHIFT = 15, + CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT, + CLK_PWM1_SEL_XIN24M = 0, + CLK_PWM1_SEL_GPLL, + CLK_PWM1_DIV_SHIFT = 8, + CLK_PWM1_DIV_MASK = 0x7f << CLK_PWM1_DIV_SHIFT, + CLK_PWM0_SEL_SHIFT = 7, + CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, + CLK_PWM0_SEL_XIN24M = 0, + CLK_PWM0_SEL_GPLL, + CLK_PWM0_DIV_SHIFT = 0, + CLK_PWM0_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL9_CON */ + CLK_SPI0_SEL_SHIFT = 7, + CLK_SPI0_SEL_MASK = 1 << CLK_SPI0_SEL_SHIFT, + CLK_SPI0_SEL_GPLL = 0, + CLK_SPI0_SEL_XIN24M, + CLK_SPI0_DIV_SHIFT = 0, + CLK_SPI0_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL13_CON */ + CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, + CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, + CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_CLK_SEL0_CON */ + CORE_HCLK_DIV_SHIFT = 8, + CORE_HCLK_DIV_MASK = 0x1f << CORE_HCLK_DIV_SHIFT, + + /* CRU_CLK_SEL1_CON */ + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 0xf << CORE_ACLK_DIV_SHIFT, + CORE_DBG_DIV_SHIFT = 0, + CORE_DBG_DIV_MASK = 0x7, + + /* CRU_CLK_SEL2_CON */ + HCLK_PDBUS_SEL_SHIFT = 15, + HCLK_PDBUS_SEL_MASK = 1 << HCLK_PDBUS_SEL_SHIFT, + HCLK_PDBUS_SEL_GPLL = 0, + HCLK_PDBUS_SEL_CPLL, + HCLK_PDBUS_DIV_SHIFT = 8, + HCLK_PDBUS_DIV_MASK = 0x1f << HCLK_PDBUS_DIV_SHIFT, + ACLK_PDBUS_SEL_SHIFT = 6, + ACLK_PDBUS_SEL_MASK = 0x3 << ACLK_PDBUS_SEL_SHIFT, + ACLK_PDBUS_SEL_GPLL = 0, + ACLK_PDBUS_SEL_CPLL, + ACLK_PDBUS_SEL_DPLL, + ACLK_PDBUS_DIV_SHIFT = 0, + ACLK_PDBUS_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL3_CON */ + CLK_SCR1_SEL_SHIFT = 15, + CLK_SCR1_SEL_MASK = 1 << CLK_SCR1_SEL_SHIFT, + CLK_SCR1_SEL_GPLL = 0, + CLK_SCR1_SEL_CPLL, + CLK_SCR1_DIV_SHIFT = 8, + CLK_SCR1_DIV_MASK = 0x1f << CLK_SCR1_DIV_SHIFT, + PCLK_PDBUS_SEL_SHIFT = 7, + PCLK_PDBUS_SEL_MASK = 1 << PCLK_PDBUS_SEL_SHIFT, + PCLK_PDBUS_SEL_GPLL = 0, + PCLK_PDBUS_SEL_CPLL, + PCLK_PDBUS_DIV_SHIFT = 0, + PCLK_PDBUS_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL4_CON */ + ACLK_CRYPTO_SEL_SHIFT = 7, + ACLK_CRYPTO_SEL_MASK = 1 << ACLK_CRYPTO_SEL_SHIFT, + ACLK_CRYPTO_SEL_GPLL = 0, + ACLK_CRYPTO_SEL_CPLL, + ACLK_CRYPTO_DIV_SHIFT = 0, + ACLK_CRYPTO_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL5_CON */ + CLK_I2C3_DIV_SHIFT = 8, + CLK_I2C3_DIV_MASK = 0x7f << CLK_I2C3_DIV_SHIFT, + CLK_I2C1_DIV_SHIFT = 0, + CLK_I2C1_DIV_MASK = 0x7f, + + /* CRU_CLK_SEL6_CON */ + CLK_I2C5_DIV_SHIFT = 8, + CLK_I2C5_DIV_MASK = 0x7f << CLK_I2C5_DIV_SHIFT, + CLK_I2C4_DIV_SHIFT = 0, + CLK_I2C4_DIV_MASK = 0x7f, + + /* CRU_CLK_SEL7_CON */ + CLK_CRYPTO_PKA_SEL_SHIFT = 15, + CLK_CRYPTO_PKA_SEL_MASK = 1 << CLK_CRYPTO_PKA_SEL_SHIFT, + CLK_CRYPTO_PKA_SEL_GPLL = 0, + CLK_CRYPTO_PKA_SEL_CPLL, + CLK_CRYPTO_PKA_DIV_SHIFT = 8, + CLK_CRYPTO_PKA_DIV_MASK = 0x1f << CLK_CRYPTO_PKA_DIV_SHIFT, + CLK_CRYPTO_CORE_SEL_SHIFT = 7, + CLK_CRYPTO_CORE_SEL_MASK = 1 << CLK_CRYPTO_CORE_SEL_SHIFT, + CLK_CRYPTO_CORE_SEL_GPLL = 0, + CLK_CRYPTO_CORE_SEL_CPLL, + CLK_CRYPTO_CORE_DIV_SHIFT = 0, + CLK_CRYPTO_CORE_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL8_CON */ + CLK_SPI1_SEL_SHIFT = 8, + CLK_SPI1_SEL_MASK = 1 << CLK_SPI1_SEL_SHIFT, + CLK_SPI1_SEL_GPLL = 0, + CLK_SPI1_SEL_XIN24M, + CLK_SPI1_DIV_SHIFT = 0, + CLK_SPI1_DIV_MASK = 0x7f, + + /* CRU_CLK_SEL9_CON */ + CLK_PWM2_SEL_SHIFT = 15, + CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT, + CLK_PWM2_SEL_XIN24M = 0, + CLK_PWM2_SEL_GPLL, + CLK_PWM2_DIV_SHIFT = 8, + CLK_PWM2_DIV_MASK = 0x7f << CLK_PWM2_DIV_SHIFT, + + /* CRU_CLK_SEL20_CON */ + CLK_SARADC_DIV_SHIFT = 0, + CLK_SARADC_DIV_MASK = 0x7ff, + + /* CRU_CLK_SEL25_CON */ + DCLK_DECOM_SEL_SHIFT = 15, + DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, + DCLK_DECOM_SEL_GPLL = 0, + DCLK_DECOM_SEL_CPLL, + DCLK_DECOM_DIV_SHIFT = 8, + DCLK_DECOM_DIV_MASK = 0x7f << DCLK_DECOM_DIV_SHIFT, + + /* CRU_CLK_SEL26_CON */ + HCLK_PDAUDIO_DIV_SHIFT = 0, + HCLK_PDAUDIO_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL45_CON */ + ACLK_PDVO_SEL_SHIFT = 7, + ACLK_PDVO_SEL_MASK = 1 << ACLK_PDVO_SEL_SHIFT, + ACLK_PDVO_SEL_GPLL = 0, + ACLK_PDVO_SEL_CPLL, + ACLK_PDVO_DIV_SHIFT = 0, + ACLK_PDVO_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL47_CON */ + DCLK_VOP_SEL_SHIFT = 8, + DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_SEL_GPLL = 0, + DCLK_VOP_SEL_CPLL, + DCLK_VOP_DIV_SHIFT = 0, + DCLK_VOP_DIV_MASK = 0xff, + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) + /* CRU_CLK_SEL49_CON */ + ACLK_PDVI_SEL_SHIFT = 6, + ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT, + ACLK_PDVI_SEL_CPLL = 0, + ACLK_PDVI_SEL_GPLL, + ACLK_PDVI_SEL_HPLL, + ACLK_PDVI_DIV_SHIFT = 0, + ACLK_PDVI_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL50_CON */ + CLK_ISP_SEL_SHIFT = 6, + CLK_ISP_SEL_MASK = 0x3 << CLK_ISP_SEL_SHIFT, + CLK_ISP_SEL_GPLL = 0, + CLK_ISP_SEL_CPLL, + CLK_ISP_SEL_HPLL, + CLK_ISP_DIV_SHIFT = 0, + CLK_ISP_DIV_MASK = 0x1f, +#endif + + /* CRU_CLK_SEL53_CON */ + HCLK_PDPHP_DIV_SHIFT = 8, + HCLK_PDPHP_DIV_MASK = 0x1f << HCLK_PDPHP_DIV_SHIFT, + ACLK_PDPHP_SEL_SHIFT = 7, + ACLK_PDPHP_SEL_MASK = 1 << ACLK_PDPHP_SEL_SHIFT, + ACLK_PDPHP_SEL_GPLL = 0, + ACLK_PDPHP_SEL_CPLL, + ACLK_PDPHP_DIV_SHIFT = 0, + ACLK_PDPHP_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL57_CON */ + EMMC_SEL_SHIFT = 14, + EMMC_SEL_MASK = 0x3 << EMMC_SEL_SHIFT, + EMMC_SEL_GPLL = 0, + EMMC_SEL_CPLL, + EMMC_SEL_XIN24M, + EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0xff, + + /* CRU_CLK_SEL58_CON */ + SCLK_SFC_SEL_SHIFT = 15, + SCLK_SFC_SEL_MASK = 0x1 << SCLK_SFC_SEL_SHIFT, + SCLK_SFC_SEL_CPLL = 0, + SCLK_SFC_SEL_GPLL, + SCLK_SFC_DIV_SHIFT = 0, + SCLK_SFC_DIV_MASK = 0xff, + + /* CRU_CLK_SEL59_CON */ + CLK_NANDC_SEL_SHIFT = 15, + CLK_NANDC_SEL_MASK = 0x1 << CLK_NANDC_SEL_SHIFT, + CLK_NANDC_SEL_GPLL = 0, + CLK_NANDC_SEL_CPLL, + CLK_NANDC_DIV_SHIFT = 0, + CLK_NANDC_DIV_MASK = 0xff, + + /* CRU_CLK_SEL61_CON */ + CLK_GMAC_OUT_SEL_SHIFT = 15, + CLK_GMAC_OUT_SEL_MASK = 0x1 << CLK_GMAC_OUT_SEL_SHIFT, + CLK_GMAC_OUT_SEL_CPLL = 0, + CLK_GMAC_OUT_SEL_GPLL, + CLK_GMAC_OUT_DIV_SHIFT = 8, + CLK_GMAC_OUT_DIV_MASK = 0x1f << CLK_GMAC_OUT_DIV_SHIFT, + + /* CRU_CLK_SEL63_CON */ + PCLK_GMAC_DIV_SHIFT = 8, + PCLK_GMAC_DIV_MASK = 0x1f << PCLK_GMAC_DIV_SHIFT, + CLK_GMAC_SRC_SEL_SHIFT = 7, + CLK_GMAC_SRC_SEL_MASK = 0x1 << CLK_GMAC_SRC_SEL_SHIFT, + CLK_GMAC_SRC_SEL_CPLL = 0, + CLK_GMAC_SRC_SEL_GPLL, + CLK_GMAC_SRC_DIV_SHIFT = 0, + CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT, + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) + /* CRU_CLK_SEL68_CON */ + ACLK_PDISPP_SEL_SHIFT = 6, + ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT, + ACLK_PDISPP_SEL_CPLL = 0, + ACLK_PDISPP_SEL_GPLL, + ACLK_PDISPP_SEL_HPLL, + ACLK_PDISPP_DIV_SHIFT = 0, + ACLK_PDISPP_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL69_CON */ + CLK_ISPP_SEL_SHIFT = 6, + CLK_ISPP_SEL_MASK = 0x3 << CLK_ISPP_SEL_SHIFT, + CLK_ISPP_SEL_CPLL = 0, + CLK_ISPP_SEL_GPLL, + CLK_ISPP_SEL_HPLL, + CLK_ISPP_DIV_SHIFT = 0, + CLK_ISPP_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL73_CON */ + MIPICSI_OUT_SEL_SHIFT = 10, + MIPICSI_OUT_SEL_MASK = 0x3 << MIPICSI_OUT_SEL_SHIFT, + MIPICSI_OUT_SEL_XIN24M = 0, + MIPICSI_OUT_SEL_DIV, + MIPICSI_OUT_SEL_FRACDIV, + MIPICSI_OUT_DIV_SHIFT = 0, + MIPICSI_OUT_DIV_MASK = 0x1f, +#endif + + /* CRU_GMAC_CON */ + GMAC_SRC_M1_SEL_SHIFT = 5, + GMAC_SRC_M1_SEL_MASK = 0x1 << GMAC_SRC_M1_SEL_SHIFT, + GMAC_SRC_M1_SEL_INT = 0, + GMAC_SRC_M1_SEL_EXT, + GMAC_MODE_SEL_SHIFT = 4, + GMAC_MODE_SEL_MASK = 0x1 << GMAC_MODE_SEL_SHIFT, + GMAC_RGMII_MODE = 0, + GMAC_RMII_MODE, + RGMII_CLK_SEL_SHIFT = 2, + RGMII_CLK_SEL_MASK = 0x3 << RGMII_CLK_SEL_SHIFT, + RGMII_CLK_DIV0 = 0, + RGMII_CLK_DIV1, + RGMII_CLK_DIV50, + RGMII_CLK_DIV5, + RMII_CLK_SEL_SHIFT = 1, + RMII_CLK_SEL_MASK = 0x1 << RMII_CLK_SEL_SHIFT, + RMII_CLK_DIV20 = 0, + RMII_CLK_DIV2, + GMAC_SRC_M0_SEL_SHIFT = 0, + GMAC_SRC_M0_SEL_MASK = 0x1, + GMAC_SRC_M0_SEL_INT = 0, + GMAC_SRC_M0_SEL_EXT, + + /* GRF_IOFUNC_CON1 */ + GMAC_SRC_SEL_SHIFT = 12, + GMAC_SRC_SEL_MASK = 1 << GMAC_SRC_SEL_SHIFT, + GMAC_SRC_SEL_M0 = 0, + GMAC_SRC_SEL_M1, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/dram_spec_timing.h b/arch/arm/include/asm/arch-rockchip/dram_spec_timing.h new file mode 100644 index 0000000..a691e97 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/dram_spec_timing.h @@ -0,0 +1,452 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Rockchip Electronics Co., Ltd + */ + +#ifndef __ROCKCHIP_DRAM_SPEC_TIMING_H__ +#define __ROCKCHIP_DRAM_SPEC_TIMING_H__ + +enum ddr3_speed_rate { + /* 5-5-5 */ + DDR3_800D = 0, + /* 6-6-6 */ + DDR3_800E = 1, + /* 6-6-6 */ + DDR3_1066E = 2, + /* 7-7-7 */ + DDR3_1066F = 3, + /* 8-8-8 */ + DDR3_1066G = 4, + /* 7-7-7 */ + DDR3_1333F = 5, + /* 8-8-8 */ + DDR3_1333G = 6, + /* 9-9-9 */ + DDR3_1333H = 7, + /* 10-10-10 */ + DDR3_1333J = 8, + /* 8-8-8 */ + DDR3_1600G = 9, + /* 9-9-9 */ + DDR3_1600H = 10, + /* 10-10-10 */ + DDR3_1600J = 11, + /* 11-11-11 */ + DDR3_1600K = 12, + /* 10-10-10 */ + DDR3_1866J = 13, + /* 11-11-11 */ + DDR3_1866K = 14, + /* 12-12-12 */ + DDR3_1866L = 15, + /* 13-13-13 */ + DDR3_1866M = 16, + /* 11-11-11 */ + DDR3_2133K = 17, + /* 12-12-12 */ + DDR3_2133L = 18, + /* 13-13-13 */ + DDR3_2133M = 19, + /* 14-14-14 */ + DDR3_2133N = 20, + DDR3_DEFAULT = 21, +}; + +enum ddr4_speed_rate { + /* DDR4_1600J (10-10-10) */ + DDR4_1600J = 0, + /* DDR4_1600K (11-11-11) */ + DDR4_1600K = 1, + /* DDR4_1600L (12-12-12) */ + DDR4_1600L = 2, + /* DDR4_1800L (12-12-12) */ + DDR4_1866L = 3, + /* DDR4_1800M (13-13-13) */ + DDR4_1866M = 4, + /* DDR4_1800N (14-14-14) */ + DDR4_1866N = 5, + /* DDR4_2133N (14-14-14) */ + DDR4_2133N = 6, + /* DDR4_2133P (15-15-15) */ + DDR4_2133P = 7, + /* DDR4_2133R (16-16-16) */ + DDR4_2133R = 8, + /* DDR4_2400P (15-15-15) */ + DDR4_2400P = 9, + /* DDR4_2400R (16-16-16) */ + DDR4_2400R = 10, + /* DDR4_2400U (18-18-18) */ + DDR4_2400U = 11, + /* DEFAULT */ + DDR4_DEFAULT = 12, +}; + +/* mr0 for ddr3 */ +#define DDR3_BL8 (0) +#define DDR3_BC4_8 (1) +#define DDR3_BC4 (2) +#define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\ + | ((((n) - 4) & 0x8) >> 1)) +#define DDR3_WR(n) (((n) & 0x7) << 9) +#define DDR3_DLL_RESET (1 << 8) +#define DDR3_DLL_DERESET (0 << 8) + +/* mr1 for ddr3 */ +#define DDR3_DLL_ENABLE (0) +#define DDR3_DLL_DISABLE (1) +#define DDR3_MR1_AL(n) (((n) & 0x3) << 3) + +#define DDR3_DS_40 (0) +#define DDR3_DS_34 BIT(1) +#define DDR3_DS_MASK ((1 << 1) | (1 << 5)) +#define DDR3_RTT_NOM_MASK ((1 << 2) | (1 << 6) | (1 << 9)) +#define DDR3_RTT_NOM_DIS (0) +#define DDR3_RTT_NOM_60 BIT(2) +#define DDR3_RTT_NOM_120 BIT(6) +#define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6)) +#define DDR3_TDQS BIT(11) + +/* mr2 for ddr3 */ +#define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3) +#define DDR3_RTT_WR_DIS (0) +#define DDR3_RTT_WR_60 (1 << 9) +#define DDR3_RTT_WR_120 (2 << 9) + +/* + * MR0 (Device Information) + * 0:DAI complete, 1:DAI still in progress + */ +#define LPDDR2_DAI (0x1) +/* 0:S2 or S4 SDRAM, 1:NVM */ +#define LPDDR2_DI (0x1 << 1) +/* 0:DNV not supported, 1:DNV supported */ +#define LPDDR2_DNVI (0x1 << 2) +#define LPDDR2_RZQI (0x3 << 3) + +/* + * 00:RZQ self test not supported, + * 01:ZQ-pin may connect to VDDCA or float + * 10:ZQ-pin may short to GND. + * 11:ZQ-pin self test completed, no error condition detected. + */ + +/* MR1 (Device Feature) */ +#define LPDDR2_BL4 (0x2) +#define LPDDR2_BL8 (0x3) +#define LPDDR2_BL16 (0x4) +#define LPDDR2_N_WR(n) (((n) - 2) << 5) + +/* MR2 (Device Feature 2) */ +#define LPDDR2_RL3_WL1 (0x1) +#define LPDDR2_RL4_WL2 (0x2) +#define LPDDR2_RL5_WL2 (0x3) +#define LPDDR2_RL6_WL3 (0x4) +#define LPDDR2_RL7_WL4 (0x5) +#define LPDDR2_RL8_WL4 (0x6) + +/* MR3 (IO Configuration 1) */ +#define LPDDR2_DS_34 (0x1) +#define LPDDR2_DS_40 (0x2) +#define LPDDR2_DS_48 (0x3) +#define LPDDR2_DS_60 (0x4) +#define LPDDR2_DS_80 (0x6) +/* optional */ +#define LPDDR2_DS_120 (0x7) + +/* MR4 (Device Temperature) */ +#define LPDDR2_TREF_MASK (0x7) +#define LPDDR2_4_TREF (0x1) +#define LPDDR2_2_TREF (0x2) +#define LPDDR2_1_TREF (0x3) +#define LPDDR2_025_TREF (0x5) +#define LPDDR2_025_TREF_DERATE (0x6) + +#define LPDDR2_TUF (0x1 << 7) + +/* MR8 (Basic configuration 4) */ +#define LPDDR2_S4 (0x0) +#define LPDDR2_S2 (0x1) +#define LPDDR2_N (0x2) +/* Unit:MB */ +#define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) +#define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) + +/* MR10 (Calibration) */ +#define LPDDR2_ZQINIT (0xff) +#define LPDDR2_ZQCL (0xab) +#define LPDDR2_ZQCS (0x56) +#define LPDDR2_ZQRESET (0xc3) + +/* MR16 (PASR Bank Mask), S2 SDRAM Only */ +#define LPDDR2_PASR_FULL (0x0) +#define LPDDR2_PASR_1_2 (0x1) +#define LPDDR2_PASR_1_4 (0x2) +#define LPDDR2_PASR_1_8 (0x3) + +/* + * MR0 (Device Information) + * 0:DAI complete, + * 1:DAI still in progress + */ +#define LPDDR3_DAI (0x1) +/* + * 00:RZQ self test not supported, + * 01:ZQ-pin may connect to VDDCA or float + * 10:ZQ-pin may short to GND. + * 11:ZQ-pin self test completed, no error condition detected. + */ +#define LPDDR3_RZQI (0x3 << 3) +/* + * 0:DRAM does not support WL(Set B), + * 1:DRAM support WL(Set B) + */ +#define LPDDR3_WL_SUPOT BIT(6) +/* + * 0:DRAM does not support RL=3,nWR=3,WL=1; + * 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166 + */ +#define LPDDR3_RL3_SUPOT BIT(7) + +/* MR1 (Device Feature) */ +#define LPDDR3_BL8 (0x3) +#define LPDDR3_N_WR(n) ((n) << 5) + +/* MR2 (Device Feature 2), WL Set A,default */ +/* <=166MHz,optional*/ +#define LPDDR3_RL3_WL1 (0x1) +/* <=400MHz*/ +#define LPDDR3_RL6_WL3 (0x4) +/* <=533MHz*/ +#define LPDDR3_RL8_WL4 (0x6) +/* <=600MHz*/ +#define LPDDR3_RL9_WL5 (0x7) +/* <=667MHz,default*/ +#define LPDDR3_RL10_WL6 (0x8) +/* <=733MHz*/ +#define LPDDR3_RL11_WL6 (0x9) +/* <=800MHz*/ +#define LPDDR3_RL12_WL6 (0xa) +/* <=933MHz*/ +#define LPDDR3_RL14_WL8 (0xc) +/* <=1066MHz*/ +#define LPDDR3_RL16_WL8 (0xe) + +/* WL Set B, optional */ +/* <=667MHz,default*/ +#define LPDDR3_RL10_WL8 (0x8) +/* <=733MHz*/ +#define LPDDR3_RL11_WL9 (0x9) +/* <=800MHz*/ +#define LPDDR3_RL12_WL9 (0xa) +/* <=933MHz*/ +#define LPDDR3_RL14_WL11 (0xc) +/* <=1066MHz*/ +#define LPDDR3_RL16_WL13 (0xe) + +/* 1:enable nWR programming > 9(default)*/ +#define LPDDR3_N_WRE BIT(4) +/* 1:Select WL Set B*/ +#define LPDDR3_WL_S BIT(6) +/* 1:enable*/ +#define LPDDR3_WR_LEVEL BIT(7) + +/* MR3 (IO Configuration 1) */ +#define LPDDR3_DS_34 (0x1) +#define LPDDR3_DS_40 (0x2) +#define LPDDR3_DS_48 (0x3) +#define LPDDR3_DS_60 (0x4) +#define LPDDR3_DS_80 (0x6) +#define LPDDR3_DS_34D_40U (0x9) +#define LPDDR3_DS_40D_48U (0xa) +#define LPDDR3_DS_34D_48U (0xb) + +/* MR4 (Device Temperature) */ +#define LPDDR3_TREF_MASK (0x7) +/* SDRAM Low temperature operating limit exceeded */ +#define LPDDR3_LT_EXED (0x0) +#define LPDDR3_4_TREF (0x1) +#define LPDDR3_2_TREF (0x2) +#define LPDDR3_1_TREF (0x3) +#define LPDDR3_05_TREF (0x4) +#define LPDDR3_025_TREF (0x5) +#define LPDDR3_025_TREF_DERATE (0x6) +/* SDRAM High temperature operating limit exceeded */ +#define LPDDR3_HT_EXED (0x7) + +/* 1:value has changed since last read of MR4 */ +#define LPDDR3_TUF (0x1 << 7) + +/* MR8 (Basic configuration 4) */ +#define LPDDR3_S8 (0x3) +#define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) +#define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) + +/* MR10 (Calibration) */ +#define LPDDR3_ZQINIT (0xff) +#define LPDDR3_ZQCL (0xab) +#define LPDDR3_ZQCS (0x56) +#define LPDDR3_ZQRESET (0xc3) + +/* MR11 (ODT Control) */ +#define LPDDR3_ODT_60 (1) +#define LPDDR3_ODT_120 (2) +#define LPDDR3_ODT_240 (3) +#define LPDDR3_ODT_DIS (0) + +/* MR2 (Device Feature 2) */ +/* RL & nRTP for DBI-RD Disabled */ +#define LPDDR4_RL6_NRTP8 (0x0) +#define LPDDR4_RL10_NRTP8 (0x1) +#define LPDDR4_RL14_NRTP8 (0x2) +#define LPDDR4_RL20_NRTP8 (0x3) +#define LPDDR4_RL24_NRTP10 (0x4) +#define LPDDR4_RL28_NRTP12 (0x5) +#define LPDDR4_RL32_NRTP14 (0x6) +#define LPDDR4_RL36_NRTP16 (0x7) +/* RL & nRTP for DBI-RD Disabled */ +#define LPDDR4_RL12_NRTP8 (0x1) +#define LPDDR4_RL16_NRTP8 (0x2) +#define LPDDR4_RL22_NRTP8 (0x3) +#define LPDDR4_RL28_NRTP10 (0x4) +#define LPDDR4_RL32_NRTP12 (0x5) +#define LPDDR4_RL36_NRTP14 (0x6) +#define LPDDR4_RL40_NRTP16 (0x7) +/* WL Set A,default */ +#define LPDDR4_A_WL4 (0x0 << 3) +#define LPDDR4_A_WL6 (0x1 << 3) +#define LPDDR4_A_WL8 (0x2 << 3) +#define LPDDR4_A_WL10 (0x3 << 3) +#define LPDDR4_A_WL12 (0x4 << 3) +#define LPDDR4_A_WL14 (0x5 << 3) +#define LPDDR4_A_WL16 (0x6 << 3) +#define LPDDR4_A_WL18 (0x7 << 3) +/* WL Set B, optional */ +#define LPDDR4_B_WL4 (0x0 << 3) +#define LPDDR4_B_WL8 (0x1 << 3) +#define LPDDR4_B_WL12 (0x2 << 3) +#define LPDDR4_B_WL18 (0x3 << 3) +#define LPDDR4_B_WL22 (0x4 << 3) +#define LPDDR4_B_WL26 (0x5 << 3) +#define LPDDR4_B_WL30 (0x6 << 3) +#define LPDDR4_B_WL34 (0x7 << 3) +/* 1:Select WL Set B*/ +#define LPDDR4_WL_B BIT(6) +/* 1:enable*/ +#define LPDDR4_WR_LEVEL BIT(7) + +/* MR3 */ +#define LPDDR4_VDDQ_2_5 (0) +#define LPDDR4_VDDQ_3 (1) +#define LPDDR4_PU_CAL_MASK (1) +#define LPDDR4_WRPST_0_5_TCK (0 << 1) +#define LPDDR4_WRPST_1_5_TCK (1 << 1) +#define LPDDR4_PPR_EN (1 << 2) +/* PDDS */ +#define LPDDR4_PDDS_MASK (0x7 << 3) +#define LPDDR4_PDDS_SHIFT (3) +#define LPDDR4_PDDS_240 (0x1 << 3) +#define LPDDR4_PDDS_120 (0x2 << 3) +#define LPDDR4_PDDS_80 (0x3 << 3) +#define LPDDR4_PDDS_60 (0x4 << 3) +#define LPDDR4_PDDS_48 (0x5 << 3) +#define LPDDR4_PDDS_40 (0x6 << 3) +#define LPDDR4_DBI_RD_EN BIT(6) +#define LPDDR4_DBI_WR_EN BIT(7) + +/* MR11 (ODT Control) */ +#define LPDDR4_DQODT_MASK (0x7) +#define LPDDR4_DQODT_SHIFT (0x0) +#define LPDDR4_DQODT_240 (1) +#define LPDDR4_DQODT_120 (2) +#define LPDDR4_DQODT_80 (3) +#define LPDDR4_DQODT_60 (4) +#define LPDDR4_DQODT_48 (5) +#define LPDDR4_DQODT_40 (6) +#define LPDDR4_DQODT_DIS (0) +#define LPDDR4_CAODT_MASK (0x7 << 4) +#define LPDDR4_CAODT_SHIFT (4) +#define LPDDR4_CAODT_240 (1 << 4) +#define LPDDR4_CAODT_120 (2 << 4) +#define LPDDR4_CAODT_80 (3 << 4) +#define LPDDR4_CAODT_60 (4 << 4) +#define LPDDR4_CAODT_48 (5 << 4) +#define LPDDR4_CAODT_40 (6 << 4) +#define LPDDR4_CAODT_DIS (0 << 4) + +/* MR22 */ +#define LPDDR4_ODTE_CK_SHIFT (3) +#define LPDDR4_ODTE_CS_SHIFT (4) +#define LPDDR4_ODTD_CA_SHIFT (5) +#define LPDDR4_SOC_ODT_MASK (0x7) +#define LPDDR4_SOC_ODT_SHIFT (0) +#define LPDDR4_SOC_ODT_240 (1) +#define LPDDR4_SOC_ODT_120 (2) +#define LPDDR4_SOC_ODT_80 (3) +#define LPDDR4_SOC_ODT_60 (4) +#define LPDDR4_SOC_ODT_48 (5) +#define LPDDR4_SOC_ODT_40 (6) +#define LPDDR4_SOC_ODT_DIS (0) + +/* LPDDR4x */ +/* MR3 */ +#define LPDDR4X_VDDQ_0_6 (0) +#define LPDDR4X_VDDQ_0_5 (1) + +/* mr0 for ddr4 */ +#define DDR4_BL8 (0) +#define DDR4_BC4_8 (1) +#define DDR4_BC4 (2) +#define DDR4_WR_RTP(n) ((n) << 9) +#define DDR4_CL(n) ((((n) & 0xe) << 3) | ((n) & 1) << 2) +#define DDR4_DLL_RESET(n) ((n) << 8) +#define DDR4_DLL_ON BIT(0) +#define DDR4_DLL_OFF (0 << 0) + +/* mr1 for ddr4 */ +#define DDR4_AL ((n) << 3) +#define DDR4_DS_34 (0) +#define DDR4_DS_48 BIT(1) +#define DDR4_DS_MASK (0x3 << 1) +#define DDR4_RTT_NOM_MASK (0x7 << 8) +#define DDR4_RTT_NOM_DIS (0) +#define DDR4_RTT_NOM_60 BIT(8) +#define DDR4_RTT_NOM_120 (2 << 8) +#define DDR4_RTT_NOM_40 (0x3 << 8) +#define DDR4_RTT_NOM_240 (0x4 << 8) +#define DDR4_RTT_NOM_48 (0x5 << 8) +#define DDR4_RTT_NOM_80 (0x6 << 8) +#define DDR4_RTT_NOM_34 (0x7 << 8) + +/* mr2 for ddr4 */ +#define DDR4_MR2_CWL(n) ((n) << 3) +#define DDR4_RTT_WR_DIS (0) +#define DDR4_RTT_WR_120 BIT(9) +#define DDR4_RTT_WR_240 (2 << 9) + +/* mr4 for ddr4 */ +#define DDR4_READ_PREAMBLE(n) ((n) << 11) +#define DDR4_WRITE_PREAMBLE(n) ((n) << 12) +#define DDR4_READ_PREAMBLE_TRAIN(n) ((n) << 10) + +/* mr5 for ddr4 */ +#define DDR4_RD_DBI(n) ((n) << 12) +#define DDR4_WR_DBI(n) ((n) << 11) +#define DDR4_DM(n) ((n) << 10) +#define DDR4_RTT_PARK_DIS (0 << 6) +#define DDR4_RTT_PARK_60 (1 << 6) +#define DDR4_RTT_PARK_120 (2 << 6) +#define DDR4_RTT_PARK_40 (3 << 6) +#define DDR4_RTT_PARK_240 (4 << 6) +#define DDR4_RTT_PARK_48 (5 << 6) +#define DDR4_RTT_PARK_80 (6 << 6) +#define DDR4_RTT_PARK_34 (7 << 6) +#define DIS_ODT_PD (1 << 5) +#define EN_ODT_PD (0 << 5) + +/* mr6 for ddr4 */ +#define DDR4_TCCD_L(n) (((n) - 4) << 10) + +#define PS_2_CLK(freq, ps) (((uint64_t)(ps) / 100 * (uint64_t)(freq) +\ + 9999) / 10000) + +#endif /* __ROCKCHIP_DRAM_SPEC_TIMING_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1126.h b/arch/arm/include/asm/arch-rockchip/grf_rv1126.h new file mode 100644 index 0000000..4e0488b --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rv1126.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + */ + +#ifndef _ASM_ARCH_GRF_RV1126_H +#define _ASM_ARCH_GRF_RV1126_H + +struct rv1126_grf { + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int reserved0[1]; + unsigned int soc_status0; + unsigned int soc_status1; + unsigned int reserved1[2]; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int reserved2[2]; + unsigned int cpu_status0; + unsigned int reserved3[3]; + unsigned int noc_con0; + unsigned int noc_con1; + unsigned int noc_con2; + unsigned int noc_con3; + unsigned int usbhost_con0; + unsigned int usbhost_con1; + unsigned int usbhost_status0; + unsigned int usbotg_con0; + unsigned int usbotg_con1; + unsigned int usbotg_status0; + unsigned int usbotg_status1; + unsigned int usbotg_status2; + unsigned int mac_con0; + unsigned int mac_con1; + unsigned int mac_con2; + unsigned int reserved4[2]; + unsigned int mac_status0; + unsigned int mac_status1; + unsigned int mac_status2; + unsigned int mem_con0; + unsigned int mem_con1; + unsigned int mem_con2; + unsigned int mem_con3; + unsigned int reserved5[(0x100 - 0x09c) / 4 - 1]; + unsigned int tsadc_con0; + unsigned int reserved6[3]; + unsigned int chip_id; + unsigned int reserved7[(0x10000 - 0x110) / 4 - 1]; + unsigned int gpio0c_iomux_h; + unsigned int gpio0d_iomux_l; + unsigned int gpio0d_iomux_h; + unsigned int reserved8[1]; + unsigned int gpio1a_iomux_l; + unsigned int gpio1a_iomux_h; + unsigned int gpio1b_iomux_l; + unsigned int gpio1b_iomux_h; + unsigned int gpio1c_iomux_l; + unsigned int gpio1c_iomux_h; + unsigned int gpio1d_iomux_l; + unsigned int gpio1d_iomux_h; + unsigned int gpio2a_iomux_l; + unsigned int gpio2a_iomux_h; + unsigned int gpio2b_iomux_l; + unsigned int gpio2b_iomux_h; + unsigned int gpio2c_iomux_l; + unsigned int gpio2c_iomux_h; + unsigned int gpio2d_iomux_l; + unsigned int gpio2d_iomux_h; + unsigned int gpio3a_iomux_l; + unsigned int gpio3a_iomux_h; + unsigned int gpio3b_iomux_l; + unsigned int gpio3b_iomux_h; + unsigned int gpio3c_iomux_l; + unsigned int gpio3c_iomux_h; + unsigned int gpio3d_iomux_l; + unsigned int gpio3d_iomux_h; + unsigned int gpio4a_iomux_l; + unsigned int reserved9[3]; + unsigned int gpio0c_ds_h; + unsigned int gpio0d_ds_l; + unsigned int gpio0d_ds_h; + unsigned int reserved10[1]; + unsigned int gpio1a_ds_l; + unsigned int gpio1a_ds_h; + unsigned int gpio1b_ds_l; + unsigned int gpio1b_ds_h; + unsigned int gpio1c_ds_l; + unsigned int gpio1c_ds_h; + unsigned int gpio1d_ds_l; + unsigned int gpio1d_ds_h; + unsigned int gpio2a_ds_l; + unsigned int gpio2a_ds_h; + unsigned int gpio2b_ds_l; + unsigned int gpio2b_ds_h; + unsigned int gpio2c_ds_l; + unsigned int gpio2c_ds_h; + unsigned int gpio2d_ds_l; + unsigned int gpio2d_ds_h; + unsigned int gpio3a_ds_l; + unsigned int gpio3a_ds_h; + unsigned int gpio3b_ds_l; + unsigned int gpio3b_ds_h; + unsigned int gpio3c_ds_l; + unsigned int gpio3c_ds_h; + unsigned int gpio3d_ds_l; + unsigned int gpio3d_ds_h; + unsigned int gpio4a_ds_l; + unsigned int reserved12[3]; + unsigned int gpio0c_p_h; + unsigned int gpio0d_p; + unsigned int gpio1a_p; + unsigned int gpio1b_p; + unsigned int gpio1c_p; + unsigned int gpio1d_p; + unsigned int gpio2a_p; + unsigned int gpio2b_p; + unsigned int gpio2c_p; + unsigned int gpio2d_p; + unsigned int gpio3a_p; + unsigned int gpio3b_p; + unsigned int gpio3c_p; + unsigned int gpio3d_p; + unsigned int gpio4a_p; + unsigned int reserved13[1]; + unsigned int gpio0c_ie_h; + unsigned int gpio0d_ie; + unsigned int gpio1a_ie; + unsigned int gpio1b_ie; + unsigned int gpio1c_ie; + unsigned int gpio1d_ie; + unsigned int gpio2a_ie; + unsigned int gpio2b_ie; + unsigned int gpio2c_ie; + unsigned int gpio2d_ie; + unsigned int gpio3a_ie; + unsigned int gpio3b_ie; + unsigned int gpio3c_ie; + unsigned int gpio3d_ie; + unsigned int gpio4a_ie; + unsigned int reserved14[1]; + unsigned int gpio0c_smt_h; + unsigned int gpio0d_smt; + unsigned int gpio1a_smt; + unsigned int gpio1b_smt; + unsigned int gpio1c_smt; + unsigned int gpio1d_smt; + unsigned int gpio2a_smt; + unsigned int gpio2b_smt; + unsigned int gpio2c_smt; + unsigned int gpio2d_smt; + unsigned int gpio3a_smt; + unsigned int gpio3b_smt; + unsigned int gpio3c_smt; + unsigned int gpio3d_smt; + unsigned int gpio4a_smt; + unsigned int reserved15[(0x10200 - 0x101b8) / 4 - 1]; + unsigned int csiphy0_con; + unsigned int reserved16[1]; + unsigned int csiphy0_status; + unsigned int reserved17[1]; + unsigned int csiphy1_con; + unsigned int reserved18[1]; + unsigned int csiphy1_status; + unsigned int reserved19[1]; + unsigned int dsiphy_con; + unsigned int reserved20[3]; + unsigned int usbphy_con0; + unsigned int usbphy_con1; + unsigned int usbphy_con2; + unsigned int reserved21[3]; + unsigned int usbphy_status; + unsigned int reserved22[1]; + unsigned int cifio_con; + unsigned int sddetflt_con; + unsigned int uart2rx_low_con; + unsigned int reserved23[1]; + unsigned int iofunc_con0; + unsigned int iofunc_con1; + unsigned int iofunc_con2; + unsigned int iofunc_con3; + unsigned int usbphy0_cfg_con; + unsigned int usbphy0_cfg_addrin; + unsigned int usbphy0_cfg_addrout; + unsigned int usbphy0_cfg_dly_con; + unsigned int usbphy1_cfg_con; + unsigned int usbphy1_cfg_addrin; + unsigned int usbphy1_cfg_addrout; + unsigned int usbphy1_cfg_dly_con; + unsigned int reserved24[(0x10300 - 0x1028c) / 4 - 1]; + unsigned int usb_sig_detect_con; + unsigned int usb_sig_detect_status; + unsigned int usb_sig_detect_clr; + unsigned int reserved25[1]; + unsigned int usb_linestate_con; + unsigned int usb_disconnect_con; + unsigned int usb_bvalid_con; + unsigned int usb_id_con; +}; + +check_member(rv1126_grf, usb_id_con, 0x1031c); + +struct rv1126_pmugrf { + unsigned int gpio0a_iomux_l; + unsigned int gpio0a_iomux_h; + unsigned int gpio0b_iomux_l; + unsigned int gpio0b_iomux_h; + unsigned int gpio0c_iomux_l; + unsigned int reserved0[3]; + unsigned int gpio0a_ds_l; + unsigned int gpio0a_ds_h; + unsigned int gpio0b_ds_l; + unsigned int gpio0b_ds_h; + unsigned int gpio0c_ds_l; + unsigned int osc_ds; + unsigned int reserved1[2]; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p_l; + unsigned int reserved2[1]; + unsigned int gpio0a_ie; + unsigned int gpio0b_ie; + unsigned int gpio0c_ie_l; + unsigned int reserved3[1]; + unsigned int gpio0a_smt; + unsigned int gpio0b_smt; + unsigned int gpio0c_smt_l; + unsigned int reserved4[(0x100 - 0x68) / 4 - 1]; + unsigned int soc_con[7]; + unsigned int reserved5[(0x140 - 0x118) / 4 - 1]; + unsigned int io_vsel; + unsigned int io_vret; + unsigned int reserved6[(0x180 - 0x144) / 4 - 1]; + unsigned int pmupvtm_clkdiv; + unsigned int reserved7[(0x200 - 0x180) / 4 - 1]; + unsigned int os_reg[12]; + unsigned int rstfunc_status; + unsigned int rstfunc_clr; + unsigned int reserved8[(0x380 - 0x234) / 4 - 1]; + unsigned int sd_detect_con; + unsigned int reserved9[3]; + unsigned int sd_detect_status; + unsigned int reserved10[3]; + unsigned int sd_detect_clr; + unsigned int reserved11[3]; + unsigned int sd_det_count; +}; + +check_member(rv1126_pmugrf, sd_det_count, 0x3b0); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 5efa6e9..e53e5a9 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -15,6 +15,210 @@ #define MIN(a, b) (((a) > (b)) ? (b) : (a)) #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +/* get head info for initial */ +#define DDR_FREQ_F0_SHIFT (0) +#define DDR_FREQ_F1_SHIFT (12) +#define DDR_FREQ_F2_SHIFT (0) +#define DDR_FREQ_F3_SHIFT (12) +#define DDR_FREQ_F4_SHIFT (0) +#define DDR_FREQ_F5_SHIFT (12) +#define DDR_FREQ_MASK (0xfff) + +#define UART_INFO_ID_SHIFT (28) +#define UART_INFO_IOMUX_SHIFT (24) +#define UART_INFO_BAUD_SHIFT (0) +#define UART_INFO_ID(n) (((n) >> 28) & 0xf) +#define UART_INFO_IOMUX(n) (((n) >> 24) & 0xf) +#define UART_INFO_BAUD(n) ((n) & 0xffffff) + +/* g_ch_info[15:0]: g_stdby_idle */ +#define STANDBY_IDLE(n) ((n) & 0xffff) + +#define SR_INFO(n) (((n) >> 16) & 0xffff) +#define PD_INFO(n) ((n) & 0xffff) + +#define FIRST_SCAN_CH(n) (((n) >> 28) & 0xf) +#define CHANNEL_MASK(n) (((n) >> 24) & 0xf) +#define STRIDE_TYPE(n) (((n) >> 16) & 0xff) + +#define DDR_2T_INFO(n) ((n) & 1) +#define PLL_SSMOD_SPREAD(n) (((n) >> 1) & 0xff) +#define PLL_SSMOD_DIV(n) (((n) >> 9) & 0xff) +#define PLL_SSMOD_DOWNSPREAD(n) (((n) >> 17) & 0x3) + +/* sdram_head_info_v2 define */ +/* for *_drv_odten and *_drv_odtoff */ +#define PHY_DQ_DRV_SHIFT 0 +#define PHY_CA_DRV_SHIFT 8 +#define PHY_CLK_DRV_SHIFT 16 +#define DRAM_DQ_DRV_SHIFT 24 +#define DRV_INFO_PHY_DQ_DRV(n) ((n) & 0xff) +#define DRV_INFO_PHY_CA_DRV(n) (((n) >> PHY_CA_DRV_SHIFT) & 0xff) +#define DRV_INFO_PHY_CLK_DRV(n) (((n) >> PHY_CLK_DRV_SHIFT) & 0xff) +#define DRV_INFO_DRAM_DQ_DRV(n) (((n) >> DRAM_DQ_DRV_SHIFT) & 0xff) + +/* for *_odt_info */ +#define DRAM_ODT_SHIFT 0 +#define PHY_ODT_SHIFT 8 +#define PHY_ODT_PUUP_EN_SHIFT 18 +#define PHY_ODT_PUDN_EN_SHIFT 19 +#define ODT_INFO_DRAM_ODT(n) (((n) >> DRAM_ODT_SHIFT) & 0xff) +#define ODT_INFO_PHY_ODT(n) (((n) >> PHY_ODT_SHIFT) & 0x3ff) +#define ODT_INFO_PULLUP_EN(n) (((n) >> PHY_ODT_PUUP_EN_SHIFT) & 1) +#define ODT_INFO_PULLDOWN_EN(n) (((n) >> PHY_ODT_PUDN_EN_SHIFT) & 1) + +/* for *odt_en_freq; */ +#define DRAM_ODT_EN_FREQ_SHIFT 0 +#define PHY_ODT_EN_FREQ_SHIFT 12 +#define DRAMODT_EN_FREQ(n) (((n) >> DRAM_ODT_EN_FREQ_SHIFT) & \ + 0xfff) +#define PHYODT_EN_FREQ(n) (((n) >> PHY_ODT_EN_FREQ_SHIFT) & 0xfff) + +#define PHY_DQ_SR_SHIFT 0 +#define PHY_CA_SR_SHIFT 8 +#define PHY_CLK_SR_SHIFT 16 +#define DQ_SR_INFO(n) (((n) >> PHY_DQ_SR_SHIFT) & 0xff) +#define CA_SR_INFO(n) (((n) >> PHY_CA_SR_SHIFT) & 0xff) +#define CLK_SR_INFO(n) (((n) >> PHY_CLK_SR_SHIFT) & 0xff) + +/* LP4 */ +#define LP4_CA_ODT_SHIFT (18) +#define LP4_DRV_PU_CAL_ODTEN_SHIFT (26) +#define LP4_DRV_PU_CAL_ODTOFF_SHIFT (27) +#define PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT (28) +#define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT (29) +#define ODT_INFO_LP4_CA_ODT(n) (((n) >> LP4_CA_ODT_SHIFT) & \ + 0xff) +#define LP4_DRV_PU_CAL_ODTEN(n) \ + (((n) >> LP4_DRV_PU_CAL_ODTEN_SHIFT) & 1) +#define LP4_DRV_PU_CAL_ODTOFF(n) \ + (((n) >> LP4_DRV_PU_CAL_ODTOFF_SHIFT) & 1) +#define PHY_LP4_DRV_PULLDOWN_EN_ODTEN(n) \ + (((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) & 1) +#define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF(n) \ + (((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT) & 1) + +#define PHY_LP4_CS_DRV_ODTEN_SHIFT (0) +#define PHY_LP4_CS_DRV_ODTOFF_SHIFT (8) +#define LP4_ODTE_CK_SHIFT (16) +#define LP4_ODTE_CS_EN_SHIFT (17) +#define LP4_ODTD_CA_EN_SHIFT (18) +#define PHY_LP4_CS_DRV_ODTEN(n) \ + (((n) >> PHY_LP4_CS_DRV_ODTEN_SHIFT) & 0xff) +#define PHY_LP4_CS_DRV_ODTOFF(n) \ + (((n) >> PHY_LP4_CS_DRV_ODTOFF_SHIFT) & 0xff) +#define LP4_ODTE_CK_EN(n) (((n) >> LP4_ODTE_CK_SHIFT) & 1) +#define LP4_ODTE_CS_EN(n) (((n) >> LP4_ODTE_CS_EN_SHIFT) & 1) +#define LP4_ODTD_CA_EN(n) (((n) >> LP4_ODTD_CA_EN_SHIFT) & 1) + +#define PHY_LP4_DQ_VREF_SHIFT (0) +#define LP4_DQ_VREF_SHIFT (10) +#define LP4_CA_VREF_SHIFT (20) + +#define PHY_LP4_DQ_VREF(n) \ + (((n) >> PHY_LP4_DQ_VREF_SHIFT) & 0x3ff) +#define LP4_DQ_VREF(n) (((n) >> LP4_DQ_VREF_SHIFT) & 0x3ff) +#define LP4_CA_VREF(n) (((n) >> LP4_CA_VREF_SHIFT) & 0x3ff) + +#define LP4_DQ_ODT_EN_FREQ_SHIFT (0) +#define PHY_LP4_ODT_EN_FREQ_SHIFT (12) +#define LP4_CA_ODT_EN_FREQ_SHIFT (0) +#define PHY_LP4_ODT_EN_FREQ(n) \ + (((n) >> PHY_LP4_ODT_EN_FREQ_SHIFT) & 0xfff) +#define LP4_DQ_ODT_EN_FREQ(n) \ + (((n) >> LP4_DQ_ODT_EN_FREQ_SHIFT) & 0xfff) +#define LP4_CA_ODT_EN_FREQ(n) \ + (((n) >> LP4_CA_ODT_EN_FREQ_SHIFT) & 0xfff) + +struct sdram_head_info_v0 { + u32 start_tag; + u32 version_info; + u32 gcpu_gen_freq; + u32 g_d2_lp2_freq; + u32 g_d3_lp3_freq; + u32 g_d4_lp4_freq; + u32 g_uart_info; + u32 g_sr_pd_idle; + u32 g_ch_info; + u32 g_2t_info; + u32 reserved11; + u32 reserved12; + u32 reserved13; +}; + +struct index_info { + u8 offset; + u8 size; +}; + +struct sdram_head_info_index_v2 { + u32 start_tag; + u32 version_info; + struct index_info cpu_gen_index; + struct index_info global_index; + + struct index_info ddr2_index; + struct index_info ddr3_index; + + struct index_info ddr4_index; + struct index_info ddr5_index; + + struct index_info lp2_index; + struct index_info lp3_index; + + struct index_info lp4_index; + struct index_info lp5_index; + + struct index_info skew_index; + struct index_info dq_map_index; + + struct index_info lp4x_index; + struct index_info reserved; +}; + +struct global_info { + u32 uart_info; + u32 sr_pd_info; + u32 ch_info; + u32 info_2t; + u32 reserved[4]; +}; + +struct ddr2_3_4_lp2_3_info { + u32 ddr_freq0_1; + u32 ddr_freq2_3; + u32 ddr_freq4_5; + u32 drv_when_odten; + u32 drv_when_odtoff; + u32 odt_info; + u32 odten_freq; + u32 sr_when_odten; + u32 sr_when_odtoff; +}; + +struct lp4_info { + u32 ddr_freq0_1; + u32 ddr_freq2_3; + u32 ddr_freq4_5; + u32 drv_when_odten; + u32 drv_when_odtoff; + u32 odt_info; + u32 dq_odten_freq; + u32 sr_when_odten; + u32 sr_when_odtoff; + u32 ca_odten_freq; + u32 cs_drv_ca_odt_info; + u32 vref_when_odten; + u32 vref_when_odtoff; +}; + +struct dq_map_info { + u32 byte_map[2]; + u32 lp3_dq0_7_map; + u32 lp2_dq0_7_map; + u32 ddr4_dq_map[4]; +}; + struct sdram_cap_info { unsigned int rank; /* dram column number, 0 means this channel is invalid */ @@ -46,6 +250,14 @@ struct sdram_base_params { }; #define DDR_SYS_REG_VERSION (0x2) +/* for modify tRFC and related timing */ +#define DIE_CAP_512MBIT 64 +#define DIE_CAP_1GBIT 128 +#define DIE_CAP_2GBIT 256 +#define DIE_CAP_4GBIT 512 +#define DIE_CAP_8GBIT 1024 +#define DIE_CAP_16GBIT 2048 +#define DIE_CAP_32GBIT 4096 /* * sys_reg2 bitfield struct * [31] row_3_4_ch1 @@ -116,7 +328,7 @@ struct sdram_base_params { void sdram_print_dram_type(unsigned char dramtype); void sdram_print_ddr_info(struct sdram_cap_info *cap_info, - struct sdram_base_params *base); + struct sdram_base_params *base, u32 split); void sdram_print_stride(unsigned int stride); void sdram_org_config(struct sdram_cap_info *cap_info, diff --git a/arch/arm/include/asm/arch-rockchip/sdram_msch.h b/arch/arm/include/asm/arch-rockchip/sdram_msch.h index cfb3d9c..d1926f4 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_msch.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_msch.h @@ -57,6 +57,18 @@ union noc_devtodev0 { } b; }; +union noc_devtodev_rv1126 { + u32 d32; + struct { + unsigned busrdtord : 3; + unsigned reserved0 : 1; + unsigned busrdtowr : 4; + unsigned buswrtord : 4; + unsigned buswrtowr : 3; + unsigned reserved2 : 17; + } b; +}; + union noc_ddrmode { u32 d32; struct { diff --git a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h index 3a36577..3780dc6 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h @@ -12,7 +12,7 @@ #endif struct ddr_pctl_regs { - u32 pctl[30][2]; + u32 pctl[35][2]; }; /* ddr pctl registers define */ @@ -25,6 +25,7 @@ struct ddr_pctl_regs { #define DDR_PCTL2_MRCTRL2 0x1c #define DDR_PCTL2_DERATEEN 0x20 #define DDR_PCTL2_DERATEINT 0x24 +#define DDR_PCTL2_MSTR2 0x28 #define DDR_PCTL2_PWRCTL 0x30 #define DDR_PCTL2_PWRTMG 0x34 #define DDR_PCTL2_HWLPCTL 0x38 @@ -122,8 +123,103 @@ struct ddr_pctl_regs { #define DDR_PCTL2_PCFGW_n 0x408 #define DDR_PCTL2_PCTRL_n 0x490 +#define UMCTL2_REGS_FREQ(n) \ + ((0x1000 * (n) + (((n) > 0) ? 0x1000 : 0))) + +/* PCTL2_MSTR */ +#define PCTL2_FREQUENCY_MODE_MASK (1) +#define PCTL2_FREQUENCY_MODE_SHIFT (29) +#define PCTL2_DLL_OFF_MODE BIT(15) +/* PCTL2_STAT */ +#define PCTL2_SELFREF_TYPE_MASK (3 << 4) +#define PCTL2_SELFREF_TYPE_SR_NOT_AUTO (2 << 4) +#define PCTL2_OPERATING_MODE_MASK (7) +#define PCTL2_OPERATING_MODE_INIT (0) +#define PCTL2_OPERATING_MODE_NORMAL (1) +#define PCTL2_OPERATING_MODE_PD (2) +#define PCTL2_OPERATING_MODE_SR (3) +/* PCTL2_MRCTRL0 */ +#define PCTL2_MR_WR BIT(31) +#define PCTL2_MR_ADDR_SHIFT (12) +#define PCTL2_MR_RANK_SHIFT (4) +#define PCTL2_MR_TYPE_WR (0) +#define PCTL2_MR_TYPE_RD (1) +/* PCTL2_MRCTRL1 */ +#define PCTL2_MR_ADDRESS_SHIFT (8) +#define PCTL2_MR_DATA_MASK (0xff) /* PCTL2_MRSTAT */ -#define MR_WR_BUSY BIT(0) +#define PCTL2_MR_WR_BUSY BIT(0) +/* PCTL2_DERATEEN */ +#define PCTL2_DERATE_ENABLE (1) +/* PCTL2_PWRCTL */ +#define PCTL2_SELFREF_SW BIT(5) +#define PCTL2_POWERDOWN_EN BIT(1) +#define PCTL2_SELFREF_EN (1) +/* PCTL2_PWRTMG */ +#define PCTL2_SELFREF_TO_X32_MASK (0xFF) +#define PCTL2_SELFREF_TO_X32_SHIFT (16) +#define PCTL2_POWERDOWN_TO_X32_MASK (0x1F) +/* PCTL2_INIT3 */ +#define PCTL2_DDR34_MR0_SHIFT (16) +#define PCTL2_LPDDR234_MR1_SHIFT (16) +#define PCTL2_DDR34_MR1_SHIFT (0) +#define PCTL2_LPDDR234_MR2_SHIFT (0) +/* PCTL2_INIT4 */ +#define PCTL2_DDR34_MR2_SHIFT (16) +#define PCTL2_LPDDR234_MR3_SHIFT (16) +#define PCTL2_DDR34_MR3_SHIFT (0) +#define PCTL2_LPDDR4_MR13_SHIFT (0) + +/* PCTL2_INIT6 */ +#define PCTL2_DDR4_MR4_SHIFT (16) +#define PCTL2_LPDDR4_MR11_SHIFT (16) +#define PCTL2_DDR4_MR5_SHIFT (0) +#define PCTL2_LPDDR4_MR12_SHIFT (0) + +/* PCTL2_INIT7 */ +#define PCTL2_LPDDR4_MR22_SHIFT (16) +#define PCTL2_DDR4_MR6_SHIFT (0) +#define PCTL2_LPDDR4_MR14_SHIFT (0) + +#define PCTL2_MR_MASK (0xffff) + +/* PCTL2_RFSHCTL3 */ +#define PCTL2_DIS_AUTO_REFRESH (1) +/* PCTL2_ZQCTL0 */ +#define PCTL2_DIS_AUTO_ZQ BIT(31) +#define PCTL2_DIS_SRX_ZQCL BIT(30) +/* PCTL2_DFILPCFG0 */ +#define PCTL2_DFI_LP_EN_SR BIT(8) +#define PCTL2_DFI_LP_EN_SR_MASK BIT(8) +#define PCTL2_DFI_LP_EN_SR_SHIFT (8) +/* PCTL2_DFIMISC */ +#define PCTL2_DFI_INIT_COMPLETE_EN (1) +/* PCTL2_DFISTAT */ +#define PCTL2_DFI_LP_ACK BIT(1) +#define PCTL2_DFI_INIT_COMPLETE (1) +/* PCTL2_DBG1 */ +#define PCTL2_DIS_HIF BIT(1) +/* PCTL2_DBGCAM */ +#define PCTL2_DBG_WR_Q_EMPTY BIT(26) +#define PCTL2_DBG_RD_Q_EMPTY BIT(25) +#define PCTL2_DBG_LPR_Q_DEPTH_MASK (0xffff << 8) +#define PCTL2_DBG_LPR_Q_DEPTH_EMPTY (0x0 << 8) +/* PCTL2_DBGCMD */ +#define PCTL2_RANK1_REFRESH BIT(1) +#define PCTL2_RANK0_REFRESH (1) +/* PCTL2_DBGSTAT */ +#define PCTL2_RANK1_REFRESH_BUSY BIT(1) +#define PCTL2_RANK0_REFRESH_BUSY (1) +/* PCTL2_SWCTL */ +#define PCTL2_SW_DONE (1) +#define PCTL2_SW_DONE_CLEAR (0) +/* PCTL2_SWSTAT */ +#define PCTL2_SW_DONE_ACK (1) +/* PCTL2_PSTAT */ +#define PCTL2_WR_PORT_BUSY_0 BIT(16) +#define PCTL2_RD_PORT_BUSY_0 (1) +/* PCTL2_PCTRLn */ +#define PCTL2_PORT_EN (1) void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num); int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg, diff --git a/arch/arm/include/asm/arch-rockchip/sdram_phy_rv1126.h b/arch/arm/include/asm/arch-rockchip/sdram_phy_rv1126.h new file mode 100644 index 0000000..5b64ec3 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_phy_rv1126.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_RK1126_PHY_H +#define _ASM_ARCH_SDRAM_RK1126_PHY_H + +/* PHY_REG0 */ +#define DIGITAL_DERESET BIT(3) +#define ANALOG_DERESET BIT(2) +#define DIGITAL_RESET (0 << 3) +#define ANALOG_RESET (0 << 2) + +/* PHY_REG1 */ +#define PHY_DDR2 (0) +#define PHY_LPDDR2 (1) +#define PHY_DDR3 (2) +#define PHY_LPDDR3 (3) +#define PHY_DDR4 (4) +#define PHY_DDR5 (5) +#define PHY_BL_4 (0 << 3) +#define PHY_BL_8_OR_16 BIT(3) + +/* PHY_REG2 */ +#define PHY_DTT_EN BIT(0) +#define PHY_DTT_DISB (0 << 0) +#define PHY_WRITE_LEVELING_EN BIT(2) +#define PHY_WRITE_LEVELING_DISB (0 << 2) +#define PHY_SELECT_CS0 (2) +#define PHY_SELECT_CS1 (1) +#define PHY_SELECT_CS0_1 (0) +#define PHY_WRITE_LEVELING_SELECTCS(n) ((n) << 6) +#define PHY_DATA_TRAINING_SELECTCS(n) ((n) << 4) + +/* PHY_REGf */ +#define PHY_DQ_WIDTH_MASK (0xf) + +/* PHY_REG51 */ +#define PHY_PBDIV_BIT9_MASK BIT(0) +#define PHY_PBDIV_BIT9_SHIFT (0) +#define PHY_POSTDIV_EN_MASK BIT(7) +#define PHY_POSTDIV_EN_SHIFT (7) + +/* PHY_REG52 */ +#define PHY_PREDIV_MASK (0x1F) +#define PHY_PREDIV_SHIFT (0) + +/* PHY_REG53*/ +#define PHY_POSTDIV_MASK (0x7) +#define PHY_POSTDIV_SHIFT (5) +#define PHY_PD_DISB BIT(3) + +/* PHY_REG90 */ +#define PHY_PLL_LOCK BIT(2) + +struct ca_skew { + u32 a0_a3_a3_cke1_a_de_skew; + u32 a1_ba1_null_cke0_b_de_skew; + u32 a2_a9_a9_a4_a_de_skew; + u32 a3_a15_null_a5_b_de_skew; + u32 a4_a6_a6_ck_a_de_skew; + u32 a5_a12_null_odt0_b_de_skew; + u32 a6_ba2_null_a0_a_de_skew; + u32 a7_a4_a4_odt0_a_de_skew; + u32 a8_a1_a1_cke0_a_de_skew; + u32 a9_a5_a5_a5_a_de_skew; + u32 a10_a8_a8_clkb_a_de_skew; + u32 a11_a7_a7_ca2_a_de_skew; + u32 a12_rasn_null_ca1_a_de_skew; + u32 a13_a13_null_ca3_a_de_skew; + u32 a14_a14_null_csb1_b_de_skew; + u32 a15_a10_null_ca0_b_de_skew; + u32 a16_a11_null_csb0_b_de_skew; + u32 a17_null_null_null_de_skew; + u32 ba0_csb1_csb1_csb0_a_de_skew; + u32 ba1_wen_null_cke1_b_de_skew; + u32 bg0_odt1_odt1_csb1_a_de_skew; + u32 bg1_a2_a2_odt1_a_de_skew; + u32 cke0_casb_null_ca1_b_de_skew; + u32 ck_ck_ck_ck_b_de_skew; + u32 ckb_ckb_ckb_ckb_b_de_skew; + u32 csb0_odt0_odt0_ca2_b_de_skew; + u32 odt0_csb0_csb0_ca4_b_de_skew; + u32 resetn_resetn_null_resetn_de_skew; + u32 actn_cke_cke_ca3_b_de_skew; + u32 null_null_null_null_de_skew; + u32 csb1_ba0_null_null_de_skew; + u32 odt1_a0_a0_odt1_b_de_skew; +}; + +#define PHY_REG(base, n) ((base) + 4 * (n)) +#endif /* _ASM_ARCH_SDRAM_RK1126_PHY_H */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h new file mode 100644 index 0000000..6a07436 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_rv1126.h @@ -0,0 +1,420 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Rockchip Electronics Co., Ltd + */ + +#ifndef _ASM_ARCH_SDRAM_RK1126_H +#define _ASM_ARCH_SDRAM_RK1126_H + +#include <asm/arch-rockchip/dram_spec_timing.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_msch.h> +#include <asm/arch-rockchip/sdram_pctl_px30.h> +#include <asm/arch-rockchip/sdram_phy_rv1126.h> + +#define AGINGX0_VAL (4) +#define AGING_CPU_VAL (0xff) +#define AGING_NPU_VAL (0xff) +#define AGING_OTHER_VAL (0x33) + +#define PATTERN (0x5aa5f00f) + +#define PHY_DDR3_RON_DISABLE (0) +#define PHY_DDR3_RON_455ohm (1) +#define PHY_DDR3_RON_230ohm (2) +#define PHY_DDR3_RON_153ohm (3) +#define PHY_DDR3_RON_115ohm (4) +#define PHY_DDR3_RON_91ohm (5) +#define PHY_DDR3_RON_76ohm (6) +#define PHY_DDR3_RON_65ohm (7) +#define PHY_DDR3_RON_57ohm (16) +#define PHY_DDR3_RON_51ohm (17) +#define PHY_DDR3_RON_46ohm (18) +#define PHY_DDR3_RON_41ohm (19) +#define PHY_DDR3_RON_38ohm (20) +#define PHY_DDR3_RON_35ohm (21) +#define PHY_DDR3_RON_32ohm (22) +#define PHY_DDR3_RON_30ohm (23) +#define PHY_DDR3_RON_28ohm (24) +#define PHY_DDR3_RON_27ohm (25) +#define PHY_DDR3_RON_25ohm (26) +#define PHY_DDR3_RON_24ohm (27) +#define PHY_DDR3_RON_23ohm (28) +#define PHY_DDR3_RON_22ohm (29) +#define PHY_DDR3_RON_21ohm (30) +#define PHY_DDR3_RON_20ohm (31) + +#define PHY_DDR3_RTT_DISABLE (0) +#define PHY_DDR3_RTT_561ohm (1) +#define PHY_DDR3_RTT_282ohm (2) +#define PHY_DDR3_RTT_188ohm (3) +#define PHY_DDR3_RTT_141ohm (4) +#define PHY_DDR3_RTT_113ohm (5) +#define PHY_DDR3_RTT_94ohm (6) +#define PHY_DDR3_RTT_81ohm (7) +#define PHY_DDR3_RTT_72ohm (16) +#define PHY_DDR3_RTT_64ohm (17) +#define PHY_DDR3_RTT_58ohm (18) +#define PHY_DDR3_RTT_52ohm (19) +#define PHY_DDR3_RTT_48ohm (20) +#define PHY_DDR3_RTT_44ohm (21) +#define PHY_DDR3_RTT_41ohm (22) +#define PHY_DDR3_RTT_38ohm (23) +#define PHY_DDR3_RTT_37ohm (24) +#define PHY_DDR3_RTT_34ohm (25) +#define PHY_DDR3_RTT_32ohm (26) +#define PHY_DDR3_RTT_31ohm (27) +#define PHY_DDR3_RTT_29ohm (28) +#define PHY_DDR3_RTT_28ohm (29) +#define PHY_DDR3_RTT_27ohm (30) +#define PHY_DDR3_RTT_25ohm (31) + +#define PHY_DDR4_LPDDR3_RON_DISABLE (0) +#define PHY_DDR4_LPDDR3_RON_482ohm (1) +#define PHY_DDR4_LPDDR3_RON_244ohm (2) +#define PHY_DDR4_LPDDR3_RON_162ohm (3) +#define PHY_DDR4_LPDDR3_RON_122ohm (4) +#define PHY_DDR4_LPDDR3_RON_97ohm (5) +#define PHY_DDR4_LPDDR3_RON_81ohm (6) +#define PHY_DDR4_LPDDR3_RON_69ohm (7) +#define PHY_DDR4_LPDDR3_RON_61ohm (16) +#define PHY_DDR4_LPDDR3_RON_54ohm (17) +#define PHY_DDR4_LPDDR3_RON_48ohm (18) +#define PHY_DDR4_LPDDR3_RON_44ohm (19) +#define PHY_DDR4_LPDDR3_RON_40ohm (20) +#define PHY_DDR4_LPDDR3_RON_37ohm (21) +#define PHY_DDR4_LPDDR3_RON_34ohm (22) +#define PHY_DDR4_LPDDR3_RON_32ohm (23) +#define PHY_DDR4_LPDDR3_RON_30ohm (24) +#define PHY_DDR4_LPDDR3_RON_28ohm (25) +#define PHY_DDR4_LPDDR3_RON_27ohm (26) +#define PHY_DDR4_LPDDR3_RON_25ohm (27) +#define PHY_DDR4_LPDDR3_RON_24ohm (28) +#define PHY_DDR4_LPDDR3_RON_23ohm (29) +#define PHY_DDR4_LPDDR3_RON_22ohm (30) +#define PHY_DDR4_LPDDR3_RON_21ohm (31) + +#define PHY_DDR4_LPDDR3_RTT_DISABLE (0) +#define PHY_DDR4_LPDDR3_RTT_586ohm (1) +#define PHY_DDR4_LPDDR3_RTT_294ohm (2) +#define PHY_DDR4_LPDDR3_RTT_196ohm (3) +#define PHY_DDR4_LPDDR3_RTT_148ohm (4) +#define PHY_DDR4_LPDDR3_RTT_118ohm (5) +#define PHY_DDR4_LPDDR3_RTT_99ohm (6) +#define PHY_DDR4_LPDDR3_RTT_85ohm (7) +#define PHY_DDR4_LPDDR3_RTT_76ohm (16) +#define PHY_DDR4_LPDDR3_RTT_67ohm (17) +#define PHY_DDR4_LPDDR3_RTT_60ohm (18) +#define PHY_DDR4_LPDDR3_RTT_55ohm (19) +#define PHY_DDR4_LPDDR3_RTT_50ohm (20) +#define PHY_DDR4_LPDDR3_RTT_46ohm (21) +#define PHY_DDR4_LPDDR3_RTT_43ohm (22) +#define PHY_DDR4_LPDDR3_RTT_40ohm (23) +#define PHY_DDR4_LPDDR3_RTT_38ohm (24) +#define PHY_DDR4_LPDDR3_RTT_36ohm (25) +#define PHY_DDR4_LPDDR3_RTT_34ohm (26) +#define PHY_DDR4_LPDDR3_RTT_32ohm (27) +#define PHY_DDR4_LPDDR3_RTT_31ohm (28) +#define PHY_DDR4_LPDDR3_RTT_29ohm (29) +#define PHY_DDR4_LPDDR3_RTT_28ohm (30) +#define PHY_DDR4_LPDDR3_RTT_27ohm (31) + +#define PHY_LPDDR4_RON_DISABLE (0) +#define PHY_LPDDR4_RON_501ohm (1) +#define PHY_LPDDR4_RON_253ohm (2) +#define PHY_LPDDR4_RON_168ohm (3) +#define PHY_LPDDR4_RON_126ohm (4) +#define PHY_LPDDR4_RON_101ohm (5) +#define PHY_LPDDR4_RON_84ohm (6) +#define PHY_LPDDR4_RON_72ohm (7) +#define PHY_LPDDR4_RON_63ohm (16) +#define PHY_LPDDR4_RON_56ohm (17) +#define PHY_LPDDR4_RON_50ohm (18) +#define PHY_LPDDR4_RON_46ohm (19) +#define PHY_LPDDR4_RON_42ohm (20) +#define PHY_LPDDR4_RON_38ohm (21) +#define PHY_LPDDR4_RON_36ohm (22) +#define PHY_LPDDR4_RON_33ohm (23) +#define PHY_LPDDR4_RON_31ohm (24) +#define PHY_LPDDR4_RON_29ohm (25) +#define PHY_LPDDR4_RON_28ohm (26) +#define PHY_LPDDR4_RON_26ohm (27) +#define PHY_LPDDR4_RON_25ohm (28) +#define PHY_LPDDR4_RON_24ohm (29) +#define PHY_LPDDR4_RON_23ohm (30) +#define PHY_LPDDR4_RON_22ohm (31) + +#define PHY_LPDDR4_RTT_DISABLE (0) +#define PHY_LPDDR4_RTT_604ohm (1) +#define PHY_LPDDR4_RTT_303ohm (2) +#define PHY_LPDDR4_RTT_202ohm (3) +#define PHY_LPDDR4_RTT_152ohm (4) +#define PHY_LPDDR4_RTT_122ohm (5) +#define PHY_LPDDR4_RTT_101ohm (6) +#define PHY_LPDDR4_RTT_87ohm (7) +#define PHY_LPDDR4_RTT_78ohm (16) +#define PHY_LPDDR4_RTT_69ohm (17) +#define PHY_LPDDR4_RTT_62ohm (18) +#define PHY_LPDDR4_RTT_56ohm (19) +#define PHY_LPDDR4_RTT_52ohm (20) +#define PHY_LPDDR4_RTT_48ohm (21) +#define PHY_LPDDR4_RTT_44ohm (22) +#define PHY_LPDDR4_RTT_41ohm (23) +#define PHY_LPDDR4_RTT_39ohm (24) +#define PHY_LPDDR4_RTT_37ohm (25) +#define PHY_LPDDR4_RTT_35ohm (26) +#define PHY_LPDDR4_RTT_33ohm (27) +#define PHY_LPDDR4_RTT_32ohm (28) +#define PHY_LPDDR4_RTT_30ohm (29) +#define PHY_LPDDR4_RTT_29ohm (30) +#define PHY_LPDDR4_RTT_27ohm (31) + +#define ADD_CMD_CA (0x150) +#define ADD_GROUP_CS0_A (0x170) +#define ADD_GROUP_CS0_B (0x1d0) +#define ADD_GROUP_CS1_A (0x1a0) +#define ADD_GROUP_CS1_B (0x200) + +/* PMUGRF */ +#define PMUGRF_OS_REG0 (0x200) +#define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) +#define PMUGRF_CON_DDRPHY_BUFFEREN_MASK (0x3 << (12 + 16)) +#define PMUGRF_CON_DDRPHY_BUFFEREN_EN (0x1 << 12) +#define PMUGRF_CON_DDRPHY_BUFFEREN_DIS (0x2 << 12) + +/* DDR GRF */ +#define DDR_GRF_CON(n) (0 + (n) * 4) +#define DDR_GRF_STATUS_BASE (0X100) +#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) +#define DDR_GRF_LP_CON (0x20) + +#define SPLIT_MODE_32_L16_VALID (0) +#define SPLIT_MODE_32_H16_VALID (1) +#define SPLIT_MODE_16_L8_VALID (2) +#define SPLIT_MODE_16_H8_VALID (3) + +#define DDR_GRF_SPLIT_CON (0x10) +#define SPLIT_MODE_MASK (0x3) +#define SPLIT_MODE_OFFSET (9) +#define SPLIT_BYPASS_MASK (1) +#define SPLIT_BYPASS_OFFSET (8) +#define SPLIT_SIZE_MASK (0xff) +#define SPLIT_SIZE_OFFSET (0) + +/* SGRF SOC_CON13 */ +#define UPCTL2_ASRSTN_REQ(n) (((0x1 << 0) << 16) | ((n) << 0)) +#define UPCTL2_PSRSTN_REQ(n) (((0x1 << 1) << 16) | ((n) << 1)) +#define UPCTL2_SRSTN_REQ(n) (((0x1 << 2) << 16) | ((n) << 2)) + +/* CRU define */ +/* CRU_PLL_CON0 */ +#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) +#define FBDIV(n) ((0xFFF << 16) | (n)) + +/* CRU_PLL_CON1 */ +#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) +#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) +#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) +#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) +#define LOCK(n) (((n) >> 10) & 0x1) +#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) +#define REFDIV(n) ((0x3F << 16) | (n)) + +/* CRU_PLL_CON3 */ +#define SSMOD_SPREAD(n) ((0x1f << (8 + 16)) | ((n) << 8)) +#define SSMOD_DIVVAL(n) ((0xf << (4 + 16)) | ((n) << 4)) +#define SSMOD_DOWNSPREAD(n) ((0x1 << (3 + 16)) | ((n) << 3)) +#define SSMOD_RESET(n) ((0x1 << (2 + 16)) | ((n) << 2)) +#define SSMOD_DIS_SSCG(n) ((0x1 << (1 + 16)) | ((n) << 1)) +#define SSMOD_BP(n) ((0x1 << (0 + 16)) | ((n) << 0)) + +/* CRU_MODE */ +#define CLOCK_FROM_XIN_OSC (0) +#define CLOCK_FROM_PLL (1) +#define CLOCK_FROM_RTC_32K (2) +#define DPLL_MODE(n) ((0x3 << (2 + 16)) | ((n) << 2)) + +/* CRU_SOFTRESET_CON1 */ +#define DDRPHY_PSRSTN_REQ(n) (((0x1 << 14) << 16) | ((n) << 14)) +#define DDRPHY_SRSTN_REQ(n) (((0x1 << 15) << 16) | ((n) << 15)) +/* CRU_CLKGATE_CON2 */ +#define DDR_MSCH_EN_MASK ((0x1 << 10) << 16) +#define DDR_MSCH_EN_SHIFT (10) + +/* CRU register */ +#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) +#define CRU_MODE (0xa0) +#define CRU_GLB_CNT_TH (0xb0) +#define CRU_CLKSEL_CON_BASE 0x100 +#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4)) +#define CRU_CLKGATE_CON_BASE 0x230 +#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4)) +#define CRU_CLKSFTRST_CON_BASE 0x300 +#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4)) + +/* SGRF_SOC_CON2 */ +#define MSCH_AXI_BYPASS_ALL_MASK (1) +#define MSCH_AXI_BYPASS_ALL_SHIFT (15) + +/* SGRF_SOC_CON12 */ +#define CLK_DDR_UPCTL_EN_MASK ((0x1 << 2) << 16) +#define CLK_DDR_UPCTL_EN_SHIFT (2) +#define ACLK_DDR_UPCTL_EN_MASK ((0x1 << 0) << 16) +#define ACLK_DDR_UPCTL_EN_SHIFT (0) + +/* DDRGRF DDR CON2 */ +#define DFI_FREQ_CHANGE_ACK BIT(10) +/* DDRGRF status8 */ +#define DFI_FREQ_CHANGE_REQ BIT(19) + +struct rv1126_ddrgrf { + u32 ddr_grf_con[4]; + u32 grf_ddrsplit_con; + u32 reserved1[(0x20 - 0x10) / 4 - 1]; + u32 ddr_grf_lp_con; + u32 reserved2[(0x40 - 0x20) / 4 - 1]; + u32 grf_ddrphy_con[6]; + u32 reserved3[(0x100 - 0x54) / 4 - 1]; + u32 ddr_grf_status[18]; + u32 reserved4[(0x150 - 0x144) / 4 - 1]; + u32 grf_ddrhold_status; + u32 reserved5[(0x160 - 0x150) / 4 - 1]; + u32 grf_ddrphy_status[2]; +}; + +struct rv1126_ddr_phy_regs { + u32 phy[8][2]; +}; + +struct msch_regs { + u32 coreid; + u32 revisionid; + u32 deviceconf; + u32 devicesize; + u32 ddrtiminga0; + u32 ddrtimingb0; + u32 ddrtimingc0; + u32 devtodev0; + u32 reserved1[(0x110 - 0x20) / 4]; + u32 ddrmode; + u32 ddr4timing; + u32 reserved2[(0x1000 - 0x118) / 4]; + u32 agingx0; + u32 reserved3[(0x1040 - 0x1004) / 4]; + u32 aging0; + u32 aging1; + u32 aging2; + u32 aging3; +}; + +struct sdram_msch_timings { + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev_rv1126 devtodev0; + union noc_ddrmode ddrmode; + union noc_ddr4timing ddr4timing; + u32 agingx0; + u32 aging0; + u32 aging1; + u32 aging2; + u32 aging3; +}; + +struct rv1126_sdram_channel { + struct sdram_cap_info cap_info; + struct sdram_msch_timings noc_timings; +}; + +struct rv1126_sdram_params { + struct rv1126_sdram_channel ch; + struct sdram_base_params base; + struct ddr_pctl_regs pctl_regs; + struct rv1126_ddr_phy_regs phy_regs; +}; + +struct rv1126_fsp_param { + u32 flag; + u32 freq_mhz; + + /* dram size */ + u32 dq_odt; + u32 ca_odt; + u32 ds_pdds; + u32 vref_ca[2]; + u32 vref_dq[2]; + + /* phy side */ + u32 wr_dq_drv; + u32 wr_ca_drv; + u32 wr_ckcs_drv; + u32 rd_odt; + u32 rd_odt_up_en; + u32 rd_odt_down_en; + u32 vref_inner; + u32 vref_out; + u32 lp4_drv_pd_en; + + struct sdram_msch_timings noc_timings; +}; + +#define MAX_IDX (4) +#define FSP_FLAG (0xfead0001) +#define SHARE_MEM_BASE (0x100000) +/* + * Borrow share memory space to temporarily store FSP parame. + * In the stage of DDR init write FSP parame to this space. + * In the stage of trust init move FSP parame to SRAM space + * from share memory space. + */ +#define FSP_PARAM_STORE_ADDR (SHARE_MEM_BASE) + +/* store result of read and write training, for ddr_dq_eye tool in u-boot */ +#define RW_TRN_RESULT_ADDR (0x2000000 + 0x8000) /* 32M + 32k */ +#define PRINT_STEP 1 + +#undef FSP_NUM +#undef CS_NUM +#undef BYTE_NUM + +#define FSP_NUM 4 +#define CS_NUM 2 +#define BYTE_NUM 4 +#define RD_DESKEW_NUM 64 +#define WR_DESKEW_NUM 64 + +#define LP4_WIDTH_REF_MHZ_H 1056 +#define LP4_RD_WIDTH_REF_H 12 +#define LP4_WR_WIDTH_REF_H 13 + +#define LP4_WIDTH_REF_MHZ_L 924 +#define LP4_RD_WIDTH_REF_L 15 +#define LP4_WR_WIDTH_REF_L 15 + +#define DDR4_WIDTH_REF_MHZ_H 1056 +#define DDR4_RD_WIDTH_REF_H 13 +#define DDR4_WR_WIDTH_REF_H 9 + +#define DDR4_WIDTH_REF_MHZ_L 924 +#define DDR4_RD_WIDTH_REF_L 15 +#define DDR4_WR_WIDTH_REF_L 11 + +#define LP3_WIDTH_REF_MHZ_H 1056 +#define LP3_RD_WIDTH_REF_H 15 +#define LP3_WR_WIDTH_REF_H 13 + +#define LP3_WIDTH_REF_MHZ_L 924 +#define LP3_RD_WIDTH_REF_L 16 +#define LP3_WR_WIDTH_REF_L 15 + +#define DDR3_WIDTH_REF_MHZ_H 1056 +#define DDR3_RD_WIDTH_REF_H 14 +#define DDR3_WR_WIDTH_REF_H 14 + +#define DDR3_WIDTH_REF_MHZ_L 924 +#define DDR3_RD_WIDTH_REF_L 17 +#define DDR3_WR_WIDTH_REF_L 17 + +#endif /* _ASM_ARCH_SDRAM_RK1126_H */ diff --git a/arch/arm/include/asm/arch-rv1126/boot0.h b/arch/arm/include/asm/arch-rv1126/boot0.h new file mode 100644 index 0000000..2e78b07 --- /dev/null +++ b/arch/arm/include/asm/arch-rv1126/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rv1126/gpio.h b/arch/arm/include/asm/arch-rv1126/gpio.h new file mode 100644 index 0000000..eca79d5 --- /dev/null +++ b/arch/arm/include/asm/arch-rv1126/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4898260..b678ec4 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -302,6 +302,51 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. +config ROCKCHIP_RV1126 + bool "Support Rockchip RV1126" + select CPU_V7A + select SKIP_LOWLEVEL_INIT_ONLY + select TPL + select SUPPORT_TPL + select TPL_NEEDS_SEPARATE_STACK + select TPL_ROCKCHIP_BACK_TO_BROM + select SPL + select SUPPORT_SPL + select SPL_STACK_R + select CLK + select FIT + select PINCTRL + select RAM + select ROCKCHIP_SDRAM_COMMON + select REGMAP + select SYSCON + select DM_PMIC + select DM_REGULATOR_FIXED + select DM_RESET + select REGULATOR_RK8XX + select PMIC_RK8XX + select BOARD_LATE_INIT + imply ROCKCHIP_COMMON_BOARD + imply TPL_DM + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_OF_CONTROL + imply TPL_OF_PLATDATA + imply TPL_RAM + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL + imply SPL_CLK + imply SPL_DM + imply SPL_DRIVERS_MISC + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_OF_CONTROL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SERIAL + imply SPL_SYSCON + config ROCKCHIP_USB_UART bool "Route uart output to usb pins" help @@ -447,4 +492,5 @@ source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" +source "arch/arm/mach-rockchip/rv1126/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 6c1c7b8..32138fa 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ +obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/ # Clear out SPL objects, in case this is a TPL build obj-spl-$(CONFIG_TPL_BUILD) = diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 28639c0..4189392 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -35,6 +35,30 @@ config TARGET_PX30_CORE * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. +config TARGET_RINGNECK_PX30 + bool "Theobroma Systems PX30-µQ7 (Ringneck)" + help + The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, + MXM-230 connector) system-on-module from Theobroma Systems[1], + featuring the Rockchip PX30. + + It provides the following feature set: + * up to 4GB DDR4 + * up to 128GB on-module eMMC (with 8-bit 1.8V interface) + * SD card (on a baseboard) via edge connector + * Fast Ethernet with on-module TI DP83825I PHY + * MIPI-DSI/LVDS + * MIPI-CSI + * USB + - 1x USB 2.0 dual-role + - 3x USB 2.0 host + * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing: + - low-power RTC functionality (ISL1208 emulation) + - fan controller (AMC6821 emulation) + - USB<->CAN bridge controller (STM32 only) + * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi + * on-module NXP SE05x Secure Element + config ROCKCHIP_BOOT_MODE_REG default 0xff010200 @@ -71,5 +95,6 @@ config DEBUG_UART_CHANNEL source "board/engicam/px30_core/Kconfig" source "board/hardkernel/odroid_go2/Kconfig" source "board/rockchip/evb_px30/Kconfig" +source "board/theobroma-systems/ringneck_px30/Kconfig" endif diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 0641e6a..3bca25c 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -5,9 +5,12 @@ #include <common.h> #include <clk.h> #include <dm.h> +#include <fdt_support.h> #include <init.h> +#include <spl.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/grf_px30.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/uart.h> @@ -15,6 +18,11 @@ #include <asm/arch-rockchip/cru_px30.h> #include <dt-bindings/clock/px30-cru.h> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff370000", +}; + static struct mm_region px30_mem_map[] = { { .virt = 0x0UL, @@ -234,6 +242,7 @@ enum { int arch_cpu_init(void) { static struct px30_grf * const grf = (void *)GRF_BASE; + static struct px30_cru * const cru = (void *)CRU_BASE; u32 __maybe_unused val; #ifdef CONFIG_SPL_BUILD @@ -285,6 +294,9 @@ int arch_cpu_init(void) /* Clear the force_jtag */ rk_clrreg(&grf->cpu_con[1], 1 << 7); + /* Make TSADC and WDT trigger a first global reset */ + clrsetbits_le32(&cru->glb_rst_con, 0x3, 0x3); + return 0; } @@ -297,8 +309,18 @@ void board_debug_uart_init(void) CONFIG_DEBUG_UART_BASE == 0xff030000) static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE; #endif +#if !defined(CONFIG_DEBUG_UART_BASE) || \ + (CONFIG_DEBUG_UART_BASE != 0xff158000 && \ + CONFIG_DEBUG_UART_BASE != 0xff168000 && \ + CONFIG_DEBUG_UART_BASE != 0xff178000 && \ + CONFIG_DEBUG_UART_BASE != 0xff030000) || \ + (defined(CONFIG_DEBUG_UART_BASE) && \ + (CONFIG_DEBUG_UART_BASE == 0xff158000 || \ + CONFIG_DEBUG_UART_BASE == 0xff168000 || \ + CONFIG_DEBUG_UART_BASE == 0xff178000)) static struct px30_grf * const grf = (void *)GRF_BASE; static struct px30_cru * const cru = (void *)CRU_BASE; +#endif #if defined(CONFIG_DEBUG_UART_BASE) && CONFIG_DEBUG_UART_BASE == 0xff030000 static struct px30_pmucru * const pmucru = (void *)PMUCRU_BASE; #endif @@ -421,3 +443,52 @@ void board_debug_uart_init(void) #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } #endif /* CONFIG_DEBUG_UART_BOARD_INIT */ + +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +const char *spl_decode_boot_device(u32 boot_device) +{ + int i; + static const struct { + u32 boot_device; + const char *ofpath; + } spl_boot_devices_tbl[] = { + { BOOT_DEVICE_MMC2, "/mmc@ff370000" }, + { BOOT_DEVICE_MMC1, "/mmc@ff390000" }, + }; + + for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i) + if (spl_boot_devices_tbl[i].boot_device == boot_device) + return spl_boot_devices_tbl[i].ofpath; + + return NULL; +} + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + void *blob = spl_image->fdt_addr; + const char *boot_ofpath; + int chosen; + + /* + * Inject the ofpath of the device the full U-Boot (or Linux in + * Falcon-mode) was booted from into the FDT, if a FDT has been + * loaded at the same time. + */ + if (!blob) + return; + + boot_ofpath = spl_decode_boot_device(spl_image->boot_device); + if (!boot_ofpath) { + pr_err("%s: could not map boot_device to ofpath\n", __func__); + return; + } + + chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); + if (chosen < 0) { + pr_err("%s: could not find/create '/chosen'\n", __func__); + return; + } + fdt_setprop_string(blob, chosen, + "u-boot,spl-boot-device", boot_ofpath); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index b48feeb..d01063a 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -39,6 +39,13 @@ config TARGET_PINEBOOK_PRO_RK3399 with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, 1920*1080 screen and all the usual laptop features. +config TARGET_PINEPHONE_PRO_RK3399 + bool "PinePhone Pro" + help + PinePhone Pro is a phone based on a variant of the Rockchip + rk3399 SoC with 4Gb RAM, onboard eMMC, USB-C, headphone jack, + 720x1440 screen and a Quectel 4G/LTE modem. + config TARGET_PUMA_RK3399 bool "Theobroma Systems RK3399-Q7 (Puma)" help @@ -165,6 +172,7 @@ endif # BOOTCOUNT_LIMIT source "board/firefly/roc-pc-rk3399/Kconfig" source "board/google/gru/Kconfig" source "board/pine64/pinebook-pro-rk3399/Kconfig" +source "board/pine64/pinephone-pro-rk3399/Kconfig" source "board/pine64/rockpro64_rk3399/Kconfig" source "board/rockchip/evb_rk3399/Kconfig" source "board/theobroma-systems/puma_rk3399/Kconfig" diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig new file mode 100644 index 0000000..7382c55 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -0,0 +1,59 @@ +if ROCKCHIP_RV1126 + +config TARGET_RV1126_NEU2 + bool "Edgeble Neural Compute Module 2(Neu2) SoM" + help + Neu2: + Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module + based on Rockchip RV1126 from Edgeble AI. + Neu2 powered with Consumer grade (0 to +80 °C) RV1126 SoC. + Neu2k powered with Industrial grade (-40 °C to +85 °C) RV1126K SoC. + + Neu2-IO: + Neural Compute Module 2(Neu2) IO board is an industrial form factor + IO board and Neu2 needs to mount on top of this IO board in order to + create complete Edgeble Neural Compute Module 2(Neu2) IO platform. + +config SOC_SPECIFIC_OPTIONS # dummy + def_bool y + select HAS_CUSTOM_SYS_INIT_SP_ADDR + +config ROCKCHIP_BOOT_MODE_REG + default 0xfe020200 + +config ROCKCHIP_STIMER_BASE + default 0xff670020 + +config SYS_SOC + default "rv1126" + +config CUSTOM_SYS_INIT_SP_ADDR + default 0x800000 + +config SPL_STACK + default 0x600000 + +config SPL_STACK_R_ADDR + default 0x800000 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl.lds" + +config TPL_STACK + default 0xff718000 + +config TPL_SYS_MALLOC_F_LEN + default 0x2000 + +config TPL_TEXT_BASE + default 0xff701000 + +config SYS_MALLOC_F_LEN + default 0x2000 + +config TEXT_BASE + default 0x600000 + +source board/edgeble/neural-compute-module-2/Kconfig + +endif diff --git a/arch/arm/mach-rockchip/rv1126/Makefile b/arch/arm/mach-rockchip/rv1126/Makefile new file mode 100644 index 0000000..b287563 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2019 Rockchip Electronics Co., Ltd +# Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rv1126.o + +ifndef CONFIG_TPL_BUILD +obj-y += clk_rv1126.o +obj-y += syscon_rv1126.o +endif diff --git a/arch/arm/mach-rockchip/rv1126/clk_rv1126.c b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c new file mode 100644 index 0000000..bd89027 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rv1126.h> +#include <linux/err.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rv1126_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rv1126_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c new file mode 100644 index 0000000..b9b8987 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rv1126.h> + +#define FIREWALL_APB_BASE 0xffa60000 +#define FW_DDR_CON_REG 0x80 +#define GRF_BASE 0xFE000000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@ffc50000", + [BROM_BOOTSOURCE_SD] = "/mmc@ffc60000", +}; + +/* GRF_GPIO3A_IOMUX_L */ +enum { + GPIO3A3_SHIFT = 12, + GPIO3A3_MASK = GENMASK(14, 12), + GPIO3A3_GPIO = 0, + GPIO3A3_UART2_RX_M1, + GPIO3A3_A7_JTAG_TMS_M1, + + GPIO3A2_SHIFT = 8, + GPIO3A2_MASK = GENMASK(10, 8), + GPIO3A2_GPIO = 0, + GPIO3A2_UART2_TX_M1, + GPIO3A2_A7_JTAG_TCK_M1, +}; + +/* GRF_IOFUNC_CON2 */ +enum { + UART2_IO_SEL_SHIFT = 8, + UART2_IO_SEL_MASK = GENMASK(8, 8), + UART2_IO_SEL_M0 = 0, + UART2_IO_SEL_M1, +}; + +void board_debug_uart_init(void) +{ + static struct rv1126_grf * const grf = (void *)GRF_BASE; + + /* Enable early UART2 channel m1 on the rv1126 */ + rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK, + UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT); + + /* Switch iomux */ + rk_clrsetreg(&grf->gpio3a_iomux_l, + GPIO3A3_MASK | GPIO3A2_MASK, + GPIO3A3_UART2_RX_M1 << GPIO3A3_SHIFT | + GPIO3A2_UART2_TX_M1 << GPIO3A2_SHIFT); +} + +#ifndef CONFIG_TPL_BUILD +int arch_cpu_init(void) +{ + /** + * Set dram area unsecure in spl + * + * usb & mmc & sfc controllers can read data to dram + * since they are unsecure. + * (Note: only secure-world can access this register) + */ + if (IS_ENABLED(CONFIG_SPL_BUILD)) + writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c new file mode 100644 index 0000000..599ea66 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rv1126_syscon_ids[] = { + { .compatible = "rockchip,rv1126-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rv1126-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rv1126) = { + .name = "rv1126_syscon", + .id = UCLASS_SYSCON, + .of_match = rv1126_syscon_ids, +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rv1126_syscon_bind_of_plat(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rv1126_pmu) = { + .name = "rockchip_rv1126_pmu", + .id = UCLASS_SYSCON, + .of_match = rv1126_syscon_ids, + .bind = rv1126_syscon_bind_of_plat, +}; + +U_BOOT_DRIVER(rockchip_rv1126_pmugrf) = { + .name = "rockchip_rv1126_pmugrf", + .id = UCLASS_SYSCON, + .of_match = rv1126_syscon_ids + 1, + .bind = rv1126_syscon_bind_of_plat, +}; +#endif |