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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/dts/px30-u-boot.dtsi2
-rw-r--r--arch/arm/dts/rk3288-u-boot.dtsi2
-rw-r--r--arch/arm/dts/rk3288.dtsi16
-rw-r--r--arch/arm/dts/rk3308-u-boot.dtsi2
-rw-r--r--arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi2
-rw-r--r--arch/arm/dts/rk3328-u-boot.dtsi2
-rw-r--r--arch/arm/dts/rk3368-u-boot.dtsi1
-rw-r--r--arch/arm/dts/rk3399-u-boot.dtsi2
-rw-r--r--arch/arm/dts/rk3568-u-boot.dtsi2
-rw-r--r--arch/arm/dts/rockchip-u-boot.dtsi46
-rw-r--r--arch/arm/mach-rockchip/Kconfig6
-rw-r--r--arch/arm/mach-rockchip/rk3308/rk3308.c6
-rw-r--r--arch/arm/mach-rockchip/rk3399/rk3399.c8
14 files changed, 79 insertions, 20 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0b72e4f..82cd456 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1974,7 +1974,7 @@ config ARCH_STM32MP
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select BLK
- select BINMAN if SPL_OPTEE || (SPL && !ARM64)
+ select BINMAN if SPL_OPTEE || SPL
select DM
select DM_GPIO
select DM_I2C
diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi
index f102b2a..462eaf6 100644
--- a/arch/arm/dts/px30-u-boot.dtsi
+++ b/arch/arm/dts/px30-u-boot.dtsi
@@ -3,6 +3,8 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
+#include "rockchip-u-boot.dtsi"
+
/ {
aliases {
mmc0 = &emmc;
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
index 9eb696b..e411445 100644
--- a/arch/arm/dts/rk3288-u-boot.dtsi
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -56,7 +56,7 @@
};
};
-#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
&binman {
rom {
filename = "u-boot.rom";
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 9fb6d86..53ee760 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -109,48 +109,48 @@
ports = <&vopl_out>, <&vopb_out>;
};
- sdmmc: dwmmc@ff0c0000 {
+ sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0c0000 0x4000>;
status = "disabled";
};
- sdio0: dwmmc@ff0d0000 {
+ sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0d0000 0x4000>;
status = "disabled";
};
- sdio1: dwmmc@ff0e0000 {
+ sdio1: mmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
<&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0e0000 0x4000>;
status = "disabled";
};
- emmc: dwmmc@ff0f0000 {
+ emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
max-frequency = <150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff0f0000 0x4000>;
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index 4bfad31..ab5bfc2 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -3,6 +3,8 @@
*(C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
+#include "rockchip-u-boot.dtsi"
+
/ {
aliases {
mmc0 = &emmc;
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 95f2652..16c3373 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
*/
+#include "rockchip-u-boot.dtsi"
+
/ {
chosen {
u-boot,spl-boot-order = &sdmmc;
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index 1633558..d4a7540 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -3,6 +3,8 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
+#include "rockchip-u-boot.dtsi"
+
/ {
aliases {
mmc0 = &emmc;
diff --git a/arch/arm/dts/rk3368-u-boot.dtsi b/arch/arm/dts/rk3368-u-boot.dtsi
index 2767c26..811d59a 100644
--- a/arch/arm/dts/rk3368-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/memory/rk3368-dmc.h>
+#include "rockchip-u-boot.dtsi"
/ {
dmc: dmc@ff610000 {
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 716b9a4..3c1a15f 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -60,7 +60,7 @@
};
-#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
&binman {
rom {
filename = "u-boot.rom";
diff --git a/arch/arm/dts/rk3568-u-boot.dtsi b/arch/arm/dts/rk3568-u-boot.dtsi
index 5a80dda..fa9b6ae 100644
--- a/arch/arm/dts/rk3568-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-u-boot.dtsi
@@ -3,6 +3,8 @@
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
+#include "rockchip-u-boot.dtsi"
+
/ {
aliases {
mmc0 = &sdhci;
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index eae3ee7..584f21e 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -17,13 +17,57 @@
filename = "u-boot-rockchip.bin";
pad-byte = <0xff>;
- blob {
+ mkimage {
filename = "idbloader.img";
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+#ifdef CONFIG_TPL
+ multiple-data-files;
+
+ u-boot-tpl {
+ };
+#endif
+ u-boot-spl {
+ };
};
+#ifdef CONFIG_ARM64
+ blob {
+ filename = "u-boot.itb";
+#else
u-boot-img {
+#endif
offset = <CONFIG_SPL_PAD_TO>;
};
};
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+ simple-bin-spi {
+ filename = "u-boot-rockchip-spi.bin";
+ pad-byte = <0xff>;
+
+ mkimage {
+ filename = "idbloader-spi.img";
+ args = "-n", CONFIG_SYS_SOC, "-T", "rkspi";
+#ifdef CONFIG_TPL
+ multiple-data-files;
+
+ u-boot-tpl {
+ };
+#endif
+ u-boot-spl {
+ };
+ };
+
+#ifdef CONFIG_ARM64
+ blob {
+ filename = "u-boot.itb";
+#else
+ u-boot-img {
+#endif
+ /* Sync with u-boot,spl-payload-offset if present */
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+ };
+ };
+#endif
};
#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index c561a77..b46cea2 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -425,12 +425,10 @@ config SPL_MMC
config ROCKCHIP_SPI_IMAGE
bool "Build a SPI image for rockchip"
- depends on HAS_ROM
help
Some Rockchip SoCs support booting from SPI flash. Enable this
- option to produce a 4MB SPI-flash image (called u-boot.rom)
- containing U-Boot. The image is built by binman. U-Boot sits near
- the start of the image.
+ option to produce a SPI-flash image containing U-Boot. The image
+ is built by binman. U-Boot sits near the start of the image.
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default SYS_TEXT_BASE
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c
index 70fe0d0..dd9109b 100644
--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -8,6 +8,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3308.h>
+#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/gpio.h>
#include <debug_uart.h>
@@ -142,6 +143,11 @@ enum {
#define GPIO0_A4 4
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000",
+ [BROM_BOOTSOURCE_SD] = "/mmc@ff480000",
+};
+
int rk_board_init(void)
{
static struct rk3308_grf * const grf = (void *)GRF_BASE;
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 01a0559..21db03b 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xff770000
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
- [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@fe330000",
[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe320000",
};
@@ -180,9 +180,9 @@ const char *spl_decode_boot_device(u32 boot_device)
u32 boot_device;
const char *ofpath;
} spl_boot_devices_tbl[] = {
- { BOOT_DEVICE_MMC1, "/mmc@fe320000" },
- { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
- { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
+ { BOOT_DEVICE_MMC2, "/mmc@fe320000" },
+ { BOOT_DEVICE_MMC1, "/mmc@fe330000" },
+ { BOOT_DEVICE_SPI, "/spi@ff1d0000/flash@0" },
};
for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
generated by cgit v1.1 at 2024-10-13 12:52:41 +0000